Bit line voltage generating circuit for non-volatile memory device and corresponding method

Abstract

Various embodiments of the present disclosure relate to a bit line voltage generation circuit and a corresponding method for a non-volatile memory device. An embodiment voltage generation circuit is used for a memory having a memory array, the memory array having a plurality of memory cells coupled to corresponding word lines and local bit lines, each memory cell having a storage element and a selector element, a bipolar transistor coupled to the storage element for selective flow of cell current during a read or verify operation, and a base terminal of the selector element coupled to the corresponding word line; associated with each bit line is a bias transistor having a control terminal, and the circuit generates a common source and common gate voltage for the control terminal; a driver stage is coupled to one end of each word line. The circuit generates the common source and common gate voltage based on a reference voltage, which is a function of the driver stage, the word line, and the simulation of the voltage drop across the memory cell, which is generated due to the current associated with the corresponding selector element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Italian U.S. Provisional Application No. 102020000001630, filed on January 28, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] The present solution relates to a bit line voltage generating circuit for a non-volatile memory device, in particular a phase change type bit line voltage generating circuit, and to a corresponding method. Background Art

[0004] As is known, non-volatile memories of the phase change type (PCM phase change memory or ePCM embedded phase change memory) envisage the storage of information in a memory cell, organized in a memory array arranged in rows formed by word lines (WL) and in columns formed by bit lines (BL), by exploiting phase change materials having the property of switching between phases with greatly different resistivity values. In particular, these materials are able to switch between an amorphous phase with a high resistivity and a crystalline or polycrystalline phase with a low resistivity. Thus, in a phase change memory cell, different values ​​of data stored to a corresponding phase (whether amorphous or crystalline) can be associated with a corresponding resistivity of the corresponding phase change memory element.

[0005] For example, elements of the sixth group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), may be used, which are called chalcogenides or chalcogenides; an alloy composed of germanium (Ge), antimony (Sb), and tellurium (Te), which is considered to be GST (having a chemical composition of Ge) that is currently widely used in such memory elements. 2 Sb 2 Te 5 ), as an element of phase change memory. Summary of the invention

[0006] Phase switching in a memory element can be achieved by locally increasing the temperature of a phase change material region, for example by passing an electrical programming current through a resistive electrode (commonly referred to as a heater) placed in contact with the phase change material region. This current produces the temperature change required for the phase change by the Joule effect.

[0007] In particular, when the phase change material is in an amorphous state with high resistivity (the so-called RESET state), it is necessary to apply a first current pulse (the so-called SET pulse) with a duration and amplitude, such as to enable the material to cool slowly. After this treatment, the phase change material changes its state and switches from a high resistivity state to a low resistivity crystalline state (the so-called SET state). Conversely, when the phase change material is in the SET state, it is necessary to apply a second current pulse (RESET pulse) with a large amplitude and short duration to return the material to a high resistivity amorphous state.

[0008] The reading (or verification) of the data stored in the memory cell can be performed by applying a sufficiently low bias voltage to the memory element of the phase change material, which is not enough to cause it to cause significant heating, and then reading the value of the current flowing in the memory cell. Assuming that the current is proportional to the conductivity of the phase change material, the phase of the material can be determined, thereby determining the data stored in the memory cell.

[0009] In particular, differential-type reading architectures are known, in which two memory cells storing opposite states are associated with each bit of a word to be read (composed of an appropriate number of bits in a known manner). For example, the value of a bit is "1" if a first memory cell (the so-called direct memory cell) and a second memory cell (the so-called complementary or reference memory cell) associated with the bit are in the SET state and the RESET state, respectively; and the value of a bit is "0" if the first memory cell and the second memory cell are in the RESET state and the SET state, respectively. Differential-type reading architectures offer advantages in terms of reliability as long as the data are stored in a redundant manner and, moreover, there is no need to generate a reference current as long as the reading is performed solely by comparing the corresponding currents flowing in the cells associated with the same bit.

[0010] in this regard, Figure 1 A part of a memory array 1 (of the PCM type) is shown, and in particular a corresponding (direct) memory cell 2 and a corresponding reference cell 2 ′ (shown schematically).

[0011] The memory cell 2 includes a phase change element 2a made of a phase change material (such as GST), and a selector element 2b (such as MOSFET or (such as Figure 1 The selector element 2b is electrically connected to a heater associated with the phase change element 2a (not shown here) so that the ... the phase change element 2a (not shown here) so that the selector element 2b is electrically connected to the heater associated with cell A designated current (hereinafter referred to as a "unit current") can selectively flow.

[0012] Each memory cell 2 , 2 ′ is coupled by means of a respective column decoding unit 5 to a respective bit line BL, BL′ (a so-called local bit line) selected for a storage operation, such as a read (or verify) operation.

[0013] In particular, the column decoding unit 5 includes a certain number of selector transistors 6 (e.g., PMOS transistors), which are connected in series (or cascade) between the corresponding local bit lines BL, BL' and the corresponding sensing main bit lines MBLs, MBLs', and receive corresponding selection signals at corresponding control terminals. Figure 1 In the figure, two selector transistors 6a, 6b are shown by way of example, which receive a first selection signal Y 0 and the second selection signal Y n : The first selector transistor 6a is connected between the local bit lines BL, BL' and the corresponding main bit lines MBL, MBL'; and the second selector transistor 6b is connected between the main bit lines MBL, MBL' and the corresponding sense main bit lines MBLs, MBLs'.

[0014] The sensing master bit lines MBLs, MBLs' associated with the memory cells 2, 2' are furthermore coupled to a sense amplifier (SA) stage 9, schematically shown, configured to compare the corresponding cell currents I at the end of reading (or verifying) the stored data. cell ,I cell’ .

[0015] In the sense amplifier stage 9, the bias transistor 7 (particularly an NMOS transistor) is connected between the above-mentioned sense main bit lines MBLs, MBLs' and the input block 9a. The input block 9a associated with the sense main bit lines MBLs, MBLs' is in turn coupled to the differential amplifier block 9b, which is configured to implement the above-mentioned comparison to read the stored data.

[0016] In particular, the bias transistor 7 receives a suitable bias voltage (the so-called cascode voltage V casc ) in order to impose a maximum allowed value on the voltage on the corresponding bit lines (sensing main bit lines MBLs, MBLs', main bit lines MBL, MBL' and local bit lines BL, BL'), thus preventing any stress and damage that may occur during reading of the stored data. In addition, the above-mentioned bias transistor 7 realizes appropriate capacitive decoupling between the corresponding sensing main bit lines MBLs, MBLs' and the input block 9a of the sense amplifier stage 9.

[0017] In a known manner, the above-mentioned cascode voltage V is required to be applied to the bit line during the read (or verify) operation. cascThe value of keeps the memory cell 2 in the on state during the entire read (or verify) operation. Regardless of the state (SET or RESET) of the memory cell 2 and the corresponding current, the bias voltage must ensure sufficient safety margin. casc The cells being read are guaranteed to operate within an optimal operating window, where the trade-off between read speed and discrimination of the stored data is met.

[0018] The voltage generating unit 8 is configured to generate a cascode voltage V to be applied during a read (or verify) operation. casc The appropriate value of the above.

[0019] Among the known solutions, Figure 2 As schematically shown in FIG. 1 , the voltage generating unit 8 has a voltage regulator architecture to generate a voltage regulator of appropriate value that depends only on the configuration current I conf The value of the cascode voltage V casc .

[0020] The voltage generating unit 8 includes an operational amplifier 10 having a voltage reference voltage V1 that receives a preset value (eg, generated by a bandgap voltage generator). r The non-inverting terminal and the cascode voltage V casc output terminals.

[0021] The voltage generating unit 8 further includes an NMOS transistor 11, which has characteristics corresponding to those of the bias transistor 7, and a control terminal thereof is connected to a transistor receiving the common source and common gate voltage V casc The output terminal of the operational amplifier 10 is coupled to receive the power supply voltage V dd The power line has a feedback voltage V fb between the internal nodes 12.

[0022] Internal node 12 is coupled to the inverting terminal of operational amplifier 10 so that due to the unity feedback gain of operational amplifier 10, the feedback voltage V fb Equal to the reference voltage V r Furthermore, a current generator 13 is coupled between the same internal node 12 and a reference terminal (eg, a ground terminal GND).

[0023] The current generator 13 generates the above configuration current I conf , whose value can be appropriately set so as to represent the distribution between the current associated with the SET state (circulating in the memory cell 2) and the current associated with the RESET state (in other words, the configuration current I confThe value of is between the lower-tail value of the SET current distribution and the upper-tail value of the RESET current distribution).

[0024] In this way, the voltage generating unit 8 operates to ensure that the required voltage value (substantially the same as the above-mentioned voltage reference V r correspond).

[0025] However, the applicant has realized that Figure 1 As shown in FIG. 1 , in the case where the selector element 2 b associated with the memory cell 2 is composed of a BJT, the above-mentioned voltage generating unit 8 has some limitations.

[0026] As mentioned above Figure 1 As shown in FIG. 1 , in this case phase change element 2a is coupled between the emitter terminal of the BJT of the corresponding selector element 2b (of pnp type in this example) and the corresponding local bit line BL. Furthermore, the base terminal of selector element 2b is electrically coupled to the corresponding word line WL.

[0027] In particular, the base terminals of the selector elements 2b of the memory cells 2 of the same row of the memory array are coupled to the same word line WL, and the phase change elements 2a of the memory cells 2 of the same column are coupled to the same local bit line BL. The collector element of the BJT of the selector element 2b is set at a reference voltage (e.g., a ground reference voltage GND).

[0028] The use of a selector element 2b of the BJT type specifically referred to in the present invention offers several advantages compared to MOSFET technology, such as a reduction in the overall area occupied by the memory cell 2 and a higher integration density of the resulting memory device.

[0029] However, the Applicant has realized that, in contrast to the use of MOSFETs, the use of selector elements of the BJT type requires due consideration of other characteristics of the base currents of the respective BJTs, which flow along the word line WL (selected for the memory operation) and which may thus cause an unwanted voltage drop along the same word line WL. In fact, due to the low gain factor (the so-called beta factor) of the BJTs, these base currents are quite high (e.g. 70% of the emitter current, i.e. the cell current I cell 70% of the total).

[0030] Figure 3 In this respect, the resistance (denoted by R) distributed along the metallization line associated with the word line WL is shown in a schematic manner. WL denoted by I), this resistor has a non-negligible value and due to the above-mentioned base current (here I B), a significant voltage drop may even occur on the same word line WL.

[0031] Figure 3 Furthermore, a part of a driver stage 15 coupled to the word line WL is shown, in particular a pull-down part which, in the example schematically represented by an NMOS pull-down transistor, is configured to couple the word line WL to a reference terminal, e.g. the ground terminal GND, when the same word line WL is selected for a read or verify operation (when not selected, the same word line WL is instead biased with a positive voltage of an appropriate value by means of a so-called pull-up part of the driver stage 15 (not shown here)).

[0032] In a manner not shown, the above-mentioned pull-down portion can generally be composed of a certain number of NMOS pull-down transistors (for example, four) connected in a cascade mode, each NMOS pull-down transistor receives a corresponding address signal and is collectively configured to implement a NAND logic combination of the corresponding address signal for selecting the corresponding word line WL.

[0033] The above base current I B A non-negligible voltage drop across the driver stage 15, in particular across the aforementioned NMOS pull-down transistor (or transistors), is therefore determined.

[0034] In addition, in the same Figure 3 The voltage drop between the base and emitter terminals of the BJT of selector element 2a is given by V BE Specifying; this voltage drop represents another element to be considered in order to obtain the desired value of the bit line voltage.

[0035] Likewise, it is necessary to consider the voltage drop across the same phase change element 2a of the memory cell 2 due to the current circulating along the bit line BL.

[0036] Basically, the applicant has recognized that, because known types (e.g. Figure 2 Voltage generating units of the type described in do not take into account the above-mentioned factors associated with the special properties of the BJT-type selector element 2b, and therefore they cannot achieve correct biasing of the bit lines, which may result in performance degradation (for example, in terms of execution speed) or even errors in reading or verification operations.

[0037] The object of the present invention is to provide a solution for the generation of a bit line voltage for a non-volatile memory device, in particular of the phase-change type, which will enable the disadvantages of the prior art to be overcome.

[0038] According to the present invention, there is provided a bit line voltage generating circuit and a corresponding method as defined in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] For a better understanding of the present invention, preferred embodiments of the present invention will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0040] Figure 1 is a schematic diagram of a portion of a nonvolatile memory device of a known type during a differential read operation;

[0041] Figure 2 Shows Figure 1 A circuit diagram of a voltage generating unit in a memory device;

[0042] Figure 3 yes Figure 1 A schematic diagram of a memory cell and associated word lines and bit lines in a memory device;

[0043] Figure 4 is a schematic block diagram of a memory device according to one aspect of the present solution;

[0044] Figure 5 The solution according to this Figure 4 A circuit diagram of a bit line voltage generating circuit in a device of; and

[0045] Figure 6 is included Figure 4 A simplified block diagram of the electronic system of a memory device. DETAILED DESCRIPTION

[0046] Figure 4 is a schematic depiction of a non-volatile memory device (particularly of the phase-change type), designated as a whole by 20, comprising a memory array 21, whose memory cells (not shown here) are coupled to respective word lines WL (arranged in rows) and respective bit lines (arranged in columns); in particular, the bit lines are arranged in the same manner as previously described with reference to Figure 1 A substantially similar approach is shown divided into main bit lines and local bit lines.

[0047] As schematically shown, the memory device 20 comprises a row decoder 24 and a column decoder 25, respectively configured to appropriately address and bias the word lines WL and local bit lines BL based on an input address Add each time they are selected for a memory operation, in particular a read and verify operation.

[0048] As previously referenced Figure 1 Discussed (reference Figure 1 ), the column decoder 25 comprises (for each local bit line BL) a certain number of selection transistors 6 (not shown here) (e.g., PMOS transistors), cascaded between the corresponding (local) bit line BL and the corresponding sensing main bit line MBLs, and receiving the corresponding selection signal (Y) at the corresponding control terminal 0 , Y n ).

[0049] The memory device 20 also includes a sense amplifier (SA) stage, designated herein by 29, selectively coupled to the sense master bit lines MBLs associated with the memory cells 2 via the column decoder 25 and configured to compare the corresponding cell currents I cell In order to enable differential reading (or verification) of the stored data.

[0050] In a manner not shown here (but previously with respect to Figure 1 ), the sense amplifier stage 29 comprises a bias transistor 7 (particularly an NMOS transistor), which is connected between each sense master bit line MBLs and an input block 9a of the same sense amplifier stage 29.

[0051] The voltage generating circuit 30 is operatively coupled to the sense amplifier stage 29 and is configured to generate a cascode voltage V casc (in particular, for the control terminal of the above-mentioned bias transistor 7; see again the previous discussion and the above-mentioned Figure 1 ) in order to obtain the desired value for the voltage present on the bit line that is selected for the read (or verify) operation.

[0052] As will be described in detail below, according to aspects of the present solution, the voltage generating circuit 30 is configured to generate the above-mentioned cascode voltage V casc , taking into account factors associated with the properties of the BJT-type selector element 2b of the memory cell 2, thereby enabling the bit line to be correctly biased and preventing errors in memory operations, particularly read (or verify) operations.

[0053] In detail, now refer to Figure 5 The voltage generating circuit 30 includes a reference generating stage 32 configured to generate a reference voltage V having an appropriate value. ref (as will be described in detail, is a function of the above factors associated with the properties of the BJT type selector element 2b), from the voltage reference V r Start with voltage reference V r It is generated by a voltage generator, for example of the bandgap type (not shown here), and therefore has a stable and precise value regardless of variations in the supply voltage and temperature and regardless of process diffusion.

[0054] The voltage generating circuit 30 is provided with an output stage 34, including an operational amplifier 40, which receives the reference voltage V ref The non-inverting terminal of the first internal node 41 is connected to the inverting terminal of the first internal node 41, and a feedback voltage V is present on the inverting terminal. fb , and provide a common source and common gate voltage Vcasc The output terminal, the cascode voltage V casc The sense amplifier stage 29 to be sent to the memory device 20, in particular the control terminal of the NMOS type bias transistor 7 connected to the corresponding sense master bit lines MBLs.

[0055] The output stage 34 also comprises an output transistor 42 of NMOS type having characteristics corresponding to those of the bias transistor 7, the control terminal of which is connected to a transistor receiving the above-mentioned cascode voltage V casc The output terminal of the operational amplifier 40 is coupled to receive the power supply voltage V dd between the power line and the second internal node 43.

[0056] The second internal node 43 is coupled to the first internal node 41 via a first emulation block 45 configured to emulate the column decoder 25. Therefore, the first emulation block 45 comprises a certain number of emulation transistors 46 (in particular PMOS transistors) which are cascaded between the second internal node 43 and the first internal node 41 and whose corresponding control terminals are connected to the ground terminal GND in this case (so as to be always in the on state).

[0057] pass Figure 5 The example in FIG. 4 shows two dummy transistors 46a, 46b connected in series between the second internal node 43 and the first internal node 41 (thus designed to dummy selection transistors 6a, 6b, which receive the first selection signal Y of the column decoder 25). 0 and the second selection signal Y n ).

[0058] The output stage 34 further includes a current generator 47 coupled between the first internal node 41 and a reference terminal (particularly a ground terminal GND). The current generator 47 is configured to generate a column current I col , column current I col The value of represents the distribution between the current associated with the SET state (circulating in the memory cell 2) and the current associated with the RESET state (in other words, the column current I col The value of is between the lower tail value of the SET current distribution and the upper tail value of the RESET current distribution and may be equal to 8 μA, for example).

[0059] Therefore, due to the unity feedback gain of the operational amplifier 40, the first internal node 41 connected to the inverting terminal of the operational amplifier 40 has a voltage which is equal to the reference voltage V ref equal voltage value, and due to the column current I col :V MBL =V ref +Vdrop , so the second internal node 43 has the same voltage as the reference voltage V ref The voltage drop V drop The sum of the voltages V MBL .

[0060] From the above Figure 5 It is obvious from the inspection that the voltage V MBL has a value corresponding to a desired voltage set on the sensing main bit line MBLs selected for a memory operation (particularly a read (or verify) operation), and the reference voltage V ref Corresponds to the voltage on the corresponding local bit line BL.

[0061] In more detail, the reference generation stage 32 has a voltage reference V generated by a voltage generator (eg, a bandgap type) designed to receive the reference voltage V r The input IN is designed to provide a reference voltage V ref The output OUT.

[0062] The reference generation stage 32 includes an input operational amplifier 50 having a voltage reference voltage connected to the input IN and receiving a voltage reference voltage V r A non-inverting terminal of the first current mirror 52 is connected to the non-inverting terminal of the third internal node 51 and to the output terminal of the first current mirror 52.

[0063] The resistor block 53 is connected between the third internal node 51 and the ground terminal GND. In particular, the resistor block 53 is composed of a series of resistors having the same resistance value R x The first current I 1 flows in the resistor block 53 (ie, in the series resistors described above), and has a value of I in the example. 1 =V r / (10·R x ).

[0064] The first current mirror 52 includes a first mirror transistor 52a (PMOS type) connected between the third internal node 51 and the power supply voltage V dd The control terminal of the second mirror transistor 52b is connected to the output terminal of the input operational amplifier 50; the second mirror transistor 52b (also of PMOS type) is coupled to the first mirror transistor 52a with a mirror ratio N / 2 (wherein the value of N can be configured between 6 and 14 in unit steps, for example), and is connected between the output OUT and the power supply voltage V ddand a third mirror transistor 52c (also of PMOS type), coupled to the first mirror transistor 52a with the same mirror ratio N / 2, connected between the fourth internal node 54 and the power supply voltage V dd Between terminals set at, and its control terminal is connected to the same output terminal of the input operational amplifier 50.

[0065] With the help of the current mirror of the first current mirror 52, the second mirror transistor 52b and the third mirror transistor 52c provide a second current I at the output OUT and the fourth internal node 54, respectively. 2 , the second current I 2 With respect to the first current I 1 is mirrored and has a value equal to I 1 N / 2.

[0066] The reference generation stage 32 also includes a second emulation block 55 configured to emulate the phase change element 2a of the memory cell 2. The second emulation block 55 is provided by an emulation resistor 56, which is manufactured so as to match the resistor 53a of the resistor block 53 and, in particular, has the same resistance value R x (In an obvious manner, the emulated resistor 56 can be physically manufactured at the resistor block 53 and with the same manufacturing technology in order to achieve a minimal spread between the corresponding resistance values).

[0067] Specifically, the emulation resistor 56 is connected between the output OUT and the fifth internal node 58 and is driven by the second current I 2 Cross in order to determine the R x I 1 N / 2 equal voltage drop V RES .

[0068] The reference generation stage 32 also includes a second current mirror 62 with a unity mirror ratio, which is coupled to the above-mentioned fifth internal node 58 and the above-mentioned fourth internal node 54 and includes: a corresponding first mirror transistor 62a (NMOS type) connected between the fourth internal node 54 and the ground terminal GND in a diode configuration; and a corresponding second mirror transistor 62b (also NMOS type) connected between the fifth internal node 58 and the ground terminal GND and whose control terminal is connected to the control terminal of the corresponding first mirror transistor 62a.

[0069] In particular, due to the current mirroring of the second current mirror 62, the corresponding second mirror transistor 62b extracts the entire second current I flowing through the second emulation block 55 (ie, flowing through the emulation resistor 56) from the fifth internal node 58. 2 .

[0070] The reference generation stage 32 also includes a third emulation block 65 coupled to the aforementioned fifth internal node 58 .

[0071] The third simulation block 65 is configured to simulate the word line WL of the memory array 21 and the corresponding memory cell 2 associated with the word line WL, in particular with respect to the base current I due to the BJT type selector element 2b associated with the same memory cell 2. B The voltage drop caused by the current circulation (as discussed earlier).

[0072] The third simulation block 65 includes: a metallization line 66, referred to as "dummy", configured to simulate the resistance effect of the word line WL; and a first cell current generator 68a, a second cell current generator 68b and a third cell current generator 68c, configured to simulate the injection of a cell current I through the corresponding memory cell. cell And are coupled to the metallization line 66 at the initial end, the central intermediate point and the final end respectively.

[0073] In particular, the cell current I cell The value of represents the current of the memory cell in the SET state (programmed state) and is therefore higher than the above column current I col , for example equal to 22μA.

[0074] The third simulation block 65 also includes a first selector transistor 69a, a second selector transistor 69b and a third selector transistor 69c (in particular, bipolar transistors, configured to simulate the selector element 2b of the memory cell 2), which are respectively connected to the first unit current generator 68a, the second unit current generator 68b and the third unit current generator 68c, and the ground terminal GND, and their base terminals are respectively connected to the initial end, the center midpoint and the final end of the metallization line 66.

[0075] In particular, the emitter of the second selector transistor 69 b , whose base terminal is connected to the central midpoint of the metallization line 66 , is connected to the fifth internal node 58 mentioned above.

[0076] It should be noted that there are a large number of memory cells 2 (associated with the selected local bit line BL) on the real word line WL of the memory array 21, for example, 37, and there are only three cell current generators 68a, 68b, 68c (each emulating the cell current I of a single memory cell 2). cell ) is coupled to metallization line 66.

[0077] To this end, the appropriate length of metallization line 66 is chosen so as to have a resistance so as to induce a voltage drop that will properly emulate the actual voltage drop on word line WL and, in particular, represent the average value of the word line voltage distribution during a read (or verify) operation.

[0078] Advantageously (also to reduce area occupation), the total length of metallization line 66 is approximately half the length of word line WL and furthermore is folded multiple times in a serpentine manner.

[0079] It should also be noted that the point of acquisition of the voltage drop, namely at the emitter of the second selector transistor 69 b connected to the central midpoint of the metallization line 66 , effectively enables the voltage drop of the average value to be obtained from the voltage drop available on the same metallization line 66 .

[0080] The reference generation stage 32 further includes a fourth emulation block 70 coupled to the aforementioned initial end of the metallization line 66 .

[0081] The fourth simulation block 70 is configured to simulate the pull-down portion of the driver stage 15 coupled to the word line WL, particularly with respect to the voltage drop due to the current circulating in the same word line WL (as previously discussed).

[0082] The fourth simulation block 70, such as Figure 5 As shown again schematically in FIG. 1 , the circuit thus comprises a certain number of NMOS type pull-down transistors 71 (four in the example shown), which are connected in series between the above-mentioned initial end of the metallization line 66 and the ground terminal GND, and the corresponding control terminals are coupled to the power supply voltage V dd The circuit set at the position ensures that the NMOS pull-down transistor 71 will always be in the ON (activated or conductive) state.

[0083] In particular, a fourth simulation block 70 is provided in order to determine a voltage drop that will appropriately simulate the actual voltage drop across the pull-down portion of the driver stage 15 .

[0084] To this end, in order to account for the lower current on metallization line 66 compared to the current on word line WL of memory array 21, NMOS pull-down transistor 71 is fabricated to have a higher resistivity than the corresponding pull-down transistor of driver stage 15, for example, four times higher.

[0085] To this end, the NMOS pull-down transistor 71 may be provided with a smaller channel width W, for example equal to one quarter compared to the channel width of the corresponding pull-down transistor of the driver stage 15 (advantageously also obtaining a reduced size of the fourth dummy block 70 ).

[0086] Based on the foregoing description, it is obvious that the reference voltage V at the output OUT of the reference generation stage 32 isref It can be expressed as the sum of the following effects: the voltage drop on the fourth simulation block 70 (i.e., the cascade of the NMOS pull-down transistor 71), represented by V pd specifies; the voltage drop on metallization line 66, given by V WL The voltage drop between the base and emitter of the second selector transistor 69b is specified by V BE and the voltage drop on the second simulation block 55 (ie, the voltage drop on the simulation resistor 56), as described above, by V RES specified.

[0087] Therefore, the reference voltage V ref It can be expressed as: V ref =V pd +V WL +V BE +V RES .

[0088] In particular, the sum of the above effects (V pd +V WL +V BE ) represents the voltage on the emitter of the second selector transistor 69b, V E is specified, and therefore depends only on the cell current I cell As previously discussed, due to the current mirroring operation performed by the first current mirror 52 and the second current mirror 62, the effect V RES It depends only on the second current I flowing through the simulation resistor 56 2 , the effect V RES Equal to (V r / 10)·N / 2, (It should be noted that this voltage does not depend on the resistance value R x ).

[0089] In other words, the reference voltage V ref is the sum of two macroscopic effects, the first of which is the emitter voltage V mentioned above. E , and the second is the voltage V on the above-mentioned simulated resistor 56 RES , they are completely independent of each other and have no influence on each other, so they can be controlled separately and independently to generate the above reference voltage V ref (In particular, the unit current I cell The second current I 2 function, that is, the voltage reference V r and the mirror factor N / 2).

[0090] As mentioned above, in addition to defining the reference voltage V refIn addition to the above-mentioned role, another role is added (outside the reference generation stage 32) to limit the common source and common gate voltage V casc The bit line voltage generated, that is, the voltage drop V on the simulation transistor 46 of the first simulation block 45 drop .

[0091] It should be noted that another effect (caused by the voltage drop V drop represents), depends only on the column current I col , is completely independent of and unaffected by other effects (the emitter voltage V E and the voltage V on the above-mentioned simulated resistor 56 RES ) and can therefore be controlled individually and independently (particularly via the column current I col of limitations).

[0092] The above description clearly shows the advantages of the present solution.

[0093] In any case, it is re-emphasized that during memory operation (particularly during a read (or verify) operation), the voltage generation circuit 30 generates the cascode voltage V for defining the bit line voltage. casc , taking into account all important factors associated with the properties of the BJT selector element 2b of the memory cell 2 (in particular associated with the corresponding base current IB), so as to achieve correct biasing of the bit line and prevent any degradation or errors in performance in memory operations (in particular in read (or verify) operations).

[0094] The voltage generating circuit 30 described above notably allows taking into account the voltage drop across the driver stage 15 of the word line WL, the voltage drop across the same word line WL, the voltage drop across the selector element 2 b of the memory cell 2 and furthermore the voltage drop across the phase change element 2 a of the same memory cell 2 .

[0095] Advantageously, the functions that determine the bit line voltage can be individually and independently controlled and configured (since they have no effect on each other).

[0096] Therefore, the above-mentioned features make it particularly advantageous to use the memory device 1 in an electronic system 80, such as Figure 6 It is schematically shown in FIG.

[0097] Electronic system 80 may be used in electronic devices such as: a PDA (personal digital assistant); a portable or fixed computer, possibly with wireless data transmission capabilities; a mobile phone; a digital audio player; a camera or camcorder; or another portable device capable of processing, storing, sending and receiving information.

[0098] The electronic system 80 includes a memory device 20 provided with a memory array 21 (not shown herein) of the previously described phase change type memory cells 2 and a controller 81 (e.g., provided with a microprocessor, DSP, or microcontroller), both of which are coupled to a bus 86 designed to route signals (e.g., for address selection) to the memory device 20.

[0099] In addition, the electronic system 80 may optionally include one or more of the following devices coupled to the bus 86: an input / output device 82 (e.g., provided with a keyboard and a display) for inputting and displaying data; a wireless interface 84 (e.g., an antenna) for sending and receiving data via a radio frequency wireless communication network; RAM 85; a battery 87, which can be used as a power source in the electronic system 80; and a photographic and / or camcorder 88.

[0100] According to various embodiments, controller 81 may be coupled to memory device 20 via a dedicated connection distinct from, and possibly in addition to, bus 86 (which may or may not be present).

[0101] Finally, it will be apparent that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

[0102] In particular, although what has been described is advantageously applicable to non-volatile memory devices of the PCM type, the same solution may also be applicable to other different non-volatile memory devices, where the state of a memory cell is associated with a current circulating therein.

[0103] Furthermore, the phase change element of the memory cell may generally be replaced by a general purpose variable resistance element provided via any available (even if not phase change type) technology.

Claims

1. A voltage generation circuit for a non-volatile memory device, the non-volatile memory device comprising a memory array having a plurality of memory cells coupled to respective word lines and local bit lines, each memory cell comprising a storage element and a selector element, the selector element comprising a bipolar transistor coupled to the storage element and configured to selectively enable a cell current to flow during a read or verify operation, wherein a base terminal of the selector element is coupled to the respective word line, wherein a sense amplifier stage is associated with the local bit line via a column decoder, wherein the sense amplifier stage comprises a respective bias transistor at an input of the sense amplifier stage, the respective bias transistors each having a control terminal, and wherein a driver stage is coupled to each word line to bias the word line during the read or verify operation, wherein the voltage generation circuit is configured to: A cascode voltage is generated for the control terminal of the bias transistor based on a reference voltage that is a function of an emulation of respective voltage drops across the driver stage, on the word line, and across the memory cell due to current associated with the corresponding selector element.

2. The circuit according to claim 1, include: a reference generation stage configured to generate at an output said reference voltage starting from a voltage reference received at an input; as well as an output stage configured to generate the cascode voltage based on the reference voltage; Wherein, the output stage comprises: an operational amplifier having a non-inverting terminal receiving the reference voltage from the reference generating stage, an inverting terminal connected to a first internal node, and an output terminal providing the cascode voltage; an output transistor having a control terminal connected to the output terminal of the operational amplifier receiving the cascode voltage and coupled between a power supply line and the first internal node; and A current generator is coupled to the first internal node and is configured to generate a column current having a value representative of an intermediate value of a current circulating in the memory cell.

3. The circuit of claim 2, wherein the reference generation stage include: A first emulation block couples the output transistor to the first internal node and is configured to emulate the column decoder with respect to a first voltage drop due to the column current.

4. The circuit according to claim 3, wherein the first simulation block includes a plurality of PMOS type simulation transistors, the plurality of PMOS type simulation transistors are cascaded between the output transistor and the first internal node, and the plurality of PMOS type simulation transistors have corresponding control terminals connected to a ground terminal so as to be in an on state.

5. The circuit of claim 3, wherein the reference generation stage include: a second simulation block configured to simulate a phase change element of the memory cell with respect to a corresponding second voltage drop; a third simulation block configured to simulate the word line of the memory array and the memory cells associated with the word line with respect to a corresponding third voltage drop; as well as a fourth simulation block configured to simulate the driver stage relative to a corresponding fourth voltage drop; The reference generation stage is configured such that, for the generation of the reference voltage, the effect of the second voltage drop is individually and independently controllable relative to the effects of the third voltage drop and the fourth voltage drop.

6. The circuit of claim 5 , wherein the second emulation block comprises an emulation resistor coupled between the output and an internal node, connected to the third emulation block, and designed to receive a mirror current from the first current mirror. ； The first current mirror has a mirror branch, a first mirror branch, and a second mirror branch, the mirror branch generates a mirror current based on the voltage reference, the first mirror branch is connected to the output and the emulation resistor and provides the mirror current based on a mirror ratio with respect to the mirror current, and the second mirror branch is connected to another internal node; as well as The reference generation stage further includes a second current mirror having a unity mirror ratio, the second current mirror being coupled between the internal node and the other internal node and being configured to extract a current from the internal node that is equal to the mirror current flowing through the emulation resistor.

7. The circuit of claim 6, wherein the reference generation stage further comprises include: a resistor block formed of a plurality of resistors having the same resistance and the voltage reference being present across the resistor block; The mirror current is a current circulating in the resistor block, wherein the emulation resistor is matched with the resistor, and the emulation resistor has substantially the same resistance as the resistor.

8. The circuit according to claim 5, wherein the third simulation block include: a metallization line configured to emulate the word line with respect to a relative voltage drop; A first unit current generator, a second unit current generator, and a third unit current generator are configured to simulate injection of a unit current on the metallization line, and the first unit current generator, the second unit current generator, and the third unit current generator are coupled to the metallization line at an initial end, a central intermediate point, and a final end, respectively; as well as The bipolar first selector transistor, the second selector transistor and the third selector transistor are configured to simulate the selector elements of the corresponding memory cells, and the bipolar first selector transistor, the second selector transistor and the third selector transistor are respectively connected between the first unit current generator, the second unit current generator and the third unit current generator and the ground terminal, and the base terminals of the bipolar first selector transistor, the second selector transistor and the third selector transistor are respectively connected to the initial end, the center midpoint and the final end of the metallization line, wherein the emitter terminal of the second selector transistor is connected to the second simulation block.

9. The circuit of claim 8, wherein the cell current has a value that represents a current of a memory cell in a programmed state and is greater than the column current.

10. The circuit of claim 8, wherein the metallization line has a total length of approximately half the length of the word line and is folded multiple times in a serpentine fashion.

11. The circuit of claim 8 , wherein the fourth simulation block comprises a plurality of NMOS type pull-down transistors connected in series between the initial end of the metallization line and a ground terminal, and the plurality of NMOS type pull-down transistors have corresponding control terminals coupled to the power line to be in an on state.

12. A circuit according to claim 8, wherein the reference voltage is given by the sum of the second voltage drop on the second simulation block, the third voltage drop on the third simulation block, and the fourth voltage drop on the fourth simulation block; and the third voltage drop is given by the sum of the voltage drop on the metallization line and the voltage drop between the base terminal and the emitter terminal of the second selector transistor.

13. The circuit of claim 1, wherein the memory cell is a phase change memory cell.

14. An electronic device, include: Non-volatile memory devices, including: a memory array having a plurality of memory cells coupled to respective word lines and local bit lines, each memory cell comprising a storage element and a selector element, each selector element comprising a bipolar transistor coupled to the storage element and configured to selectively enable a cell current to flow during a read or verify operation, wherein a base terminal of the selector element is coupled to the respective word line, wherein a bias transistor has a control terminal associated with each local bit line via a column decoder, and wherein a driver stage is coupled to one end of each word line for biasing the word line during the read or verify operation; A voltage generating circuit is configured to generate a cascode voltage for a control terminal of the bias transistor based on a reference voltage, wherein the reference voltage is a function of an emulation of corresponding voltage drops across the driver stage, on the word line, and across the memory cell due to current associated with the corresponding selector element.

15. The electronic device according to claim 14, further comprising: include: A controller is coupled to the non-volatile memory device.

16. The electronic device of claim 14, wherein the memory cell is a phase change memory cell.

17. A method of voltage generation for a non-volatile memory device, the non-volatile memory device comprising a memory array having a plurality of memory cells coupled to respective word lines and local bit lines, each memory cell comprising a storage element and a selector element, the selector element comprising a bipolar transistor coupled to the storage element and configured to selectively enable a cell current to flow during a read or verify operation, a base terminal of the selector element coupled to the respective word line, a bias transistor having a control terminal associated with each local bit line via a column decoder, and a driver stage coupled to one end of each word line for biasing the word line during the read or verify operation, the method include: A cascode voltage is generated for the control terminal based on a reference voltage that is a function of an emulation of voltage drops across the driver stage, across the word line, and across the memory cell due to current associated with the corresponding selector element.

18. The method of claim 17, wherein generating a cascode voltage include: For said generation of said reference voltage, the action of a voltage drop across a simulation block is individually and independently controlled, said simulation block being configured to simulate a phase change element of said memory cell relative to the action of another simulation block, said other simulation block being configured to respectively simulate said word lines of said memory array and memory cells associated with said word lines, and said driver stage.

19. The method of claim 18, wherein generating the cascode voltage further comprises: include: The column decoder is simulated relative to a corresponding voltage drop due to a column current having a value representative of an intermediate value of a current circulating in the memory cell.

20. The method of claim 17, wherein the memory cell is a phase change memory cell.

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