Semiconductor device

Abstract

A semiconductor device includes a substrate, a shallow trench isolation, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation is arranged in the substrate and comprises a first insulating layer higher than the surface of the substrate and a second insulating layer lower than the surface of the substrate. The bit line structure is arranged on the substrate and at least comprises a conductive layer. At least one bit line structure crosses the active region and the first insulating layer and the second insulating layer of the shallow trench isolation, and is respectively provided with a first insulating stack structure, a second insulating stack structure and a third insulating stack structure. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces coplanar with each other and different stack materials. Therefore, the assembly efficiency of the bit line structure is improved, and the operation performance of the semiconductor device is optimized.

Description

Technical Field

[0001] This application relates to a semiconductor device, in particular to a semiconductor device with a bitline structure. Background Art

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitive structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is formed by aggregating a large number of memory cells to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the memory cell density in the array region must be continuously increased, resulting in an increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technologies or structures need to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the Utility Model

[0003] One object of this application is to provide a semiconductor device. By providing an insulating stack structure with the same top surface height and different stacked materials on the conductive layer of the bitline structure, different insulating effects can be achieved in the corresponding extension regions of the bitline structure. Thus, the semiconductor device of this application has a more optimized component structure and performance, thereby improving the operation performance of the semiconductor device.

[0004] To achieve the above object, an embodiment of the present application provides a semiconductor device, including a substrate, shallow trench isolation, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation is disposed in the substrate and includes a first insulating layer higher than the surface of the substrate and a second insulating layer lower than the surface of the substrate, and the second insulating layer is located on the first insulating layer. The bit line structures are disposed on the substrate, extend in a first direction and are arranged in a second direction perpendicular to the first direction, and each of the bit line structures at least includes a conductive layer disposed on the substrate. Wherein, at least one of the bit line structures spans the active region, and the first insulating layer and the second insulating layer of the shallow trench isolation in the first direction. The at least one bit line structure has a first insulating stack structure, a second insulating stack structure, and a third insulating stack structure on the active region, and the first insulating layer and the second insulating layer of the shallow trench isolation, respectively. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces in the same horizontal plane and different stack materials.

[0005] To achieve the above object, another embodiment of the present application provides a method for manufacturing a semiconductor device, including the following steps. Provide a substrate, the substrate including a plurality of active regions. Form shallow trench isolation in the substrate, the shallow trench isolation including a first insulating layer higher than the surface of the substrate and a second insulating layer lower than the surface of the substrate, and the second insulating layer is located on the first insulating layer. Form a plurality of bit line structures on the substrate, the bit line structures extending in a first direction and arranged in a second direction perpendicular to the first direction, and each of the bit line structures at least includes a conductive layer disposed on the substrate. Wherein, at least one of the bit line structures spans the active region, and the first insulating layer and the second insulating layer of the shallow trench isolation in the first direction. The at least one bit line structure has a first insulating stack structure, a second insulating stack structure, and a third insulating stack structure on the active region, and the first insulating layer and the second insulating layer of the shallow trench isolation, respectively. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces in the same horizontal plane and different stack materials.

[0006] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by the technical features of these technical solutions, the other technical problems that can be solved by the semiconductor device provided by the embodiments of the present application, the other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. Description of the Drawings

[0007] The accompanying drawings provide a deeper understanding of the embodiments of the present application and are incorporated herein as a part of this specification. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all the drawings are schematic diagrams, adjusted in relative dimensions and proportions for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

[0008] Figure 1 A top view schematic diagram of the semiconductor device provided by the embodiment of the present application;

[0009] Figure 2 is Figure 1 A cross-sectional schematic diagram taken along the section lines A-A' and B-B' in

[0010] Figure 3 is Figure 1 A cross-sectional schematic diagram taken along the section line C-C' in

[0011] Figure 4 is Figure 1 A cross-sectional schematic diagram taken along the section line D-D' in

[0012] Figure 5 is Figure 1 A cross-sectional schematic diagram taken along the section line E-E' in

[0013] Figure 6 A cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present application after forming the spacer layer;

[0014] Figure 7 A cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present application after forming the first capping material layer;

[0015] Figure 8 A cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present application after performing the first planarization process;

[0016] Figure 9 A cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present application after forming the second capping material layer.

[0017] Among them, the reference signs are explained as follows:

[0018] 10 Semiconductor device

[0019] 100 Substrate

[0020] 100A Cell region

[0021] 100B Peripheral region

[0022] 100s Surface

[0023] 102 Shallow Trench Isolation

[0024] 104 Third Insulating Layer

[0025] 104t Top Surface

[0026] 106 First Insulating Layer

[0027] 106t Top Surface

[0028] 108 Second Insulating Layer

[0029] 108t Top Surface

[0030] 110 Active Region

[0031] 114 Insulating Layer

[0032] 116 Semiconductor Layer

[0033] 118 Metal Layer

[0034] 120 Conductive Layer

[0035] 122 First Capping Layer

[0036] 124 Spacer Layer

[0037] 126 Barrier Layer

[0038] 128 Oxide Layer

[0039] 130 Second Capping Layer

[0040] 140 Bit Line Structure

[0041] 140c Bit Line Plug

[0042] 140t Top Surface

[0043] 142 Second Insulating Stack Structure

[0044] 144 Third Insulating Stack Structure

[0045] 146 Fourth Insulating Stack Structure

[0046] 148 First Insulating Stack Structure

[0047] 214 Gate Dielectric Layer

[0048] 216 Doped Region

[0049] 220 Conductive Layer

[0050] 222 Capping Layer

[0051] 224 Spacer Layer

[0052] 226 First covering layer

[0053] 228 Second covering layer

[0054] 230 Third covering layer

[0055] 230t Flat top surface

[0056] 240 Gate structure

[0057] 326 Barrier material layer

[0058] 328 Oxide material layer

[0059] 330 Second covering material layer

[0060] t1, t2, t3, t4, t5 Topmost surface

[0061] t4 Top surface

[0062] t5 Concave top surface Detailed implementation manners

[0063] To enable those of ordinary skill in the art to which this application pertains to further understand this application, the following particularly lists the preferred embodiments of this application and, in conjunction with the accompanying drawings, details the composition and intended effects of this application. It should be noted that, without departing from the spirit of this application, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments.

[0064] Please refer to Figure 1 and Figure 5 as shown, what is illustrated is a schematic diagram of a semiconductor device 10 according to the first embodiment of this application. First, as Figure 1 and Figure 2As shown, the semiconductor device 10 includes a substrate 100, a shallow trench isolation 102, and a plurality of bit line structures 140. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc. The substrate 100 includes both a cell region 100A with a relatively high component integration density and a peripheral region 100B with a relatively low component integration density. The cell region 100A and the peripheral region 100B are, for example, adjacent to each other, but this is not limiting. The shallow trench isolation 102 is further disposed within the substrate 100 to define a plurality of active regions 110 extending in the same direction D1 on the substrate 100. The shallow trench isolation 102 includes a composite structure, for example, including a third insulating layer 104, a first insulating layer 106, and a second insulating layer 108 arranged in sequence. Among them, the top surface 106t of the first insulating layer 106 is higher than the surface 100s of the substrate 100, and the top surfaces 104t, 108t of the third insulating layer 104 and the second insulating layer 108, while the top surfaces 104t, 108t of the third insulating layer 104 and the second insulating layer 108 are lower than the surface 100s of the substrate 100, and the top surface 104t of the third insulating layer 104 is higher than the top surface 108t of the second insulating layer 108, but this is not limiting. The bit line structure 140 is disposed on the substrate 100 and specifically includes a conductive layer 120 and an insulating stack structure arranged in sequence on the substrate 100. The conductive layer 120 of each bit line structure 140 extends within the cell region 100A along the first direction D2 and is arranged in parallel in the second direction D3 perpendicular to the first direction D2, and can simultaneously span the active region 110 and the shallow trench isolation 102 of the substrate 100. Thus, those skilled in the art can easily understand the bit line structure 140 as a strip-shaped structure extending in the first direction D2 and arranged in the second direction D3, and in this embodiment Figure 1 The illustration of the insulating stack layers (such as the second capping layer 130, the second cover layer 228, etc.) disposed above is omitted to clearly present the strip-shaped structure.

[0065] It should be noted that, for another example Figure 1 and Figure 2As shown, each bit line structure 140 straddles the active region 110 and the shallow trench isolation 102 of the substrate 100 at the same time, so that the conductive layer 120 and the insulating stack layer above it conformally cover the third insulating layer 104, the first insulating layer 106 and the second insulating layer 108 of the active region 110 and the shallow trench isolation 102. The portions of the bit line structure 140 on the first insulating layer 106 and the second insulating layer 108 of the active region 110 and the shallow trench isolation 102 respectively have different insulating stack structures. Among them, the portion of the bit line structure 140 located on the active region 110 has a first insulating stack structure 148, the portion of the bit line structure 140 located on the first insulating layer 106 has a second insulating stack structure 142, and the portion of the bit line structure 140 located on the second insulating layer 108 has a third insulating stack structure 144. As Figure 2 shown, the top surfaces of the first insulating stack structure 148, the second insulating stack structure 142 and the third insulating stack structure 144 are located on the same plane 140t, and include different numbers of stacked layers and stacked materials from each other. Thus, by providing different first insulating stack structures 148, second insulating stack structures 142 and third insulating stack structures 144 on the conductive layer 120, different insulating effects are achieved in the corresponding extended regions of the bit line structure 140. In this way, the semiconductor device of the present application can have a more optimized component structure and performance, thereby improving the operation performance of the semiconductor device.

[0066] As Figure 2 and Figure 3 shown, the conductive layer 120 further includes a semiconductor layer 116 (such as including semiconductor materials such as doped polysilicon and doped amorphous silicon), a barrier layer (not shown, such as including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), and a metal layer 118 (such as including low-resistance metal materials such as tungsten, aluminum or copper) sequentially arranged on the substrate 100 from bottom to top. Each bit line structure 140 is generally located on an insulating layer 114 (such as including an oxide-nitride-oxide structure stacked in sequence) provided above the substrate 100, and a part of the semiconductor layer 116 extends into the substrate 100 to form a bit line contact (BLC) 140c, so that each bit line structure 140 can be electrically connected to the active region 112 through the bit line plug 140c integrally formed therewith.

[0067] In detail, the first insulating stack structure 148 located on the active region 110 includes a first capping layer 122, a barrier layer 126, and a second capping layer 130 that are sequentially disposed on the conductive layer 120 from bottom to top. Among them, the sequentially disposed first capping layer 122, barrier layer 126, and second capping layer 130 are in physical contact with each other. In an embodiment, the first capping layer 122, barrier layer 126, and second capping layer 130 respectively include insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride, or a combination of the above insulating materials. Preferably, the first capping layer 122, barrier layer 126, and second capping layer 130 include different insulating materials, but this is not limited thereto. On the other hand, the third insulating stack structure 144 located on the second insulating layer 108 includes a first capping layer 122, a barrier layer 126, an oxide layer 128, and a second capping layer 130 that are sequentially disposed on the conductive layer 120 from bottom to top. In other words, an oxide layer 128 is additionally disposed between the barrier layer 126 and the second capping layer 130 in the third insulating stack structure 144. The oxide layer 128 includes an insulating material such as silicon oxide and is in physical contact with the second capping layer 130 disposed above and the barrier layer 126 disposed below.

[0068] As Figure 2 and Figure 4 shown, the second insulating stack structure 142 located on the first insulating layer 106 includes, for example, a first capping layer 122 and a second capping layer 130 that are sequentially disposed on the conductive layer 120 from bottom to top. That is to say, no barrier layer 126 is disposed between the first capping layer 122 and the second capping layer 130 in the second insulating stack structure 142, and they are in physical contact with each other. Among them, the top surface t1 of the first capping layer 122 in the first insulating stack structure 148 is higher than the top surface t3 of the first capping layer 122 in the third insulating stack structure 144 and lower than the top surface t2 of the first capping layer 122 in the second insulating stack structure 142, but this is not limited thereto.

[0069] As Figure 2 and Figure 5As shown, the end of each bit line structure 140 further has a fourth insulating stack structure 146. And, depending on the different extension regions of each bit line structure 140, the fourth insulating stack structure 146 can be selectively disposed on the active region 110 and / or the shallow trench isolation 102, and includes different stacked layers, and its top surface is also in the same plane 140t as the top surfaces of the first insulating stack structure 148, the second insulating stack structure 142, and the third insulating stack structure 144. Specifically, when the end of the bit line structure 140 straddles the active region 110, the fourth insulating stack structure 146 includes a spacer layer 124, a barrier layer 126, and a second capping layer 130 that are sequentially disposed on the conductive layer 120 from bottom to top. And, the spacer layer 124 in the fourth insulating stack structure 146 has a relatively high top surface t4. On the other hand, when the end of the bit line structure 140 straddles the shallow trench isolation 102, the fourth insulating stack structure 146 includes a spacer layer 124, a barrier layer 126, an oxide layer 128, and a second capping layer 130 that are sequentially disposed on the conductive layer 120 from bottom to top. And, the spacer layer 124 in the fourth insulating stack structure 146 has a relatively low recessed top surface t5, but is not limited thereto. In one embodiment, the spacer layer 124 includes, for example, insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, preferably including an insulating material different from the barrier layer 126, but is not limited thereto. And in another embodiment, the spacer layer 124 can also selectively include a composite layer structure, such as including a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer sequentially disposed on the sidewalls of each bit line structure 140, but is not limited thereto.

[0070] Again, Figure 1 and Figure 2As shown, the semiconductor device 10 further includes a gate structure 240 disposed on the substrate 100. Specifically, the gate structure 240 extends in the peripheral region 100B along the second direction D3 respectively and is arranged in the first direction D2, and can also span the active region 110 and the shallow trench isolation 102 of the substrate 100 at the same time. Each gate structure 240 specifically includes a gate dielectric layer 214, a conductive layer 220, a capping layer 222, and a spacer layer 224 disposed on the sidewalls of the gate dielectric layer 214, the conductive layer 220, and the capping layer 222 in sequence. Among them, the conductive layer 220 of the gate structure 240 also includes a semiconductor layer 116 (for example, including semiconductor materials such as doped polysilicon and doped amorphous silicon) disposed in sequence from bottom to top, a barrier layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), and a metal layer 118 (for example, including low-resistance metal materials such as tungsten, aluminum, or copper). In a preferred embodiment, the conductive layer 220 of the gate structure 240 includes, for example, the same material as the conductive layer 120 in the bit line structure 140, the capping layer 222 of the gate structure 240 includes, for example, the same material as the first capping layer 122 in the bit line structure 140, and the spacer layer 224 of the gate structure 240 includes, for example, the same material as the spacer layer 124 in the bit line structure 140, but not limited thereto.

[0071] Moreover, a first capping layer 226, a second capping layer 228, and a third capping layer 230 are sequentially disposed above the gate structure 240. The first capping layer 226 conformally covers the spacer layer 224, the gate structure 240, and the substrate 100. The second capping layer 228 covers the first capping layer 226 and is flush with the first capping layer 226 disposed directly above the gate structure 240. The third capping layer 230 integrally covers the second capping layer 228 and the first capping layer 226 and has a flat top surface 230t. Among them, the flat top surface 230t of the third capping layer 230 in the peripheral region 100B is preferably flush with the top surfaces (i.e., the plane 140t) of the first insulating stack structure 148, the second insulating stack structure 142, the third insulating stack structure 144, and the fourth insulating stack structure 146 in the cell region 100A, but not limited thereto. In an embodiment, the first capping layer 226, the second capping layer 228, and the third capping layer 230 include, for example, different insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, etc. And the first capping layer 226 in the peripheral region 100B includes, for example, the same material as the barrier layer 126 in the cell region 100A, the second capping layer 228 in the peripheral region 100B includes, for example, the same material as the oxide layer 128 in the cell region 100A, and the third capping layer 230 in the peripheral region 100B includes, for example, the same material as the second capping layer 130 in the cell region 100A, but not limited thereto.

[0072] Under this setting, the gate structure 240 located in the peripheral region 100B and the doped regions 216 in the substrate 100 on both sides thereof together form a transistor component, while the bit line structure 140 located in the cell region 100A can form a dynamic random access memory (DRAM) together with another transistor component (not shown), a capacitor (not shown), and a word line structure, both of which are also located in the cell region 100A, and receive voltage information from the substrate 100 through the bit line structure 140 and the word line structure. Moreover, since the bit line structure 140 has different insulating stack structures in different extended regions, different insulating effects can be achieved in the corresponding extended regions, thereby improving the operating performance of the dynamic random access memory.

[0073] For the semiconductor device according to this embodiment, an insulating stack structure with a flush top surface, including different stacked layers and stacked materials, is provided on the conductive layer of the bit line structure, so that the bit line structure can have different insulating stack structures in different regions, and different insulating effects can be achieved in the corresponding extended regions. Thus, the semiconductor device of this embodiment has a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0074] To enable those of ordinary skill in the art to which this application pertains to easily understand the semiconductor device 10 of this application, the manufacturing method of the semiconductor device 10 of this application will be further described below.

[0075] Please refer to Figures 6 to 9 As shown, it is a schematic diagram of the manufacturing method of the semiconductor device 10 in the preferred embodiment of this application. First, as Figure 6 shown, a substrate 100 is provided, and shallow trench isolation 102 is formed in the cell region 100A and the peripheral region 100B of the substrate 100, while the active regions 110 are simultaneously defined. In one embodiment, the formation of the shallow trench isolation 102 is, for example, to first form a plurality of trenches (not shown) in the substrate 100 by an etching process, and then sequentially form a third insulating layer 104, a first insulating layer 106, and a second insulating layer 108 in the trenches. Among them, the top surface 106t of the first insulating layer 106 is higher than the surface 100s of the substrate 100, and the top surfaces 104t, 108t of the third insulating layer 104 and the second insulating layer 108, while the top surfaces 104t, 108t of the third insulating layer 104 and the second insulating layer 108 are lower than the surface 100s of the substrate 100, and the top surface 104t of the third insulating layer 104 is higher than the top surface 108t of the second insulating layer 108, but this is not limited thereto.

[0076] Next, an insulating layer 114 is formed on the substrate 100, conformally covering the third insulating layer 104, the first insulating layer 106, and the second insulating layer 108 of the active region 110 and the shallow trench isolation 102. Then, after removing the insulating layer 114 in the peripheral region 100B, a conductive layer 120 and a first capping layer 122 of the bit line structure 140 are formed in the cell region 100A, and a gate structure 240 is formed in the peripheral region 100B. In one embodiment, the formation of the gate structure 240 can be integrated into the manufacturing process of the conductive layer 120 and the first capping layer 122, for example, including but not limited to the following steps. First, a plurality of openings penetrating the insulating layer 114 are formed in the cell region 100A through a mask layer (not shown). Then, a chemical vapor deposition (CVD) process is simultaneously performed in the cell region 100A and the peripheral region 100B to form a semiconductor material layer (not shown, such as doped silicon, doped phosphorus, or silicon phosphorus and other semiconductor materials) that fills the openings and integrally covers the substrate 100. Then, a barrier material layer (not shown, such as tantalum and / or tantalum nitride, titanium and / or titanium nitride, etc., conductive barrier materials), a metal material layer (not shown, such as aluminum, titanium, copper, or tungsten and other low-resistance metal materials), and a first covering material layer (not shown, such as silicon nitride, silicon carbonitride, or silicon oxynitride and other insulating materials) that also integrally cover the substrate 100 are sequentially deposited. It should be noted that due to the uneven top surface heights of the third insulating layer 104, the first insulating layer 106, and the second insulating layer 108 of the shallow trench isolation 102, the first covering material layer, the metal material layer, the barrier material layer, the semiconductor material layer, and the insulating layer 114 formed thereon correspondingly have uneven profiles, as Figure 6 shown.

[0077] After that, at least one lithography process is performed to pattern the first covering material layer and the underlying stacked conductive material layers (including the metal material layer, the barrier material layer, and the metal material layer), forming a conductive layer 120 extending along the first direction D2 and the first capping layer 122 thereon in the cell region 100A, and forming a gate structure 240 extending along the second direction D3 in the peripheral region 100B. In this way, the conductive layer 220 and the capping layer 222 of the gate structure 240 can preferably include the same materials as the conductive layer 120 and the first capping layer 122 of the bit line structure 140, but not limited thereto. Then, through the same process, a spacer layer 124 is formed on the sidewalls of the conductive layer 120 and the first capping layer 122 of the bit line structure 140, and a spacer layer 224 is formed on the sidewalls of the conductive layer 220 and the capping layer 222 of the gate structure 240. In one embodiment, the formation of the spacer layer 224 can also be integrated into the manufacturing process of the spacer layer 124 in the cell region 100A, such that the spacer layer 224 in the peripheral region 100B and the spacer layer 124 in the cell region 100A can include the same materials, but not limited thereto.

[0078] As Figure 7 shown, a chemical vapor deposition process is synchronously performed again within the cell region 100A and within the peripheral region 100B to sequentially form a barrier material layer 326 and an oxide material layer 328. Among them, the barrier material layer 326 also conformally covers the substrate 100 within the cell region 100A, the conductive layer 120 and the first capping layer 122 of the bit line structure 140, and the substrate 100 and the gate structure 240 within the peripheral region 100B, and also has a non-uniform profile. The oxide material layer 328 integrally covers the barrier material layer 326 and has a flat top surface. In one embodiment, the barrier material layer 326 includes, for example, insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, preferably including an insulating material different from the spacer layer 124 or the spacer layer 224, and the oxide material layer 328 includes, for example, insulating materials such as silicon oxide or silicon oxynitride, but is not limited thereto.

[0079] As Figure 8 shown, a first planarization process is performed to partially remove the oxide material layer 328 and simultaneously form an oxide layer 128 within the cell region 100A and a second capping layer 228 within the peripheral region 100B. It should be noted that when the first planarization process is performed, the barrier material layer 326 located above the gate structure 240 within the peripheral region 100B is used as a stop layer. Moreover, since the barrier material layer 326 within the cell region 100A has a non-uniform profile, when the first planarization process is performed, the barrier material layer 326 within the cell region 100A and a part of the first capping layer 122 below it are also removed, and a barrier layer 126 is formed within the cell region 100A and a first capping layer 226 is formed within the peripheral region 100B. That is to say, after the first planarization process is performed, the barrier material layer 326 covering the first insulating layer 106 of the shallow trench isolation 102 within the cell region 100A is removed, directly exposing the underlying first capping layer 122.

[0080] As Figure 9 shown, a chemical vapor deposition process is synchronously performed again within the cell region 100A and within the peripheral region 100B to form a second capping material layer 330, which integrally covers the barrier layer 126 and the oxide layer 128 within the cell region 100A and the second capping layer 228 within the peripheral region 100B and has a flat top surface. In one embodiment, the second capping material layer 330 includes, for example, insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride or a combination of the above insulating materials, preferably including an insulating material different from the oxide material layer 328, but is not limited thereto. Then, a second planarization process is performed to partially remove the second capping material layer 330 within the cell region 100A and within the peripheral region 100B, and then, as shown in Figure 2the second capping layer 130 shown, and a third capping layer 230 as shown is formed within the peripheral region 100B. Thus, the first capping layer 122, the barrier layer 126, and the second capping layer 130 that are sequentially stacked on the conductive layer 120 above the active region 110 within the cell region 100A form the first insulating stack structure 148 as shown Figure 2 whereas the first capping layer 122 and the second capping layer 130 that are sequentially stacked on the conductive layer 120 above the first insulating layer 106 of the shallow trench isolation 102 form the second insulating stack structure 142 as shown Figure 2 whereas the first capping layer 122, the barrier layer 126, the oxide layer 128, and the second capping layer 130 that are sequentially stacked on the conductive layer 120 above the second insulating layer 108 of the shallow trench isolation 102 form the third insulating stack structure 144 as shown Figure 2 whereas the spacer layer 124, the barrier layer 126, the oxide layer 128, and the second capping layer 130 that are sequentially stacked on the conductive layer 120 above the second insulating layer 108 of the shallow trench isolation 102 form the fourth insulating stack structure 146 and are located at the ends of the respective bit line structures 140. Thus, the fabrication of the semiconductor device 10 in this embodiment is completed. On the premise of process simplification, insulating stack structures with the same top surface height and different stacked materials can be formed above the conductive layer 120 of the bit line structure 140 to achieve different insulating effects in the corresponding extended regions Figure 2 According to the fabrication method of this embodiment, before fabricating the conductive layer of the bit line structure, a shallow trench isolation with uneven top surface heights is pre-formed, so that the conductive layer subsequently spanning the active region and the shallow trench isolation correspondingly has uneven contours. Under this operation, insulating stack structures with the same top surface height and different stacked materials can be formed on the conductive layer spanning both the active region and the shallow trench isolation, enabling the bit line structure to achieve different insulating effects in the corresponding extended regions. Thus, the fabrication method of this embodiment is conducive to forming a semiconductor device with more optimized structure and performance

[0081] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application

[0082] ​

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate including a plurality of active regions; Shallow trench isolation disposed in the substrate; the shallow trench isolation includes a first insulating layer above the surface of the substrate and a second insulating layer below the surface of the substrate, and the second insulating layer is located on the first insulating layer; And A plurality of bit line structures disposed on the substrate, the bit line structures extending in a first direction and arranged in a second direction perpendicular to the first direction, and each of the bit line structures at least includes a conductive layer disposed on the substrate; Wherein, at least one of the bit line structures spans the active region, the first insulating layer and the second insulating layer of the shallow trench isolation in the first direction, and the at least one bit line structure has a first insulating stack structure, a second insulating stack structure and a third insulating stack structure on the active region, the first insulating layer and the second insulating layer of the shallow trench isolation respectively, and the first insulating stack structure, the second insulating stack structure and the third insulating stack structure include top surfaces in the same horizontal plane and different stacking materials.

2. The semiconductor device according to claim 1, characterized in that, The second insulating stack structure includes a first capping layer and a second capping layer that are physically in contact with each other and are sequentially disposed on the conductive layer from bottom to top, and the third insulating stack structure includes the first capping layer, a barrier layer, an oxide layer and the second capping layer that are physically in contact with each other and are sequentially disposed on the conductive layer from bottom to top.

3. The semiconductor device according to claim 2, wherein, The topmost surface of the first capping layer of the second insulating stack structure is higher than the topmost surface of the first capping layer of the third insulating stack structure.

4. The semiconductor device according to claim 2, wherein, The first insulating stack structure includes the first capping layer, the barrier layer and the second capping layer that are physically in contact with each other and are sequentially disposed on the conductive layer from bottom to top.

5. The semiconductor device according to claim 2, wherein The topmost surface of the first capping layer of the first insulating stack structure is higher than the topmost surface of the first capping layer of the third insulating stack structure and lower than the topmost surface of the first capping layer of the second insulating stack structure.

6. The semiconductor device according to claim 2, wherein, The shallow trench isolation further includes a third insulating layer, the top surface of the third insulating layer is lower than the surface of the substrate and the top surface of the first insulating layer, the top surface of the third insulating layer is higher than the top surface of the second insulating layer, and the first insulating layer is located on the third insulating layer.

7. The semiconductor device according to claim 6, wherein At least one of the bit line structures further includes a fourth insulating stack structure disposed on the second insulating layer, wherein the fourth insulating stack structure includes a spacer layer, the barrier layer, the oxide layer and the second capping layer.

8. The semiconductor device according to claim 7, wherein The top surface of the fourth insulating stack structure, the top surface of the first insulating stack structure, the top surface of the second insulating stack structure and the top surface of the third insulating stack structure are in the same plane.

9. The semiconductor device according to claim 7, characterized in that, Further comprising: At least one gate structure disposed on the substrate, at least including another conductive layer and another spacer layer, and the another conductive layer of the at least one gate structure and the conductive layer of the at least one bit line structure include the same conductive material; A first capping layer disposed on the at least one gate structure; A second capping layer disposed on the first capping layer; And A third capping layer disposed on the second capping layer.

10. The semiconductor device according to claim 9, wherein, The first covering layer and the barrier layer are made of the same material, the second covering layer and the oxide layer are made of the same material, and the third covering layer and the second cover layer are made of the same material.

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