Non-volatile memory device

Abstract

A non-volatile memory device includes processing circuitry configured to apply a sub-voltage to a first word line, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the first word line, apply the sub-voltage to a second word line, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the second word line, apply the desired first read voltage to the first word line when simultaneously reading the first memory cells connected to the first word line, and apply the desired second read voltage to the second word line when simultaneously reading the second memory cells connected to the second word line, the desired second read voltage being different from the desired first read voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0009847, filed on January 28, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] At least one example embodiment relates to a non-volatile memory device. Background Technology

[0004] A memory device is a device capable of storing and retrieving data when needed and / or when necessary. Memory devices can be broadly classified into: non-volatile memory (NVM), which retains its stored data even when no power is supplied; and volatile memory (VM), which loses its stored data when no power is supplied.

[0005] The characteristics of such memory devices can change due to various reasons, such as the usage environment, the number of times they are used, and / or the duration of use. Therefore, the reliability of memory devices can be compromised. Consequently, methods to improve the reliability of memory devices have become mainstream. Summary of the Invention

[0006] Various aspects of the various example embodiments provide a non-volatile memory device with improved product reliability.

[0007] However, the aspects of the exemplary embodiments are not limited to those set forth herein. These and other aspects of the exemplary embodiments will become more apparent to those skilled in the art upon which the exemplary embodiments pertain, by referring to the following detailed description of the exemplary embodiments given.

[0008] According to an aspect of at least one example embodiment, there is provided a non-volatile memory device, including: a memory including a first memory group and a second memory group, the first memory group including a plurality of first word lines, and the second memory group including a plurality of second word lines different from the plurality of first word lines; and a processing circuitry configured to apply a sub-voltage to the plurality of first word lines simultaneously, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the plurality of first word lines sensed in response to the sub-voltage applied to the plurality of first word lines, apply a sub-voltage to the plurality of second word lines simultaneously, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the plurality of second word lines sensed in response to the sub-voltage applied to the plurality of second word lines, apply the desired first read voltage to the plurality of first word lines when reading the plurality of first memory cells connected to the plurality of first word lines, and apply the desired second read voltage to the plurality of second word lines when reading the plurality of second memory cells connected to the plurality of second word lines simultaneously, the desired second read voltage being different from the desired first read voltage.

[0009] According to an aspect of at least one example embodiment, there is provided a non-volatile memory device, including: a memory including a first memory group and a second memory group, the first memory group including a plurality of first word lines, and the second memory group including a plurality of second word lines different from the plurality of first word lines; and a processing circuitry configured to perform an erase operation by applying an erase voltage to the memory in response to receiving an erase command for the memory, and when performing an erase verify operation after the erase operation, apply a desired first read voltage to the plurality of first word lines, and apply a desired second read voltage to the plurality of second word lines, the desired second read voltage being different from the desired first read voltage.

[0010] According to another aspect of at least one example embodiment, there is provided a non-volatile memory device, comprising: a first memory chip comprising a first memory block and a first processing circuitry; and a second memory chip comprising a second memory block and a second processing circuitry, wherein the first memory block comprises a plurality of first memory cells and a plurality of first word lines connected to the plurality of first memory cells, the first processing circuitry is configured to perform a first erase operation by applying a first erase voltage to the first memory based on a first erase command for the first memory block, and to apply a desired first read voltage to the plurality of first word lines when performing a first erase verify operation after performing the first erase operation, the second memory block comprises a plurality of second memory cells and a plurality of second word lines connected to the plurality of second memory cells, and the second processing circuitry is configured to perform a second erase operation by applying a second erase voltage to the second memory block based on a second erase command for the second memory block, and to apply a desired second read voltage to the plurality of second word lines when performing a second erase verify operation after performing the second erase operation, and the desired first read voltage is different from the desired second read voltage. BRIEF DESCRIPTION OF DRAWINGS

[0011] These and / or other aspects will become apparent and more readily appreciated from the following description of the example embodiments, taken in conjunction with the accompanying drawings in which:

[0012] Figure 1 is a block diagram of a non-volatile memory system according to at least one example embodiment;

[0013] Figure 2 is a block diagram of a non-volatile memory device according to at least one example embodiment; Figure 1

[0014] Figure 3 is an example circuit diagram of a memory block according to at least one example embodiment; Figure 2

[0015] Figure 4A and Figure 4B shows a threshold voltage distribution of a memory cell according to at least one example embodiment; Figure 3

[0016] Figures 5 to 10 is a graph for illustrating an operation of a non-volatile memory device according to some example embodiments;

[0017] Figure 11 is a flowchart showing a method of operating a non-volatile memory device according to at least one example embodiment;

[0018] Figures 12 to 16 ​​​is a diagram for explaining an operation of a non-volatile memory device according to some example embodiments;

[0019] Figure 17 and Figure 18 is a diagram for explaining an operation of a non-volatile memory device according to some example embodiments;

[0020] Figure 19 is a block diagram of a non-volatile memory system according to at least one example embodiment;

[0021] Figure 20 is a block diagram of a memory chip according to at least one example embodiment; Figure 19 is a block diagram of a memory chip according to at least one example embodiment; and

[0022] Figure 21 is a diagram for explaining an operation of a non-volatile memory device according to at least one example embodiment. Figure 19 is a diagram for explaining an operation of a non-volatile memory device according to at least one example embodiment. DETAILED DESCRIPTION

[0023] Figure 1 is a block diagram of a non-volatile memory system according to at least one example embodiment.

[0024] Referring to Figure 1 , a non-volatile memory system according to at least one example embodiment can include a memory controller 100 and / or a non-volatile memory device 200, but example embodiments are not limited thereto, and for example, can include a greater or lesser number of constituent components, such as a plurality of non-volatile memory devices, a plurality of memory controllers, etc.

[0025] The memory controller 100 can control overall operations of the non-volatile memory device 200. The memory controller 100 can provide a plurality of signals, such as a command CMD, an address ADDR, a control signal CTRL, and / or data DATA, etc., along an input / output (I / O) line connected to the non-volatile memory device 200.

[0026] The memory controller 100 can be configured to provide an interface between the non-volatile memory device 200 and at least one host device HOST. The memory controller 100 can access the non-volatile memory device 200 in response to a request (e.g., an instruction, a command, a signal, etc.) of the host device HOST. The memory controller 100 can interpret a command received from the host device HOST and control an operation (e.g., a program, a read, and an erase operation) of the non-volatile memory device 200 according to and / or based on the interpretation result. According to some example embodiments, the memory controller 100 can include hardware, such as a logic circuit (e.g., a processing circuit, etc.), a hardware / software combination, such as at least one processor core executing software and / or executing any instruction set, or a combination thereof. For example, the memory controller 100 can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor (DSP), a graphics processing unit (GPU), a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0027] The non-volatile memory device 200 can include, for example, NAND flash memory, vertical NAND (VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-transfer torque random access memory (STT-RAM), etc., but example embodiments are not limited to these examples.

[0028] The memory controller 100 and the non-volatile memory device 200 can each be provided as one chip, one package, or one module, but are not limited thereto. In addition, the memory controller 100 and the non-volatile memory device 200 can be mounted using a package, such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual-in-line package (PDIP), a wafer level package chip, a die in a wafer form, a chip on board (COB), a ceramic dual-in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a thin quad flat package (TQFP), a system in package (SIP), a multi-chip package (MCP), a wafer level fabricated package (WFP), and a wafer level processed stack package (WSP), etc.

[0029] Figure 2 is a block diagram of a non-volatile memory device 200 according to at least one example embodiment. Figure 1 is a block diagram of a non-volatile memory device 200 according to at least one example embodiment.

[0030] Referring to Figure 1 and Figure 2 The non-volatile memory device 200 can include a voltage generator 210, an address decoder 220, a data I / O circuit 230, a page buffer circuit 240, control logic 250 (e.g., control logic circuitry, control logic circuit, processing circuit, etc.), and / or a memory cell array 260, although example embodiments are not limited thereto and can include a greater or lesser number of constituent components, for example.

[0031] The voltage generator 210 can generate operating voltages desired and / or required by the non-volatile memory device 200 by using a power supply voltage. The operating voltages can include a program voltage, a pass voltage, a read voltage, a read pass voltage, a verify voltage, an erase voltage, a bit line voltage, and / or a common source voltage, for example, although example embodiments are not limited thereto.

[0032] The address decoder 220 can select any one of a plurality of memory blocks BLK1 to BLKi in response to an address ADDR. In addition, the address decoder 220 can be connected to the memory cell array 260 through a plurality of word lines WL, at least one string select line SSL, and / or at least one ground select line GSL, although example embodiments are not limited thereto.

[0033] The data I / O circuit 230 can be connected to the control logic 250. The data I / O circuit 230 can perform operations, such as input and output operations, based on operating signals from the control logic 250. The data I / O circuit 230 can provide an address ADD, a command CMD, and / or a control signal CTRL received from the memory controller 100 to the control logic 250, although example embodiments are not limited thereto.

[0034] The page buffer circuit 240 can be connected to the memory cell array 260 through a bit line BL. According to at least one example embodiment, the page buffer circuit 240 can provide the same voltage to each bit line BL during an erase operation, although example embodiments are not limited thereto. The page buffer circuit 240 can receive operating signals from the control logic 250. The page buffer circuit 240 can perform operations, such as erase, verify, and / or program operations, according to and / or based on the operating signals from the control logic 250.

[0035] Control logic 250 can generate operation signals, such as erase signals, verification signals, and / or programming signals, based on commands CMD and / or control signals CTRL from memory controller 100. Control logic 250 can provide the generated operation signals to voltage generator 210, address decoder 220, page buffer circuitry 240, or data I / O circuitry 230. The non-volatile memory device 200 may include more or fewer elements than those shown, if desired and / or necessary. According to some example embodiments, control logic 250 may be processing circuitry and may include: hardware, such as logic circuitry (e.g., control logic circuitry, etc.); hardware / software combinations, such as at least one processor core executing software and / or executing any instruction set; or combinations thereof. For example, control logic 250 may more specifically include, but is not limited to, a central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor (DSP), field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0036] When reading and / or simultaneously reading memory cells connected to word lines, control logic 250 may store and / or pre-store read voltages to be applied to and / or simultaneously applied to the multiple word lines included in each memory bank. A memory bank may refer to a group comprising multiple word lines, for example, a group of multiple word lines, memory blocks, and / or memory chips, etc.

[0037] When control logic 250 reads and / or simultaneously reads memory cells connected to multiple word lines, it can control the desired and / or predetermined read voltage applied to the corresponding word lines during operations (e.g., erase verification operations). See later. Figures 5 to 11 This will be described in detail.

[0038] The memory cell array 260 may include multiple memory blocks BLK1 to BLKi. Each of the memory blocks BLK1 to BLKi can be connected to the address decoder 220 via multiple word lines WL, at least one serial select line SSL, at least one ground select line GSL, and / or a common source line CSL, but is not limited thereto. Additionally, each of the memory blocks BLK1 to BLKi can be connected to the page buffer circuit 240 via multiple bit lines BL. The memory cell array 260 may be a two-dimensional memory cell array or a three-dimensional memory cell array.

[0039] Figure 3 According to at least one example embodiment Figure 2 Example circuit diagram of memory block BLK1.

[0040] refer to Figure 3A plurality of cell strings NS11 to NS33 can be between a plurality of bit lines BL1 to BL3 and a common source line CSL, although example embodiments are not limited thereto. Each cell string (e.g., NS11) can include a ground select transistor GST, a plurality of memory cells MC1 to MC8, and / or a string select transistor SST, etc.

[0041] The string select transistor SST can be connected to a string select line SSL. For example, the string select line SSL can be divided into a first string select line SSL1 to a third string select line SSL3, although example embodiments are not limited thereto. The ground select transistor GST can be connected to a plurality of ground select lines, e.g., GSL1 to GSL3, etc. In some example embodiments, the ground select lines (e.g., GSL1 to GSL3) can be connected to each other. The string select transistor SST can be connected to a plurality of bit lines (e.g., BL1 to BL3, etc.), and the ground select transistor GST can be connected to a common source line CSL.

[0042] The memory cells (e.g., MC1 to MC8, etc.) can be respectively connected to a corresponding plurality of word lines (e.g., WL1 to WL8, etc.). A group of memory cells connected to one word line and programmed at the same time can be referred to as a page. As shown, the memory block BLK1 can include a plurality of pages. In addition, a plurality of pages can be connected to one word line. For example, a word line (e.g., WL4) located at a particular height from the common source line CSL can be commonly connected to three pages, although example embodiments are not limited thereto.

[0043] A page can be a unit for data programming (e.g., writing) and reading, and a memory block BLK1 can be a unit for data erasing. That is, data can be programmed (e.g., written) and / or read page by page when the non-volatile memory device 200 performs a programming and / or reading operation, and data can be erased memory block by memory block when the non-volatile memory device 200 performs an erasing operation. That is, data in all memory cells (e.g., MC1 to MC8) included in one memory block can be erased at a time.

[0044] Each of the memory cells (e.g., MC1 to MC8, etc.) can store 1-bit data or 2-bit or more data. Each of the memory cells (e.g., MC1 to MC8) can be, for example, a single-level cell (SLC) recording 1-bit data or a multi-level cell (MLC) storing 2-bit or more data. The multi-level cell can be, for example, a triple-level cell (TLC) recording 3-bit data, a quad-level cell (QLC) recording 4-bit data, etc.

[0045] Figure 4A and Figure 4B A non-volatile memory device according to some example embodiments is illustrated Figure 3threshold voltage distribution of the memory cells MC1 to MC8. In Figure 4A and Figure 4B , the horizontal axis indicates a desired threshold voltage, and the vertical axis indicates the number of memory cells. Figure 4A An example threshold voltage distribution is shown in the case where the memory cells MC1 to MC8 (see Figure 3 ) are multi-level cells storing 2-bit data, and Figure 4B An example threshold voltage distribution is shown in the case where the memory cells MC1 to MC8 (see Figure 3 ) are multi-level cells storing 4-bit data, but example embodiments are not limited thereto.

[0046] Referring to Figure 3 and Figure 4A , the memory cells MC1 to MC8 can be programmed to have an erase state E and first to third states P1 to P3, but example embodiments are not limited thereto. When an erase verify operation is performed after an erase operation is performed on the memory cells MC1 to MC8, an erase verify voltage Vvfy can be applied to the memory cells MC1 to MC8. For example, after the erase verify voltage Vvfy is applied, a result of the erase operation, e.g., erase pass or erase fail, can be determined according to the number of on cells and off cells among the memory cells MC1 to MC8. Here, a difference between a first threshold voltage (e.g., a high threshold voltage, a maximum threshold voltage, etc.) in the erase state E and a second threshold voltage (e.g., a low threshold voltage, a minimum threshold voltage, etc.) in the first state P1 can be a first voltage V1.

[0047] Referring to Figure 3 and Figure 4B , the memory cells MC1 to MC8 can have an erase state E and first to seventh program states P1 to P7, but example embodiments are not limited thereto. When an erase verify operation is performed after an erase operation is performed on the memory cells MC1 to MC8, an erase verify voltage Vvfy can be applied to the memory cells MC1 to MC8. For example, after the erase verify voltage Vvfy is applied, a result of the erase operation, e.g., erase pass or erase fail, can be determined according to the number of on cells and off cells among the memory cells MC1 to MC8. Here, a difference between a first threshold voltage (e.g., a high threshold voltage, a maximum threshold voltage, etc.) in the erase state E and a second threshold voltage (e.g., a low threshold voltage, a minimum threshold voltage, etc.) in the first program state P1 can be a second voltage V2.

[0048] The first voltage V1 can be greater than the second voltage V2, but example embodiments are not limited thereto. That is, since the memory cells MC1 to MC8 have a multi-level cell structure, a sensing margin of erase verification can decrease, and the importance of setting the erase verification voltage Vvfy can increase, but example embodiments are not limited thereto. Here, the erase verification voltage Vvfy can be determined and / or set at any time (e.g., before the non-volatile memory device 200 is shipped), but is not limited thereto.

[0049] Accordingly, the non-volatile memory device 200 according to at least one example embodiment can determine a read voltage in advance according to a case in which memory cells connected to a plurality of word lines are read at the same time (e.g., an erase verification operation), and when memory cells connected to a plurality of word lines are read at the same time, a desired and / or predetermined read voltage can be applied to the word lines. Accordingly, a sensing margin can be ensured.

[0050] Figures 5 to 10 is a graph for explaining an operation of a non-volatile memory device according to some example embodiments.

[0051] Each of the plurality of groups (e.g., group 1 to group 4) can include two or more word lines, but example embodiments are not limited thereto. Here, the memory cells can be erased before the product is shipped, but are not limited thereto. In Figures 5 to 10 In, a dotted line indicates group 1, a dashed line indicates group 2, a thick solid line indicates group 3, and a solid line indicates group 4. Each of group 1 to group 4 can be, for example, a group of memory cells generated by a specific process, a group of memory cells included in a specific memory block, a group of memory cells included in a specific chip, and / or a group of memory cells included in a specific area, etc.

[0052] Figure 5 is shown a threshold voltage distribution of a memory cell connected to one of the word lines included in each of group 1 to group 4 by applying a sub-voltage to the one of the word lines according to some example embodiments. Here, the horizontal axis indicates a threshold voltage, and the vertical axis indicates the number of memory cells. The threshold voltage distribution of the memory cells can be checked by sequentially applying a plurality of sub-voltages, but example embodiments are not limited thereto.

[0053] Referring to Figure 5 , the threshold voltage distribution of the memory cells connected to one of the word lines can be similar in group 1 to group 4, but according to a process of each group or a location where each group is located, the threshold voltage distribution is slightly different according to characteristics of the memory cells, but example embodiments are not limited thereto.

[0054] Figure 6The erase verify voltage Vvfy according to the threshold voltage distribution of the memory cells connected with one word line included in each of the group 1 to group 4 is shown according to some example embodiments. Here, the horizontal axis denotes the number of memory cells, and the vertical axis denotes the erase verify voltage Vvfy.

[0055] Referring to Figure 6 The level of the erase verify voltage Vvfy can be set according to the threshold voltage distribution of the memory cells connected with one word line included in each of the group 1 to group 4 (as shown in Figure 5 The erase verify voltage Vvfy can be set to the third voltage Va since the threshold voltage distribution of the memory cells connected to one word line is similar in the group 1 to group 4. That is, the third voltage Va can be the erase verify voltage advantageously and / or optimally set for the case of reading the memory cells connected to one word line.

[0056] Figure 7 The counted erase cycles when the erase verify voltage Vvfy of each of the group 1 to group 4 is the third voltage Va is shown according to some example embodiments. Here, the horizontal axis denotes the number of memory cells, and the vertical axis denotes the erase cycles counted until the erase operation is terminated.

[0057] Referring to Figure 7 The non-volatile memory device shipped can perform an erase cycle in response to an erase command, but example embodiments are not limited thereto. The erase cycle can include an erase operation and an erase verify operation, but is not limited thereto. In the erase cycle, in the case where an erase pass result is obtained in response to the erase verify operation, the erase operation can be terminated. On the other hand, in the case where an erase fail result is obtained in response to the erase verify operation, the erase cycle can be counted, and a next erase cycle can be performed.

[0058] The number of counted erase cycles of each of the group 1 and group 2 can be 1, but example embodiments are not limited thereto. That is, each of the group 1 and group 2 can be erased by performing a first erase cycle. On the other hand, the number of counted erase cycles of each of the group 3 and group 4 can be 1 or 2, but example embodiments are not limited thereto, and the number of counted erase cycles can be greater than 2. Each of the group 3 and group 4 can include memory cells erased by performing a first erase cycle, and memory cells 1 erased by performing a first erase cycle and a second erase cycle (i.e., two erase cycle operations), etc.

[0059] That is, all of the memory cells included in each of the group 1 to group 4 can be in an erase pass state, but as Figure 7As shown in FIG. 1, there can be memory cells 1 in which an additional erase cycle will be performed due to the erase verify voltage Vvfy having the third voltage Va. This will be described in detail below with reference to Figure 8 This will be described in detail.

[0060] Figure 8 A threshold voltage distribution of memory cells connected to all word lines read by simultaneously applying a sub voltage to each of the word lines included in sub group 1 to group 4 according to some example embodiments is shown. Here, the horizontal axis represents a threshold voltage, and the vertical axis represents the number of memory cells. The threshold voltage distribution of memory cells can be checked by sequentially applying a plurality of sub voltages, but example embodiments are not limited thereto.

[0061] As shown in FIG. 1, there can be memory cells 1 in which an additional erase cycle will be performed due to the erase verify voltage Vvfy having the third voltage Va. This will be described in detail below with reference to Figure 8 As shown in FIG. 1, there can be memory cells 1 in which an additional erase cycle will be performed due to the erase verify voltage Vvfy having the third voltage Va. This will be described in detail below with reference to Figure 7 As shown in FIG. 1, there can be memory cells 1 in which an additional erase cycle will be performed due to the erase verify voltage Vvfy having the third voltage Va. This will be described in detail below with reference to Figure 7 ).

[0062] Referring to FIG. 1, Figure 8 As shown in FIG. 1, there can be memory cells 1 in which an additional erase cycle will be performed due to the erase verify voltage Vvfy having the third voltage Va. This will be described in detail below with reference to

[0063] As shown in FIG. 1, there can be memory cells 1 in which an additional erase cycle will be performed due to the erase verify voltage Vvfy having the third voltage Va. This will be described in detail below with reference to Figure 5The threshold voltage distribution shown in FIG. 1A is different because the characteristics (e.g., physical characteristics, electrical characteristics, etc.) of the memory cells included in each of the plurality of groups (group 1 to group 4) are different. The threshold voltage distribution of the memory cells can be shifted (e.g., increased) to the right when the memory cells connected to all the word lines included in each of the plurality of groups (e.g., group 1 to group 4) are read at the same time, compared to the threshold voltage distribution of the memory cells when the memory cells connected to one word line are read. That is, the threshold voltage can increase.

[0064] Figure 9 FIG. 1B illustrates an erase verify voltage Vvfy determined according to a threshold voltage distribution of memory cells when the memory cells connected to all the word lines included in each of the plurality of groups (e.g., group 1 to group 4, etc.) are read at the same time, according to some example embodiments. The threshold voltage distribution of the memory cells can be different in each of the plurality of groups (group 1 to group 4, etc.) when the memory cells connected to all the word lines included in each of the plurality of groups (e.g., group 1 to group 4) are read at the same time. Accordingly, the erase verify voltage Vvfy of each of the plurality of groups (e.g., group 1 to group 4, etc.) can be set to different voltages, but example embodiments are not limited thereto. Figure 8

[0065] The non-volatile memory device according to at least one example embodiment can check the threshold voltage distribution of the memory cells connected to a plurality of word lines included in each of the plurality of groups (group 1 to group 4) by simultaneously applying a sub voltage to the word lines, and can determine the erase verify voltage Vvfy in advance based on the threshold voltage distribution. The erase verify voltage Vvfy can be required and / or predetermined according to the characteristics of the memory cells included in each memory group to improve and / or optimize the erase verify voltage Vvfy for the case of simultaneously reading the memory cells connected to a plurality of word lines.

[0066] Figure 10 FIG. 1C illustrates the number of erase cycles counted during an erase operation for each of group 1 to group 4 when the erase verify voltage Vvfy (as shown in FIG. 1B) is determined, according to some example embodiments. Figure 9

[0067] Referring to FIG. 1D, the respective number of erase cycles counted for group 1 to group 4 can all be 1, but example embodiments are not limited thereto. Each of group 1 to group 4 can be erased by performing the same number of erase cycles, but is not limited thereto. Figure 10 That is, the erase verify voltage Vvfy can be determined according to the threshold voltage distribution of the memory cells when the memory cells connected to all the word lines included in each of the plurality of groups (e.g., group 1 to group 4, etc.) are read at the same time.

[0068] Figure 7 ​​​In contrast, the non-volatile memory device according to at least one example embodiment does not perform excessive erase operations on the memory cells due to the erase verify voltage Vvfy. Thus, deterioration of the memory cells can be improved and / or prevented by not performing and / or preventing additional erase cycles, and power consumption can be reduced.

[0069] Figure 11 FIG. 1 is a flowchart illustrating a method of operating a non-volatile memory device according to at least one example embodiment.

[0070] Referring to Figure 11 , the method of operating a non-volatile memory device according to at least one example embodiment can start by simultaneously applying a sub-voltage to word lines connected to memory cells included in a memory group (operation S10). Here, the memory group can be, for example, a group of memory cells generated by a certain process, a group of memory cells included in a certain memory block, a group of memory cells included in a certain chip, a group of memory cells included in a certain area, and / or a group of memory chips connected to a certain channel. That is, the memory group can refer to any unit including a plurality of word lines.

[0071] Next, a threshold voltage of the memory group can be checked (operation S20). For example, the threshold voltage of the memory group can be checked by performing a plurality of read operations by sequentially applying a first sub-voltage to an Nth sub-voltage to the plurality of word lines included in the memory group.

[0072] Next, a read voltage of the memory group can be determined according to the checked threshold voltage of the memory cells included in the memory group (operation S30).

[0073] Next, the determined read voltage of the memory group can be stored in, for example, the control logic 250 (see Figure 2 ), but is not limited thereto. Then, when simultaneously reading the memory cells connected to the word lines included in the memory group, the control logic 250 (see Figure 2 ) included in the shipped non-volatile memory device can apply the stored read voltage to the word lines.

[0074] Thus, the non-volatile memory device according to one or more example embodiments can simultaneously read the memory cells connected to the plurality of word lines included in the memory group by using a desired and / or predetermined read voltage, which is improved and / or optimized for the case of simultaneously reading the memory cells connected to the word lines included in the memory group.

[0075] Figures 12 to 16 FIG. 1 is a flowchart illustrating a method of operating a non-volatile memory device according to at least one example embodiment.

[0076] Referring to Figure 12 , a non-volatile memory device according to at least one example embodiment can include a first memory group 11 including a plurality of first word lines WL1 to WLj, and a second memory group 12 including a plurality of second word lines WLj+1 to WLn, but example embodiments are not limited thereto, and more or less memory groups and / or more or less word lines can be included in each memory group. The first memory group 11 and the second memory group 12 can be included in one memory block, but are not limited thereto. The first word lines WL1 to WLj and the second word lines WLj+1 to WLn can have the same structure, but are not limited thereto. First memory cells connected to the first word lines WL1 to WLj and second memory cells connected to the second word lines WLj+1 to WLn can have the same structure, but are not limited thereto.

[0077] According to at least one example embodiment, the first memory group 11 can be above the second memory group 12, but is not limited thereto. For example, the first word lines WL1 to WLj can be above the second word lines WLj+1 to WLn, and the like.

[0078] When the control logic 250 (see Figure 2 ) simultaneously reads the first memory cells connected to the first word lines WL1 to WLj included in the first memory group 11, the control logic 250 can simultaneously apply a first read voltage Vread1 to the first word lines WL1 to WLj. Here, the first read voltage Vread1 can be a desired voltage determined and / or set at any time (e.g., before the non-volatile memory device is shipped, etc.).

[0079] The first read voltage Vread1 can be a desired voltage determined and / or set at any time (e.g., before the non-volatile memory device is shipped, etc.) considering a threshold voltage distribution of the first memory cells connected to the first word lines WL1 to WLj read by simultaneously applying a sub voltage to the first word lines WL1 to WLj. That is, the first read voltage Vread1 can be a desired voltage improved and / or optimized for a case of simultaneously reading the first memory cells connected to the first word lines WL1 to WLj.

[0080] When the control logic 250 (see Figure 2 ) simultaneously reads the second word lines WLj+1 to WLn included in the second memory group 12, the control logic 250 can simultaneously apply a second read voltage Vread2 to the second word lines WLj+1 to WLn.

[0081] The second read voltage Vread2 can be a desired voltage determined and / or set at any time (e.g., before the non-volatile memory device is shipped) in consideration of threshold voltage distributions of the second memory cells connected to the second word lines WLj+1 to WLn read by simultaneously applying the sub-voltages to the second word lines WLj+1 to WLn. That is, the second read voltage Vread2 can be a desired voltage improved and / or optimized for a case of simultaneously reading the second word lines WLj+1 to WLn.

[0082] The first read voltage Vread1 and the second read voltage Vread2 can be different voltages, but are not limited thereto.

[0083] When the control logic 250 (see Figure 2 ) simultaneously reads the first word lines WL1 to WLj included in the first memory group 11 and the second word lines WLj+1 to WLn included in the second memory group 12, the control logic 250 can simultaneously apply the first read voltage Vread1 to the first word lines WL1 to WLj and apply the second read voltage Vread2 to the second word lines WLj+1 to WLn. In addition, according to some example embodiments, the control logic 250 can include a plurality of control logic circuits, a plurality of control logic circuitries, and / or a plurality of processing circuits associated with each of the plurality of memory groups connected to the control logic 250, etc. For example, the control logic 250 can include a first control logic and / or a first processing circuit (not shown) connected to the first memory group 11, and a second control logic and / or a second processing circuit (not shown) connected to the second memory group 12, etc., but example embodiments are not limited thereto.

[0084] When the control logic 250 (see Figure 2 ) performs an erase verify operation, for example, on a memory block including the first memory group 11 and the second memory group 12, the control logic 250 can control an erase verify operation performed on the first memory cells and the second memory cells included in the first memory group 11 and the second memory group 12 by applying an erase verify voltage to each of the first memory group 11 and the second memory group 12. The control logic 250 (see Figure 2 ) can control a first erase verify operation performed on the first memory cells included in the first memory group 11 and a second erase verify operation performed on the second memory cells included in the second memory group 12 to be sequentially or simultaneously performed. Accordingly, the control logic 250 (see Figure 2 ) can simultaneously apply the second read voltage Vread2 to the second word lines WLj+1 to WLn included in the second memory group 12 after or at the same time as applying the first read voltage Vread1 to the first word lines WL1 to WLj included in the first memory group 11, but example embodiments are not limited thereto.

[0085] The above applies to some example embodiments of the inventive concept, and example embodiments are not limited thereto. The second memory group 12 can also be above the first memory group 11, and the second word lines WLj+1 to WLn can also be above the first word lines WL1 to WLj, and so on. In addition, since the first memory group 11 and the second memory group 12 need only include a plurality of word lines, the number of the first word lines WL1 to WLj and the number of the second word lines WLj+1 to WLn can be any number greater than 1.

[0086] Figure 13 is a diagram for explaining the operation of a non-volatile memory device according to at least one example embodiment. The following description will focus on the differences from Figure 12 .

[0087] Referring to Figure 13 , a non-volatile memory device according to at least one example embodiment can include a memory block including a first memory group 11 and a second memory group 12, but example embodiments are not limited thereto, and a greater or smaller number of memory groups can be included in the memory block.

[0088] The first memory group 11 can include a (natural number 2 or more) number of first word lines. The second memory group 12 can include a number of second word lines. That is, according to at least one example embodiment, the number of first word lines and the number of second word lines can be equal, and the first memory group 11 and the second memory group 12 can include the same number of word lines, but example embodiments are not limited thereto, and the number of word lines can be different for the first memory group 11 and the second memory group 12.

[0089] When the control logic 250 (see Figure 2 ) simultaneously reads the first memory cells connected to the first word lines included in the first memory group 11, the control logic 250 can simultaneously apply a first read voltage Vread1 to the first word lines, but is not limited thereto. When the control logic 250 (see Figure 2 ) simultaneously reads the second memory cells connected to the second word lines included in the second memory group 12, the control logic 250 can simultaneously apply a second read voltage Vread2 to the second word lines, but is not limited thereto. The first read voltage Vread1 and the second read voltage Vread2 can be desired and / or predetermined voltages as described above in Figure 12 .

[0090] In addition, when the control logic 250 (see Figure 2) performing an erase verify operation on a memory block including the first memory group 11 and the second memory group 12, the control logic 250 can apply the first read voltage Vread1 to the first word lines included in the first memory group 11 and the second read voltage Vread2 to the second word lines included in the second memory group 12, as described above in Figure 12 .

[0091] Figure 14 is a diagram for explaining a method of operating a non-volatile memory device according to at least one example embodiment. The following description will focus on the differences from Figure 12 .

[0092] Referring to Figure 14 , a non-volatile memory device according to at least one example embodiment can include a first memory group 11 including a plurality of first word lines WL1, WL3, WL5 to WLn-1 (where n is an even number) and a second memory group 12 including a plurality of second word lines WL2, WL4, WL6 to WLn, although example embodiments are not limited thereto and can include a greater or lesser number of memory groups and / or a greater or lesser number of word lines per memory group. The first memory group 11 and the second memory group 12 can be included in one memory block. According to at least one example embodiment, the first word lines WL1, WL3, WL5 to WLn-1 included in the first memory group 11 can include odd-numbered word lines, and the second word lines WL2, WL4, WL6 to WLn included in the second memory group 12 can include even-numbered word lines, although are not limited thereto.

[0093] When the control logic 250 (see Figure 2 ) simultaneously reads first memory cells connected to the first word lines WL1, WL3, WL5 to WLn-1 included in the first memory group 11, the control logic 250 can simultaneously apply the first read voltage Vread1 to the first word lines WL1, WL3, WL5 to WLn-1. When the control logic 250 (see Figure 2 ) simultaneously reads second memory cells connected to the second word lines WL2, WL4, WL6 to WLn included in the second memory group 12, the control logic 250 can simultaneously apply the second read voltage Vread2 to the second word lines WL2, WL4, WL6 to WLn.

[0094] The above applies to some example embodiments of the inventive concept, and example embodiments are not limited thereto. The first word lines included in the first memory group 11 can also include an even number of word lines, and the second word lines included in the second memory group 12 can also include odd-numbered word lines, etc.

[0095] Figure 15 is a diagram for explaining a method of operating a nonvolatile memory device according to at least one example embodiment. The following description will focus on the differences from Figure 12 .

[0096] A nonvolatile memory device according to at least one example embodiment can include a first memory group 11 including a plurality of first word lines WLn-2, WLn-1 and WLn located at the top of a memory block, and a plurality of first word lines WL1, WL2 and WL3 located at the bottom of the memory block, and a second memory group 12 including a plurality of second word lines WL4 to WLn-3 except for the first word lines WL1, WL2, WL3, WLn-2, WLn-1 and WLn, but example embodiments are not limited thereto. The first memory group 11 and the second memory group 12 can be included in one block.

[0097] The second memory group 12 can be included between portions of the first memory group 11, the second memory group 12 can be included in the middle of a memory block, and the first memory group 11 can be outside of the second memory group 12, but example embodiments are not limited thereto.

[0098] The above applies to some example embodiments of the inventive concept, and example embodiments are not limited thereto. For example, the first memory group 11 can also be included between portions of the second memory group 12, the first memory group 11 can also be included in the middle of a memory block, and the second memory group 12 can also be outside of the first memory group 11, and the like. In addition, example embodiments are not limited to the number of word lines shown in the current diagram, as long as the number of first word lines WL1, WL2, WL3, WLn-2, WLn-1 and WLn and the number of second word lines WL4 to WLn-3 are natural numbers equal to or greater than 2.

[0099] Figure 16 is a diagram for explaining a method of operating a nonvolatile memory device according to at least one example embodiment. The following description will focus on the differences from Figure 12 .

[0100] Referring to Figure 16The nonvolatile memory device according to at least one example embodiment can include a first memory group 11 including a plurality of first word lines WL1 to WL3, a second memory group 12 including a plurality of second word lines WL4 to WLn-4, and a third memory group 13 including a plurality of third word lines WLn-3 to WLn, and so on. The first memory group 11, the second memory group 12, and the third memory group 13 can be included in one memory block, but are not limited thereto. The first word lines WL1 to WL3, the second word lines WL4 to WLn-4, and the third word lines WLn-3 to WLn can have the same structure, but are not limited thereto.

[0101] When the control logic 250 (see Figure 2 ) reads the first memory cells connected to the first word lines WL1 to WL3 included in the first memory group 11 at the same time, the control logic 250 can apply the first read voltage Vread1 to the first word lines WL1 to WL3 at the same time. When the control logic 250 (see Figure 2 ) reads the second memory cells connected to the second word lines WL4 to WLn-4 included in the second memory group 12 at the same time, the control logic 250 can apply the second read voltage Vread2 to the second word lines WL4 to WLn-4 at the same time. When the control logic 250 (see Figure 2 ) reads the third memory cells connected to the third word lines WLn-3 to WLn included in the third memory group 13 at the same time, the control logic 250 can apply the third read voltage Vread3 to the third word lines WLn-3 to WLn at the same time.

[0102] Here, the first read voltage Vread1 and the second read voltage Vread2 are determined and / or set in the same manner as the above-described manner. The third read voltage Vread3 can be a desired voltage determined and / or set at any time (e.g., before the nonvolatile memory device is shipped) considering a threshold voltage distribution of the third memory cells connected to the third word lines WLn-3 to WLn read by applying the verify voltage to the third word lines WLn-3 to WLn at the same time. That is, the third read voltage Vread3 can be an improved and / or optimized voltage for the case of reading the third word lines WLn-3 to WLn at the same time.

[0103] The first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 can be different voltages, etc.

[0104] When the control logic 250 (see Figure 2) When performing an operation (e.g., an erase verify operation, etc.) on a memory block including the first memory group 11, the second memory group 12, and the third memory group 13, the control logic 250 can control an erase verify operation to be performed on the first memory cells to the third memory cells included in the first memory group 11, the second memory group 12, and the third memory group 13 by applying an erase verify voltage to each of the first memory group 11, the second memory group 12, and the third memory group 13. The control logic 250 (see Figure 2 ) can apply a second read voltage Vread2 to the second word lines WL4 to WLn-4 and a third read voltage Vread3 to the third word lines WLn-3 to WLn after or at the same time as applying the first read voltage Vread1 to the first word lines WL1 to WL3. That is, the control logic 250 (see Figure 2 ) can simultaneously apply the first read voltage Vread1 to the third read voltage Vread3 to the first word lines to the third word lines WL1 to WLn, respectively.

[0105] The above is applicable to some example embodiments of the inventive concept, but example embodiments are not limited thereto. The non-volatile memory device can further include N memory groups having a plurality of word lines. When simultaneously reading the plurality of word lines included in each of the first memory group to the Nth memory group, different read voltages can be applied to the word lines included in each of the first memory group to the Nth memory group. When reading memory cells connected to the word lines included in each memory group, the read voltage can be determined based on a threshold voltage distribution of the memory cells.

[0106] Figure 17 and Figure 18 are diagrams for explaining an operation of a non-volatile memory device according to some example embodiments when a memory group is a memory block.

[0107] Referring to Figure 17 , a non-volatile memory device according to at least one example embodiment can include a first memory block BLK1 including a first memory group and a second memory block BLK2 including a second memory group, but is not limited thereto. That is, a memory group can be a memory block, etc.

[0108] When first memory cells connected to a plurality of first word lines WL1 to WLn included in the first memory block BLK1 are read at the same time, a first read voltage Vread1 can be applied to the first word lines WL1 to WLn. When second memory cells connected to a plurality of second word lines WL1 to WLn included in the second memory block BLK2 are read at the same time, a second read voltage Vread2 can be applied to the second word lines WL1 to WLn. Here, the first read voltage Vread1 and the second read voltage Vread2 can be different, or can be the same. The first read voltage Vread1 and the second read voltage Vread2 can be determined as described above and stored in the control logic 250 (see Figure 2 ).

[0109] For example, the first read voltage Vread1 can be applied to the first word lines WL1 to WLn in an erase verify operation performed on the first memory block BLK1, and the second read voltage Vread2 can be applied to the second word lines WL1 to WLn in an erase verify operation performed on the second memory block BLK2. That is, the erase verify voltages of the first memory block BLK1 and the second memory block BLK2 can be different, or can be the same.

[0110] Figure 18 is a diagram for explaining an operation of a non-volatile memory device according to at least one example embodiment.

[0111] Referring to Figure 2 and Figure 18 , the memory cell array 260 can include a plurality of memory blocks BLK1 to BLKi. The memory blocks BLK1 to BLKi can have, for example, different erase verify voltages. The erase verify voltage for the first memory block BLK1 can be a first read voltage Vread1, and the erase verify voltage for the i-th memory block BLKi can be an i-th read voltage Vreadi. The first read voltage Vread1 to the i-th read voltage Vreadi can be different from each other.

[0112] Figures 19 to 21 is a diagram for explaining an operation of a non-volatile memory device according to some example embodiments when a memory group is a memory chip.

[0113] Figure 19 is a block diagram of a non-volatile memory system according to at least one example embodiment. Referring to Figure 19 , the non-volatile memory device 200 according to at least one example embodiment can include a plurality of memory chips 200_1 to 200_k, but is not limited thereto. A memory group can be a memory chip or the like.

[0114] Figure 20 isFigure 19 a block diagram of the memory chip 200_1. Referring to Figure 20 , the memory chip 200_1 can include a plurality of memory blocks 260_1 and control logic 260_2, but is not limited thereto. The control logic 260_2 can store a desired and / or predetermined read voltage to be applied to a plurality of word lines connected to memory cells included in the memory block 260_1 when the memory cells are read at a desired time (e.g., before the non-volatile memory device 200 is shipped, etc.). The read voltage can be predetermined and / or set according to a threshold voltage distribution of the memory cells connected to the plurality of word lines included in the memory block 260_1 read by applying a verify voltage to the plurality of word lines included in the memory block 260_1, but example embodiments are not limited thereto.

[0115] Accordingly, when the control logic 260_2 reads the memory cells connected to the plurality of word lines included in the memory chip 200_1, the control logic 260_2 can apply the desired and / or predetermined read voltage to the plurality of word lines.

[0116] Figure 21 is a diagram for explaining an operation of the non-volatile memory device 200 according to some example embodiments. Figure 19

[0117] Referring to Figure 21 , when the memory cells connected to the plurality of word lines included in the memory chips 200_1 to 200_k are read at the same time, different desired and / or predetermined read voltages Vread1 to Vreadk can be applied to the plurality of word lines. For example, an erase verify voltage applied to a memory block included in the first memory chip 200_1 can be a first read voltage Vread1, and an erase verify voltage applied to a memory block included in the k-th memory chip 200_k can be a k-th read voltage Vreadk.

[0118] Accordingly, the non-volatile memory device 200 according to at least one example embodiment can apply different erase verify voltages to each of the memory chips 200_1 to 200_k.

[0119] While various example embodiments of the inventive concept have been particularly shown and described with reference to example embodiments of the inventive concept, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the inventive concept defined by the appended claims. The example embodiments should be considered in a descriptive sense only and not for purposes of limitation.​

Claims

1. A non-volatile memory device, comprising: The memory includes a first memory group and a second memory group, the first memory group including a plurality of first word lines, and the second memory group including a plurality of second word lines different from the plurality of first word lines; and The processing circuit is configured as follows: Simultaneously, sub-voltages are applied to the multiple first word lines. Based on the threshold voltage distribution of a plurality of first memory cells connected to the plurality of first word lines sensed in response to the application of the sub-voltage to the plurality of first word lines, a desired first read voltage is determined. Simultaneously, the sub-voltage is applied to the plurality of second word lines. The desired second read voltage is determined based on the threshold voltage distribution of a plurality of second memory cells connected to the plurality of second word lines sensed in response to the application of the sub-voltage to the plurality of second word lines. When simultaneously reading the plurality of first memory cells connected to the plurality of first word lines, the desired first read voltage is applied to the plurality of first word lines, and When simultaneously reading the plurality of second memory cells connected to the plurality of second word lines, a desired second read voltage is applied to the plurality of second word lines, the desired second read voltage being different from the desired first read voltage.

2. The non-volatile memory device of claim 1, wherein the memory comprises a first memory block and a second memory block, the first memory block comprising the first memory group, and the second memory block comprising the second memory group.

3. The non-volatile memory device according to claim 1, wherein the memory comprises a memory block, and the memory block comprises the first memory group and the second memory group.

4. The non-volatile memory device according to claim 3, wherein the processing circuitry is further configured to: When an erase verification operation is performed on the memory block, the desired first read voltage is applied to the plurality of first word lines, and the desired second read voltage is applied to the plurality of second word lines.

5. The non-volatile memory device according to claim 4, wherein the processing circuitry is further configured to: The desired first read voltage is applied to the plurality of first word lines, and the desired second read voltage is applied to the plurality of second word lines simultaneously.

6. The non-volatile memory device according to claim 3, wherein The plurality of first letter lines includes letter lines with odd-numbered codes; and The multiple second word lines include word lines with even-numbered numbers.

7. The non-volatile memory device of claim 3, wherein the number of the plurality of first word lines is equal to the number of the plurality of second word lines.

8. The non-volatile memory device of claim 3, wherein at least one of the plurality of first word lines is between adjacent second word lines in the plurality of second word lines.

9. The non-volatile memory device of claim 3, wherein the plurality of first word lines are above the plurality of second word lines.

10. The non-volatile memory device according to claim 3, wherein The memory block includes a third memory group, the third memory group including a plurality of third word lines different from the plurality of first word lines and the plurality of second word lines; and The processing circuit is further configured to: Simultaneously, the sub-voltage is applied to the plurality of third word lines. Based on the threshold voltage distribution of multiple third memory cells connected to the multiple third word lines sensed in response to the application of the sub-voltage to the multiple third word lines, a desired third read voltage is determined, and When simultaneously reading the plurality of third memory cells connected to the plurality of third word lines, the desired third read voltage is applied to the plurality of third word lines, and The desired third read voltage is different from the desired first read voltage and the desired second read voltage.

11. The non-volatile memory device of claim 10, wherein the processing circuitry is further configured to: When performing an erase verification operation on the memory block, the desired first read voltage is applied to the plurality of first word lines, and the desired third read voltage is applied to the plurality of third word lines.

12. The non-volatile memory device according to claim 1, wherein The memory includes a first memory chip and a second memory chip, the first memory chip including a first memory group, and the second memory chip including a second memory group; and The processing circuit includes a first processing circuit and a second processing circuit. The first processing circuit is configured to: apply the desired first read voltage to the plurality of first word lines while simultaneously reading the plurality of first memory cells connected to the plurality of first word lines; and The second processing circuit is configured to apply the desired second read voltage to the plurality of second word lines while simultaneously reading the plurality of second memory cells connected to the plurality of second word lines.

13. The non-volatile memory device of claim 11, wherein the processing circuitry is further configured to: When an erase verification operation is performed on the memory block, the desired first read voltage is applied to the plurality of first word lines included in the first memory group, and the desired second read voltage is applied to the plurality of second word lines included in the second memory group.

14. A non-volatile memory device, comprising: The memory includes a first memory group and a second memory group, the first memory group including a plurality of first word lines, and the second memory group including a plurality of second word lines different from the plurality of first word lines; as well as The processing circuit is configured as follows: In response to receiving an erase command for the memory, an erase operation is performed by applying an erase voltage to the memory. Simultaneously, sub-voltages are applied to the multiple first word lines; Simultaneously, the sub-voltage is applied to the plurality of second word lines; as well as When an erase verification operation is performed after the erase operation, a desired first read voltage is applied to the plurality of first word lines, and a desired second read voltage is applied to the plurality of second word lines. The desired second read voltage is different from the desired first read voltage, wherein the desired first read voltage is determined based on the sub-voltages simultaneously applied to the plurality of first word lines, and the desired second read voltage is determined based on the sub-voltages simultaneously applied to the plurality of second word lines.

15. The non-volatile memory device of claim 14, wherein the processing circuitry is further configured to: The desired first read voltage is determined based on a first threshold voltage distribution of a plurality of first memory cells connected to the plurality of first word lines sensed in response to the application of the sub-voltage to the plurality of first word lines; and The desired second read voltage is determined based on a second threshold voltage distribution of a plurality of second memory cells connected to the plurality of second word lines sensed in response to the application of the sub-voltage to the plurality of second word lines.

16. The non-volatile memory device of claim 15, wherein the processing circuitry is further configured to: The sub-voltage is applied to the first word line among the plurality of first word lines; Determine a third threshold voltage distribution of a first memory cell connected to the first word line, sensed in response to the application of the sub-voltage to the first word line, the third threshold voltage distribution being different from the first threshold voltage distribution; Apply the sub-voltage to the second word line of the plurality of second word lines; and A fourth threshold voltage distribution of a second memory cell connected to the second word line is determined in response to the application of the sub-voltage to the second word line, the fourth threshold voltage distribution being different from the second threshold voltage distribution.

17. The non-volatile memory device of claim 16, wherein the high threshold voltage value of the first threshold voltage distribution is greater than the high threshold voltage value of the third threshold voltage distribution, and the high threshold voltage value of the second threshold voltage distribution is greater than the high threshold voltage value of the fourth threshold voltage distribution.

18. The non-volatile memory device of claim 14, wherein the threshold voltage of the plurality of first memory cells connected to one of the plurality of first word lines is equal to the threshold voltage of the plurality of second memory cells connected to one of the plurality of second word lines.

19. A non-volatile memory device, comprising: The first memory chip includes a first memory block and a first processing circuit. as well as The second memory chip includes a second memory block and a second processing circuit, wherein... The first memory block includes a plurality of first memory cells and a plurality of first word lines connected to the plurality of first memory cells. The first processing circuit is configured as follows: A first erase operation is performed by applying a first erase voltage to the first memory block based on a first erase command targeting the first memory block. Simultaneously, sub-voltages are applied to the multiple first word lines; as well as When performing a first erase verification operation after performing the first erase operation, a desired first read voltage is applied to the plurality of first word lines, wherein the desired first read voltage is determined based on the sub-voltages simultaneously applied to the plurality of first word lines; The second memory block includes a plurality of second memory cells and a plurality of second word lines connected to the plurality of second memory cells, and The second processing circuit is configured as follows: The second erase operation is performed by applying a second erase voltage to the second memory block based on the second erase command for the second memory block. Simultaneously apply the sub-voltage to the plurality of second word lines; and When performing a second erase verification operation after performing the second erase operation, a desired second read voltage is applied to the plurality of second word lines, wherein the desired second read voltage is determined based on the sub-voltages simultaneously applied to the plurality of second word lines, and the desired first read voltage is different from the desired second read voltage.

20. The non-volatile memory device of claim 19, wherein... The first processing circuit is further configured to: The desired first read voltage is determined based on a first threshold voltage distribution of the plurality of first memory cells connected to the plurality of first word lines sensed in response to the application of the sub-voltage to the plurality of first word lines; and The second processing circuit is further configured to: The desired second read voltage is determined based on the second threshold voltage distribution of the plurality of second memory cells connected to the plurality of second word lines sensed in response to the application of the sub-voltage to the plurality of second word lines.

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