Semiconductor structure and method for forming the same

Abstract

In an embodiment of the present application, a semiconductor structure includes: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having an upper portion and a lower portion, wherein a first width of the upper portion continuously decreases along a first direction extending away from a top surface of the semiconductor substrate, and a second width of the lower portion is constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source / drain region adjacent to a second sidewall of the gate spacer. According to other embodiments of the present application, a method for forming a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and layers of semiconductor material over a semiconductor substrate; and patterning the multiple material layers using photolithography to form circuit components and elements on the multiple material layers.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] According to an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a dummy gate dielectric above a semiconductor substrate; forming a dummy gate electrode above the dummy gate dielectric; depositing a gate spacer near the dummy gate electrode and the dummy gate dielectric; removing the dummy gate electrode to form a groove; injecting impurities into a first region of the gate spacer to increase an etching rate of the first region of the gate spacer, with a second region of the gate spacer not being changed by the injection; removing the dummy gate dielectric and the first region of the gate spacer; and forming a replacement gate in the groove, the replacement gate contacting the second region of the gate spacer.

[0005] According to an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having a first sidewall and a second sidewall opposite to the first sidewall; an epitaxial source / drain region adjacent to the first sidewall of the gate spacer; a gate dielectric extending along the second sidewall of the gate spacer and the top surface of the semiconductor substrate; and a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion continuously increasing along a first direction extending away from the top surface of the semiconductor substrate, and a second width of the lower portion being constant along the first direction.

[0006] According to an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion continuously decreasing along a first direction extending away from the top surface of the semiconductor substrate, and a second width of the lower portion being constant along the first direction; a gate stack extending along a first side wall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source / drain region adjacent to the second side wall of the gate spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. Indeed, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET is shown in a three-dimensional view in accordance with some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A and Figure 7B are various views of intermediate stages in fabricating a FinFET according to some embodiments.

[0010] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 8E 、 Figure 8F and Figure 8G are various views of intermediate stages in fabricating a replacement gate according to some embodiments.

[0011] Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B and Figure 11C are various views of other intermediate stages in the fabrication of a FinFET according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides a variety of different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not, by itself, represent a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," and "upper," may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] According to some embodiments, a funnel-shaped gate electrode is formed during a replacement gate process for a FinFET. During the replacement gate process, a recess for the replacement gate may be widened to have a funnel shape. The recess may be widened by implanting impurities into the upper region of the FinFET's gate spacer and then removing the upper region of the gate spacer through an etch selective for the impurities. Widening the recess into a funnel shape helps avoid the formation of seams (or voids) when filling the replacement gate.

[0015] Figure 1 An example of a simplified fin field-effect transistor (FinFET) in a three-dimensional view is shown in accordance with some embodiments. For clarity, some other components of the FinFET (described below) are omitted. The illustrated FinFETs can be electrically connected or coupled in a manner such that they can operate as one transistor or multiple transistors (e.g., two transistors).

[0016] The FinFET includes a fin 52 extending from a substrate 50. Shallow trench isolation (STI) regions 56 are provided above the substrate 50, and the fin 52 protrudes above and between adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer solely to a semiconductor substrate or a semiconductor substrate including isolation regions. Additionally, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. As used herein, the fin 52 refers to the portion extending between adjacent STI regions 56.

[0017] A gate dielectric 92 is disposed along the sidewalls and above the top surface of the fin 52, and a gate electrode 94 is disposed above the gate dielectric 92. Source / drain regions 70 are disposed on opposite sides of the fin 52 relative to the gate dielectric 92 and the gate electrode 94. Gate spacers 66 separate the source / drain regions 70 from the gate dielectric 92 and the gate electrode 94. An interlayer dielectric (ILD) layer 82 is disposed above the source / drain regions 70 and the STI regions 56. In embodiments where multiple transistors are formed, the source / drain regions 70 can be shared between the transistors. In embodiments where a transistor is formed from multiple fins 52, adjacent source / drain regions 70 can be electrically connected, such as by coalescing the source / drain regions 70 through epitaxial growth or by coupling the source / drain regions 70 to the same source / drain contact.

[0018] Figure 1 Several reference cross sections are also shown. Cross section AA is along the longitudinal axis of the fin 52 and, for example, in the direction of current flow between the source / drain regions 70 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the gate electrode 94 and, for example, in a direction perpendicular to the direction of current flow between the source / drain regions 70 of the FinFET. Cross section CC is parallel to cross section BB and extends through the source / drain regions 70 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Figures 2 to 11B are various views of intermediate stages in fabricating a FinFET according to some embodiments. Figure 2 and Figure 3 is a 3D view. Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 9A 、 Figure 10A and Figure 11A It is along Figure 1 The cross-sectional view shown in FIG. 5 is the same as that shown in FIG. 5 , but shows three gate structures. Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 9B 、 Figure 10B and Figure 11B It is along Figure 1 A cross-sectional view is shown with reference to section BB in , but only two fins 52 are shown. Figure 4C and Figure 4D It is along Figure 1 A cross-sectional view is shown with reference to section CC in , but only two fins 52 are shown.

[0020] exist Figure 2 In the present invention, a substrate 50 is provided. Substrate 50 can be a doped (e.g., doped with p-type or n-type dopants) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. Substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. For example, the insulator layer can be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates can also be used. In some embodiments, the semiconductor material of substrate 50 can include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0021] Substrate 50 has a region 50N and a region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. Region 50N can be physically separated from region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0022] Fins 52 are formed to extend from substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic. After formation, fins 52 have a width W1, and fins 52 in the same region 50N / 50P are spaced apart by a pitch P1. Width W1 can be in the range of approximately 3 nm to approximately 30 nm. Pitch P1 can be in the range of approximately 20 nm to approximately 100 nm.

[0023] The fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithographic processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing for the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0024] STI regions 56 are formed above substrate 50 and between adjacent fins 52. As an example of forming STI regions 56, an insulating material is formed above the intermediate structure. The insulating material may be an oxide such as silicon oxide, a nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD)-based material deposition in a remote plasma system followed by post-curing to convert it into another material such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the fins 52. Some embodiments may utilize multiple layers. For example, in some embodiments, a liner layer (not shown) may first be formed along the surfaces of substrate 50 and fins 52. Thereafter, a filler material such as described above may be formed over the liner layer. A stripping process is then applied to the insulating material to remove excess insulating material over the fins 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin 52 so that after the planarization process is completed, the fin 52 and the top surface of the insulating material are flush. The insulating material is then grooved, and the remaining portion of the insulating material forms the STI region 56. The insulating material is grooved so that the upper portion of the fin 52 in the region 50N and the region 50P protrudes from between the adjacent STI regions 56. After the grooves are formed, the exposed portion of the fin 52 extends a height H1 above the top surface of the STI region 56. The height H1 may be greater than about 40 nm, such as in the range of about 50 nm to about 80 nm. The exposed portion of the fin 52 includes a region that will become the channel region of the resulting FinFET.

[0025] Furthermore, the top surface of STI region 56 can have a flat surface (as shown), a convex surface, a concave surface (e.g., recessed), or a combination thereof. The top surface of STI region 56 can be formed to be flat, convex, and / or concave by suitable etching. STI region 56 can be grooved using an acceptable etching process, such as an etching process that is selective for the insulating material (e.g., etches the insulating material at a faster rate than the material of fin 52). For example, chemical oxide removal using a suitable etching process such as dilute hydrofluoric acid (dHF) can be used.

[0026] The process described above is merely one example of how the fin 52 is formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be grooved so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, after the insulating material of the STI region 56 is planarized by the fin 52, the fin 52 may be grooved, and a material different from the fin 52 may be epitaxially grown above the grooved fin 52. In such an embodiment, the fin 52 includes the grooved material and the epitaxially grown material arranged above the grooved material. In another embodiment, a dielectric layer may be formed above the top surface of the substrate 50, and the trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a different material than substrate 50, and the dielectric layer may be grooved so that the heteroepitaxial structure protrudes from the dielectric layer to form fins 52. In some embodiments where a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid both prior and subsequent implants, although both in-situ and implant doping may be used together.

[0027] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x , where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that may be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0028] In addition, appropriate wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, either a P-well or an N-well may be formed in both region 50N and region 50P.

[0029] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , such as at about 10 17 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0030] After the implantation of region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant is performed in region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity can be boron, BF2, indium, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , such as at about 10 17 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0031] After implantation of regions 50N and 50P, an anneal may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fin may be doped in situ during growth, which may avoid implantation, although in-situ and implantation doping may be used together.

[0032] exist Figure 3 In the embodiment of the present invention, a dummy gate dielectric 60 is formed over the fin 52, and a dummy gate electrode 62 is formed over the dummy gate dielectric 60. The dummy gate dielectric 60 and the dummy gate electrode 62 may be collectively referred to as a dummy gate stack. The dummy gate stack extends along the sidewalls and top surface of the fin 52.

[0033] As an example of forming the dummy gate dielectric 60 and dummy gate electrode 62, a dummy dielectric layer is formed on the fin 52. The dummy dielectric layer 58 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed over the dummy dielectric layer, and a mask layer is formed over the dummy gate layer. The dummy gate layer 60 may be deposited over the dummy dielectric layer 58 and then planarized, such as by CMP. The mask layer may be deposited over the dummy gate layer. The dummy gate layer may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art for depositing conductive materials. The dummy gate layer may be made of other materials having high etch selectivity to etching of the STI regions 56. The mask layer may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer and a single mask layer are formed across regions 50N and 50P. In some embodiments, a dummy dielectric layer can be deposited such that the dummy dielectric layer covers the STI region 56 extending between the dummy gate layer and the STI region 56. The mask layer is then patterned using acceptable photolithography and etching techniques to form a mask 64. The pattern of mask 64 is then transferred to the dummy gate layer using acceptable etching techniques to form a dummy gate electrode 62. The pattern of mask 64 is further transferred to the dummy dielectric layer to form a dummy gate dielectric 60. The dummy gate electrode 62 covers the corresponding channel region 58 of the fin 52. The dummy gate electrode 62 may also have a length direction that is substantially perpendicular (within process limitations) to the length direction of the corresponding fin 52.

[0034] exist Figure 4A and Figure 4BIn the embodiment of the present invention, gate spacers 66 are formed on the exposed surfaces of the dummy gate electrode 62, the mask 64 and / or the fin 52. The gate spacers 66 can be formed by conformal deposition of an insulating material and subsequent etching of the insulating material. The insulating material of the gate spacers 66 can be silicon nitride, silicon carbonitride, silicon carbon oxynitride, combinations thereof, or the like, and can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. Once formed, the insulating material can be etched, for example, by wet etching to form the gate spacers 66. The etching of the gate spacers 66 can be anisotropic. After etching, the gate spacers 66 can have curved sidewalls (as shown) or can have straight sidewalls (not shown).

[0035] In some embodiments, gate spacer 66 is formed from one or more silicon oxycarbonitride layers (such as two silicon oxycarbonitride layers). In some embodiments, each silicon oxycarbonitride layer has a composition of approximately 34% silicon by mass, 36% oxygen by mass, 8% carbon by mass, and 21% nitrogen by mass. The silicon oxycarbonitride layers can be deposited using a dielectric material precursor including a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., oxygen (O2)), a carbon source precursor (e.g., propylene (C3H6)), and a nitrogen source precursor (e.g., ammonia (NH3)). In embodiments where deposition is performed by CVD, the composition of the silicon oxycarbonitride layers can be controlled by controlling the flow rates of the source precursors during CVD. For example, a silicon source precursor may be dispensed at a rate within a range of about 100 sccm to about 1000 sccm, an oxygen source precursor may be dispensed at a rate within a range of about 1000 sccm to about 20,000 sccm, a carbon source precursor may be dispensed at a rate within a range of about 1000 sccm to about 10,000 sccm, and a nitrogen source precursor may be dispensed at a rate within a range of about 5,000 sccm to about 30,000 sccm. Once formed, the silicon oxycarbonitride layer may be etched as described above to form gate spacers 66.

[0036] Prior to or during the formation of gate spacers 66, implantation for lightly doped source / drain (LDD) regions 68 may be performed. In embodiments having different device types, similar to the implantation discussed, a mask, such as a photoresist, may be formed over region 50N while exposing region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into the exposed fins 52 in region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over region 50P while exposing region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into the exposed fins 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a density of approximately 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0037] Epitaxial source / drain regions 70 are then formed in the fins 52 to apply stress in the corresponding channel regions 58, thereby improving performance. The epitaxial source / drain regions 70 are formed in the fins 52 such that each dummy gate electrode 62 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 70. The epitaxial source / drain regions 70 extend into and may also penetrate the LDD regions 68. In some embodiments, gate spacers 66 are used to offset the epitaxial source / drain regions 70 from the dummy gate electrodes 62 by an appropriate lateral distance so that the epitaxial source / drain regions 70 do not short-circuit the gate of the final FinFET that is subsequently formed.

[0038] Epitaxial source / drain regions 70 in region 50N (e.g., an NMOS region) can be formed by masking region 50P, such as a PMOS region, and etching the source / drain regions of fin 52 in region 50N to form recesses in fin 52. Epitaxial source / drain regions 70 in region 50N are then epitaxially grown in the recesses. Epitaxial source / drain regions 70 can include any acceptable material, such as that suitable for n-type FinFETs. For example, if fin 52 is silicon, epitaxial source / drain regions 70 in region 50N can include a material that imparts tensile strain in channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. Epitaxial source / drain regions 70 in region 50N can have surfaces elevated from corresponding surfaces of fin 52 and can have facets.

[0039] Epitaxial source / drain regions 70 in region 50P (e.g., a PMOS region) can be formed by masking region 50N, such as an NMOS region, and etching the source / drain regions of fin 52 in region 50P to form recesses in fin 52. Epitaxial source / drain regions 70 in region 50P are then epitaxially grown in the recesses. Epitaxial source / drain regions 70 can include any acceptable material, such as that suitable for p-type FinFETs. For example, if fin 52 is silicon, epitaxial source / drain regions 70 in region 50P can include a material that imposes compressive strain in channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, etc. Epitaxial source / drain regions 70 in region 50P can also have surfaces elevated from the corresponding surfaces of fin 52 and can be faceted.

[0040] The epitaxial source / drain regions 70 and / or fins 52 may be implanted with dopants to form source / drain regions similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a thickness between about 10 19 cm -3 With about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 70 can be doped in situ during growth.

[0041] As a result of the epitaxial process used to form epitaxial source / drain regions 70 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets allow adjacent epitaxial source / drain regions 70 of the same FinFET to merge, e.g., Figure 4C In other embodiments, as shown Figure 4D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 70 remain separated. Figure 4C and Figure 4D In the embodiment shown, gate spacers 66 are formed to cover portions of the sidewalls of fins 52 that extend over STI regions 56, thereby preventing epitaxial growth. In some other embodiments, the etch used to form gate spacers 66 can be tailored to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI regions 56.

[0042] exist Figure 5A and Figure 5BIn the embodiment of the present invention, a first ILD layer 82 is deposited over the intermediate structure. The first ILD layer 82 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include silicate glass, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 80 is disposed between the first ILD layer 82 and the epitaxial source / drain regions 70, the gate spacers 66, and the mask 64. The CESL 80 can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having a different etch rate than the material of the overlying first ILD layer 82.

[0043] exist Figure 6A and Figure 6B During the planarization process, a planarization process such as CMP may be performed to make the upper surface of the first ILD layer 82 flush with the upper surface of the dummy gate electrode 62 or the mask 64. The planarization process may also remove the mask 64 on the dummy gate electrode 62 and the portion of the gate spacer 66 along the sidewalls of the mask 64. After the planarization process, the top surfaces of the dummy gate electrode 62, the gate spacer 66, and the first ILD layer 82 are flush. Therefore, the top surface of the dummy gate electrode 62 is exposed through the first ILD layer 82. In some embodiments, the mask 64 may be retained, in which case the planarization process makes the top surface of the first ILD layer 82 flush with the top surface of the mask 64.

[0044] exist Figure 7A and Figure 7B In the embodiment of the present invention, the dummy gate electrode 62 and the optional dummy gate dielectric 60 are removed and replaced by a replacement gate 90. The replacement gate 90 includes a gate dielectric 92 and a gate electrode 94. As discussed further below, the replacement gate 90 is formed in a funnel shape, wherein a lower portion of the replacement gate 90 has parallel opposing sidewalls and an upper portion of the replacement gate 90 has inclined opposing sidewalls. Forming the replacement gate 90 in a funnel shape helps avoid the formation of a seam (or void) in the gate electrode 94, which can improve the work function of the gate electrode 94 and reduce the internal gate resistance (R g ). Therefore, the performance and yield of the obtained FinFET can be improved.

[0045] Figures 8A to 8G are various views of intermediate stages of a process for forming a replacement gate 90 according to some embodiments. Figure 7A50R in FIG. In the illustrated process, the dummy gate dielectric 60 and the dummy gate electrode 62 are removed and replaced with a replacement gate 90. In some embodiments, the dummy gate dielectric 60 is removed in a first region of the die (e.g., the core logic region) and remains in a second region of the die (e.g., the input / output region). In other words, the illustrated gate replacement process can be performed in the first region of the die (e.g., the core logic region), and a gate replacement process without removing the dummy gate dielectric 60 can be performed in the second region of the die (e.g., the input / output region).

[0046] exist Figure 8A In one or more etching steps, the dummy gate electrode 62 and the mask 64 (if present) are removed, thereby forming recesses 96. In some embodiments, the dummy gate electrode 62 is removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using a reactive gas that selectively etches the dummy gate electrode 62 without etching the first ILD layer 82 or the gate spacers 66. During the removal, the dummy gate dielectric 60 can serve as an etch stop when etching the dummy gate electrode 62. Each recess 96 exposes the dummy gate dielectric 60 and covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 70.

[0047] Recess 96 can be very small. For example, recess 96 can have a width W2 in the range of about 10 nm to about 25 nm, and can have a height H2 in the range of about 6 nm to about 90 nm. The width W2 of recess 96 corresponds to the length of the corresponding channel region 58. Forming the channel region 58 (and recess 96) to a shorter length can improve the performance of the resulting FinFET. However, forming the channel region 58 to a shorter length causes recess 96 to have a high aspect ratio (e.g., the ratio of height H2 to width W2). When recess 96 has a high aspect ratio, seams (or voids) may form in the material deposited in recess 96. As discussed further below, recess 96 will be widened to have a funnel shape, which can help avoid the formation of such seams.

[0048] exist Figure 8BIn the embodiment of the present invention, impurities are implanted into the first region of the gate spacer 66 to change the etch rate of the first region of the gate spacer 66 as compared to the second region of the gate spacer that is not implanted with impurities. As discussed in more detail below, the first region of the gate spacer 66 is etched to widen the recess 96 to reduce or prevent the formation of voids or seams when the recess 96 is subsequently filled. During / after the impurity implantation, the second region of the gate spacer 66 remains unchanged or changes little. In an embodiment where the gate spacer 66 includes silicon oxycarbonitride as described above, the impurity can be oxygen and is implanted by a plasma oxidation process. The plasma oxidation process oxidizes the region 66O of the gate spacer 66, while the unoxidized region 66N of the gate spacer 66 is not affected by the plasma oxidation process.

[0049] The oxidized regions 66O of the gate spacers 66 are enriched with oxygen. For example, both the oxidized regions 66O and the unoxidized regions 66N of the gate spacers 66 may include silicon oxycarbonitride, wherein, after implantation, the oxidized regions 66O have a greater oxygen concentration (e.g., mass percentage) than the unoxidized regions 66N of the gate spacers 66. In some embodiments, the unoxidized regions 66N of the gate spacers 66 retain their initial oxygen concentration. As discussed further below, a selective etching is subsequently performed on the doped (e.g., oxygen-rich) regions to remove the oxidized regions 66O of the gate spacers 66, thereby widening the recess 96. During the plasma oxidation process, the CESL 80 and the first ILD layer 82 may also be implanted with oxygen; however, since these layers are formed of different materials than the gate spacers 66, their etch selectivity is not significantly altered.

[0050] The plasma oxidation process can be performed by implantation. Implantation can be performed in a chamber in which a chuck supports the substrate 50. A precursor gas is supplied to the chamber, and a plasma generator can be used to generate plasma from the precursor gas. The plasma generator can be an inductively coupled plasma (CIP) generator, a capacitively coupled plasma (CCP) generator, a remote plasma generator, or the like.

[0051] During the plasma oxidation process, a source gas is provided (e.g., flowed) over the substrate 50. The source gas includes an oxygen source precursor gas (e.g., oxygen (O2)), an optional nitrogen source precursor gas (e.g., nitrogen (N2)), and a carrier gas (e.g., xenon, helium, argon, neon, krypton, radon, etc., or a combination thereof). For example, in some embodiments, the source gas includes oxygen, argon, and helium. In such embodiments, the oxygen source precursor gas is provided at a flow rate in a range of about 10 sccm to about 1000 sccm; the nitrogen source precursor gas, if present, is provided at a flow rate in a range of about 10 sccm to about 1000 sccm; and the carrier gas is provided at a flow rate in a range of about 10 sccm to about 1000 sccm.

[0052] The plasma generator generates radio frequency power to generate plasma from a gas source. The plasma includes oxygen ions 98 (O + ) and oxygen free radicals 100 (O * ). A DC bias voltage is generated between the plasma generator and the chuck supporting the substrate 50. The DC bias voltage is a high voltage negative offset and is pulsed to perform the implantation. Oxygen ions 98 are accelerated on the plasma by the DC bias voltage and implanted into the gate spacer 66 to form the oxidized region 66O. The DC bias voltage may be as high as about 100 kV. In such an embodiment, the implantation energy of oxygen obtained may be as high as about 40 keV. The plasma oxidation process may be performed for a duration in the range of about 10 seconds to about 120 seconds, thereby obtaining an implanted oxygen dose of about 10 15 cm -3 to about 10 19 cm -3 within the range.

[0053] During the plasma oxidation process, oxygen ions 98 collide with oxygen radicals 100, which can result in low implant directionality, thereby creating shadows during implantation. In other words, implantation is performed in a non-directional manner. According to some embodiments, the generated plasma includes few oxygen ions 98 and many oxygen radicals 100. For example, the generated plasma may contain approximately 0.1% to approximately 10% oxygen ions 98 and approximately 90% to approximately 99.9% oxygen radicals 100. Generating a plasma with many oxygen radicals 100 causes the oxygen ions 98 to collide with more oxygen radicals 100 during implantation, thereby increasing the amount of shadows and resulting in fewer oxygen ions 98 being directed toward the dummy gate dielectric 60. As a result, the majority of the oxygen ions 98 are implanted at an acute angle relative to a major surface of the structure (e.g., the topmost surface of the first ILD layer 82 or the major surface of the substrate 50). The angle of incidence can be very small, such as in the range of approximately 3 degrees to approximately 50 degrees.

[0054] By controlling the environment in which the plasma is generated, the amount of shadowing during the plasma oxidation process can be increased. Specifically, temperature, pressure, and RF power can all affect the amount of oxygen ions 98 and oxygen radicals 100 generated. According to some embodiments, the plasma is generated at low temperature, low pressure, and low RF power. For example, the plasma can be generated at a temperature ranging from about room temperature (e.g., about 20°C) to about 500°C, a pressure ranging from about 200 mTorr to about 300 mTorr, and an RF power ranging from about 200 watts to about 2000 watts. Such a plasma generation environment achieves a high amount of shadowing during implantation.

[0055] When the recess 96 has a high aspect ratio, the implantation of oxygen ions 98 with a large amount of shadowing results in fewer oxygen ions 98 being implanted in the lower portion of the recess 96 than in the upper portion of the recess 96. Due to the large amount of shadowing, an oxidized region 66O is formed by implanting the top surface and exposed sidewalls of the gate spacer 66. The oxidized region 66O has a right triangle shape. The shape of the gate spacer 66 resulting from the triangular region 66O will be discussed further below.

[0056] exist Figure 8C In one or more etching steps, the modified regions of gate spacers 66 (e.g., oxidized regions 66O) are removed, thereby widening recess 96. The etching steps are selective to the impurities implanted into gate spacers 66. For example, when gate spacers 66 comprise silicon oxycarbonitride and oxidized regions 66O are oxygen-rich regions, the etching process may include dry etching using a reactive gas selective for oxide. Because oxidized regions 66O have a greater oxygen concentration than unoxidized regions 66N, the etching process etches oxidized regions 66O at a greater rate than unoxidized regions 66N. For example, the etching rate of oxidized regions 66O may be approximately 2 to 100 times the etching rate of unoxidized regions 66N relative to the etching process. Furthermore, since dummy gate dielectric 60 and first ILD layer 82 are also oxides, they are also etched at a high rate by the etching process. In some embodiments, the etching process removes dummy gate dielectric 60 to deepen recess 96 and recesses first ILD layer 82 to form recess 102. The recess 102 may have a depth D2 in the range of about 10 nm to about 35 nm.

[0057] In some embodiments, the etching process is an anisotropic dry etch. For example, the dry etch can be performed using an etching gas containing ammonia (NH3) and hydrogen fluoride (HF). The etching gas can flow through the substrate 50, such as in the recess 96, without generating a plasma. The dry etch can be performed in a range of about 10 seconds to about 30 seconds at a temperature between about room temperature (e.g., about 20°C) and about 200°C. The dry etch converts the materials of the oxidized region 66O, the dummy gate dielectric 60, and the first ILD layer 82 into various byproducts. Depending on the etching temperature, the byproducts may include gaseous byproducts (e.g., carbon, oxygen) and solid byproducts (e.g., ammonium fluorosilicate). Following the dry etch, a heat treatment can be performed at a sufficiently high temperature and duration to sublimate the solid byproducts and generate additional gaseous byproducts. For example, the heat treatment can be performed at a temperature between about 100°C and about 150°C, at a pressure between about 5 mTorr and about 10 Torr, and for a duration between about 20 seconds and about 200 seconds. The heat treatment is performed at a higher temperature than the dry etch. Once the solid phase by-products sublime into gas phase by-products, they can be evacuated from the recess 96 by, for example, a vacuum.

[0058] In some embodiments, the etching process may include multiple cycles of dry etching and thermal treatment. The cycles may be performed until substantially all of the oxidized regions 66O and the dummy gate dielectric 60 are removed. For example, about 3 to about 6 cycles of dry etching and thermal treatment may be performed.

[0059] After the etching process, unoxidized regions 66N of gate spacer 66 remain. The remaining portion of gate spacer 66 includes an upper portion 66U and a lower portion 66L, which together form a funnel shape for recess 96. The width of upper portion 66U continuously decreases as it extends away from the top surface of fin 52. The width of lower portion 66L is constant as it extends away from the top surface of fin 52. In some embodiments, gate spacer 66 has an inner corner 66C at the interface between upper portion 66U and lower portion 66L. Inner corners 66C face each other and are exposed to recess 96. Inner corner 66C is arranged at a height H3 from the topmost surface of fin 52. Height H3 can be in a range of approximately 12 nm to approximately 30 nm. In some embodiments, the interface between upper portion 66U and lower portion 66L does not have a sharp inner corner 66C, but rather has a rounded inner corner 66C. Lower portion 66L has parallel opposing sidewalls separated by a width W3. Width W3 can be in a range of approximately 10 nm to approximately 25 nm. Because the unoxidized regions 66N of the gate spacers 66 may experience some etching, the width W3 is smaller than the width W2 (see FIG. Figure 8A ). The upper portion 66U has angled sidewalls that intersect at an apex. The opposing sidewalls of the upper portion 66U have an interior angle θ1. The angle θ1 may be in the range of about 1 degree to about 80 degrees. The respective vertices of the upper portion 66U are spaced apart by a width W4. The width W4 may be in the range of about 15 nm to about 40 nm. The vertices of the upper portion 66U are disposed at a height H4 from the topmost surface of the fin 52. The height H4 may be in the range of about 45 nm to about 90 nm. The height H4 is the final height of the recess 96 and is greater than the initial height H2 of the height of the recess 96 due to the removal of the dummy gate dielectric 60 (see Figure 8A ).

[0060] Widening the groove 96 to have a funnel shape can help avoid pinch-off effects when filling the groove 96, thereby preventing the formation of seams. The ratio of width W4 to width W3 can be in the range of about 1 to about 3, and the ratio of height H4 to height H3 can be in the range of about 1 to about 10. Such ratios help form a funnel shape that helps avoid pinch-off effects during subsequent filling. Values ​​greater than or less than these ratios may not form a funnel shape that avoids pinch-off effects during subsequent filling.

[0061] In some embodiments, the remaining portion of the gate spacer 66 further includes a protruding portion 66P that extends away from the lower portion 66L. Figure 8BWhen the fin 52 extends downwardly toward the dummy gate dielectric 60, such as when a small amount of oxygen ions 98 are implanted into the lower portion of the recess 96, a protrusion 66P may be formed. The width of the protrusion 66P is constant along a direction extending away from the top surface of the fin 52. The protrusions 66P may be spaced apart by a width W5, which may be in a range of approximately 10 nm to approximately 25 nm. The width W5 is less than the width W3.

[0062] exist Figure 8D , a gate dielectric layer 108 and a gate electrode layer 110 are formed. The gate dielectric layer 108 is conformally deposited in the recesses 96 and 102 , such as on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate spacers 66 . The gate dielectric layer 108 may also be formed on the top surface of the first ILD layer 82 . When the gate spacers 66 have protrusions 66P, the gate dielectric layer 108 has recesses 108N, where the protrusions 66P extend into the gate dielectric layer 108 . According to some embodiments, the gate dielectric layer 108 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 108 comprises a high-k dielectric material. In these embodiments, the gate dielectric layer 108 may have a k value greater than approximately 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 108 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess 96 , the gate dielectric layer 108 includes the material of the dummy gate dielectric 60 (eg, silicon oxide).

[0063] A gate electrode layer 110 is deposited over the gate dielectric layer 108 and fills the remaining portions of the recesses 96 and 102. When the gate dielectric layer 108 has a recess 108N, the gate electrode layer 110 has a recess 110N, wherein the recess 108N extends into the gate electrode layer 110. The gate electrode layer 110 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers. For example, although a single gate electrode layer 110 is shown, the gate electrode layer 110 may include any number of liner layers, any number of work function adjustment layers, and filler materials.

[0064] exist Figure 8E In the embodiment of the present invention, a planarization process such as CMP is performed to remove excess portions of the gate dielectric layer 108 and the gate electrode layer 110 outside the recess 96, for example, above the top surface of the first ILD layer 82. The remaining portions of the gate dielectric layer 108 and the gate electrode layer 110 form the gate dielectric layer 92 and the gate electrode 94, respectively, which together form the replacement gate 90. The replacement gate 90 may also be referred to as a "gate stack" or a "metal gate stack." The replacement gate 90 may extend along the sidewalls of the channel region 58 of the fin 52.

[0065] about Figure 8D and Figure 8E The steps discussed can be performed simultaneously in region 50N and region 50P, or can be performed separately in region 50N and region 50P. In some embodiments, gate dielectric 92 in each region can be formed by a different process, such that gate dielectric 92 can be a different material, and / or gate electrode 94 in each region can be formed by a different process, such that gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose appropriate areas.

[0066] After the planarization process, the replacement gate 90 has a reduced height H5, which is measured from the topmost surface of the fin 52. The height H5 can be in the range of about 10 nm to about 30 nm. In addition, after the planarization process, the replacement gate 90 has a width W6 measured at its topmost surface. The width W6 can be in the range of about 3 nm to about 300 nm. The width W6 of the replacement gate 90 can vary on the same substrate 50, such as in embodiments forming devices with different channel region lengths.

[0067] In some embodiments, the upper portion 66U of the gate spacer 66 remains after the planarization process, as shown in FIG. Figure 8E Thus, the height H5 is smaller than the height H4 and larger than the height H3 (see Figure 8C ), and the width W6 is smaller than the width W4 and larger than the width W3 (see Figure 8C ). Thus, the gate electrode 94 has an upper portion 94U and a lower portion 94L, which together form a funnel shape. The width of the upper portion 94U continuously increases in a direction extending away from the top surface of the fin 52. The width of the lower portion 94L is constant along the direction extending away from the top surface of the fin 52. The width of the gate dielectric 92 is constant along the sidewalls of the gate electrode 94. The gate electrode 94 has an inner angle 94C at the interface between the upper portion 94U and the lower portion 94L. The sidewalls of the gate electrode 94 form an inner angle θ2 at the inner angle 94C of the gate electrode 94, and the inner angle θ2 is the same as the inner angle θ1 (see Figure 8C ) is equal to 180 degrees. In other words, the interior angle θ2 may be in the range of about 181 degrees to about 260 degrees.

[0068] In some embodiments, as Figure 8F As shown, gate electrode 94 has a rounded internal angle at the interface between upper portion 94U and lower portion 94L, rather than a sharp internal angle. A plane parallel to the sidewalls of gate electrode 94 may still form an angle θ2 in the range of about 181 degrees to about 260 degrees, but the internal angle itself may not form such an angle.

[0069] In some embodiments, the upper portion 66U of the gate spacer 66 is removed by a planarization process, such as Figure 8G As shown. Thus, the height H5 is smaller than the height H3 (see Figure 8C ), and the width W6 is equal to the width W3 (see Figure 8C ). Thus, gate electrode 94 has straight sidewalls without inner corners. In such an embodiment, only lower portion 66L and protruding portion 66P of gate spacer 66 remain.

[0070] The discussion of Figures 8A to 8G However, it should be understood that any impurity can be injected (see Figure 8B ) into the gate spacer 66 to change the etch rate of portions of the gate spacer 66. An etch selective to the impurities may then be performed (see Figure 8C ) to remove the modified portion of the gate spacer 66 and widen the groove 96.

[0071] exist Figure 9A and Figure 9B In the embodiment of the present invention, a lower source / drain contact 112 is formed in the epitaxial source / drain region 70. An opening for the lower source / drain contact 112 is formed through the first ILD layer 82 and the CESL 80. The opening can be formed using acceptable photolithography and etching techniques. A liner layer, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the first ILD layer 82 and the replacement gate 90. The remaining liner layer and conductive material form the lower source / drain contact 112 in the opening. An annealing process can be performed to form a silicide 114 at the interface between the epitaxial source / drain region 70 and the lower source / drain contact 112. Lower source / drain contacts 112 are physically and electrically coupled to epitaxial source / drain regions 70 .

[0072] exist Figure 10A and Figure 10BIn the embodiment of the present invention, a second ILD layer 116 is deposited over the first ILD layer 82. In some embodiments, the second ILD layer 116 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 116 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. According to some embodiments, before forming the second ILD layer 116, the replacement gate 90 can be grooved to form a groove directly above the replacement gate 90 and between the opposing portions of the gate spacers 66. A gate mask 118 comprising one or more layers of a dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the groove, and a planarization process is then performed to remove excess dielectric material extending over the first ILD layer 82.

[0073] exist Figure 11A and Figure 11B In the embodiment of the present invention, upper source / drain contacts 120 and gate contact 122 are formed through second ILD layer 116. An opening for upper source / drain contacts 120 is formed through second ILD layer 116, and an opening for gate contact 122 is formed through second ILD layer 116 and gate mask 118. The opening can be formed using acceptable photolithography and etching techniques. A liner layer, such as a diffusion barrier layer, an adhesion layer, and a conductive material are formed in the opening. The liner layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of second ILD layer 116. The remaining liner layer and conductive material form upper source / drain contacts 120 and gate contact 122 in the opening. The upper source / drain contact 120 is physically and electrically coupled to the lower source / drain contact 112, and the gate contact 122 is physically and electrically coupled to the gate electrode 94. The upper source / drain contact 120 and the gate contact 122 can be formed in different processes or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the upper source / drain contact 120 and the gate contact 122 can be formed in different cross-sections, which can avoid shorting of the contacts.

[0074] Figure 11C is shown in more detail Figure 11A In an embodiment where the upper portion 66U of the gate spacer 66 is retained, a gate mask 118 may be formed extending into the upper portion 94U of the gate electrode 94. Thus, the gate mask 118 may have inclined sidewalls.

[0075] Embodiments can achieve advantages. Performing impurity implantation enables modification of the first region (e.g., region 66O) of gate spacer 66 without modifying the second region (e.g., region 66N) of gate spacer 66. Consequently, an etch selective to the impurities can be performed to remove the first region (e.g., region 66O) of gate spacer 66 while substantially leaving the second region (e.g., region 66N) of gate spacer 66 unetched. Thus, recess 96 has an upper portion whose width continuously increases in a direction away from fin 52. Forming recess 96 in this shape can help avoid pinch-off effects when filling recess 96 with gate electrode layer 110, particularly when gate electrode layer 110 includes multiple sublayers (such as multiple work function adjustment layers). Consequently, the gap fill window for gate electrode layer 110 can be improved, which can be particularly advantageous when forming a work function adjustment layer having a specific desired thickness. Improving the gap fill window for gate electrode layer 110 can avoid or reduce the formation of seams (or voids) in gate electrode 94. Consequently, the work function and internal gate resistance (R g ), thereby improving the performance and yield of the resulting FinFET.

[0076] In one embodiment, a method includes: forming a dummy gate dielectric over a semiconductor substrate; forming a dummy gate electrode over the dummy gate dielectric; depositing a gate spacer near the dummy gate electrode and the dummy gate dielectric; removing the dummy gate electrode to form a recess exposing a first region and a second region of the gate spacer; implanting impurities in the first region of the gate spacer to increase an etch rate of the first region of the gate spacer, the second region of the gate spacer not being modified by the implantation; removing the dummy gate dielectric and the first region of the gate spacer; and forming a replacement gate in the recess.

[0077] In some embodiments of the method, the impurity is oxygen, and implanting the impurity into the first region of the gate spacer includes: flowing a gas source comprising an oxygen source precursor gas and a carrier gas through the semiconductor substrate; generating a plasma from the gas source, the plasma comprising oxygen ions and oxygen radicals; and accelerating the oxygen ions in the plasma in a non-directional manner toward the gate spacers. In some embodiments of the method, the plasma comprises 0.1% to 10% oxygen ions and 90% to 99.9% oxygen radicals. In some embodiments of the method, the plasma is generated at a temperature in the range of 20° C. to 500° C., at a pressure in the range of 200 mTorr to 300 mTorr, and at an RF power in the range of 200 to 200 Watts. In some embodiments of the method, during implantation, a majority of the oxygen ions are accelerated toward the gate spacers at an acute angle relative to a major surface of the semiconductor substrate, the acute angle being in the range of 3 degrees to 50 degrees. In some embodiments of the method, removing the first region of the dummy gate dielectric and gate spacers includes: performing an anisotropic dry etch in the recess using an etching gas that converts the first region of the dummy gate dielectric and gate spacers into solid-phase byproducts; performing a heat treatment to sublimate the solid-phase byproducts into gas-phase byproducts; and extracting the gas-phase byproducts from the recess. In some embodiments of the method, the impurities include oxygen, the gate spacer includes silicon carbonitride, the etching gas includes ammonia and hydrogen fluoride, and the solid-phase byproducts include ammonium fluorosilicate. In some embodiments of the method, the anisotropic dry etch is performed at a first temperature, and the heat treatment is performed at a second temperature greater than the first temperature. In some embodiments of the method, the first temperature is in a range of 20°C to 200°C, and the second temperature is in a range of 100°C to 150°C. In some embodiments, the method further includes repeating the anisotropic dry etch and heat treatment for 3 to 6 cycles.

[0078] In an embodiment, a structure includes: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having a first sidewall and a second sidewall opposite the first sidewall; an epitaxial source / drain region adjacent to the first sidewall of the gate spacer; a gate dielectric extending along the second sidewall of the gate spacer and a top surface of the semiconductor substrate; and a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, wherein a first width of the upper portion continuously increases along a first direction extending away from the top surface of the semiconductor substrate, and a second width of the lower portion is constant along the first direction.

[0079] In some embodiments of the structure, the gate electrode includes an inner corner located at the interface of the upper and lower portions, and the sidewalls of the gate electrode form an angle at the inner corner. In some embodiments of the structure, the angle is in the range of 181 degrees to 260 degrees. In some embodiments of the structure, the gate spacer has an upper portion and a lower portion, the third width of the upper portion continuously decreases along the first direction, and the fourth width of the lower portion is constant along the first direction. In some embodiments of the structure, the gate spacer has a protrusion extending from the lower portion, the protrusion extending into the gate dielectric. In some embodiments, the structure further includes: a gate mask located above the gate electrode and the gate dielectric, the gate mask having inclined sidewalls; and a gate contact extending through the gate mask to contact the gate electrode.

[0080] In an embodiment, a structure includes: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion continuously decreasing along a first direction extending away from a top surface of the semiconductor substrate, and a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source / drain region adjacent to a second sidewall of the gate spacer.

[0081] In some embodiments of this structure, the gate spacer has a protruding portion extending from a first sidewall of a lower portion into the gate stack. In some embodiments of this structure, the gate stack includes: a gate dielectric extending along the first sidewall of the gate spacer and a top surface of the semiconductor substrate, the gate dielectric having a first recess, wherein the protruding portion of the gate spacer extends into the gate dielectric; and a gate electrode located on the gate dielectric, the gate electrode having a second recess, wherein the first recess of the gate dielectric extends into the gate electrode. In some embodiments of this structure, the gate spacer comprises silicon oxycarbon nitride.

[0082] In some embodiments, a method of forming a semiconductor device includes: forming a dummy gate dielectric over a semiconductor substrate; forming a dummy gate electrode over the dummy gate dielectric; depositing gate spacers near the dummy gate electrode and the dummy gate dielectric; removing the dummy gate electrode to form a recess; implanting an impurity into a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, with a second region of the gate spacer remaining unchanged by the implant; removing the dummy gate dielectric and the first region of the gate spacer; and forming a replacement gate in the recess, the replacement gate contacting the second region of the gate spacer. In some embodiments, the impurity is oxygen, and implanting the impurity into the first region of the gate spacer includes: flowing a gas source comprising an oxygen source precursor gas and a carrier gas through the semiconductor substrate; generating a plasma from the gas source, the plasma comprising oxygen ions and oxygen radicals; and accelerating the oxygen ions in the plasma in a non-directional manner toward the gate spacer. In some embodiments, the plasma comprises 0.1% to 1% oxygen ions and 90% to 99.9% oxygen radicals. In some embodiments, the plasma is generated at a temperature in a range of 20° C. to 500° C., at a pressure in a range of 200 mTorr to 300 mTorr, and at an RF power in a range of 200 to 2000 watts. In some embodiments, during implantation, a majority of the oxygen ions are accelerated toward the gate spacer at an acute angle relative to the main surface of the semiconductor substrate, the acute angle being in a range of 3 degrees to 50 degrees. In some embodiments, removing the dummy gate dielectric and the first region of the gate spacer comprises: performing an anisotropic dry etch in the recess using an etching gas that converts the dummy gate dielectric and the first region of the gate spacer into solid-phase byproducts; performing a thermal treatment to sublimate the solid-phase byproducts into gas-phase byproducts; and extracting the gas-phase byproducts from the recess. In some embodiments, the impurity comprises oxygen, the gate spacer comprises silicon carbonitride, the etching gas comprises ammonia and hydrogen fluoride, and the solid-phase byproducts comprise ammonium fluorosilicate. In some embodiments, the anisotropic dry etch is performed at a first temperature, and the thermal treatment is performed at a second temperature, the second temperature being greater than the first temperature. In some embodiments, the first temperature is in a range of 20° C. to 200° C., and the second temperature is in a range of 100° C. to 150° C. In some embodiments, the method further comprises repeating the anisotropic dry etching and the heat treatment for 3 to 6 cycles.

[0083] In some embodiments, a semiconductor structure includes: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having a first sidewall and a second sidewall opposite the first sidewall; an epitaxial source / drain region adjacent to the first sidewall of the gate spacer; a gate dielectric extending along the second sidewall of the gate spacer and a top surface of the semiconductor substrate; and a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, the upper portion having a first width that continuously increases along a first direction extending away from the top surface of the semiconductor substrate, and the lower portion having a second width that is constant along the first direction. In some embodiments, the gate electrode includes an inner corner at an interface between the upper and lower portions, the sidewalls of the gate electrode forming an angle at the inner corner. In some embodiments, the angle is in a range of 181 degrees to 260 degrees. In some embodiments, the gate spacer has an upper portion and a lower portion, the upper portion having a third width that continuously decreases along the first direction, and the lower portion having a fourth width that is constant along the first direction. In some embodiments, the gate spacer has a protrusion extending from the lower portion, the protrusion extending into the gate dielectric. In some embodiments, the method further includes: a gate mask located over the gate electrode and the gate dielectric, the gate mask having inclined sidewalls; and a gate contact extending through the gate mask to contact the gate electrode.

[0084] In some embodiments, a semiconductor structure includes: a semiconductor substrate; a gate spacer located above the semiconductor substrate, the gate spacer having an upper portion and a lower portion, the upper portion having a first width that continuously decreases along a first direction extending away from a top surface of the semiconductor substrate, and the lower portion having a second width that is constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and epitaxial source / drain regions adjacent to a second sidewall of the gate spacer. In some embodiments, the gate spacer has a protruding portion extending from the first sidewall of the lower portion of the gate stack. In some embodiments, the gate stack includes: a gate dielectric extending along the first sidewall of the gate spacer and the top surface of the semiconductor substrate, the gate dielectric having a first recess, wherein the protruding portion of the gate spacer extends into the gate dielectric; and a gate electrode located on the gate dielectric, the gate electrode having a second recess, wherein the first recess of the gate dielectric extends into the gate electrode. In some embodiments, the gate spacer comprises silicon oxycarbon nitride.

[0085] The components of several embodiments have been discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It will be appreciated by those skilled in the art that the present invention can be easily used as a basis to design or modify other processes and structures to achieve the same purpose and / or advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that these equivalent structures do not depart from the spirit and scope of the present invention, and that various variations, replacements, and changes may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming a dummy gate dielectric over the semiconductor substrate; forming a dummy gate electrode over the dummy gate dielectric; depositing a gate spacer adjacent to the dummy gate electrode and the dummy gate dielectric; removing the dummy gate electrode to form a groove; implanting impurities into a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, wherein a second region of the gate spacer is not altered by the implantation; removing the dummy gate dielectric and the first region of the gate spacer; as well as forming a replacement gate in the recess, the replacement gate contacting the second region of the gate spacer; Wherein, the impurity is oxygen, and implanting the impurity into the first region of the gate spacer comprises: flowing a source gas comprising an oxygen source precursor gas and a carrier gas through the semiconductor substrate; generating a plasma from the gas source, the plasma comprising oxygen ions and oxygen radicals; and Oxygen ions in the plasma are accelerated in a non-directional manner toward the gate spacers.

2. The method according to claim 1, wherein The oxygen source precursor gas is provided at a flow rate in a range of 10 sccm to 1000 sccm; and the carrier gas is provided at a flow rate in a range of 10 sccm to 1000 sccm.

3. The method according to claim 1, wherein The plasma contains 0.1% to 1% oxygen ions and 90% to 99.9% oxygen radicals.

4. The method according to claim 1, wherein The plasma is generated at a temperature in a range of 20° C. to 500° C., at a pressure in a range of 200 mTorr to 300 mTorr, and at an RF power in a range of 200 to 2000 Watts. 5 . The method of claim 1 , wherein during the implantation, most oxygen ions are accelerated toward the gate spacers at an acute angle relative to the main surface of the semiconductor substrate, the acute angle being in a range of 3 degrees to 50 degrees.

6. The method according to claim 1, wherein Removing the dummy gate dielectric and the first region of the gate spacer includes: performing an anisotropic dry etch using an etching gas in the groove, the etching gas converting the dummy gate dielectric and the first region of the gate spacer into solid phase byproducts; performing a heat treatment to sublime the solid-phase by-product into a gas-phase by-product; and The gaseous byproducts are withdrawn from the recess.

7. The method according to claim 6, wherein: The impurities include oxygen, the gate spacers include silicon carbonitride, the etching gas includes ammonia and hydrogen fluoride, and the solid-phase byproducts include ammonium fluorosilicate.

8. The method according to claim 6, wherein: The anisotropic dry etching is performed at a first temperature, and the heat treatment is performed at a second temperature, the second temperature being higher than the first temperature.

9. The method according to claim 8, wherein The first temperature is in the range of 20°C to 200°C, and the second temperature is in the range of 100°C to 150°C.

10. The method according to claim 6, further comprising: The anisotropic dry etching and the heat treatment are repeated 3 to 6 cycles.

11. A semiconductor structure comprising: semiconductor substrates; a gate spacer located above the semiconductor substrate, the gate spacer having a first sidewall and a second sidewall opposite to the first sidewall, wherein the gate spacer has an upper portion, a lower portion connected to the upper portion, and a protrusion extending from the lower portion of the gate spacer; an epitaxial source / drain region adjacent to the first sidewall of the gate spacer; A lightly doped source / drain region located below the protrusion, and a channel region located between the lightly doped source / drain regions; a gate dielectric extending along the second sidewall of the gate spacer and the top surface of the semiconductor substrate; and a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion of the gate electrode continuously increasing along a first direction extending away from the top surface of the semiconductor substrate, a second width of the lower portion of the gate electrode being constant along the first direction, wherein a first height of the lower portion of the gate electrode is greater than a second height of the protrusion; In which, the interface between the lightly doped source / drain region and the channel region is flush with the inner side wall of the protrusion, and the width W4 of the upper spacing of the gate spacer continuously increases along the first direction, the width W3 of the lower spacing of the gate spacer is constant along the first direction, and the width W5 of the protrusion spacing is constant along the first direction, and W3 is greater than W5.

12. The semiconductor structure according to claim 11, wherein The gate electrode includes an inner corner at an interface between an upper portion of the gate electrode and a lower portion of the gate electrode, and a sidewall of the gate electrode forms an angle at the inner corner.

13. The semiconductor structure according to claim 12, wherein: The angle is in the range of 181 degrees to 260 degrees.

14. The semiconductor structure according to claim 11, wherein A third width of the upper portion of the gate spacer continuously decreases along the first direction, and a fourth width of the lower portion of the gate spacer is constant along the first direction.

15. The semiconductor structure according to claim 14, wherein The protrusion extends into the gate dielectric.

16. The semiconductor structure of claim 11, further comprising: a gate mask positioned over the gate electrode and the gate dielectric, the gate mask having sloped sidewalls; as well as A gate contact extends through the gate mask to contact the gate electrode.

17. A semiconductor structure comprising: semiconductor substrates; a gate spacer located above the semiconductor substrate, the gate spacer having an upper portion and a lower portion connected to the upper portion and a protruding portion extending from the lower portion of the gate spacer, a first width of the upper portion continuously decreasing along a first direction extending away from a top surface of the semiconductor substrate, and a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and a top surface of the semiconductor substrate; as well as an epitaxial source / drain region adjacent to the second sidewall of the gate spacer; a lightly doped source / drain region located below the protruding portion, and a channel region located between the lightly doped source / drain regions; wherein the upper surface of the epitaxial source / drain region is higher than the upper surface of the protruding portion and lower than the upper surface of the gate stack; In which, the interface between the lightly doped source / drain region and the channel region is flush with the inner side wall of the protruding portion, and the width W4 of the upper spacing continuously increases along the first direction, the width W3 of the lower spacing is constant along the first direction, and the width W5 of the protruding portion spacing is constant along the first direction, and W3 is greater than W5.

18. The semiconductor structure according to claim 17, wherein The protrusion extends from a first sidewall of a lower portion of the gate stack.

19. The semiconductor structure according to claim 18, wherein The gate stack comprises: a gate dielectric extending along a first sidewall of the gate spacer and a top surface of the semiconductor substrate, the gate dielectric having a first recess, wherein a protruding portion of the gate spacer extends into the gate dielectric; and A gate electrode is located on the gate dielectric, the gate electrode having a second recess, wherein the first recess of the gate dielectric extends into the gate electrode.

20. The semiconductor structure of claim 17, wherein: The gate spacer includes silicon oxycarbon nitride.

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