Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device package including a transmit device and a first build-up circuit. The transmit device defines a cavity in the transmit device. The first build-up circuit is disposed on the transmit device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly, to a semiconductor device package including an antenna and a method of manufacturing the same. Background Technology

[0002] For example, mobile phone wireless communication devices typically include antennas for transmitting and receiving radio frequency (RF) signals. Similarly, wireless communication devices include antennas and communication modules, each mounted on different parts of a circuit board. In this approach, the antenna and communication module are manufactured separately and electrically connected to each other after being placed on the circuit board. Therefore, each component may incur separate manufacturing costs. Furthermore, it may be difficult to reduce the size of the wireless communication device to achieve a suitable compact product design. To reduce cost and package size, the Antenna in Package (AiP) approach is offered. Generally, organic substrates are commonly used in AiP systems. However, due to the limitations of organic substrate manufacturing processes, it is difficult to achieve fine pitch (less than 15 / 15 μm), and the relatively thick organic substrate hinders the miniaturization of AiP systems. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor device package includes an emitter and a first building circuit. The emitter defines a cavity within the emitter. The first building circuit is disposed on the emitter.

[0004] According to some embodiments of this disclosure, a semiconductor device package includes an emitter and an encapsulation. The emitter defines a cavity within the emitter. The encapsulation covers a side of the emitter and exposes a second surface of the emitter.

[0005] According to some embodiments of this disclosure, a method of manufacturing an optical module includes: setting up the transmitting device including a cavity in the transmitting device; and constructing a redistribution layer on the transmitting device. Attached Figure Description

[0006] Figure 1A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0007] Figure 1B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0008] Figure 1C A top view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0009] Figure 2 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0010] Figure 3A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0011] Figure 3B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0012] Figure 4A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0013] Figure 4B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0014] Figure 4C A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0015] Figure 4D A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0016] Figure 4E A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0017] Figure 4F A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0018] Figure 5A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0019] Figure 5B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0020] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0021] Common reference numerals are used throughout the accompanying drawings and detailed embodiments to indicate the same or similar components. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0022] Figure 1AThe illustration shows a cross-sectional view of a semiconductor device package 1A according to some embodiments of the present disclosure. The semiconductor device package 1A includes a carrier 10, circuit layers 11, 13, 14, 20, interconnect structures 12a, 12b, electronic components 15, electrical contacts 16, and package bodies 17, 18, and 19.

[0023] In some embodiments, the carrier 10 may be or comprise a glass substrate. In some embodiments, the carrier 10 may be or comprise a transmitting element having one or more transmitting components (e.g., an antenna, a light-emitting element, a sensor, or the like) disposed thereon. The carrier 10 may comprise conductive pads, traces, and interconnects (e.g., vias). In some embodiments, the carrier 10 may comprise a transparent material. In some embodiments, the carrier 10 may comprise an opaque material. Compared to organic substrates, controlling the thickness of a glass carrier is easier, which can contribute to the miniaturization of the semiconductor device package 1A. The carrier 10 comprises a material having a loss tangent or dissipation factor (Df) of less than about 0.005. The carrier 10 comprises a material having a loss tangent or Df of less than about 0.003. In some embodiments, the coefficient of thermal expansion (CTE) of the carrier 10 is in the range of about 0.5 to about 13. In some embodiments, the CTE of the carrier 10 is in the range of about 3.6 to about 8.5. In some embodiments, the thickness of the carrier 10 is in the range of about 100 μm to about 200 μm.

[0024] The carrier 10 has a surface 101, a surface 102 opposite to surface 101, and a side surface 103 extending between surface 101 and surface 102. A conductive layer 10p is disposed on surface 101 of the carrier 10. In some embodiments, the conductive layer 10p defines a patterned antenna, such as a directional antenna, an omnidirectional antenna, or an antenna array. For example, the conductive layer 10p defines a patch antenna. The conductive layer 10p is or contains a conductive material, such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or combinations of two or more of these. In some embodiments, the conductive layer 10p may be replaced by one or more light-emitting elements or sensors.

[0025] The circuit layer 20 (or the building block circuit) has a surface 201 facing away from the carrier 10, a surface 202 opposite to the surface 201, and a side surface 203 extending between the surfaces 201 and 202. The circuit layer 20 is disposed on the carrier 10 and spaced apart from the carrier 10 by a support element 10m. For example, the circuit layer 20, the support element 10m, and the carrier 10 define a space 10s. The support element 10m may be disposed at or adjacent to the periphery of the carrier 10. In some embodiments, the support element 10m may be formed of, or comprise, an attachment film, metal, or any other suitable material. In some embodiments, the thickness of the support element 10m is in the range of about 100 μm to about 200 μm. In some embodiments, the width of the circuit layer 20 is substantially the same as the width of the carrier 10. For example, the side surface 203 of the circuit layer 20 is substantially coplanar with the side surface 103 of the carrier 10. In other embodiments, depending on different design specifications, the width of circuit layer 20 may be greater than or less than the width of carrier 10.

[0026] In some embodiments, such as the top view illustrating the support element 10m and the carrier 10 Figure 1C As shown, the support element 10m can completely surround the periphery of the carrier 10. For example, the carrier 10, the support element 10m, and the circuit layer 20 can define a sealed space 10s. This prevents the package 17 from entering the space 10s during the manufacturing process. In other embodiments, if the package 17 is omitted, the support element 10m may not completely surround the periphery of the carrier 10. For example, there may be a gap between two adjacent support elements 10m, or the support element 10m may include one or more openings.

[0027] Circuit layer 20 includes one or more conductive layers (e.g., redistribution layers, RDLs, or conductive vias) 20c, 20v, and one or more dielectric layers 20p. A portion of the conductive layer (e.g., 20v) is covered or encapsulated by dielectric layer 20p, while another portion of the conductive layer (e.g., 20c) is exposed from dielectric layer 20p to provide electrical connectivity. In some embodiments, the surface of conductive layer 20c facing the carrier 10 and exposed from dielectric layer 20p is within a space 10s. In some embodiments, conductive layer 20c is patterned to correspond to conductive layer 10p. For example, conductive layer 20c is substantially aligned with conductive layer 10p. Conductive layer 20c is spaced apart from conductive layer 10p. Signals can be transmitted between conductive layer 20c and conductive layer 10p via coupling. The presence of a space 10s (e.g., an air cavity) between conductive layer 20c and conductive layer 10p enhances the performance of signal transmission between them. In some embodiments, circuit layer 20 may act as an intermediary layer. In some embodiments, the carrier 10, conductive layer 10p, support element 10m, and circuit layer 20 may also be referred to as a transmitting device.

[0028] In some embodiments, dielectric layer 20p may comprise polyimide (PI), prepreg composite fibers (e.g., a prepreg), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination of two or more of these, or the like. Examples of prepregs may comprise, but are not limited to, multilayer structures formed by stacking or laminating several prepreg materials / sheets. In some embodiments, depending on design specifications, any number of conductive layers 20c may be present. In some embodiments, conductive layer 20c is formed of Au, Ag, Cu, Pt, Pd, or alloys thereof, or comprises Au, Ag, Cu, Pt, Pd, or alloys thereof. In some embodiments, dielectric layer 20p and package 17 may comprise the same material. Alternatively, dielectric layer 20p and package 17 may comprise different materials.

[0029] A circuit layer 11 (or a building block circuit) is disposed on a circuit layer 20. The circuit layer 11 has a surface 111 facing away from the circuit layer 20, a surface 112 opposite to the surface 111, and a side surface 113 extending between the surfaces 111 and 112. The circuit layer 11 is electrically connected to the circuit layer 20. The surface 112 of the circuit layer 11 contacts the surface 201 of the circuit layer 20. In some embodiments, the side surface 113 of the circuit layer 11 and the side surface 203 of the circuit layer 20 (or the side surface 103 of the carrier 10) are non-coplanar or discontinuous. For example, the side surface 203 of the circuit layer 20 (or the side surface 103 of the carrier 10) is recessed from the side surface 113 of the circuit layer 11. For example, the width of the circuit layer 20 or the carrier 10 is smaller than the width of the circuit layer 11.

[0030] Circuit layer 11 includes one or more conductive layers (e.g., redistribution layers, RDLs) 11c and one or more dielectric layers 11d. A portion of the conductive layer 11c is covered or encapsulated by the dielectric layer 11d, while another portion of the conductive layer 11c is exposed from the dielectric layer 11d to provide electrical connectivity. In some embodiments, the surface of the conductive layer 11c facing the circuit layer 20 and exposed from the dielectric layer 11d contacts the surface 201 of the circuit layer 20. In some embodiments, the conductive layer 11c may be or include one or more antenna patterns, optical elements, sensors, or the like.

[0031] In some embodiments, dielectric layer 11d may comprise PI, prepreg composite fibers (e.g., prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination of two or more of these, or the like. Examples of prepregs may comprise, but are not limited to, multilayer structures formed by stacking or laminating several prepreg materials / sheets. In some embodiments, depending on design specifications, any number of conductive layers 11c may be present. In some embodiments, conductive layer 11c is formed of Au, Ag, Cu, Pt, Pd, or alloys thereof, or comprises Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0032] Package 17 is disposed on surface 112 of circuit layer 11. Package 17 covers carrier 10, support element 10m, and circuit layer 20. Package 17 covers side 103 of carrier 10, side 10m of support element 10m, and side 203 of circuit layer 20. Surface 102 of carrier 10 is exposed from package 17. For example, surface 102 of carrier 10 is substantially coplanar with surface 172 of package 17. In some embodiments, package 17 has side 173 that is substantially coplanar with side 113 of circuit layer 11. Side 103 of carrier 10 and side 203 of circuit layer 20 are recessed from side 173 of package 17. For example, there is a distance between side 103 of carrier 10 (or side 203 of circuit layer 20) and side 173 of package 17. In some embodiments, the encapsulation 17 comprises an epoxy resin containing filler, a molding material (e.g., epoxy molding material or other molding material), PI, a phenolic material or material, a material containing silicone dispersed therein, or a combination thereof.

[0033] One or more interconnect structures 12a (e.g., conductive pillars or conductive elements) are disposed on the surface 111 of the circuit layer 11. The interconnect structures 12a are electrically connected to the circuit layer 11 (i.e., electrically connected to the conductive layer 11c exposed from the dielectric layer 11d). In some embodiments, the interconnect structures 12a define an antenna structure. The interconnect structures 12a are or contain a conductive material, such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0034] Package 18 is disposed on surface 111 of circuit layer 11. Package 18 covers interconnect structure 12a. In some embodiments, package 18 has side surface 183 that is substantially coplanar with side surface 113 of circuit layer 11. In some embodiments, package 18 comprises epoxy resin containing filler, molding material (e.g., epoxy molding material or other molding material), PI, phenolic material or material, material containing silicone dispersed therein, or combinations thereof.

[0035] A circuit layer 13 (or a circuitry layer) is disposed on a package 18. The circuit layer 13 has one or more dielectric layers 13d and one or more conductive layers 13c. In some embodiments, the dielectric layer 13d may contain the same material as dielectric layer 11d. Alternatively, the dielectric layer 13d and dielectric layer 11d may contain different materials. The conductive layers 13c are electrically connected to the interconnect structure 12a. In some embodiments, depending on design specifications, any number of conductive layers 13c may be present.

[0036] One or more interconnect structures 12b (e.g., conductive pillars or conductive elements) are disposed on the surface of circuit layer 13 facing away from circuit layer 11. The interconnect structures 12b are electrically connected to circuit layer 13. The interconnect structures 12b are or contain conductive materials, such as metals or metal alloys. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0037] Electronic component 15 is disposed on the surface of circuit layer 13 facing away from circuit layer 11. Electronic component 15 may be an active electronic component, such as an integrated circuit (IC) chip or die. The active surface of electronic component 15 faces circuit layer 13. Electronic component 15 is electrically connected to circuit layer 13 (e.g., electrically connected to conductive layer 13c) via electrical contacts (e.g., solder balls), and the electrical connection may be achieved, for example, using flip-chip technology.

[0038] Package 19 is disposed on the surface of circuit layer 13 opposite to circuit layer 11. Package 19 covers interconnect structure 12b and electronic component 15. In some embodiments, package 19 has sides that are substantially coplanar with the sides of circuit layer 13. In some embodiments, package 19 comprises epoxy resin containing filler, molding material (e.g., epoxy molding material or other molding material), PI, phenolic material or material, material containing silicone dispersed therein, or combinations thereof.

[0039] A circuit layer 14 (or a circuitry layer) is disposed on a package 19. The circuit layer 14 has one or more dielectric layers 14d and one or more conductive layers 14c. In some embodiments, the dielectric layer 14d may contain the same material as dielectric layer 11d. Alternatively, the dielectric layer 14d and dielectric layer 11d may contain different materials. The conductive layers 14c are electrically connected to the interconnect structure 12b. In some embodiments, depending on design specifications, any number of conductive layers 14c may be present.

[0040] Electrical contact 16 is disposed on conductive layer 14c exposed from dielectric layer 14d. In some embodiments, electrical contact 16 may comprise solder or other suitable material.

[0041] In some embodiments, the side 103 of the carrier 10 may be coplanar with the side 113 of the circuit layer 11. For example, the side 103 of the carrier 10 is exposed from the package 17. This structure can be formed by: (i) setting a glass wafer; (ii) forming circuit layers 11, 13, 14, interconnect structures 12a, 12b, packages 17, 18, 19, and electronic components 15 on the glass wafer; and (iii) isomeric assembly of the circuit layers 11, 13, 14, packages 17, 18, 19, and carrier wafer. To meet the performance requirements of the antenna structure, the glass wafer should be selected from materials with a relatively low Dk (e.g., less than 5). However, a glass wafer with a relatively low Dk will also have a relatively low CTE (e.g., less than 13). Warpage problems will occur due to the CTE mismatch between the glass wafer and the package 17 (e.g., the package typically has a CTE greater than 20). As the size of the glass wafer increases, the warpage problem becomes more severe, which may lead to cracking or damage to the glass wafer.

[0042] According to such Figure 1A In the embodiment shown, the side 103 of the carrier 10 is recessed from the side 111 of the circuit layer 11. This structure can be formed by the following operations (details of which will be described later): (i) monomerizing the glass wafer to divide the glass wafer into multiple glass carriers (e.g., as shown in the figure). Figure 1A (ii) a carrier 10 shown in the figure; (iii) a glass carrier (separate from each other) attached to a release membrane, each glass carrier having a support element and circuitry on the support element to define a cavity; and (iv) circuit layers 11, 13, 14, interconnect structures 12a, 12b, package 17, 18, 19, and electronic components 15 formed on the glass carrier. Since the size of the partitioned glass carriers is much smaller than the size of the glass wafer, warpage problems are significantly mitigated. Furthermore, since signals are transmitted between conductive layers 10p and 20c via air (e.g., 10s) rather than the carrier 10, a low-Dk material does not need to be selected for the carrier 10. This increases the flexibility in selecting materials for the carrier 10 to meet other requirements (e.g., low Df, high hardness, or high CTE) to improve the electrical or structural performance of the semiconductor device package 1A.

[0043] Figure 1B This illustration shows a cross-sectional view of a semiconductor device package 1B according to some embodiments of the present disclosure. The semiconductor device package 1B is similar to... Figure 1A The semiconductor device package 1A shown in the figure is described below, and the differences therein are described.

[0044] The side 113 of the circuit layer 11 is recessed from the side 173 of the package 17 or the side 183 of the package 18. For example, there is a gap between the side 113 of the circuit layer 11 and the side 183 of the package 18. For example, the side 113 of the circuit layer 11 is covered by the package 18. For example, the width of the circuit layer 11 is smaller than the width of the package 18. The package 18 can directly contact the package 17.

[0045] In some embodiments, the side surface 113 of the circuit layer 11 may be connected to, for example, Figure 1B The side surface 203 of the circuit layer 20 shown is substantially coplanar. For example, the width of the circuit layer 11 is substantially the same as the width of the circuit layer 20. In some embodiments, the side surface 113 of the circuit layer 11 is not coplanar with the side surface 203 of the circuit layer 20 and the side surface 183 of the package 18. For example, the width of the circuit layer 11 is greater than the width of the circuit layer 20 and less than the width of the package 18.

[0046] Figure 2 This illustration shows a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. Except for the omission of circuit layer 20 in the semiconductor device package 2, the semiconductor device package 2 is similar to... Figure 1A The semiconductor device package 1A shown in the figure.

[0047] The surface of conductive layer 11c facing the carrier 10 and exposed from dielectric layer 11d is in space 10s. In some embodiments, the exposed portion of conductive layer 11c is patterned to correspond to conductive layer 10p. For example, conductive layer 11c and conductive layer 10p are substantially aligned. Conductive layer 11c and conductive layer 10p are spaced apart. Signals can be transmitted between conductive layer 11c and conductive layer 10p via coupling.

[0048] Figure 3A This illustration shows a cross-sectional view of a semiconductor device package 3A according to some embodiments of the present disclosure. The semiconductor device package 3A is similar to... Figure 1A The semiconductor device package 1A shown in the figure is described below, and the differences therein are described.

[0049] Electronic component 15 is disposed on the surface of circuit layer 13 facing circuit layer 14. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 13 via an adhesive layer 15a (e.g., die attachment film DAF). Electronic component 15 has an active surface facing circuit layer 14 and electrically connected to circuit layer 14 via an interconnect structure 15c (e.g., conductive pillars).

[0050] Figure 3B This illustration shows a cross-sectional view of a semiconductor device package 3B according to some embodiments of the present disclosure. The semiconductor device package 3B is similar to... Figure 1BThe semiconductor device package 1B shown in the figure is described below, and the differences therein are described.

[0051] Electronic component 15 is disposed on the surface of circuit layer 13 facing circuit layer 14. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 13 via an adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 14 and electrically connected to circuit layer 14 via an interconnection structure 15c (e.g., conductive pillar).

[0052] Figure 4A This illustration shows a cross-sectional view of a semiconductor device package 4A according to some embodiments of the present disclosure. Except that the semiconductor device package 4A further includes a protective layer 40, the semiconductor device package 4A is similar to... Figure 1A The semiconductor device package 1A shown in the figure. A protective layer 40 is disposed on the surface 172 of the package 17 and the surface 102 of the carrier 10. The protective layer 40 covers the surface 172 of the package 17 and the surface 102 of the carrier 10.

[0053] Figure 4B This illustration shows a cross-sectional view of a semiconductor device package 4B according to some embodiments of the present disclosure. Except that the semiconductor device package 4B further includes a protective layer 40, the semiconductor device package 4B is similar to... Figure 1B The semiconductor device package 1B shown in the figure has a protective layer 40 disposed on the surface 172 of the package 17 and the surface 102 of the carrier 10. The protective layer 40 covers the surface 172 of the package 17 and the surface 102 of the carrier 10.

[0054] Figure 4C This illustration shows a cross-sectional view of a semiconductor device package 4C according to some embodiments of the present disclosure. Except that the semiconductor device package 4C further includes a protective layer 40, the semiconductor device package 4C is similar to... Figure 3A The semiconductor device package 3A shown in the figure has a protective layer 40 disposed on the surface 172 of the package 17 and the surface 102 of the carrier 10. The protective layer 40 covers the surface 172 of the package 17 and the surface 102 of the carrier 10.

[0055] Figure 4D This illustration shows a cross-sectional view of a semiconductor device package 4D according to some embodiments of the present disclosure. The semiconductor device package 4D is similar to... Figure 4A The semiconductor device package 4A shown in the figure is described below, and the differences between them are described below.

[0056] A protective layer 40 is disposed on the surface 102 of the carrier 10. The protective layer 40 covers the surface 102 of the carrier 10. The width of the protective layer 40 is substantially the same as the width of the carrier 10. The protective layer 40 is disposed within the package 17. The package 17 covers the sides of the protective layer 40. The lower surface of the protective layer 40 is substantially coplanar with the surface 172 of the package.

[0057] Figure 4E This illustration shows a cross-sectional view of a semiconductor device package 4E according to some embodiments of the present disclosure. The semiconductor device package 4E is similar to... Figure 4B The semiconductor device package 4B is shown in the figure, and the differences between them are described below.

[0058] A protective layer 40 is disposed on the surface 102 of the carrier 10. The protective layer 40 covers the surface 102 of the carrier 10. The width of the protective layer 40 is substantially the same as the width of the carrier 10. The protective layer 40 is disposed within the package 17. The package 17 covers the sides of the protective layer 40. The lower surface of the protective layer 40 is substantially coplanar with the surface 172 of the package.

[0059] Figure 4F This illustration shows a cross-sectional view of a semiconductor device package 4F according to some embodiments of the present disclosure. The semiconductor device package 4F is similar to... Figure 4C The semiconductor device package 4C is shown in the figure, and the differences between them are described below.

[0060] A protective layer 40 is disposed on the surface 102 of the carrier 10. The protective layer 40 covers the surface 102 of the carrier 10. The width of the protective layer 40 is substantially the same as the width of the carrier 10. The protective layer 40 is disposed within the package 17. The package 17 covers the sides of the protective layer 40. The lower surface of the protective layer 40 is substantially coplanar with the surface 172 of the package.

[0061] Figure 5A This illustration shows a cross-sectional view of a semiconductor device package 5A according to some embodiments of the present disclosure. The semiconductor device package 5A is similar to... Figure 1A The semiconductor device package 1A shown in the figure is described below, and the differences therein are described.

[0062] Semiconductor device package 5A may comprise two parts 5A and 5B. Part 5A includes a circuit layer 13a, a package body 19, electronic components 15, a circuit layer 14, and an interconnect structure 12b. The circuit layer 13a includes one or more dielectric layers 13d1 and one or more conductive layers 13c1. Part 5B includes a circuit layer 13b, packages 17, 18, circuit layers 11, 20, and a carrier 10. The circuit layer 13b includes one or more dielectric layers 13d2 and one or more conductive layers 13c2. Parts 5A and 5B may be manufactured separately and then connected to each other via electrical contacts 51s (e.g., solder balls). This improves the yield of semiconductor device package 5A. In some embodiments, an undercoat 51h may be disposed between parts 5A and 5B to cover the electrical contacts 51s. In some embodiments, the width of part 5A is the same as the width of part 5B. Alternatively, depending on design specifications, the width of part 5A may be greater than or less than the width of part 5B.

[0063] Figure 5B This illustration shows a cross-sectional view of a semiconductor device package 5B according to some embodiments of the present disclosure. The semiconductor device package 5B is similar to... Figure 5A The semiconductor device package 5A shown in the figure is described below, and the differences between them are described below.

[0064] Electronic component 15 is disposed on the surface of circuit layer 14 facing circuit layer 13a. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 14 via an adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 13a and electrically connected to circuit layer 13a via an interconnection structure 15c (e.g., conductive pillar).

[0065] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure. In some embodiments, Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F The method described in the text can be used to manufacture Figure 1A Semiconductor device package 1A.

[0066] refer to Figure 6AA carrier 69 is provided. A circuit layer 20 comprising one or more conductive layers 20c, 20v and one or more dielectric layers 20p is formed on the carrier 69. A portion of the conductive layer (e.g., conductive layer 20c) is exposed from the dielectric layer 20p. In some embodiments, the conductive layers 20c, 20v may be antenna patterns, optical elements, or sensors. A support element 10m is formed on the circuit layer 20 (e.g., on the dielectric layer 20p of the circuit layer 20). In some embodiments, the circuit layer 20 may be formed by a fan-out process, a bump process, or other suitable photolithography process. For example, the circuit layer 20 may be formed by: (i) forming the dielectric layer 20p by a coating operation; and (ii) forming the conductive layers 20c, 20v by an exposure operation, a development operation, a plating operation, and the like. In some embodiments, the conductive layer 20v may be a conductive material formed in a via of the dielectric layer 20p. The via may be formed by a photolithography process.

[0067] refer to Figure 6B Multiple carriers 10 (e.g., glass carriers) are disposed on a support element 10m to define a space 10s (e.g., an air cavity). In some embodiments, the carriers 10 are formed by a monomerization operation of a wafer-type carrier (panel-type carrier or strip-type carrier) to divide the wafer-type carrier into multiple carriers 10. Each of the carriers 10 has a conductive layer 10p on the surface of the carrier 10 facing the circuit layer 20. In some embodiments, the conductive layer 10p may be an antenna pattern, an optical element, or a sensor. The conductive layer 10p is substantially aligned with the conductive layer 20c. The conductive layers 10p and 20c are located within the space 10s. A monomerization operation is then performed by the support element 10m and the circuit layer 20. Monomerization may be performed, for example, by using a dicing machine, laser, or other suitable cutting techniques. The carrier 69 is then removed.

[0068] refer to Figure 6C The carrier 10 is placed on the release membrane 68. The carriers 10 are separated from each other. For example, there is a gap or distance between any two adjacent carriers. Then, a reconing process is performed.

[0069] refer to Figure 6DA package 17 is formed on a release film 69 to cover the carrier 10, the support element 10m, and the circuit layer 20. In some embodiments, the package 17 is formed, for example, by transfer molding, compression, or any other suitable technique. A circuit layer 11 comprising one or more conductive layers 11c and one or more dielectric layers 11d is formed on the circuit layer 20. The dielectric layers 11d are formed by, for example, (but not limited to) photolithography. Interconnect structures 12a are formed on the circuit layer 11 to be electrically connected to the circuit layer 11. In some embodiments, the interconnect structures 12a can be formed by, for example, (but not limited to) plating. In some embodiments, the circuit layer 11 can be formed by fan-out, bumping, or other suitable photolithography processes.

[0070] Next, a package 18 is formed on the circuit layer 11 to cover the interconnect layer 12a. In some embodiments, the package 18 may be formed to completely cover the interconnect structure 12a. A portion of the package 18 is removed by, for example, grinding or any other suitable technique to expose the top portion of the interconnect structure 12a for electrical connection. In some embodiments, the package 18 is formed by, for example, transfer molding, compression or any other suitable technique.

[0071] refer to Figure 6E A circuit layer 13, comprising one or more conductive layers 13c and one or more dielectric layers 13d, is formed on the package 18 and electrically connected to an interconnect structure 12a exposed from the package 18. An electronic component 15 is then disposed on and electrically connected to the circuit layer 13. In some embodiments, the electronic component 15 may be connected to the circuit layer 13 via flip-chip technology or any other suitable process. In some embodiments, the circuit layer 13 may be formed via fan-out technology, bumping technology, or other suitable photolithography processes.

[0072] refer to Figure 6F Interconnect structure 12b is formed on circuit layer 13 for electrical connection to circuit layer 13. Package 19 is formed on circuit layer 13 to cover interconnect structure 12b and electronic component 15. In some embodiments, package 19 may be formed to completely cover interconnect structure 12b and electronic component 15. A portion of package 19 is removed by, for example, grinding or any other suitable technique to expose the top portion of interconnect structure 12b for electrical connection. In some embodiments, package 19 is formed by, for example, transfer molding, compression or any other suitable technique.

[0073] A circuit layer 14 comprising one or more conductive layers 14c and one or more dielectric layers 14d is formed on the package 19 and electrically connected to an interconnect structure 12b exposed from the package 19. In some embodiments, the circuit layer 14 may be formed by a fan-out process, a bump process or other suitable photolithography process.

[0074] Next, electrical contacts 16 are placed on the conductive layer 14c exposed from the dielectric layer 14d. Monomerization can be performed to isolate components such as... Figure 1A The semiconductor packaging equipment 1A shown herein is an individual semiconductor packaging device. That is, it is individualized through circuit layers 11, 13, 14 and packages 17, 18 and 19. Individualization can be performed, for example, by using a dicing machine, laser or other suitable cutting techniques.

[0075] As used herein, the terms “generally,” “approximately,” “about,” and “approximately” are used to indicate and explain small variations. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer being “generally uniform” may refer to a standard deviation of the average thickness of the film or layer less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces located within a few micrometers along the same plane, such as two surfaces located within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane. If the angle between two surfaces or components is, for example, 90° ± 10°, or ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°, then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "substantially," "approximately," and "about" can refer to situations where the event or situation occurs precisely, or situations where the event or situation occurs very approximately.

[0076] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component) and situations where one or more intervening components are located between the preceding and following components.

[0077] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials generally indicate those that exhibit very little or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material may vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0078] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0079] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between process reproductions in this disclosure and actual apparatuses due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to suit particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: A launching device, which defines a cavity within the launching device; A first construction circuit is disposed on the transmitting device, the first construction circuit having a first surface and a second surface opposite to the first surface, the second surface of the first construction circuit facing the transmitting device; Electronic components, which are disposed above the first surface of the first building circuit. The first set of conductive pillars is disposed above the first surface of the first building circuit; and A second package is disposed above the first surface of the first building circuit and covers the first set of conductive pillars, wherein a portion of the conductive pillars in the first set of conductive pillars fall within the projected area of ​​the electronic component on the transmitting device, and the remaining conductive pillars in the first set of conductive pillars fall outside the projected area of ​​the electronic component on the transmitting device. The width of the transmitting device is smaller than the width of the first constructing circuit. The transmitting device has a glass substrate containing a transparent material, the width of which is smaller than the width of the first constructed circuit.

2. The semiconductor device package of claim 1, wherein the side of the transmitting device is recessed from the side of the first building circuit, and the first surface of the transmitting device contacts the second surface of the first building circuit.

3. The semiconductor device package according to claim 1, wherein the coefficient of thermal expansion of the glass substrate is less than 13.

4. The semiconductor device package of claim 1, wherein the side of the transmitting device is substantially coplanar with the side of the first constructing circuit.

5. The semiconductor device package of claim 1, further comprising a first package covering a side of the transmitting device and exposing a second surface of a glass substrate of the transmitting device, the lower surface of the first package being substantially coplanar with the second surface of the glass substrate, wherein the transmitting device has a support element and a circuit layer, the support element completely sealing the cavity to prevent the first package from entering the cavity during the manufacturing process, wherein the first package simultaneously contacts a side of the glass substrate, the outermost side of the support element, the outermost side of the dielectric layer of the circuit layer, and the second surface of the first circuitry.

6. The semiconductor device package of claim 1, wherein the transmitting device comprises: A first emitting layer comprising the transparent material; A support element is disposed on the first emission layer; and The second emission layer is mounted on the support element.

7. The semiconductor device package according to claim 6, wherein... The first emission layer includes a first emission pattern; The second emission layer includes a dielectric layer, a via penetrating the dielectric layer, and a second emission pattern connected to the via; and The second emission pattern faces the first emission pattern and is substantially aligned with the first emission pattern. The first construction circuit includes an antenna pattern that is in close contact with and substantially aligned with the second transmission pattern.

8. The semiconductor device package of claim 7, further comprising a first package body covering the side of the support element, the side of the first emitter layer and the side of the second emitter layer, the first package body contacting the second surface of the first building circuit, the outer side of the first package body being substantially coplanar with the outer side of the first building circuit.

9. The semiconductor device package of claim 8, wherein the dielectric layer of the first package and the second emitter layer comprises the same material.

10. The semiconductor device package of claim 7, wherein the support element is in direct contact with the dielectric layer of the second emitter layer.

11. The semiconductor device package of claim 6, wherein the support element may completely or partially surround the cavity.

12. The semiconductor device package of claim 1, further comprising: A second construction circuit is disposed on the second package; The second set of conductive posts is disposed on the second building circuit, and the second set of conductive posts is substantially aligned with the first set of conductive posts; and A third package is disposed on the second building circuit and covers the electronic component and the second set of conductive pillars, the electronic component having a back surface that contacts the third package.

13. The semiconductor device package of claim 12, wherein the electronic component is disposed on the second building circuit and covered by the third package, the electronic component having an active surface facing the second building circuit and electrically connected to the second building circuit, the active surface of the electronic component being relative to the back surface of the electronic component.

14. A semiconductor device package comprising: A launching device, which defines a cavity within the launching device; A first encapsulation body covers the side of the transmitting device and exposes the second surface of the transmitting device; and A first construction circuit is disposed on the transmitting device and the first encapsulation body. The first construction circuit has a first surface and a second surface opposite to the first surface. The second surface of the first construction circuit faces the transmitting device and the first encapsulation body. Electronic components, which are disposed above the first surface of the first building circuit. The first set of conductive pillars is disposed above the first surface of the first building circuit; and A second encapsulation is disposed above the first surface of the first building circuit and covers the first set of conductive pillars, wherein a portion of the conductive pillars in the first set of conductive pillars fall within the projected area of ​​the electronic component on the transmitting device, and the remaining conductive pillars in the first set of conductive pillars fall outside the projected area of ​​the electronic component on the transmitting device. The width of the transmitting device is smaller than the width of the first constructing circuit. The transmitting device has a glass substrate containing a transparent material, the width of which is smaller than the width of the first constructed circuit.

15. The semiconductor device package of claim 14, wherein the transmitting device comprises: A support element, which is disposed on the glass substrate, completely seals the cavity; and The second emission layer is mounted on the support element.

16. The semiconductor device package of claim 15, wherein... The glass substrate includes a first emission pattern; The second emission layer includes a dielectric layer, a via penetrating the dielectric layer, and a second emission pattern connected to the via; and The second emission pattern faces the first emission pattern and is substantially aligned with the first emission pattern.

17. The semiconductor device package according to claim 15, The support element completely surrounds the cavity, and The semiconductor device package further includes: A second construction circuit is disposed on the second encapsulation body; The second set of conductive posts is disposed on the second building circuit, and the second set of conductive posts is substantially aligned with the first set of conductive posts; A third encapsulation is disposed on the second building circuit and covers the electronic components and the second set of conductive pillars; A third construction circuit is disposed on the third encapsulation; and A third package is disposed on the third building block circuit.

18. A method for manufacturing an optical module, the method comprising: (a) The transmitting device includes a cavity in the transmitting device; (b) A redistribution layer is constructed on the transmitting device to form a construction circuit having a first surface and a second surface opposite to the first surface, the second surface of the construction circuit facing the transmitting device, and the transmitting device having a glass substrate comprising a transparent material, the width of the glass substrate of the transmitting device being smaller than the width of the construction circuit; and (c) An electronic component, a conductive pillar, and a package are disposed above the first surface of the circuit, wherein the package covers the conductive pillar; A portion of the conductive pillars fall within the projected area of ​​the electronic component on the transmitting device, while the remaining conductive pillars fall outside the projected area of ​​the electronic component on the transmitting device.

19. The method of claim 18, further comprising forming an encapsulation to cover the sides of the transmitting device prior to operation (b), wherein the transmitting device comprises: The glass substrate comprising a transparent material, the glass substrate comprising a first emission pattern; A support element is disposed on the glass substrate, and the support element completely seals the cavity; and The second emission layer is mounted on the support element. The second emission layer includes a dielectric layer, a via penetrating the dielectric layer, and a second emission pattern connected to the via; and The second emission pattern faces the first emission pattern and is substantially aligned with the first emission pattern.

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