Semiconductor package including chips stacked on a base module

Abstract

A semiconductor package including chips stacked on a base module. A semiconductor package includes: a package substrate; a base module disposed on the package substrate and configured to include an intermediate chip; bonding wires connecting the intermediate chip to the package substrate; a lower left chip disposed between the base module and the package substrate; and an upper left chip disposed on the base module. The base module also includes: an encapsulant encapsulating the intermediate chip; a through-hole electrically connected to the upper left chip; and a redistribution line RDL connecting the intermediate chip to the through-hole and extending to provide a connection portion, the connection portion being spaced apart from the through-hole and connected to the lower left chip.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packaging technology, and more particularly, to a semiconductor package including a plurality of chips stacked on a base module. Background Art

[0002] Recently, a lot of efforts have been focused on integrating multiple semiconductor chips into one semiconductor package. That is, attempts have been made to increase the package integration density to achieve high-performance semiconductor packages that process a large amount of data at high speed. For example, a stacked package structure including multiple vertically stacked semiconductor chips has been proposed to achieve high-performance semiconductor packages. Various interconnect structures have been proposed to electrically connect the vertically stacked semiconductor chips to each other. Summary of the invention

[0003] According to an embodiment, a semiconductor package includes: a package substrate; a base module disposed on the package substrate; a lower left chip and a lower right chip disposed between the base module and the package substrate; and an upper left chip disposed on the base module opposite to the lower left chip. The base module includes: an intermediate chip having a first intermediate chip pad and a second intermediate chip pad; a sealant encapsulating the intermediate chip; a first through hole and a second through hole penetrating the sealant to be electrically connected to the upper left chip; and a first redistribution line (RDL) and a second RDL configured to connect the first intermediate chip pad and the second intermediate chip pad to corresponding through holes in the first through hole and the second through hole and configured to be electrically connected to the lower left chip and the lower right chip.

[0004] According to another embodiment, a semiconductor package includes: a package substrate; a base module, which is disposed on the package substrate and is configured to include an intermediate chip; a bonding wire, which connects the intermediate chip to the package substrate; a lower left chip, which is disposed between the base module and the package substrate; and an upper left chip, which is disposed on the base module opposite to the lower left chip. The intermediate chip includes: a first intermediate chip pad; a second intermediate chip pad; and a wire bonding pad, which is disposed to be spaced apart from the first intermediate chip pad and the second intermediate chip pad and connected to the bonding wire. The lower left chip includes a first lower left chip pad corresponding to the first intermediate chip pad and a second lower left chip pad corresponding to the second intermediate chip pad. The upper left chip includes a first upper left chip pad corresponding to the first intermediate chip pad and a second upper left chip pad corresponding to the second intermediate chip pad. The basic module also includes: a sealant that encapsulates the intermediate chip; a first through-hole and a second through-hole that penetrate the sealant to electrically connect to corresponding pads of the first upper left chip pad and the second upper left chip pad; a first redistribution line (RDL) that is configured to connect the first intermediate chip pad to the first through-hole and is configured to extend to provide a first connection portion that is spaced apart from the first through-hole and connected to the first lower left chip pad; and a second RDL that is configured to connect the second intermediate chip pad to the second through-hole and is configured to extend to provide a second connection portion that is disposed between the second through-hole and the first connection portion and connected to the second lower left chip pad.

[0005] According to another embodiment, a semiconductor package includes: a package substrate; a base module disposed on the package substrate and configured to include an intermediate chip; a bonding wire connecting the intermediate chip to the package substrate; a lower left chip disposed between the base module and the package substrate; and an upper left chip disposed on the base module. The base module also includes: a sealant encapsulating the intermediate chip; a through hole penetrating the sealant to electrically connect to the upper left chip; and a redistribution line (RDL) configured to connect the intermediate chip to the through hole and configured to extend to provide a connection portion that is spaced apart from the through hole and connected to the lower left chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0007] Figure 2 and Figure 3 It is shown that the Figure 1 A plan view of a basic module in a semiconductor package is shown.

[0008] Figure 4 It is shown that the Figure 1A plan view of the connection between the base module and the lower left chip in the semiconductor package shown.

[0009] Figure 5 It is shown that the Figure 1 A plan view of the connection between the base module and the lower right chip in the semiconductor package shown.

[0010] Figure 6 It is shown that the Figure 1 A plan view of the connection between the base module and the upper left chip in the semiconductor package shown.

[0011] Figure 7 It is shown that the Figure 1 A plan view of the connection between the base module and the upper right chip in the semiconductor package shown.

[0012] Figure 8 is a block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment.

[0013] Fig. 9 is a block diagram illustrating another electronic system including a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0014] The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be interpreted as being different according to the ordinary technicians in the field to which the embodiments belong. If defined in detail, the terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings as commonly understood by ordinary technicians in the field to which the embodiments belong.

[0015] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, rather than being used to limit the elements themselves or to mean a specific order.

[0016] It will also be understood that when an element or layer is referred to as being "on," "over," "under," "beneath," or "outside" another element or layer, the element or layer may be in direct contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" versus "directly between" or "adjacent" versus "directly adjacent").

[0017] Spatially relative terms such as "under," "beneath," "down," "above," "up," "top," "bottom," and the like may be used to describe the relationship of an element and / or feature to another element and / or feature (e.g., as shown in the figures). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as under and / or beneath other elements or features would be oriented as above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] In the following embodiments, the semiconductor package may include an electronic device such as a semiconductor chip or a semiconductor die. The semiconductor chip or semiconductor die may be obtained by separating a semiconductor substrate such as a wafer into multiple pieces using a dicing process. The semiconductor chip may correspond to a memory chip, a logic chip, an application specific integrated circuit (ASIC) chip, an application processor (AP), a graphics processing unit (GPU), a central processing unit (CPU), or a system chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND flash memory circuit, a NOR flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include a logic circuit integrated on a semiconductor substrate. The semiconductor package may be used in a communication system such as a mobile phone, an electronic system associated with biotechnology or health care, or a wearable electronic system. The semiconductor package may be applied to the Internet of Things (IoT).

[0019] Throughout the specification, the same reference numerals refer to the same elements. Even if a reference numeral is not mentioned or described with reference to one figure, the reference numeral may be mentioned or described with reference to another figure. In addition, even if a reference numeral is not shown in a figure, it may refer to the figure.

[0020] Figure 1 is a cross-sectional view showing a semiconductor package 10 according to an embodiment.

[0021] Reference Figure 1 The semiconductor package 10 may be configured to include a package substrate 100, a base module 200, a lower left chip 310, an upper left chip 410, and a package encapsulant 190. The semiconductor package 10 may be configured to further include a lower right chip 350 and an upper right chip 450.

[0022] The lower left chip 310 may be a chip located on the opposite side of the basic module 200 from the upper left chip 410, and the lower right chip 350 may be a chip located on the opposite side of the basic module 200 from the upper right chip 450. The lower left chip 310 and the lower right chip 350 may be chips disposed on the bottom surface of the basic module 200, and the upper left chip 410 and the upper right chip 450 may be chips disposed on the top surface of the basic module 200. The lower left chip 310 and the lower right chip 350 may be disposed symmetrically about a vertical line (not shown) passing through the center point of the basic module 200, and the upper left chip 410 and the upper right chip 450 may also be disposed symmetrically about a vertical line passing through the center point of the basic module 200. In the lower left chip 310, the lower right chip 350, the upper left chip 410, and the upper right chip 450, the terms "left", "right", "upper", and "lower" are used only to distinguish one chip from another chip.

[0023] The semiconductor package 10 may further include bonding wires 150 corresponding to connection members for electrically connecting the base module 200 to the package substrate 100. The semiconductor package 10 may further include inner connectors 500 corresponding to connection members for electrically connecting the base module 200 to the chips 310, 410, 350, and 450.

[0024] Some inner connectors 500 may be provided between the base module 200 and the lower left chip 310 to electrically connect the base module 200 to the lower left chip 310. Some other inner connectors 500 may be provided between the base module 200 and the lower right chip 350 to electrically connect the base module 200 to the lower right chip 350. In addition, other inner connectors 500 may be provided between the base module 200 and the upper left chip 410 and between the base module 200 and the upper right chip 450 to electrically connect the base module 200 to the upper left chip 410 and to electrically connect the base module 200 to the upper right chip 450. The inner connectors 500 may be conductive bumps.

[0025] The basic module 200 may be disposed to be vertically spaced apart from the package substrate 100. The lower left chip 310 and the lower right chip 350 may be laterally spaced apart from each other and may be disposed between the package substrate 100 and the basic module 200. The upper left chip 410 and the upper right chip 450 may be laterally spaced apart from each other and may be disposed on the top surface of the basic module 200 opposite to the lower left chip 310 and the lower right chip 350. The left portion of the basic module 200 may be located between the lower left chip 310 and the upper left chip 410, and the lower left chip 310 and the upper left chip 410 may partially overlap each other vertically.

[0026] Still refer to Figure 1, the basic module 200 may be configured to include the middle chip 210, the sealant 290, the through-hole 230, the first redistribution line (RDL) 260, and the second RDL 280. The basic module 200 may be a component that modularizes the middle chip 210 and the through-hole 230 through the sealant 290. The basic module 200 may be a component that provides a basic structure in which the upper left chip 410 and the upper right chip 450 are stacked.

[0027] The sealant 290 may be formed to encapsulate and protect the intermediate chip 210. The sealant 290 may be formed by molding an epoxy molding compound (EMC) material. The sealant 290 may be formed to expose the surface 210S of the intermediate chip 210. The basic module 200 may be disposed on the packaging substrate 100 so that the surface 210S of the intermediate chip 210 faces the packaging substrate 100. The sealant 290 may be a layer that is distinguished from the encapsulation sealant 190 and may serve as a basic sealant that provides the shape of the basic module 200. The encapsulation sealant 190 may be formed on the packaging substrate 100 to cover and protect the basic module 200, the lower left chip 310, the lower right chip 350, the upper left chip 410, and the upper right chip 450. The encapsulation sealant 190 may also be formed by molding an EMC material.

[0028] Figure 2 It is shown that the Figure 1 A plan view of the layout of the intermediate chip 210 and the through-vias 230 in the base module 200 is shown. Figure 3 It is shown that the Figure 1 A plan view of the layout of the first RDL 260 and the second RDL 280 in the base module 200 is shown. Figure 2 and Figure 3 is a plan view showing the base module 200 when viewed in the first direction V1.

[0029] Reference Figure 1 and Figure 2 , the basic module 200 may be configured to include an intermediate chip 210 and a through hole 230 disposed to be spaced apart from the intermediate chip 210. The intermediate chip 210 may be a semiconductor chip including a first intermediate chip pad 221 and a second intermediate chip pad 222 disposed on the surface 210S. Figure 2 An example is shown in which the first intermediate chip pad 221 and the second intermediate chip pad 222 are disposed adjacent to each other, but additional intermediate chip pads may be disposed on the surface 210S.

[0030] The first middle chip pad 221 and the second middle chip pad 222 may be connection terminals to which a data signal is applied to or output from the middle chip 210. Other chips (e.g., the lower left chip 310, the lower right chip 350, the upper left chip 410, and the upper right chip 450) may be electrically connected to the first middle chip pad 221 and the second middle chip pad 222 through the first RDL 260 and the second RDL 280. The first middle chip pad 221 and the second middle chip pad 222 may be connection terminals for the middle chip 210 to communicate with the lower left chip 310, the lower right chip 350, the upper left chip 410, and the upper right chip 450.

[0031] A wire bonding pad 225 may be additionally disposed on the surface 210S to be spaced apart from the first intermediate chip pad 221 and the second intermediate chip pad 222. The wire bonding pad 225 may be a connection terminal to which the bonding wire 150 is connected. When the bonding wire 150 electrically connects the wire bonding pad 225 to the package substrate 100, the intermediate chip 210 may be electrically connected to the package substrate 100. Additional wire bonding pads may be disposed adjacent to the wire bonding pad 225 or the first intermediate chip pad 221 and the second intermediate chip pad 222 on the surface 210S.

[0032] The through hole 230 may be provided to be spaced apart from the middle chip 210. The through hole 230 may be a vertical electrode that vertically penetrates the sealant 290. The through hole 230 may be formed to include a conductive material such as a copper material. The first through hole 231 and the second through hole 232 in the through hole 230 may be provided to be connected to the upper left chip 410. The third through hole 233 and the fourth through hole 234 in the through hole 230 may be provided to be connected to the upper right chip 450. The through hole 230 may provide a partial path for connecting the upper left chip 410 or the upper right chip 450 to the middle chip 210.

[0033] Reference Figure 3, the first RDL 260 and the second RDL 280 may extend to traverse the surface 210S of the intermediate chip 210 and reach a portion of the surface 290S of the sealant 290. The first RDL 260 may extend to overlap the first intermediate chip pad 221, and may be a conductive pattern electrically connected to the first intermediate chip pad 221. The first RDL 260 may further extend to overlap the first through-hole 231 and the third through-hole 233, and may be a conductive pattern electrically connected to the first through-hole 231 and the third through-hole 233. The second RDL 280 may extend to overlap the second intermediate chip pad 222, and may be a conductive pattern electrically connected to the second intermediate chip pad 222. The second RDL 280 may further extend to overlap the second through-hole 232 and the fourth through-hole 234, and may be a conductive pattern electrically connected to the second through-hole 232 and the fourth through-hole 234. The first RDL 260 may electrically connect the first intermediate chip pad 221 to the first and third through vias 231 and 233 , and the second RDL 280 may electrically connect the second intermediate chip pad 222 to the second and fourth through vias 232 and 234 .

[0034] The first through-hole 231 may be disposed to correspond to the first intermediate chip pad 221 of the intermediate chip 210, and may be electrically connected to the first intermediate chip pad 221 through the first RDL 260. The second through-hole 232 may be disposed to correspond to the second intermediate chip pad 222 of the intermediate chip 210, and may be electrically connected to the second intermediate chip pad 222 through the second RDL 280. The third through-hole 233 may be disposed to correspond to the first intermediate chip pad 221 of the intermediate chip 210, and the first RDL 260 may be further extended to electrically connect the first intermediate chip pad 221 to the third through-hole 233. The fourth through-hole 234 may be disposed to correspond to the second intermediate chip pad 222 of the intermediate chip 210, and the second RDL 280 may be further extended to electrically connect the second intermediate chip pad 222 to the fourth through-hole 234.

[0035] The third through hole 233 may be located on a side of the intermediate chip 210 opposite to the second through hole 232. The fourth through hole 234 may be located on a side of the intermediate chip 210 opposite to the first through hole 231. The third through hole 233 may be disposed between the fourth through hole 234 and the intermediate chip 210.

[0036] Reference Figure 2 and Figure 3, the first middle chip pad 221 may be arranged so that the distance between the first middle chip pad 221 and the first through hole 231 is smaller than the distance between the second middle chip pad 222 and the first through hole 231. The second through hole 232 may be arranged between the first through hole 231 and the first middle chip pad 221. These positional relationships between the first through hole 231 and the second through hole 232 and the first middle chip pad 221 and the second middle chip pad 222 may be required to electrically connect the middle chip 210 to the upper left chip ( Figure 1 The positional relationship between the first through hole 231 and the second through hole 232 and the first middle chip pad 221 and the second middle chip pad 222 will be described in more detail later.

[0037] The first RDL 260 may extend to bypass the second through-hole 232 so as to electrically connect the first intermediate chip pad 221 to the first through-hole 231. The second RDL 280 may extend to bypass the first intermediate chip pad 221 so as to electrically connect the second intermediate chip pad 222 to the second through-hole 232. In the case where an additional intermediate chip (not shown) is disposed between the second intermediate chip pad 222 and the first intermediate chip pad 221, the first RDL 260 and the second RDL 280 may extend to even bypass the additional intermediate chip.

[0038] Figure 4 It is shown that the Figure 1 FIG. 1 is a plan view of a connection portion between a base module 200 and a lower left chip 310 in a semiconductor package 10 . Figure 4 The plan view of the base module 200 shown may correspond to Figure 1 The layout of the basic module 200 when viewed in the first direction V1 indicated in FIG. Figure 4 The plan view of the lower left chip 310 shown may correspond to the Figure 1 Layout of the lower left chip 310 when viewed from the second direction V2 indicated in FIG. The first direction V1 and the second direction V2 may be opposite to each other.

[0039] Reference Figure 1 , Figure 3 and Figure 4 , the first RDL 260 and the second RDL 280 may be further extended to provide a first connection portion 260-1 and a second connection portion 280-1, respectively. The first connection portion 260-1 and the second connection portion 280-1 may be electrically connected to the lower left chip 310. Since the lower left chip 310 is electrically connected to the first connection portion 260-1 and the second connection portion 280-1, the lower left chip 310 may be electrically connected to the middle chip 210 through the first RDL 260 and the second RDL 280.

[0040] The lower left chip 310 may be a semiconductor chip including a first lower left chip pad 321 and a second lower left chip pad 322 disposed on a surface 310S of the lower left chip 310. The first lower left chip pad 321 and the second lower left chip pad 322 may be electrical connection terminals for applying data signals to or outputting data signals from the lower left chip 310. The first lower left chip pad 321 and the second lower left chip pad 322 may be electrically connected to the first middle chip pad 221 and the second middle chip pad 222, respectively.

[0041] The first lower left chip pad 321 may be disposed to correspond to the first middle chip pad 221, and may be electrically connected to the first middle chip pad 221 through the first RDL 260. The first lower left chip pad 321 may be electrically connected to the first connection portion 260-1 through any one of the inner connectors 500. The lower left chip 310 may be disposed below the base module 200 such that the first connection portion 260-1 vertically overlaps the first lower left chip pad 321.

[0042] The second lower left chip pad 322 may be disposed to correspond to the second middle chip pad 222 and may be electrically connected to the second middle chip pad 222 through the second RDL 280. The second lower left chip pad 322 may be electrically connected to the second connection portion 260-2 through one of the inner connectors 500. The second connection portion 280-1 may be disposed between the first connection portion 260-1 and the second through hole 232 such that the second connection portion 280-1 vertically overlaps the second lower left chip pad 322.

[0043] The lower left chip 310 may be disposed on the package substrate 100 such that a surface 310S of the lower left chip 310 faces the basic module 200. The lower left chip 310 may partially overlap with the middle chip 210 such that a portion of the surface 310S of the lower left chip 310 faces the surface 210S of the middle chip 210. Since the basic module 200 is stacked on the lower left chip 310 such that the surface 310S of the lower left chip 310 faces the surface 210S of the middle chip 210, the distance between the first lower left chip pad 321 and the first middle chip pad 221 may be smaller than the distance between the first lower left chip pad 321 and the second middle chip pad 222. The distance between the second lower left chip pad 322 and the first middle chip pad 221 may be larger than the distance between the first lower left chip pad 321 and the first middle chip pad 221.

[0044] like Figure 4As shown, the arrangement order of the first lower left chip pad 321 and the second lower left chip pad 322 (the second lower left chip pad 322 is located on the left side of the first lower left chip pad 321) may be opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222 (the second middle chip pad 222 is located on the right side of the first middle chip pad 221). As described above, since the arrangement order of the first lower left chip pad 321 and the second lower left chip pad 322 is opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222, the first connection portion 260-1 and the second connection portion 280-1 may also be arranged in an arrangement order opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222, so as to connect the first lower left chip pad 321 to the first middle chip pad 221. Therefore, the first and second RDLs 260 and 280 may be extended to fit a layout in which the first and second connection portions 260 - 1 and 280 - 1 are arranged in a reverse arrangement order to the first and second intermediate chip pads 221 and 222 .

[0045] Figure 5 It is shown that the Figure 1 FIG. 1 is a plan view of a connection portion between a base module 200 and a lower right chip 350 in a semiconductor package 10 . Figure 5 The plan view of the base module 200 shown may correspond to Figure 1 The layout of the basic module 200 when viewed in the first direction V1 indicated in FIG. Figure 5 The plan view of the lower right chip 350 shown may correspond to the Figure 1 The layout of the lower right chip 350 when viewed in the second direction V2 indicated in FIG.

[0046] Reference Figure 1 , Figure 3 and Figure 5 , the first RDL 260 and the second RDL 280 may be further extended to provide a third connection portion 260-2 and a fourth connection portion 280-2, respectively. The third connection portion 260-2 and the fourth connection portion 280-2 may be electrically connected to the lower right chip 350. Since the lower right chip 350 is electrically connected to the third connection portion 260-2 and the fourth connection portion 280-2, the lower right chip 350 may be electrically connected to the middle chip 210 through the first RDL 260 and the second RDL 280.

[0047] The lower right chip 350 may be a semiconductor chip including a first lower right chip pad 361 and a second lower right chip pad 362 disposed on a surface 350S of the lower right chip 350. The first lower right chip pad 361 and the second lower right chip pad 362 may be electrical connection terminals for applying data signals to or outputting data signals from the lower right chip 350. The first lower right chip pad 361 and the second lower right chip pad 362 may be electrically connected to the first middle chip pad 221 and the second middle chip pad 222, respectively.

[0048] The first lower right chip pad 361 may be disposed to correspond to the first middle chip pad 221 and the first lower left chip pad 321, and may be electrically connected to the first middle chip pad 221 and the first lower left chip pad 321 through the first RDL 260. Since the first lower right chip pad 361 is electrically connected to the third connection portion 260-2 through any one of the inner connectors 500, the first lower right chip pad 361 may be electrically connected to the first middle chip pad 221 through the first RDL 260. The lower right chip 350 may be disposed below the base module 200 such that the third connection portion 260-2 vertically overlaps the first lower right chip pad 361.

[0049] The second lower right chip pad 362 may be disposed to correspond to the second middle chip pad 222 and the second lower left chip pad 322, and may be electrically connected to the second middle chip pad 222 and the second lower left chip pad 322 through the second RDL 280. Since the second lower right chip pad 362 is electrically connected to the fourth connection portion 280-2 through one of the inner connectors 500, the second lower right chip pad 362 may be electrically connected to the second middle chip pad 222 through the second RDL 280. The fourth connection portion 280-2 may be disposed between the third connection portion 260-2 and the middle chip 210 such that the fourth connection portion 280-2 vertically overlaps the second lower right chip pad 362.

[0050] The lower right chip 350 may be disposed on the package substrate 100 such that a surface 350S of the lower right chip 350 faces the basic module 200. The lower right chip 350 may partially overlap with the middle chip 210 such that a portion of the surface 350S of the lower right chip 350 faces the surface 210S of the middle chip 210. Since the basic module 200 is stacked on the lower right chip 350 such that the surface 350S of the lower right chip 350 faces the surface 210S of the middle chip 210, the distance between the first lower right chip pad 361 and the second middle chip pad 222 may be smaller than the distance between the first lower right chip pad 361 and the first middle chip pad 221. The distance between the second lower right chip pad 362 and the second middle chip pad 222 may be smaller than the distance between the first lower right chip pad 361 and the second middle chip pad 222.

[0051] like Figure 5 As shown, the arrangement order of the first lower right chip pad 361 and the second lower right chip pad 362 (the second lower right chip pad 362 is located on the left side of the first lower right chip pad 361) may be opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222 (the second middle chip pad 222 is located on the right side of the first middle chip pad 221). Therefore, the first RDL 260 and the second RDL 280 may be extended to fit the layout in which the third connection part 260-2 and the fourth connection part 280-2 are arranged in an arrangement order opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222, so as to connect the first lower right chip pad 361 to the first middle chip pad 221.

[0052] Figure 6 It is shown that the Figure 1 FIG. 4 is a plan view of a connection portion between a base module 200 and an upper left chip 410 in a semiconductor package 10 . Figure 6 The plan view of the basic module 200 and the upper left chip 410 shown may correspond to the Figure 1 Layout of the basic module 200 and the upper left chip 410 when viewed from the first direction V1 indicated in FIG.

[0053] Reference Figure 1 , Figure 3 and Figure 6 Since the upper left chip 410 is connected to the first through-via 231 and the second through-via 232, the upper left chip 410 may be electrically connected to the middle chip 210 through the first RDL 260 and the second RDL 280. The upper left chip 410 may be a semiconductor chip including a first upper left chip pad 421 and a second upper left chip pad 422 disposed on a surface 410S of the upper left chip 410.

[0054] The first upper left chip pad 421 and the second upper left chip pad 422 may be electrical connection terminals for applying a data signal to or outputting a data signal from the upper left chip 410. The first upper left chip pad 421 may be disposed to correspond to the first middle chip pad 221 and may be electrically connected to the first middle chip pad 221 through the first RDL 260. The first upper left chip pad 421 may be disposed to correspond to the first lower left chip pad 321 and the first lower right chip pad 361 and may be electrically connected to the first lower left chip pad 321 and the first lower right chip pad 361 through the first RDL 260.

[0055] The second upper left chip pad 422 can be set to correspond to the second middle chip pad 222, the second lower left chip pad 322 and the second lower right chip pad 362, and can be electrically connected to the second middle chip pad 222, the second lower left chip pad 322 and the second lower right chip pad 362 through the second RDL 280.

[0056] The first upper left chip pad 421 and the second upper left chip pad 422 may be electrically connected to corresponding through holes in the first through holes 231 and the second through holes 232 through two inner connectors 500. The upper left chip 410 may be disposed on the base module 200 such that the first upper left chip pad 421 and the second upper left chip pad 422 vertically overlap with corresponding through holes in the first through holes 231 and the second through holes 232.

[0057] The upper left chip 410 may be disposed on the base module 200 so that the surface 410S of the upper left chip 410 faces the base module 200. Since the upper left chip 410 and the middle chip 210 are disposed above the package substrate 100 so that the surfaces 410S and 210S of the upper left chip 410 and the middle chip 210 both face the package substrate 100, the arrangement order of the first upper left chip pad 421 and the second upper left chip pad 422 may be substantially the same as the arrangement order of the first middle chip pad 221 and the second middle chip pad 222. The distance between the first upper left chip pad 421 and the first middle chip pad 221 may be smaller than the distance between the first upper left chip pad 421 and the second middle chip pad 222. The distance between the second upper left chip pad 422 and the first middle chip pad 221 may be smaller than the distance between the first upper left chip pad 421 and the first middle chip pad 221.

[0058] Reference Figure 4 and Figure 6 , the arrangement order of the first upper left chip pad 421 and the second upper left chip pad 422 may be opposite to the arrangement order of the first lower left chip pad 321 and the second lower left chip pad 322. The first lower left chip pad 321 may be connected to the first connection portion 260-1. Since the arrangement order of the first connection portion 260-1 and the second connection portion 280-1 is opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222, the first upper left chip pad 421 may share the first RDL 260 with the first lower left chip pad 321 and may be connected to the first middle chip pad 221.

[0059] Figure 7 It is shown that the Figure 1 FIG. 1 is a plan view of a connection portion between a base module 200 and an upper right chip 450 in a semiconductor package 10 . Figure 7 The plan view of the basic module 200 and the upper right chip 450 shown may correspond to the Figure 1 Layout of the basic module 200 and the upper right chip 450 when viewed from the first direction V1 indicated in FIG.

[0060] Reference Figure 1 , Figure 3 and Figure 7 , since the upper right chip 450 is connected to the third through-hole 233 and the fourth through-hole 234, the upper right chip 450 may be electrically connected to the middle chip 210 through the first RDL 260 and the second RDL 280. The upper right chip 450 may be a semiconductor chip including a first upper right chip pad 461 and a second upper right chip pad 462 disposed on a surface 450S of the upper right chip 450.

[0061] The first upper right chip pad 461 and the second upper right chip pad 462 may be electrical connection terminals for applying data signals to or outputting data signals from the upper right chip 450. The first upper right chip pad 461 may be disposed to correspond to the first middle chip pad 221, and may be electrically connected to the first middle chip pad 221 through the first RDL 260. The first upper right chip pad 461 may be disposed to correspond to the first lower left chip pad 321, the first lower right chip pad 361, and the first upper left chip pad 421, and may be electrically connected to the first lower left chip pad 321, the first lower right chip pad 361, and the first upper left chip pad 421 through the first RDL 260.

[0062] The second upper right chip pad 462 can be set to correspond to the second middle chip pad 222, the second lower left chip pad 322, the second lower right chip pad 362 and the second upper left chip pad 422, and can be electrically connected to the second middle chip pad 222, the second lower left chip pad 322, the second lower right chip pad 362 and the second upper left chip pad 422 through the second RDL 280.

[0063] The first upper right chip pad 461 and the second upper right chip pad 462 may be electrically connected to corresponding through holes in the third through hole 233 and the fourth through hole 234 through two inner connectors 500. The upper right chip 450 may be disposed on the base module 200 such that the first upper right chip pad 461 and the second upper right chip pad 462 vertically overlap with corresponding through holes in the third through hole 233 and the fourth through hole 234.

[0064] The upper right chip 450 may be disposed on the basic module 200 so that the surface 450S of the upper right chip 450 faces the basic module 200. Since the upper right chip 450 and the middle chip 210 are disposed above the package substrate 100 so that the surfaces 450S and 210S of the upper right chip 450 and the middle chip 210 both face the package substrate 100, the arrangement order of the first upper right chip pad 461 and the second upper right chip pad 462 may be substantially the same as the arrangement order of the first middle chip pad 221 and the second middle chip pad 222. The distance between the first upper right chip pad 461 and the first middle chip pad 221 may be greater than the distance between the first upper right chip pad 461 and the second middle chip pad 222. The distance between the second upper right chip pad 462 and the first middle chip pad 221 may be greater than the distance between the first upper right chip pad 461 and the first middle chip pad 221.

[0065] Reference Figure 5 and Figure 7 , the arrangement order of the first upper right chip pad 461 and the second upper right chip pad 462 may be opposite to the arrangement order of the first lower right chip pad 361 and the second lower right chip pad 362. The first lower right chip pad 361 may be connected to the third connection portion 260-2. Since the arrangement order of the third connection portion 260-2 and the fourth connection portion 280-2 is opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222, the first upper right chip pad 461 may share the first RDL 260 with the first lower right chip pad 361 and may be connected to the first middle chip pad 221.

[0066] In an embodiment, the upper right chip 450 may be provided as a dummy chip that does not substantially operate. In this case, the upper right chip 450 may be provided to maintain the balance of the semiconductor package 10 .

[0067] Refer to Figure 1 and Figure 4, the lower left chip 310 and the middle chip 210 may be semiconductor chips having substantially the same configuration. The lower left chip 310 and the middle chip 210 may be memory semiconductor chips. When the middle chip 210 is configured to have a pad array including a first middle chip pad 221 and a second middle chip pad 222 and a wire bonding pad 225, the lower left chip 310 may have a pad array substantially the same as that of the middle chip 210, and the pad array of the lower left chip 310 may be disposed on a surface 310S of the lower left chip 310. The lower left chip 310 may include a first lower left chip pad 321 and a second lower left chip pad 322 disposed on the surface 310S to correspond to respective pads in the first middle chip pad 221 and the second middle chip pad 222, and may also include a wire bonding pad 325 disposed on the surface 310S to correspond to the wire bonding pad 225.

[0068] The lower left chip 310 may be connected to the middle chip 210 through the first RDL 260 and the second RDL 280, may be connected to the bonding wires 150 through the middle chip 210, and may be connected to the package substrate 100 through the bonding wires 150. Therefore, no bonding wires are connected to the wire bonding pads 325. Since the lower left chip 310 is connected to the package substrate 100 through the middle chip 210, the middle chip 210 may act as a master chip that controls the transmission of data signals between the lower left chip 310 and the package substrate 100. The lower left chip 310 may act as a slave chip whose operation is controlled by the middle chip 210.

[0069] Since the lower left chip 310 has substantially the same pad array as the middle chip 210, when Figure 1 The lower left chip 310 and the middle chip 210 are arranged so that when the surfaces 310S and 210S of the lower left chip 310 and the middle chip 210 face each other, the arrangement order of the first lower left chip pad 321 and the second lower left chip pad 322 may be opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222. In order to compensate for the arrangement order of the first lower left chip pad 321 and the second lower left chip pad 322 opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222, the first connection portion 260-1 and the second connection portion 280-1 may be arranged in an arrangement order opposite to the arrangement order of the first middle chip pad 221 and the second middle chip pad 222.

[0070] Reference Figure 1 and Figure 5, the lower right chip 350 and the middle chip 210 can be semiconductor chips having substantially the same configuration. The lower right chip 350 may include a pad array, which is arranged on the surface 350S to have a configuration substantially the same as the pad array of the first middle chip pad 221 and the second middle chip pad 222 and the wire bonding pad 225. The lower right chip 350 may also include a wire bonding pad 365, which is arranged on the surface 350S to correspond to the wire bonding pad 225 of the middle chip 210. The lower right chip 350 can act as another slave chip controlled by the middle chip 210. Therefore, for an embodiment, no wire bonding pad is connected to the wire bonding pad 365 included in the lower right chip 350.

[0071] Reference Figure 1 and Figure 6 , the upper left chip 410 and the middle chip 210 may be semiconductor chips having substantially the same configuration. The upper left chip 410 may include a pad array, which is arranged on the surface 410S to have a configuration substantially the same as the pad array of the first middle chip pad 221 and the second middle chip pad 222 and the wire bonding pad 225. The upper left chip 410 may also include a wire bonding pad 425, which is arranged on the surface 410S to correspond to the wire bonding pad 225 of the middle chip 210. The upper left chip 410 may act as another slave chip controlled by the middle chip 210. Therefore, for an embodiment, no wire bonding pad is connected to the wire bonding pad 425 included in the upper left chip 410.

[0072] Reference Figure 1 and Figure 7 , the upper right chip 450 and the middle chip 210 may be semiconductor chips having substantially the same configuration. The upper right chip 450 may include a pad array, which is arranged on the surface 450S to have a configuration substantially the same as the pad array of the first middle chip pad 221 and the second middle chip pad 222 and the wire bonding pad 225. The upper right chip 450 may also include a wire bonding pad 465, which is arranged on the surface 450S to correspond to the wire bonding pad 225 of the middle chip 210. The upper right chip 450 may act as another slave chip controlled by the middle chip 210. Therefore, for an embodiment, no wire bonding pad is connected to the wire bonding pad 465 included in the upper right chip 450.

[0073] As described above, the lower left chip 310, the upper left chip 410, the lower right chip 350, and the upper right chip 450 may be connected to the package substrate 100 through the intermediate chip 210. The upper left chip 410, the lower right chip 350, and the upper right chip 450 may be indirectly connected to the package substrate 100. The basic module 200 may provide a first RDL 260 and a second RDL 280 corresponding to a path connecting the lower left chip 310 and the lower right chip 350 to the intermediate chip 210. The basic module 200 may provide a first RDL 260 and a second RDL 280 corresponding to a path connecting the upper left chip 410 and the upper right chip 450 to the intermediate chip 210.

[0074] Refer to Figure 1 , the package substrate 100 may be configured to further include a through slit 105. When viewed from a plan view, the through slit 105 may be disposed to overlap with the wire bonding pad 225 of the intermediate chip 210. The package substrate 100 may have a first surface 101 facing the base module 200 and a second surface 102 located on the opposite side of the first surface 101. The through slit 105 may have a hole shape or an opening shape penetrating from the first surface 101 to the second surface 102. The package substrate 100 may further include a bonding finger 151 disposed on the second surface 102.

[0075] The bonding wire 150 may be disposed to connect the wire bonding pad 225 to the bonding finger 151. Since the base module 200 is disposed on the first surface 101 of the package substrate 100, the bonding wire 150 may be disposed to face the first surface 101. In order to connect the wire bonding pad 225 to the bonding finger 151 disposed on the second surface 102 of the package substrate 100 opposite to the base module 200, the bonding wire 150 may extend through the through slit 105. The lower left chip 310 and the lower right chip 350 may be disposed on the first surface 101 of the package substrate 100 to be spaced apart from each other by the through slit 105. The bonding wire 150 may extend through the space between the lower left chip 310 and the lower right chip 350 and through the through slit 105.

[0076] The package encapsulant 190 may extend to fill the through slits 105 and cover the bonding wires 150 and the bonding fingers 151. The package substrate 100 may further include ball pads 159 disposed on the second surface 102 to be spaced apart from the bonding fingers 151. External connectors 109 such as solder balls may be attached to the ball pads 159.

[0077] Reference Figure 1, the lower left chip 310 may be disposed between the base module 200 and the package substrate 100, and the upper left chip 410 may be disposed on the surface of the base module 200 opposite to the lower left chip 310. In an embodiment, the semiconductor package 10 may be configured without the lower right chip 350 and the upper right chip 450. The base module 200 may be configured to include a through hole 230 penetrating the sealant 290 to connect to the upper left chip 410. The base module 200 may also include RDLs 260 and 280 connecting the intermediate chip 210 to the through hole 230. The RDLs 260 and 280 may extend to provide connection portions 260-1 and 280-1 spaced apart from the through hole 230. The lower left chip 310 may be electrically connected to the connection portions 260-1 and 280-1.

[0078] According to the above embodiment, a basic module is provided, which includes an electrical connection structure having a through hole and an RDL and includes a semiconductor chip connected to the electrical connection structure. At least two additional semiconductor chips are respectively arranged above and below the basic module to provide a semiconductor package. The additional semiconductor chip can be electrically connected to the semiconductor chip included in the basic module through the through hole and the RDL.

[0079] Figure 8 7800 is a block diagram showing an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include one or more semiconductor packages according to the embodiments.

[0080] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from the host 7830 .

[0081] Fig. 9 8710 is a block diagram showing an electronic system 8710 including at least one of the semiconductor packages according to the embodiment. The electronic system 8710 may include a controller 8711, an input / output unit 8712, and a memory 8713. The controller 8711, the input / output unit 8712, and the memory 8713 may be connected to each other through a bus 8715 that provides a path for data movement.

[0082] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one of the semiconductor packages according to the embodiments of the present disclosure. The input / output unit 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0083] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0084] The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0085] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0086] If the electronic system 8710 is a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0087] As described above, the concept of the present invention is disclosed in conjunction with some embodiments. It will be appreciated by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but should be considered from an illustrative perspective. The scope of the concept of the present invention is not limited to the above description, but is limited by the appended claims, and all different features within the equivalent scope should be interpreted as being included in the concept of the present invention.

[0088] CROSS-REFERENCE TO RELATED APPLICATIONS

[0089] This application claims priority from Korean Application No. 10-2020-0010124, filed on January 28, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: Package substrate; A basic module, which is arranged on the packaging substrate; A lower left chip and a lower right chip, wherein the lower left chip and the lower right chip are arranged between the basic module and the packaging substrate; as well as an upper left chip, which is arranged on the base module opposite to the lower left chip, Wherein, the basic module includes: An intermediate chip having a first intermediate chip pad and a second intermediate chip pad; A sealant encapsulating the intermediate chip; a first through hole and a second through hole penetrating the sealant to be electrically connected to the upper left chip; and A first RDL and a second RDL are configured to connect the first and second middle chip pads to corresponding ones of the first and second through vias and are configured to be electrically connected to the lower left chip and the lower right chip.

2. The semiconductor package according to claim 1, in, The distance between the first intermediate chip pad and the first through hole is smaller than the distance between the second intermediate chip pad and the first through hole; Wherein, the second through hole is arranged between the first through hole and the first intermediate chip pad; wherein the first RDL extends to bypass the second through hole; and Wherein, the second RDL extends to bypass the first middle chip pad.

3. The semiconductor package according to claim 2, in, The lower left chip comprises a first lower left chip pad corresponding to the first middle chip pad and a second lower left chip pad corresponding to the second middle chip pad; wherein the first RDL provides a first connection portion connected to the first lower left chip pad; wherein the first connection portion is disposed between the second through hole and the first middle chip pad to overlap with the first lower left chip pad; wherein the second RDL provides a second connection portion connected to the second lower left chip pad; and Wherein, the second connection portion is disposed between the first connection portion and the second through hole to overlap with the second lower left chip pad.

4. The semiconductor package according to claim 3, wherein: The lower left chip is arranged to partially overlap with the middle chip such that: The distance between the first lower left chip pad and the first middle chip pad is smaller than the distance between the first lower left chip pad and the second middle chip pad; and A distance between the second lower left chip pad and the first middle chip pad is greater than a distance between the second lower left chip pad and the first middle chip pad.

5. The semiconductor package according to claim 3, wherein: The lower right chip includes: a first lower right chip pad, the first lower right chip pad being arranged to correspond to the first middle chip pad and the first lower left chip pad, such that a distance between the first lower right chip pad and the second middle chip pad is smaller than a distance between the first lower right chip pad and the first middle chip pad; and a second lower right chip pad, the second lower right chip pad being arranged to correspond to the second middle chip pad and the second lower left chip pad, such that a distance between the second lower right chip pad and the second middle chip pad is smaller than a distance between the second lower right chip pad and the first middle chip pad, wherein the first RDL extends to provide a third connection portion connected to the first lower right chip pad; Wherein, the third connection portion overlaps with the first lower right chip pad; wherein the second RDL extends to provide a fourth connection portion connected to the second lower right chip pad; and Wherein, the fourth connecting portion overlaps with the second lower right chip pad.

6. The semiconductor package according to claim 5, wherein: The basic module also includes: a third through-hole provided on a side of the intermediate chip opposite to the second through-hole to correspond to the first through-hole and connected to the first RDL; and a fourth through hole, which is disposed on a side of the intermediate chip opposite to the first through hole to correspond to the second through hole and is connected to the second RDL, Wherein, the third through hole is arranged between the second middle chip pad and the fourth through hole.

7. The semiconductor package according to claim 6, wherein: The upper left chip comprises: a first upper left chip pad connected to the first through hole and arranged to correspond to the first middle chip pad, the first lower left chip pad, and the first lower right chip pad; and A second upper left chip pad is connected to the second through hole and is disposed to correspond to the second middle chip pad, the second lower left chip pad, and the second lower right chip pad.

8. The semiconductor package according to claim 7, further comprising an upper right chip disposed on the base module opposite to the lower right chip to be spaced apart from the upper left chip, in, The upper right chip comprises: a first upper right chip pad connected to the third through hole and arranged to correspond to the first middle chip pad, the first lower left chip pad, the first lower right chip pad, and the first upper left chip pad; and A second upper right chip pad is connected to the fourth through hole and is arranged to correspond to the second middle chip pad, the second lower left chip pad, the second lower right chip pad and the second upper left chip pad. 9 . The semiconductor package according to claim 6 , further comprising a dummy chip connected to the third through-via and the fourth through-via. 10 . The semiconductor package of claim 1 , further comprising conductive bumps connecting the upper left chip to the first and second vias.

11. The semiconductor package according to claim 1, in, The intermediate chip further includes a wire bonding pad disposed spaced apart from the first intermediate chip pad and the second intermediate chip pad; and The semiconductor package further includes bonding wires connecting the package substrate to the wire bonding pads.

12. The semiconductor package according to claim 11, wherein The packaging substrate comprises: a through slit penetrating a portion of the package substrate to overlap the wire bonding pad; and a bonding finger disposed on a surface of the package substrate opposite to the base module to be adjacent to the through slit, The bonding wire passes through the through slit to connect the wire bonding pad to the bonding finger.

13. The semiconductor package according to claim 11, wherein The lower left chip includes a pad array having the same configuration as the pad array including the first and second middle chip pads and the wire bonding pads.

14. A semiconductor package, comprising: Package substrate; A basic module, which is disposed on the packaging substrate and is configured to include an intermediate chip; bonding wires connecting the intermediate chip to the packaging substrate; A lower left chip, the lower left chip is arranged between the basic module and the packaging substrate; as well as an upper left chip, which is arranged on the base module opposite to the lower left chip, Wherein, the intermediate chip comprises: a first middle chip pad and a second middle chip pad; and a wire bonding pad disposed spaced apart from the first intermediate chip pad and the second intermediate chip pad and connected to the bonding wire, Wherein, the lower left chip comprises: a first lower left chip pad corresponding to the first middle chip pad; and a second lower left chip pad corresponding to the second middle chip pad, Wherein, the upper left chip comprises: a first upper left chip pad corresponding to the first middle chip pad; and a second upper left chip pad corresponding to the second middle chip pad, Wherein, the basic module also includes: A sealant encapsulating the intermediate chip; a first through hole and a second through hole, the first through hole and the second through hole penetrating the sealant to be electrically connected to corresponding pads of the first upper left chip pad and the second upper left chip pad; a first RDL configured to connect the first middle chip pad to the first through-hole and configured to extend to provide a first connection portion that is spaced apart from the first through-hole and connected to the first lower left chip pad; and A second RDL is configured to connect the second middle chip pad to the second through-via and is configured to extend to provide a second connection portion disposed between the second through-via and the first connection portion and connected to the second lower left chip pad.

15. The semiconductor package according to claim 14, in, The distance between the first intermediate chip pad and the first through hole is smaller than the distance between the second intermediate chip pad and the first through hole; Wherein, the second through hole is arranged between the first through hole and the first intermediate chip pad; wherein the first RDL extends to bypass the second through hole; and Wherein, the second RDL extends to bypass the first middle chip pad.

16. The semiconductor package according to claim 15, wherein: The lower left chip is arranged to partially overlap with the middle chip such that: The distance between the first lower left chip pad and the first middle chip pad is smaller than the distance between the first lower left chip pad and the second middle chip pad; and A distance between the second lower left chip pad and the first middle chip pad is greater than a distance between the second lower left chip pad and the first middle chip pad. 17 . The semiconductor package of claim 14 , further comprising conductive bumps connecting the upper left chip to the first and second vias.

18. The semiconductor package according to claim 14, wherein: The packaging substrate comprises: a through slit penetrating a portion of the package substrate to overlap the wire bonding pad; and a bonding finger disposed on a surface of the package substrate opposite to the base module to be adjacent to the through slit, The bonding wire passes through the through slit to connect the wire bonding pad to the bonding finger.

19. A semiconductor package, comprising: Package substrate; A basic module, which is disposed on the packaging substrate and is configured to include an intermediate chip; bonding wires connecting the intermediate chip to the packaging substrate; A lower left chip, the lower left chip is arranged between the basic module and the packaging substrate; as well as an upper left chip, the upper left chip being arranged on the basic module, Wherein, the basic module also includes: A sealant encapsulating the intermediate chip; a through hole penetrating the sealant to be electrically connected to the upper left chip; and A redistribution line RDL is configured to connect the middle chip to the through-via and is configured to extend to provide a connection portion that is spaced apart from the through-via and connected to the lower left chip.

20. The semiconductor package according to claim 19, wherein The packaging substrate comprises: a through slit that penetrates a portion of the packaging substrate; and a bonding finger disposed on a surface of the package substrate opposite to the base module to be adjacent to the through slit, The semiconductor package further includes bonding wires passing through the through slits to connect the intermediate chip to the bonding fingers.

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