Dipole-designed high-K gate dielectric and method of forming the same

Abstract

The present disclosure relates to a dipole-design high-k gate dielectric and a method for forming the same. The method includes forming an oxide layer on a first semiconductor region and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method also includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and in contact with a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive dipole dopants in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

Description

Technical Field

[0001] The present disclosure generally relates to dipole design high-K gate dielectrics and methods of forming the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices are fundamental building blocks in integrated circuits. Recent developments in MOS devices include forming a replacement gate, which includes a high-k gate dielectric and a metal gate electrode atop the high-k gate dielectric. Forming a replacement gate typically involves depositing a high-k gate dielectric layer, depositing a metal layer atop the high-k gate dielectric layer, and then performing chemical mechanical polishing (CMP) to remove excess portions of the high-k gate dielectric and metal layers. The remaining portion of the metal layer forms the metal gate.

[0003] In conventional MOS device formation methods, the threshold voltage of a MOS device can be adjusted by performing a thermal annealing process while conducting ammonia to treat a high-k dielectric layer. Although the threshold voltage can be varied, it is difficult to adjust the threshold voltage to a desired value, and further adjustment must be achieved by using different work function metals and adjusting the thickness of the work function metal. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a first oxide layer on a first semiconductor region; depositing a first high-k dielectric layer over the first oxide layer, wherein the first high-k dielectric layer is formed of a first high-k dielectric material; depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material; depositing a first dipole film over and in contact with the first and second high-k dielectric layers, wherein the first dipole film is in contact with a first layer, and the first layer is one of the first and second high-k dielectric layers; performing a first annealing process to drive a first dipole dopant in the first dipole film into the first layer; removing the first dipole film; and forming a first gate electrode over the second high-k dielectric layer.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first oxide layer on a first semiconductor region; a first high-k dielectric layer including a first high-k dielectric material; a second high-k dielectric layer including a second high-k dielectric material different from the first high-k dielectric material, wherein the second high-k dielectric layer covers the first high-k dielectric layer and contacts the first high-k dielectric layer; a first dipole dopant in the first high-k dielectric layer and the second high-k dielectric layer, wherein a first peak concentration of the first dipole dopant is at a first top surface of the first high-k dielectric layer or a second top surface of the second high-k dielectric layer; a gate electrode on the second high-k dielectric layer; and a source / drain region on one side of the gate electrode.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first transistor, the first transistor including: a first portion of a first high-k dielectric layer; a first portion of a second high-k dielectric layer, wherein the second high-k dielectric layer is above the first high-k dielectric layer and wherein the first high-k dielectric layer and the second high-k dielectric layer have different k values; a first dipole dopant having a first peak concentration at an interface between the first portion of the first high-k dielectric layer and the first portion of the second high-k dielectric layer; and a second transistor including: a second portion of the first high-k dielectric layer; a second portion of the second high-k dielectric layer; and a second dipole dopant having a second peak concentration at a top surface of the second high-k dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1-6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B and Figure 10-20 Perspective and cross-sectional views are shown of intermediate stages in forming a fin field effect transistor (FinFET), according to some embodiments.

[0009] Figures 21 to 23 The distribution of dipole dopants according to some embodiments is shown.

[0010] Figure 24A process flow for forming a FinFET is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, represent a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element(s) or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] According to various embodiments, transistors having a dipole-designed high-k dielectric layer and methods for incorporating dipole dopants into the high-k dielectric layer are provided. The dipole dopants diffuse into the high-k dielectric layer by thermal diffusion. The threshold voltage of the corresponding transistor is adjusted. The magnitude of the adjustment depends on the material and doping location of the high-k dielectric layer. Thus, more than one high-k dielectric layer is formed, which may have different dielectric constant (k) values. Dipole dopants can be selectively doped into one or more high-k dielectric layers to provide different threshold voltage adjustment capabilities. In addition, device performance is improved by doping with dipole dopants. The capacitance equivalent thickness (CET) of the high-k dielectric layer is reduced. According to some embodiments, intermediate stages of forming a transistor are shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. According to some embodiments, the formation of a fin field-effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Other types of transistors (e.g., planar transistors and gate-all-around (GAA) transistors) may also employ the concepts of the present disclosure.

[0014] Figure 1-6 、 Figure 7A 、 Figure 7B、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B and Figure 10-20 The process shown in these figures is also schematically reflected in the following figures: Figure 24 In the process flow 400 shown.

[0015] exist Figure 1 In the embodiment of the present invention, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, for example, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (for example, with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10 (for example, a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, for example, a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include: silicon; germanium; compound semiconductors including carbon silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0016] Further references Figure 1 , a well region 22 is formed in the substrate 20. The corresponding process is shown as Figure 24 The process 402 in the process flow 400 is shown. According to some embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities (such as phosphorus, arsenic, antimony, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (such as boron, indium, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 within the range between.

[0017] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. The corresponding process is shown as Figure 24 Process 404 in the process flow 400 shown. The portion of the substrate 20 between adjacent STI regions 24 is called a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 can be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to form a hard mask layer 30 as shown in FIG. Figure 2 A hard mask 30 is shown.

[0018] Next, patterned hard mask layer 30 is used as an etch mask to etch pad oxide layer 28 and substrate 20, and the resulting trenches in substrate 20 are then filled with dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material(s) are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 24 may also include a dielectric material overlying the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material overlying the liner dielectric may include silicon oxide.

[0019] The top surface of hard mask 30 and the top surface of STI regions 24 may be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are portions of original substrate 20, and thus, the material of semiconductor strips 26 is the same as that of substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are replacement strips formed by etching portions of substrate 20 between STI regions 24 to form recesses, and performing epitaxy to re-grow another semiconductor material in the recesses. Thus, the semiconductor material forming semiconductor strips 26 is different from the semiconductor material of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0020] refer to Figure 3 , STI region 24 is recessed so that the top portion of semiconductor strip 26 protrudes above top surface 24A of the remaining portion of STI region 24 to form protruding fin 36. The corresponding process is shown as Figure 24 Process 406 in process flow 400 is shown. Etching can be performed using a dry etching process in which, for example, a mixture of HF3 and NH3 is used as the etching gas. During the etching process, a plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, recessing of STI regions 24 is performed using a wet etching process. The etching chemical can include, for example, HF.

[0021] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-aligned process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0022] refer to Figure 4 , a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (protruding) fin 36. The corresponding process is shown as Figure 24 The process 408 in the process flow 400 is shown. The dummy gate stack 38 may include a dummy gate dielectric 40 ( Figure 7B and Figure 7C), and a dummy gate electrode 42 on the dummy gate dielectric 40. The dummy gate electrode 42 can be formed, for example, using polysilicon or amorphous silicon, and other materials can also be used. Each dummy gate stack 38 can also include one (or more) hard mask layers 44 on the dummy gate electrode 42. The hard mask layer 44 can be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 can span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction that is perpendicular to the length direction of the protruding fin 36.

[0023] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. The corresponding process is also shown as Figure 24 The process flow 400 includes process 408. According to some embodiments of the present disclosure, the gate spacer 46 is formed of one or more dielectric materials such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0024] The portion of the protruding fin 36 not covered by the dummy gate stack 38 and the gate spacer 46 is then etched to obtain Figure 5 The corresponding process is shown as Figure 24 Process 410 of process flow 400 is shown. The recess can be anisotropic, and thus the portion of fin 36 directly below dummy gate stack 38 and gate spacer 46 is protected and not etched. According to some embodiments, the top surface of recessed semiconductor strip 26 can be lower than top surface 24A of STI region 24. Recess 50 is formed accordingly. Recess 50 includes portions on opposite sides of dummy gate stack 38 and a portion between the remaining portions of protruding fin 36.

[0025] Next, epitaxial regions (source / drain regions) 52 are formed by selectively growing semiconductor material in the recesses 50 (by epitaxy). Figure 6 The corresponding process is shown as Figure 24Process 412 in the process flow 400 shown. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 52 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or multiple layers thereof. After the groove 50 is filled with the epitaxial region 52, further epitaxial growth of the epitaxial region 52 causes the epitaxial region 52 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 52 can also cause adjacent epitaxial regions 52 to merge with each other. A void (air gap) 53 may be generated.

[0026] After the epitaxial growth process, the epitaxial region 52 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted by reference numeral 52. According to an alternative embodiment of the present disclosure, when the epitaxial region 52 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation process is skipped.

[0027] Figure 7A 1 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. The corresponding process is shown as Figure 24 Process 414 in the process flow 400 shown. CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process can be performed to make the top surfaces of ILD 60, dummy gate stack 38, and gate spacers 46 flush with each other.

[0028] Figure 7B and Figure 7C A cross-sectional view of an intermediate structure in which a first FinFET and a second FinFET are formed on the same substrate 20 (and in the same die and the same wafer) is shown. Figure 7BThe cross-sectional views of both the first FinFET and the second FinFET shown in FIG may correspond to a cross-sectional view from a circuit including Figure 7A Cross-sectional view obtained in a plane perpendicular to line AA. Figure 7C The cross-sectional views of both the first FinFET and the second FinFET shown may correspond to a cross-sectional view from a circuit including Figure 7A . According to some embodiments, the first FinFET is a logic device (sometimes referred to as a core device) and is formed in device region 12-LG. The second FinFET is an input-output (IO) device formed in device region 12-IO.

[0029] In the formation Figure 7A 、 Figure 7B and Figure 7C After the structure shown in FIG. 1 is formed, the hard mask layer 44 and the dummy gate electrode 42 are removed to form the structure shown in FIG. Figure 8A The corresponding process is shown as Figure 24 The process flow 400 is shown as process 416. The top surfaces and sidewalls of the protruding fins 36 in the device regions 12-LG and 12-10 are exposed. Next, an etch mask such as a photoresist 62 is formed in the device region 12-10 to protect the dummy gate dielectric 40 in the device region 12-10. Figure 8B The structure is shown in another cross section.

[0030] In a subsequent process, for example, the dummy gate dielectric 40 in the device region 12-LG is removed by an isotropic etching process (which may be a dry etching process or a wet etching process). The etching mask 62 ( Figure 8A and Figure 8B The resulting structure is Figure 9A and Figure 9B The corresponding process is shown as Figure 24 Process 418 in process flow 400 is shown.

[0031] Figures 10 to 20 1 shows a gate stack for forming a FinFET in device region 100 and a FinFET in device region 200, and a dipole engineering process according to some embodiments. According to some embodiments, each of device regions 100 and 200 can be selected from a core device region, an IO device region, a memory device region, etc. in any combination. For example, device region 100 can be a core device region (e.g., Figure 9A and Figure 9B 12-LG in the device region 200, and the device region 200 may be an IO device region (e.g., Figure 9A and Figure 9BRegion 12-IO in the device region 100). The device regions 100 and 200 may also both be core device regions, both be IO regions, both be memory regions, etc. In addition, each of the first FinFET and the second FinFET may be any combination of n-type FinFETs or p-type FinFETs. For example, according to some embodiments, the two FinFETs in the device regions 100 and 200 may be n-type FinFETs or p-type FinFETs. According to an alternative embodiment of the present disclosure, the FinFET in the device region 100 is an n-type FinFET, and the FinFET in the device region 200 is a p-type FinFET. Alternatively, the FinFET in the device region 100 is a p-type FinFET, and the FinFET in the device region 200 is an n-type FinFET. In the examples shown subsequently, it is assumed that both device regions 100 and 200 are logic FinFETs, and the corresponding gate dielectrics 40 are replaced by an interface layer. According to an alternative embodiment, one or both of the device regions 100 and 200 are IO device regions. A replacement gate stack is formed for an IO device with Figures 10 to 20 , except that the gate dielectric layer 40 is not replaced by the interfacial layer.

[0032] To distinguish features in device region 100 from features in device region 200, features in device region 100 may be distinguished using Figure 7A The reference numerals of the corresponding features in the device area 200 are indicated by adding the number 100, and the features in the device area 200 can be represented by using Figure 7A The reference numerals of the corresponding features in the embodiment are indicated by adding the number 200. For example, Figure 10 The source / drain regions 152 and 252 in FIG. Figure 7A source / drain regions 52 in the CMOS process, and Figure 10 The gate spacers 146 and 246 in FIG. Figure 7A The gate spacer 46 in FIG.

[0033] refer to Figure 10 , forming interface layers (IL) 164 and 264. The corresponding process is shown as Figure 24 The process 420 in the process flow 400 is shown. The ILs 164 and 264 are formed on the top surface and sidewalls of the protruding fins 136 and 236, wherein Figure 10 Portions of the IL 164 and 264 are shown on the top surfaces of the protruding fins 136 and 236. According to an alternative embodiment where one of the device regions is an IO region, the original gate dielectric 40 ( Figure 9B) remains, and a subsequently deposited high-k dielectric layer is formed over the original gate dielectric 40. ILs 164 and 264 may include an oxide layer, such as a silicon oxide layer, which is formed by a thermal oxidation process or a chemical oxidation process to oxidize the surface portions of the protruding fins 136 and 236. ILs 164 and 264 may also be formed by a deposition process. The chemical oxidation process may be performed using a chemical solution including NH4OH, H2O2, and H2O (sometimes referred to as a standard clean 1 (SC1) solution). The chemical oxidation process may also be performed using a sulfuric acid peroxide mixture (SPM) solution, which is a solution of sulfuric acid and hydrogen peroxide. Alternatively, the chemical oxidation process may be performed using a chemical solution including ozone (O3) dissolved in water.

[0034] According to alternative embodiments, ILs 164 and 264 are formed by thermal oxidation, which may be performed in a process gas such as N2O, O2, a mixture of N2O and H2, a mixture of H2 and O2, etc. The oxidation temperature may be in a range between about 500° C. and about 1000° C. According to some embodiments, the thickness T1 ( Figure 9B ) is greater than approximately And can be in about peace treaty Replace IL (for example, Figure 10 The thickness T2 of the IL 164 and 264 is less than the thickness T1. According to some embodiments, the thickness T2 is about peace treaty within the range between.

[0035] Next, refer to Figure 11 , first high-k dielectric layers 166 and 266 are deposited over respective ILs 164 and 264. The corresponding process is shown as Figure 24Process 422 of process flow 400 is shown. High-k dielectric layers 166 and 266 can be formed from a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), or combinations thereof, such as HfZrO, HfTiO, or the like. The high-k dielectric material can be pure (e.g., pure HfO2, pure ZrO2, or pure TiO2) or substantially pure (e.g., greater than approximately 90 atomic percent or 95 atomic percent). The high-k dielectric material has a dielectric constant (k value) greater than 3.9 and can be greater than approximately 7.0. High-k dielectric layers 166 and 266 overly and may be in physical contact with the corresponding underlying IL 164 and 264 (or gate dielectric layer 40). The high-k dielectric layers 166 and 266 are formed as conformal layers and extend over the sidewalls of the protruding fins 136 and 236, and the top surfaces and sidewalls of the gate spacers 146 and 246, respectively. According to some embodiments of the present disclosure, the high-k dielectric layers 166 and 266 are formed using ALD or CVD. The deposition temperature may be in the range of about 200° C. to about 400° C. The thickness T3 may be about 100° C. to about 100° C. peace treaty The first high-k dielectric layers 166 and 266 may be deposited in a common process and thus may be formed of the same material, or may be deposited in different processes and may be formed of different materials.

[0036] Further references Figure 11 , the first dipole film is deposited in the deposition process. The corresponding process is shown as Figure 24 Process 424 in process flow 400 is shown. The dipole film includes a dipole film (portion) 168 in device region 100 and a dipole film (portion) 268 in device region 200. Dipole films 168 and 268 are formed by a conformal deposition process such as an ALD process or a CVD process, such that the horizontal thickness of the horizontal portion and the vertical thickness of the vertical portion of dipole films 168 and 268 are substantially equal to each other, for example, with a thickness variation difference of less than about 20% or 10%. According to some embodiments of the present disclosure, dipole films 168 and 268 extend into openings 161 and 261 and include portions above ILD 60.

[0037] Dipole films 168 and 268 include dipole design dopants (hereinafter referred to as dipole dopants), such as lanthanum, aluminum, yttrium, titanium, magnesium, niobium, gallium, indium, etc. These elements can increase the number of dipoles when diffused into the high-k dielectric layer and cause the threshold voltage (Vt) of the corresponding FinFET to change. Different dipole dopants may have different effects on p-type transistors and n-type transistors. For example, La-based dipole dopants will cause the Vt of n-type transistors to decrease and will increase the Vt of p-type transistors. In contrast, Al-based dipole dopants will cause the Vt of n-type transistors to increase and the Vt of p-type transistors to decrease. Each dipole dopant can be present in both n-type transistors and p-type transistors at the same time, and any combination of different dipole dopants (as described above) can be present in n-type transistors or p-type transistors, or in p-type transistors and n-type transistors at the same time.

[0038] The dipole films 168 and 268 may be oxides and / or nitrides of dipole dopants. For example, the dipole films 168 and 268 containing La may be in the form of lanthanum oxide (La2O3), lanthanum nitride (LaN), etc., or a combination thereof. The dipole films 168 and 268 containing Al may be in the form of aluminum oxide (Al2O3), aluminum nitride (AlN), etc., or a combination thereof. The thickness T4 of the dipole films 168 and 268 may be about 1000 nm. peace treaty It has been appreciated that the thickness T4 of the dipole films 168 and 268 may generally be related to the magnitude of the desired threshold voltage adjustment, and that the greater the desired threshold voltage adjustment, the greater the thickness T4.

[0039] refer to Figure 12 , forming and patterning an etch mask 70. According to some embodiments, the etch mask 70 includes a bottom anti-reflective coating (BARC) 70A and a photoresist 70B on the BARC 70A. A hard mask (not shown) may also be added under the BARC 70A to assist in the etching process. The hard mask may be formed of a metal oxide such as titanium oxide, a metal nitride such as titanium nitride, or may include a metal nitride layer on top of a metal oxide layer.

[0040] Next, an etching process is performed in which the dipole film 168 is removed using the etching mask 70. The corresponding process is shown as Figure 24 As a result, the high-k dielectric layer 166 is exposed. Figure 13The resulting structure is shown in . According to some embodiments of the present disclosure, the etching process is performed by wet etching. For example, when the dipole film 168 is formed as a La-based material, an acidic wet etching chemical solution can be used. For example, the wet etching chemical may include an acid such as HCl, H2SO4, H2CO3, HF, etc., and the acid may be mixed with hydrogen peroxide (H2O2) and water, etc. When the dipole film 168 is formed as an Al-based material, an alkaline wet etching chemical solution may be used. For example, the wet etching chemical may include ammonia (NH3), hydrogen peroxide (H2O2), water, etc.

[0041] The etching mask 70 is then removed, resulting in Figure 14 The structure shown, wherein the dipole film 268 remains on the high-k dielectric layer 266, while no dipole film is on the high-k dielectric layer 166. Further reference Figure 14 , a drive-in annealing process 72 is performed. The corresponding process is shown as Figure 24 Process 428 in process flow 400 is shown. According to some embodiments, annealing process 72 is performed by soak annealing, spike rapid thermal annealing, or the like. When soak annealing is employed, the annealing duration may be in a range between approximately 5 seconds and approximately 5 minutes. The annealing temperature may be in a range between approximately 500° C. and approximately 950° C. The annealing process may be performed in a process gas such as N2, H2, NH3, or a mixture thereof. When a spike rapid thermal annealing process is employed, the annealing duration may be in a range between approximately 0.5 seconds and approximately 3.5 seconds. The annealing temperature may be in a range between approximately 700° C. and approximately 950° C. The annealing process may also be performed in a process gas such as N2, H2, NH3, or a mixture thereof. The annealing causes the dipole dopant to be driven into the high-k dielectric layer 266. Throughout the description, the high-k dielectric layer 266 doped with the dipole dopant is referred to as the (dipole dopant-containing) high-k dielectric layer 266′. Due to the nature of diffusion, the highest concentration of the dipole dopant is at the interface between layers 266' and 268, and the dopant concentration gradually decreases in the direction of arrow 73. According to some embodiments, the dose of the dipole dopant in the high-k dielectric layer and the underlying layers is approximately 0 atoms / cm 2 to about 1E17 atoms / cm 2 within the range.

[0042] After the drive-in annealing process 72, the dipole film 268 is removed in an etching process. The corresponding process is shown as Figure 24 The process 430 in the process flow 400 is shown. The etching process can be performed from the Figure 12 The etching process shown in FIG. 1 is selected from the same set of candidate processes and uses the same set of candidate etching chemicals. Therefore, the details are not repeated here. The resulting structure is shown in FIG. Figure 15shown.

[0043] According to alternative embodiments and / or in another device region, the process of removing dipole film 168 prior to drive-in annealing process 72 is omitted. Therefore, the dipole dopant in dipole film 168 also diffuses into high-k dielectric 166. According to these embodiments, both high-k dielectric layers 166 and 266 are doped with the dipole dopant.

[0044] Figures 16 to 20 Deposition of a second high-k dielectric layer and a second drive-in anneal process are shown in accordance with some embodiments. It should be understood that some material and process details may vary. Figures 11 to 15 These details are not repeated and can be found in the description of the previous process.

[0045] refer to Figure 16 , high-k dielectric layers 174 and 274 are deposited. The corresponding process is shown as Figure 24 The process 432 in the process flow 400 is shown. The materials of the high-k dielectric layers 174 and 274 can be selected from the same materials used to form the high-k dielectric layers 166 and 266 ( Figure 11 ) and may include HfO2, ZrO2, TiO2, etc., or a combination thereof, for example, HfZrO, HfTiO, etc. The high-k dielectric layers 174 and 274 overlie the corresponding underlying high-k dielectric layers 166 and 266 and may be in contact therewith. According to some embodiments of the present disclosure, the high-k dielectric layers 174 and 274 are formed using ALD or CVD. The deposition temperature may be in a range between about 200°C and about 400°C. The thickness T5 may be equal to or less than the thickness of the underlying high-k dielectric layers 166 and 266'. For example, the thickness T5 may be about peace treaty within the range between.

[0046] According to some embodiments, high-k dielectric layers 174 and 274 are formed of a material having a lower k value than that of high-k dielectric layer 166. For example, high-k dielectric layers 174 and 274 may be formed of HfO2, while high-k dielectric layers 166 and 266 may be formed of ZrO2 or TiO2. According to alternative embodiments, high-k dielectric layers 174 and 274 have the same k value as high-k dielectric layers 166 and 266 and are formed of the same material. According to yet another alternative embodiment, high-k dielectric layers 174 and 274 have a greater k value than high-k dielectric layers 166 and 266. For example, high-k dielectric layers 174 and 274 may be formed of ZrO2 or TiO2, while high-k dielectric layers 166 and 266 may be formed of HfO2.

[0047] Further references Figure 16, the dipole films 176 and 276 are formed by a conformal deposition process such as an ALD process or a CVD process. The corresponding process is shown as Figure 24 The process 434 in the process flow 400 is shown. The dipole films 176 and 276 include a dipole dopant, such as lanthanum (e.g., La2O3 or LaN), aluminum (e.g., Al2O3 or AlN), etc. The dipole dopant of the dipole films 176 and 276 can be the same as or different from the dipole dopant of the dipole films 168 and 268. The thickness T6 of the dipole films 176 and 276 can be about peace treaty within the range between.

[0048] Figure 16 It is further shown that an etching mask 78 is formed, which may have a structure similar to that of the etching mask 70. Therefore, the details are not repeated here. In a subsequent process, an etching process is performed to remove the dipole film 276, and thus the high-k dielectric layer 274 is exposed, as shown in FIG. Figure 17 The corresponding process is shown as Figure 24 The process 436 in the process flow 400 is shown. The etching process can be Figure 12 and Figure 13 The same as shown. Then remove the etching mask 78 (as Figure 16 ), exposing the dipole film 176.

[0049] Further references Figure 17 , a drive-in annealing process 80 is performed. The corresponding process is shown as Figure 24 The process 438 in the process flow 400 is shown. The drive-in annealing process 80 is similar to Figure 14 The drive-in annealing process 72 in FIG. 1 is described in detail, and therefore the details are not repeated here. The dipole dopant in the dipole film 176 diffuses into the high-k dielectric layer 174 and may diffuse into the high-k dielectric layer 166 at a lower doping concentration than in the high-k dielectric layer 174. In the following paragraphs, the high-k dielectric layer 174 doped with the dipole dopant is referred to as the (dipole dopant-containing) high-k dielectric layer 174′.

[0050] After the drive-in annealing process, the dipole film 176 is removed in an etching process. The corresponding process is shown as Figure 24 The process 440 in the process flow 400 is shown. The etching process can be selected from Figure 12 The etching process shown in FIG. 1 is the same set of candidate processes and uses the same set of candidate etching chemicals. Therefore, the details will not be repeated here. The resulting structure is shown in FIG. Figure 18 shown.

[0051] According to alternative embodiments and / or in another device region, the process of removing dipole film 276 prior to drive-in annealing process 80 is omitted. Therefore, the dipole dopant in dipole film 276 also diffuses into high-k dielectric 274. According to these embodiments, both high-k dielectric layers 174 and 274 are doped with the dipole dopant.

[0052] As described above, the k value of the lower high-k dielectric layer 166 / 266 can be less than, equal to, or greater than the k value of the upper high-k dielectric layer 174 / 274. Furthermore, dipole doping can be performed on either the lower high-k dielectric layer (e.g., 266) or the upper high-k dielectric layer (e.g., 174). Doping the lower high-k dielectric layer has a different effect on adjusting Vt than doping the upper high-k dielectric layer. For example, doping the lower high-k dielectric layer can change Vt more than doping the upper high-k dielectric layer. Additionally, doping a high-k dielectric layer with a lower k value has a different effect on adjusting Vt than doping a high-k dielectric layer with a higher k value. For example, doping a high-k dielectric layer with a higher k value can change Vt more than doping a high-k dielectric layer with a lower k value. Therefore, by selecting whether the upper high-k dielectric layer has a k value higher, equal to, or lower than the lower high-k dielectric layer (with three possibilities), and selecting whether to dope the upper high-k dielectric layer, the lower dielectric layer, or both (with three possibilities), 9 (3×3) potential Vt adjustment levels are generated. According to some embodiments, FinFETs with these different Vt adjustment levels are formed on the same chip according to design requirements. In addition, since different dipole dopants such as La and Al also have different Vt adjustment capabilities, the Vt adjustment levels are further multiplied by using different dipole dopants for different FinFETs.

[0053] Figure 19 The formation of gate electrodes 186 and 286 is shown, which include stacked layers 182 and 282 and possible metal fill regions 184 and 284, respectively. The corresponding process is shown as Figure 24Process 442 in the process flow 400 is shown. According to some embodiments of the present disclosure, each of the stacked layers 182 and 282 includes an adhesion layer (also called a barrier layer, not shown), which can be formed of TiN, TiSiN, etc. The stacked layers 182 and 282 also include a work function layer, which can include a TiN layer, a TaN layer, and / or an Al-based layer (for example, formed of TiAlN, TiAlC, TaAlN, or TaAlC), depending on whether the corresponding FinFET is a p-type FinFET or an n-type FinFET. If layers 182 and 282 do not completely fill the trench, a barrier layer (not shown) and a fill metal represented by layers 184 and 284 are then deposited. Otherwise, layers 184 and 284 are not required. A planarization process such as a CMP process or a mechanical grinding process is then performed to form gate electrodes 186 and 286. Replacement gate stacks 188 and 288 are also formed, including respective gate electrodes 186 and 286 and respective gate dielectrics 164 / 166 / 174' and 264 / 266' / 274, thereby forming FinFETs 190 and 290.

[0054] refer to Figure 20 , gate stacks 188 and 288 are recessed and filled with a dielectric material (e.g., SiN) to form hard masks 192 and 292. An etch stop layer 93 is formed over hard masks 192 and 292 and ILD 60. Etch stop layer 93 is formed of a dielectric material, which may include silicon carbide, silicon nitride, silicon oxynitride, etc. ILD 94 is formed over etch stop layer 78, and gate contact plugs 195 and 295 are formed.

[0055] Figure 21 shows that the dipole dopant Figure 20 Distribution in some parts of the gate stack shown. Figure 21 Region 502 ( Figure 20 ) and an enlarged view of region 504 ( Figure 20 ). Schematic dopant concentrations are shown on the left side of the respective enlarged views of regions 502 and 504. In region 502, before forming stacked metal layer 182, the peak concentration of the dipole concentration occurs at the top surface of high-k dielectric layer 174'. In subsequent thermal processes, the dipole dopant diffuses upward and downward, and thus produces Figure 21 1 . The dopant profile is shown, wherein the peak dipole dopant concentration profile 506 is located at (or slightly below) the top surface of the high-k dielectric layer 174'. The dipole dopant concentration gradually decreases in the upward and downward directions. In region 504, the peak dipole dopant concentration profile 508 is located at (or slightly below) the top surface of the high-k dielectric layer 266' and gradually decreases in the upward and downward directions.

[0056] Figure 22 shows the assumption that when executing Figure 14 During the drive-in annealing process 72 shown, the dipole film 168 is not removed ( Figure 12 ) dopant concentration. Thus, in region 502, high-k dielectric layer 166 is also diffused with a dipole dopant, and thus high-k dielectric layer 166' is formed. The resulting dipole dopant concentration profiles 510 and 512 are schematically shown, and dipole dopant concentration profile 510 represents the dopant of dipole film 168, with its peak located at (or slightly below) the top surface of high-k dielectric layer 166'. Dipole dopant concentration profile 512 represents the dopant of dipole film 176, with its peak located at (or slightly below) the top surface of high-k dielectric layer 174'. Thus, the total dipole dopant concentration is the sum of dipole dopant concentration profiles 510 and 512. The dipole dopants of profiles 510 and 512 can be the same as or different from each other. For example, one of dopant profiles 510 and 512 can be La, and the other can be Al. Although La and Al may have opposite effects (one increases Vt and the other decreases Vt), the combination produces an additional Vt level.

[0057] Figure 23 Example embodiments are shown in which each of high-k dielectric layers 166 and 174 is formed using multiple deposition processes to form multiple sublayers. For each sublayer of high-k dielectric layers 166 and 174, multiple dipole film deposition processes, drive-in annealing processes, and dopant film removal processes are interleaved between the multiple deposition processes. According to these embodiments, the sublayers of high-k dielectric layer 166 are formed from the same high-k dielectric material and have the same k value. The first dipole dopant of the sublayers of high-k dielectric layer 166 is also identical to one another. Similarly, the sublayers of high-k dielectric layer 174 are formed from the same high-k dielectric material and have the same k value. The second dipole dopant of the sublayers of high-k dielectric layer 174 is also identical to one another. The first dipole dopant can be the same as or different from the second dipole dopant. The distribution of the first dipole dopant is shown as 514, and the distribution of the second dipole dopant is shown as 516. Alternating deposition and drive-in annealing processes can produce a more uniform dipole dopant distribution.

[0058] It should be understood that including Figure 21 、 Figure 22 and Figure 23 The aforementioned embodiments may coexist in the same chip and on the same semiconductor substrate 20. In addition, multiple (eg, 1, 2, or 3) high-k dielectric layers may be formed on the Figure 20 The dielectric layer shown is above the high-k dielectric layer, and each high-k dielectric layer is doped or not doped by a corresponding subsequent dipole dopant deposition and drive-in anneal process. This produces more Vt adjustment levels for different FinFETs on the same chip.

[0059] The disclosed embodiments have several advantageous features. By forming multiple high-k dielectric layers with the same or different k values, and further selectively doping selected high-k dielectric layers with dipole dopants, multiple Vt adjustment levels can be achieved to meet different circuit requirements. By doping with dipoles, the CET value of the transistor is increased, enhancing the feasibility of CET scaling.

[0060] According to some embodiments of the present disclosure, a method includes: forming a first oxide layer on a first semiconductor region; depositing a first high-k dielectric layer over the first oxide layer, wherein the first high-k dielectric layer is formed of a first high-k dielectric material; depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material; depositing a first dipole film over and in contact with a first layer selected from the first high-k dielectric layer and the second high-k dielectric layer; performing a first annealing process to drive a first dipole dopant in the first dipole film into the first layer; removing the first dipole film; and forming a first gate electrode over the second high-k dielectric layer. In one embodiment, the first dipole film is deposited over and in contact with the first high-k dielectric layer. In one embodiment, the first dipole film is deposited over and in contact with the second high-k dielectric layer. In one embodiment, the second high-k dielectric layer has a higher k value than the first high-k dielectric layer. In one embodiment, the second high-k dielectric layer has a lower k value than the first high-k dielectric layer. In one embodiment, the method further includes: forming a second oxide layer on the second semiconductor region, wherein both the first high-k dielectric layer and the second high-k dielectric layer further extend on the second oxide layer; depositing a second dipole film on and in contact with a second layer selected from the first high-k dielectric layer and the second high-k dielectric layer, wherein the second layer is different from the first layer and wherein the second dipole film overlaps the second semiconductor region; performing a second annealing process to drive a second dipole dopant in the second dipole film into the second layer; removing the second dipole film; and forming a second gate electrode on the second high-k dielectric layer, wherein the second gate electrode overlaps the second semiconductor region. In one embodiment, the method further includes: removing the second dipole film from a region directly above the first semiconductor region before the second annealing process. In one embodiment, the first dipole film comprises a material selected from lanthanum oxide, lanthanum nitride, aluminum oxide, aluminum nitride, or a combination thereof.

[0061] According to some embodiments of the present disclosure, a device includes: a first oxide layer on a first semiconductor region; a first high-k dielectric layer including a first high-k dielectric material; a second high-k dielectric layer including a second high-k dielectric material different from the first high-k dielectric material, wherein the second high-k dielectric layer overlies and contacts the first high-k dielectric layer; a first dipole dopant in the first high-k dielectric layer and the second high-k dielectric layer, wherein a first peak concentration of the first dipole dopant is at a first top surface of the first high-k dielectric layer or a second top surface of the second high-k dielectric layer; a gate electrode on the second high-k dielectric layer; and a source / drain region on one side of the gate electrode. In one embodiment, the first dipole dopant includes lanthanum. In one embodiment, the first dipole dopant includes aluminum. In one embodiment, the first peak concentration of the first dipole dopant is at the first top surface, and the device further includes a second dipole dopant different from the first dipole dopant, wherein the second dipole dopant has a second peak concentration at the second top surface. In one embodiment, a first of the first and second dipole dopants is lanthanum, and a second of the first and second dipole dopants is aluminum, and both lanthanum and aluminum are diffused into each of the first and second high-k dielectric layers. In one embodiment, the second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

[0062] According to some embodiments of the present disclosure, a device includes: a first transistor, the first transistor including: a first portion of a first high-k dielectric layer; a first portion of a second high-k dielectric layer, wherein the second high-k dielectric layer is above the first high-k dielectric layer and wherein the first high-k dielectric layer and the second high-k dielectric layer have different k values; a first dipole dopant having a first peak concentration at an interface between the first portion of the first high-k dielectric layer and the first portion of the second high-k dielectric layer; and a second transistor, the second transistor including: a second portion of the first high-k dielectric layer; a second portion of the second high-k dielectric layer; and a second dipole dopant having a second peak concentration at a top surface of the second high-k dielectric layer. In one embodiment, the first dipole dopant and the second dipole dopant are the same. In one embodiment, the first dipole dopant and the second dipole dopant are different from each other. In one embodiment, the first dipole dopant and the second dipole dopant are selected from lanthanum and aluminum. In one embodiment, a first of the first dipole dopant and the second dipole dopant is lanthanum, and a second of the first dipole dopant and the second dipole dopant is aluminum. In one embodiment, the first transistor and the second transistor have the same conductivity type.

[0063] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0064] Example 1 is a method for forming a semiconductor device, comprising: forming a first oxide layer on a first semiconductor region; depositing a first high-k dielectric layer over the first oxide layer, wherein the first high-k dielectric layer is formed of a first high-k dielectric material; depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material; depositing a first dipole film over and in contact with the first high-k dielectric layer and the second high-k dielectric layer, wherein the first dipole film is in contact with a first layer and the first layer is one of the first high-k dielectric layer and the second high-k dielectric layer; performing a first annealing process to drive a first dipole dopant in the first dipole film into the first layer; removing the first dipole film; and forming a first gate electrode over the second high-k dielectric layer.

[0065] Example 2 is the method of Example 1, wherein the first dipole film is deposited over and in contact with the first high-k dielectric layer.

[0066] Example 3 is the method of Example 1, wherein the first dipole film is deposited over and in contact with the second high-k dielectric layer.

[0067] Example 4 is the method of Example 1, wherein the second high-k dielectric layer has a higher k value than the first high-k dielectric layer.

[0068] Example 5 is the method of Example 1, wherein the second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

[0069] Example 6 is the method described in Example 1, further comprising: forming a second oxide layer on the second semiconductor region, wherein both the first high-k dielectric layer and the second high-k dielectric layer further extend on the second oxide layer; depositing a second dipole film on and in contact with a second layer selected from the first high-k dielectric layer and the second high-k dielectric layer, wherein the second layer is different from the first layer, and wherein the second dipole film overlaps with the second semiconductor region; performing a second annealing process to drive a second dipole dopant in the second dipole film into the second layer; removing the second dipole film; and forming a second gate electrode on the second high-k dielectric layer, wherein the second gate electrode overlaps with the second semiconductor region.

[0070] Example 7 is the method of Example 6, further comprising: before the second annealing process, removing the second dipole film from a region directly above the first semiconductor region.

[0071] Example 8 is the method of Example 1, wherein the first dipole film comprises a material selected from lanthanum oxide, lanthanum nitride, aluminum oxide, aluminum nitride, or a combination thereof.

[0072] Example 9 is a semiconductor device comprising: a first oxide layer on a first semiconductor region; a first high-k dielectric layer comprising a first high-k dielectric material; a second high-k dielectric layer comprising a second high-k dielectric material different from the first high-k dielectric material, wherein the second high-k dielectric layer overlies the first high-k dielectric layer and contacts the first high-k dielectric layer; a first dipole dopant in the first high-k dielectric layer and the second high-k dielectric layer, wherein a first peak concentration of the first dipole dopant is at a first top surface of the first high-k dielectric layer or a second top surface of the second high-k dielectric layer; a gate electrode on the second high-k dielectric layer; and a source / drain region on one side of the gate electrode.

[0073] Example 10 is the device of Example 9, wherein the first dipole dopant comprises lanthanum.

[0074] Example 11 is the device of Example 9, wherein the first dipole dopant comprises aluminum.

[0075] Example 12 is the device of Example 9, wherein the first peak concentration of the first dipole dopant is at the first top surface, and the device further comprises a second dipole dopant different from the first dipole dopant, wherein the second dipole dopant has a second peak concentration at the second top surface.

[0076] Example 13 is the device of Example 12, wherein a first of the first dipole dopant and the second dipole dopant is lanthanum, and a second of the first dipole dopant and the second dipole dopant is aluminum, and both lanthanum and aluminum are diffused into each of the first high-k dielectric layer and the second high-k dielectric layer.

[0077] Example 14 is the device of Example 9, wherein the second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

[0078] Example 15 is a semiconductor device comprising: a first transistor, the first transistor comprising: a first portion of a first high-k dielectric layer; a first portion of a second high-k dielectric layer, wherein the second high-k dielectric layer is above the first high-k dielectric layer and wherein the first high-k dielectric layer and the second high-k dielectric layer have different k values; a first dipole dopant having a first peak concentration at an interface between the first portion of the first high-k dielectric layer and the first portion of the second high-k dielectric layer; and a second transistor comprising: a second portion of the first high-k dielectric layer; a second portion of the second high-k dielectric layer; and a second dipole dopant having a second peak concentration at a top surface of the second high-k dielectric layer.

[0079] Example 16 is the device of Example 15, wherein the first dipole dopant is the same as the second dipole dopant.

[0080] Example 17 is the device of Example 15, wherein the first dipole dopant and the second dipole dopant are different from each other.

[0081] Example 18 is the device of Example 15, wherein the first dipole dopant and the second dipole dopant are selected from lanthanum and aluminum.

[0082] Example 19 is the device of Example 15, wherein a first one of the first dipole dopant and the second dipole dopant is lanthanum, and a second one of the first dipole dopant and the second dipole dopant is aluminum.

[0083] Example 20 is the device of Example 19, wherein the first transistor and the second transistor have the same conductivity type.

Claims

1. A method for forming a semiconductor device, comprising: forming a first oxide layer on the first semiconductor region; depositing a first high-k dielectric layer over the first oxide layer, wherein the first high-k dielectric layer is formed of a first high-k dielectric material; depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material; depositing a first dipole film over and in contact with the second high-k dielectric layer; performing a first annealing process to drive a first dipole dopant in the first dipole film into the second high-k dielectric layer; removing the first dipole film; and forming a first gate electrode over the second high-k dielectric layer; The method further comprises: before depositing the second high-k dielectric layer, depositing a second dipole film over and in contact with the first high-k dielectric layer; After depositing the second dipole film, performing a second annealing process to drive the second dipole dopant in the second dipole film into the first high-k dielectric layer; After the second annealing process is performed, the second dipole film is removed.

2. The method according to claim 1, wherein The second high-k dielectric layer has a higher k value than the first high-k dielectric layer.

3. The method according to claim 1, wherein The second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

4. The method according to claim 1, further comprising: forming a second oxide layer on the second semiconductor region, wherein the first high-k dielectric layer is also deposited on the second oxide layer; and After removing the second dipole film and depositing the second high-k dielectric layer on the first high-k dielectric layer, a second gate electrode is formed on the second high-k dielectric layer, wherein the second gate electrode overlaps the second semiconductor region.

5. The method according to claim 4, further comprising: Before the second annealing process, the second dipole film is removed from a region directly above the first semiconductor region.

6. The method according to claim 1, wherein The first dipole film includes a material selected from lanthanum oxide, lanthanum nitride, aluminum oxide, aluminum nitride, or a combination thereof.

7. A semiconductor device comprising: a first oxide layer on the first semiconductor region; a first high-k dielectric layer comprising a first high-k dielectric material overlying the first oxide layer; a second high-k dielectric layer comprising a second high-k dielectric material different from the first high-k dielectric material, wherein the second high-k dielectric layer overlies and contacts the first high-k dielectric layer; a first dipole dopant in the first high-k dielectric layer and the second high-k dielectric layer; a gate electrode on the second high-k dielectric layer; and source / drain regions, on one side of the gate electrode, wherein the first dipole dopant has a first peak concentration at a first top surface of the first high-k dielectric layer, and the device further comprises a second dipole dopant different from the first dipole dopant, wherein the second dipole dopant has a second peak concentration at a second top surface of the second high-k dielectric layer.

8. The device according to claim 7, wherein The first dipole dopant includes lanthanum.

9. The device according to claim 7, wherein The first dipole dopant includes aluminum.

10. The device according to claim 7, wherein A first of the first and second dipole dopants is lanthanum, and a second of the first and second dipole dopants is aluminum, and both lanthanum and aluminum are diffused into each of the first and second high-k dielectric layers.

11. The device according to claim 7, wherein The second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

12. A semiconductor device comprising: A first transistor, the first transistor comprising: a first portion of a first high-k dielectric layer; a first portion of a second high-k dielectric layer, wherein the second high-k dielectric layer is over the first high-k dielectric layer, and wherein the first high-k dielectric layer and the second high-k dielectric layer have different k values; a first dipole dopant having a first peak concentration at an interface between a first portion of the first high-k dielectric layer and a first portion of the second high-k dielectric layer; a second dipole dopant having a second peak concentration at a top surface of the first portion of the second high-k dielectric layer, wherein the second dipole dopant is different from the first dipole dopant, and A second transistor comprising: a second portion of the first high-k dielectric layer; a second portion of the second high-k dielectric layer; and The second dipole dopant has a third peak concentration at the top surface of the second high-k dielectric layer.

13. The device according to claim 12, wherein The first dipole dopant is the same as the second dipole dopant.

14. The device according to claim 12, wherein The first dipole dopant and the second dipole dopant are different from each other.

15. The device according to claim 12, wherein The first dipole dopant and the second dipole dopant are selected from lanthanum and aluminum.

16. The device according to claim 12, wherein A first of the first dipole dopant and the second dipole dopant is lanthanum, and a second of the first dipole dopant and the second dipole dopant is aluminum.

17. The device according to claim 16, wherein The first transistor and the second transistor have the same conductivity type.

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