Semiconductor device and manufacturing method thereof

Abstract

Disclosed are a semiconductor device having improved selector characteristics of a memory cell and a method for manufacturing the same. The semiconductor device includes a plurality of memory cells, where each of the memory cells includes: a memory layer; a selector layer formed in an upper portion or a lower portion of the memory layer to select the memory layer; and a buffer layer directly coupled to an upper portion or a lower portion of the selector layer, where the buffer layer includes an amorphous silicon layer including at least one dopant selected from a group including Group 13 elements, Group 14 elements, and Group 15 elements of the periodic table.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0108359, filed on August 13, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor technology, and more specifically, to a semiconductor device including a memory cell having a selector and a method for manufacturing the semiconductor device. Background Technology

[0004] Recently, there has been a need for semiconductor devices capable of storing data in various electronic devices such as computers and portable communication devices to address the trends of miniaturization, low power consumption, high performance, and diversification in electronic devices. Researchers and industry are researching and developing such semiconductor devices. Semiconductor devices can store data by utilizing the property of switching between different resistance states according to the applied voltage or current, and can include: resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuses, etc.

[0005] Memory devices with variable resistance elements may include selectors as elements for selecting a specific memory cell among a plurality of memory cells arranged in an array, and the selector may be implemented as a thin layer in the memory cell. Summary of the Invention

[0006] Embodiments of this disclosure relate to a semiconductor device with improved selector characteristics for memory cells and a method for manufacturing the semiconductor device.

[0007] According to embodiments of the present disclosure, a semiconductor device includes: a plurality of memory cells, wherein each memory cell includes: a memory layer; a selector layer formed in an upper or lower portion of the memory layer to select the memory layer; and a buffer layer directly coupled to the upper or lower portion of the selector layer, and the buffer layer includes an amorphous silicon layer comprising at least one dopant selected from the group consisting of elements of Group 13, Group 14 and Group 15 of the periodic table.

[0008] According to another embodiment of the disclosure, a method for manufacturing a semiconductor device including a plurality of memory cells includes forming a selector layer; and forming an amorphous silicon layer including a dopant as a buffer layer on an upper portion or a lower portion of the selector layer, wherein the buffer layer includes an amorphous silicon layer including at least one dopant selected from a group including a group 13 element, a group 14 element, and a group 15 element of the periodic table.

[0009] These and other features and advantages of embodiments of the present application will be better understood by persons of ordinary skill in the art upon reading the details of the following examples in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1A and FIG. 1B A semiconductor device according to an embodiment of the disclosure is illustrated.

[0011] FIG. 2 is a cross-sectional view illustrating a structure of a selector unit SU according to an embodiment of the disclosure.

[0012] FIG. 3A and FIG. 3B A semiconductor device according to another embodiment of the disclosure is illustrated.

[0013] FIG. 4 is a cross-sectional view illustrating a structure of a selector unit SU in an off state and an on state according to an embodiment of the disclosure.

[0014] FIG. 5 An operation of a selector unit SU according to an embodiment of the disclosure is illustrated.

[0015] FIGS. 6A-7D is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0016] Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0017] Embodiments of the disclosure will be described in greater detail below with reference to the accompanying drawings. However, the embodiments can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, the embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. In the entire disclosure, the same reference numerals refer to the same components throughout the various drawings and embodiments of the disclosure.

[0018] The drawings are not necessarily to scale and, in some instances, proportionalities can have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it not only refers to the case where the first layer is directly formed on the second layer or the substrate, but also refers to the case where a third layer is present between the first layer and the second layer or the substrate.

[0019] FIG. 1A and FIG. 1B A semiconductor memory according to an embodiment of the disclosure is illustrated. FIG. 1A is a perspective view, and FIG. 1B is a cross-sectional view taken along FIG. 1A line A-A' shown. A semiconductor memory according to an embodiment of the disclosure can have a structure in which a buffer layer 131 is formed over a selector layer 140.

[0020] Referring to FIG. 1A and FIG. 1B , a semiconductor device according to an embodiment of the disclosure can have a cross-point structure including a substrate 100, a plurality of first conductive lines 110 disposed over the substrate 100 and extending in a first direction, a plurality of second conductive lines 120 disposed over the first conductive lines 110 and extending in a second direction intersecting the first direction, and a plurality of memory cells MC disposed to overlap with intersection regions between the first conductive lines 110 and the second conductive lines 120. Here, the first direction and the second direction can refer to directions substantially parallel to a surface of the substrate 100. Hereinafter, a direction substantially perpendicular to the surface of the substrate 100 can be referred to as a vertical direction.

[0021] The substrate 100 can include a semiconductor material such as silicon. In addition, a predetermined desired lower structure (not shown) can be formed in the substrate 100. For example, an integrated circuit for driving the first conductive lines 110 and / or the second conductive lines 120 can be formed in the substrate 100.

[0022] The first conductive lines 110 can be disposed at regular intervals from each other along the second direction. The first conductive lines 110 can include various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or the like, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof. The first conductive lines 110 can have a single-layer structure or a multi-layer structure.

[0023] The plurality of second conductive lines 120 can be disposed at regular intervals from each other in the first direction. The second conductive lines 120 can include various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or the like, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof. The second conductive lines 120 can have a single-layer structure or a multi-layer structure.

[0024] Each memory cell MC can include a memory cell MU that actually stores data and a selector unit SU that controls access to the memory cell MU. Each memory cell MC can include a first electrode layer 130 disposed below the selector layer 140 and a second electrode layer 150 and / or a third electrode layer 170 disposed above the selector layer 140. In each memory cell MC, a buffer layer 131 can be disposed between the selector layer 140 and the first electrode layer 130. For example, the memory cell MC can include a stack structure of the first electrode layer 130, the buffer layer 131, the selector layer 140, the second electrode layer 150, the memory layer 160, and the third electrode layer 170, which are stacked in the order on a corresponding one of the first conductive lines 110. For example, the order of the buffer layer 131 and the selector layer 140 can be switched. The selector unit SU can include the first electrode layer 130, the buffer layer 131, the selector layer 140, and the second electrode layer 150. The memory cell MU can include the second electrode layer 150, the memory layer 160, and the third electrode layer 170. Accordingly, the second electrode layer 150 can be shared by the selector unit SU and the memory cell MU.

[0025] The first electrode layer 130 and the third electrode layer 170 can be disposed at both end portions, i.e., a bottom end portion and a top end portion, of the memory cell MC, respectively, and can be used to apply a voltage or a current required to operate the memory cell MC. The second electrode layer 150 can be used to electrically connect the selector layer 140 and the memory layer 160 to each other while physically separating them from each other. The first electrode layer 130, the second electrode layer 150, or the third electrode layer 170 can include various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), or the like, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof. In addition, the first electrode layer 130, the second electrode layer 150, or the third electrode layer 170 can include a carbon electrode. Each memory cell MC can include a thin layer of SiN at an interface between the first electrode layer 130 and the selector layer 140, and a thin layer of carbon (C) at an interface between the selector layer 140 and the second electrode layer 150.

[0026] The storage layer 160 can be used to store data in various ways. For example, the storage layer 160 can include a variable resistance layer that stores different data by switching between different resistance states according to a voltage or a current supplied through upper and lower end portions of the storage layer 160. The variable resistance layer can have a single layer structure or a multi-layer structure including various materials used in resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), etc.: for example, metal oxides such as transition metal oxides, perovskite-based materials, etc., phase change materials such as chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc.

[0027] The selector layer 140 can be formed as a thin layer in the storage cells. A thin layer as described herein refers to a layer having a thickness of 1 nm to 100 nm, 1 nm to 50 nm, or 1 nm to 30 nm. The selector layer 140 can have a function of preventing current leakage that can occur between storage cells sharing the first or second conductive lines 110 and 120, while controlling electrical access to one of the storage cells in the array arrangement. To this end, the selector layer 140 can have a threshold switching characteristic that blocks current or keeps current from flowing almost at all when a voltage level supplied to upper and lower end portions of the selector layer 140 is below a predetermined threshold voltage level. This means that below the threshold voltage, the selector layer 140 allows almost no current to flow, effectively blocking current. However, at a voltage level equal to or higher than the predetermined threshold voltage level, the selector layer 140 allows current to flow freely. The selector layer 140 can be turned on at a voltage level equal to or higher than the threshold voltage level, and turned off at a voltage level below the threshold voltage level.

[0028] In general, the selector layer 140 can use a dielectric material in which a dopant is implanted. The dielectric material included in the selector layer 140 can include a silicon oxide layer or an amorphous silicon layer. The dopant implanted into the selector layer 140 can include an N-type dopant or a P-type dopant, and the dopant can be implanted through an ion implantation process. The dopant can include, for example, one or more selected from a group including boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), and germanium (Ge).

[0029] Generally, an oxide layer such as SiO2may be formed by mixing a source gas containing silicon (Si) and oxygen (O) using a method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. Since the deposited oxide layer formed in this way has a relatively low density, there is a problem that, when a dopant is subsequently injected through an ion implantation process, micro voids are formed in the inside of a portion of the surface of the first electrode layer 130 disposed in the lower portion of the deposited oxide layer, or the portion of the surface can be damaged, so that the interface between the selector layer 140 and the first electrode layer 130 is not clear.

[0030] In the selector layer 140, strong scattering can occur due to the bonding of silicon (Si) and oxygen (O), and the possibility of forming clusters can increase. Scattering refers to a phenomenon in which an electron changes its direction or speed by interacting with other physical objects in a semiconductor material or semiconductor device. Electron scattering can have a significant impact on the determination of the electron movement path and the determination of electrical characteristics. A cluster can refer to a group of atoms or molecules present in a semiconductor material or semiconductor structure. These clusters can have a significant impact on the characteristics of a semiconductor device, and generally affect the performance or stability of the device. Clusters can cause dispersion of key performance indicators (KPIs), and can cause instability in the manufacturing process.

[0031] To address this problem, in the preferred embodiments of the present disclosure, a buffer layer 131 including an amorphous silicon layer directly coupled to the upper or lower portion of the selector layer 140 and having one or more dopants selected from the group including a group 13 element, a group 14 element, and a group 15 element of the periodic table can be used. This can suppress the occurrence of clusters in the selector layer and reduce the dispersion of KPIs.

[0032] According to embodiments of the present disclosure, the following advantages can be obtained compared to a comparative example. Herein, the comparative example corresponds to a case where a selector layer is formed by implanting arsenic (As) ions into silicon oxide and there is no buffer layer. FIG. 2 The graph of FIG. 1 illustrates the thickness distribution of a selector according to the comparative example (arsenic (As) doped silicon oxide with 1 standard deviation, and no buffer layer), and the thickness distribution of a selector according to an embodiment of the present disclosure in which a buffer layer of boron (B) doped amorphous silicon layer with 1 standard deviation is disposed in the upper or lower portion of the selector. The standard deviation (σ) is an index for measuring the standard deviation of the distribution of data in statistics. Thus, 1 standard deviation can represent a range that differs from the average value by one standard deviation.

[0033] Here, #10 is Example 1 in which an oxide layer having a thickness of about 10 nm and a boron (B) doped amorphous silicon layer having a thickness of about 10 nm are sequentially deposited on the selector layer. Here, #10 is Example 1 in which an oxide layer having a thickness of about 10 nm and a boron (B) doped amorphous silicon layer having a thickness of about 10 nm are sequentially deposited on the selector layer. A boron-doped amorphous silicon layer, and #11 is Example 2, wherein a thickness of approximately [thickness missing] is sequentially deposited on top of the selector layer. The boron-doped amorphous silicon layer has a thickness of approximately The oxide layer. Furthermore, #13 is Example 3, where a thickness of approximately [thickness missing] is deposited over the selector layer. A boron-doped amorphous silicon layer, and #12 is a comparative example, wherein a thickness of approximately [thickness missing] is deposited on top of the selector layer. The oxide layer. As described herein, when referring to numerical ranges, the term "about" means within ±5% of the stated value. Here, all selector layers may have an arsenic-doped silicon oxide layer. FIG. 2 As shown, the thickness dispersion of the selector according to the comparative example, without a buffer layer having a boron-doped amorphous silicon layer, is about 8.03%, while the thickness dispersion of the selectors according to Examples 1 to 3, wherein a buffer layer having a boron-doped amorphous silicon layer is disposed above the selector, is very low, at about 1.47%, 1.73%, and 1.74%, respectively. This demonstrates that embodiments of the present disclosure can minimize scattering and clustering of the selector and reduce the thickness dispersion of the selector. The oxide layer disposed above the selector layer can preferably have about 20 to... The buffer layer, having a thickness of approximately 20 and having a boron-doped amorphous silicon layer, can preferably have a thickness of approximately 20. The thickness.

[0034] In the buffer layer according to embodiments of this disclosure, conductive paths can be formed in the vacant sites lacking monovalent by doping amorphous silicon (a group 14 element of the periodic table) with a first dopant (a group 13 element of the periodic table), and the amorphous silicon layer can be made conductive by ion implantation of a second dopant (a group 14 or 15 element of the periodic table) to form leakage paths with similar conductivity. By providing a buffer layer with a sheet resistance (Rp) value different from that of the selector layer above or below the selector layer, scattering and clustering of the selector layer can be minimized when a large mass of the second dopant is ion implanted, thereby forming a stable selector layer.

[0035] Return to reference FIG. 1A and FIG. 1B A buffer layer 131 can be disposed between the selector layer 140 and the second electrode layer 150. When forming the selector layer 140, the buffer layer 131 can be formed as an initial buffer layer 221 that is partially retained after the ion implantation process. The buffer layer 131 according to embodiments of this disclosure can correspond to the following... FIG. 6DThe initial buffer layer 222. The initial buffer layer 221 can be used to prevent the formation of microvoids within the selector layer 140 during subsequent ion implantation processes (which are performed under harsh conditions that the layer material cannot withstand), and to protect the first electrode layer 130. According to embodiments of this disclosure, a portion of the initial buffer layer 221 can be retained after the ion implantation process without being absorbed into the selector layer 140, and can be controlled to a level that does not affect electrical characteristics. Therefore, the resistance of the memory cell MC can be easily controlled as needed.

[0036] The thickness of the buffer layer 131 can be so thin that it does not affect the flow of current; that is, the buffer layer 131 can have a thickness that is electrically insignificant. For example, the thickness of the buffer layer 131 can be approximately... to Within the range.

[0037] Buffer layer 131 may use a dielectric material in which dopants are implanted. According to a preferred embodiment of this disclosure, buffer layer 131 may comprise a boron (B)-doped amorphous silicon layer. According to yet another embodiment of this disclosure, buffer layer 131 may be doped with arsenic (As) by performing additional ion implantation into the boron-doped amorphous silicon layer.

[0038] According to embodiments of this disclosure, the dopant incorporated into the amorphous silicon layer may be a group 13 element of the periodic table instead of boron (B), and may be a group 14 or group 15 element of the periodic table instead of arsenic (As).

[0039] Please refer to later FIGS. 6A-7D The formation of buffer layer 131 is described in detail.

[0040] FIG. 3A and FIG. 3B A semiconductor device according to another embodiment of the present disclosure is shown. FIG. 3A A 3D view is shown, and FIG. 3B Show along FIG. 3A The diagram shows a cross-sectional view taken along line A-A'. A semiconductor memory according to an embodiment of this disclosure can have a structure in which a buffer layer 131 is formed in the lower portion of the selector layer 140. In addition to forming a buffer layer 131 in the lower portion of the selector layer 140, FIG. 3A and FIG. 3B The semiconductor device shown is similar to FIG. 1A and FIG. 1B The semiconductor device shown. (For use with...) FIG. 1A and FIG. 1B The embodiments shown in this disclosure are similar to those described herein, and detailed descriptions thereof will be omitted herein.

[0041] refer to FIG. 3A andFIG. 3B The buffer layer 131 can be interposed between the first electrode layer 130 and the second selector layer 140. The buffer layer 131 can be formed as an initial buffer layer 221 that is partially remained after an ion implantation process when the selector layer 140 is formed. In other words, the buffer layer 131 according to an embodiment of the present application can correspond to the buffer layer 222 shown in FIG. 2B, which will be described below. According to an embodiment of the present disclosure, a portion of the initial buffer layer 221 can be remained after the ion implantation process without being absorbed into the selector layer 140, but can be controlled to a level that does not affect electrical characteristics. Accordingly, the resistance of the memory cell MC can be easily controlled as needed. FIG. 7D

[0042] According to an embodiment of the present disclosure, a structure in which the buffer layer 131 is formed in the lower portion of the selector layer 140 can be implemented. In the amorphous silicon layer having the first dopant, silicon (Si) can form a chemical bond between hydrogen (H) and the first dopant, and the second dopant can be absorbed into a vacancy therebetween, thereby preventing scattering of the selector layer. In the structure in which the buffer layer 131 is formed on the upper portion of the selector layer 140, and in the structure in which the buffer layer 131 is formed in the lower portion of the selector layer 140, the second dopant can be absorbed into the vacancy of the amorphous silicon layer of the buffer layer 131. Accordingly, even in the present embodiment of the present disclosure, all the advantages described in the above-described embodiments of the present disclosure can be obtained.

[0043] Although the memory cell MC of FIG. 1A , FIG. 1B , FIG. 3A and FIG. 3B shows a stacked structure of the first electrode layer 130, the selector layer 140, the second electrode layer 150, the storage layer 160, and the third electrode layer 170, the concept and spirit of the present application are not limited thereto, and different changes can be made to the layer structure of the memory cell MC. For example, at least one of the first electrode layer 130, the second electrode layer 150, and the third electrode layer 170 can be omitted. For example, the memory cell MC can include the selector layer 140, the first electrode layer 130 disposed under the selector layer 140, and the third electrode layer 170 disposed above the selector layer 140. For example, the first electrode layer 130 disposed under the selector layer 140 can include titanium nitride (TiN), and the third electrode layer 170 disposed above the selector layer 140 can include a carbon (C) electrode. In addition, for another embodiment, the upper and lower positions of the selector layer 140 and the storage layer 160 can be switched with each other. In addition, for yet another embodiment, the memory cell MC can further include one or more layers (not shown) to improve characteristics or to improve a process.

[0044] FIG. 4 ​is a cross-sectional view illustrating a structure of a selector unit SU according to an embodiment of the disclosure.

[0045] Referring to FIG. 4 , the selector unit SU can include a first electrode layer 130, a selector layer 140, and a second electrode layer 150.

[0046] As described above, the first electrode layer 130 and the second electrode layer 150 can include various conductive materials such as a metal, a metal nitride, etc. The first electrode layer 130 and the second electrode layer 150 can be formed of the same material to have the same work function. For example, the first electrode layer 130 and the second electrode layer 150 can include titanium nitride (TiN) having a work function of about 4.4 to 4.6 eV. However, the technical concepts and scope of the disclosure are not limited thereto, and the first electrode layer 130 and the second electrode layer 150 can be formed of different materials to have different work functions.

[0047] The selector layer 140 can include an amorphous silicon layer 142 and a dopant 144 implanted in the amorphous silicon layer 142.

[0048] The amorphous silicon layer 142 can be a dielectric material having a relatively wide band gap, for example, a dielectric material having a band gap of about 5.0 eV or more. For example, there can be a deep trap in the amorphous silicon layer 142, the energy level of which is closer to the energy level of the valence band than the energy level of the conduction band of the thin layer. The dopant 144 can be used to form a shallow trap that provides a path for a conductive carrier (for example, an electron or a hole) to move in the amorphous silicon layer 142. The shallow trap can have an energy level closer to the energy level of the conduction band than the energy level of the valence band of the amorphous silicon layer 142.

[0049] The dopant 144 can include one or more selected from a group including a group 13 element, a group 14 element, and a group 15 element of the periodic table having a different valence from the valence of silicon (Si).

[0050] For example, the dopant 144 can include a group 13 element of the periodic table such as boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, the dopant 144 can include a group 14 element of the periodic table such as carbon (C), silicon (Si), germanium (Ge), or tin (Sn), and a group 13 element of the periodic table. For example, the dopant 144 can include a group 15 element of the periodic table such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), and a group 13 element of the periodic table. For example, the dopant 144 can include boron (B), and the dopant 144 can further include one or more of phosphorus (P) and arsenic (As) and boron (B).

[0051] The concentration of the dopant and the ratio of amorphous silicon in the doped amorphous silicon layer can vary greatly depending on the process conditions. The concentration of the dopant can be controlled by controlling the flow rates and hydraulic pressures of diborane (B2H6) and silane gas (SiH4). For example, increasing the flow rate of diborane can increase the concentration of the dopant, and, conversely, increasing the flow rate of silane gas can increase the ratio of amorphous silicon. When the doped amorphous silicon layer is formed by reacting diborane with silane gas under temperature conditions of about 300°C, the dopant 144 can have a concentration of about 10 wt% to 30 wt% and amorphous silicon can have a concentration of about 90 wt% to 70 wt% in the doped amorphous silicon layer. When the doped amorphous silicon layer is formed by reacting diborane with silane gas under temperature conditions of about 400°C, the diffusion of the dopant can become more active, so that the amorphous silicon layer can be more easily doped with the dopant. Accordingly, in this case, the dopant 144 can have a concentration of about 30 wt% to 90 wt% and amorphous silicon can have a concentration of about 70 wt% to 10 wt% in the doped amorphous silicon layer. x H y ) of the flow rates and hydraulic pressures. For example, increasing the flow rate of diborane can increase the concentration of the dopant, and, conversely, increasing the flow rate of silane gas can increase the ratio of amorphous silicon. When the doped amorphous silicon layer is formed by reacting diborane with silane gas under temperature conditions of about 300°C, the dopant 144 can have a concentration of about 10 wt% to 30 wt% and amorphous silicon can have a concentration of about 90 wt% to 70 wt% in the doped amorphous silicon layer. When the doped amorphous silicon layer is formed by reacting diborane with silane gas under temperature conditions of about 400°C, the diffusion of the dopant can become more active, so that the amorphous silicon layer can be more easily doped with the dopant. Accordingly, in this case, the dopant 144 can have a concentration of about 30 wt% to 90 wt% and amorphous silicon can have a concentration of about 70 wt% to 10 wt% in the doped amorphous silicon layer.

[0052] FIG. 5 The operation of the selector unit SU shown is illustrated. FIG. 4 The operation of the selector unit SU shown is illustrated.

[0053] Referring to FIG. 1, the selector layer 140 can be formed by doping amorphous silicon with a dopant 144. FIG. 5 In the off state in which no voltage is applied to the selector layer 140, conductive carriers (e.g., electrons (e)) can be trapped in the deep traps T1 of the selector layer 140.

[0054] When a voltage equal to or higher than a threshold voltage level is applied to the selector layer 140 in the off state through the first electrode layer 130 and the second electrode layer 150, an on state in which current flows through the selector layer 140 can be achieved. Specifically, when a voltage equal to or higher than the threshold voltage level is applied to the selector layer 140, the conductive carriers trapped in the deep traps T1 can jump into the shallow traps T2 through a thermal emission process or a tunneling process, and the conductive carriers can move through the shallow traps T2 to form a conductive path that couples the first electrode layer 130 and the second electrode layer 150.

[0055] When the voltage applied to the selector layer 140 in the on state is lowered, the number of conductive carriers moving from the deep traps T1 to the shallow traps T2 also decreases, so that the selector layer 140 is again turned off.

[0056] In this way, the selector layer 140 can be turned on and off.

[0057] FIGS. 6A-6C A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is illustrated.

[0058] Referring to FIG. 6A A substrate 200 formed with a predetermined lower structure can be provided. The substrate 200 can include various circuits as needed. For example, the substrate 200 can include a wire similar to the first wire 110 as described above. FIG. 1A and FIG. 3A a wire of the first wire 110.

[0059] Subsequently, a first electrode layer 210 can be formed on the substrate 200. The first electrode layer 210 can be implemented as a TiN thin layer. As used herein, the TiN thin layer refers to a layer having a thickness of 5 nm to 100 nm, or more specifically, 5 nm to 50 nm.

[0060] Subsequently, an initial selector layer 220 can be formed on the first electrode layer 210. The initial selector layer 220 can include a silicon oxide layer, or an amorphous silicon layer doped with a dopant as a silicon (Si) containing layer. Here, a method for forming the silicon oxide layer or the amorphous silicon layer doped with the dopant can be implemented as a method of depositing the silicon oxide layer or the amorphous silicon layer doped with the dopant. The dopant can include at least one selected from a group including boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), and germanium (Ge).

[0061] Subsequently, referring to FIG. 6B An initial buffer layer 221 can be formed on the initial selector layer 220. Subsequently, an amorphous silicon layer doped with a dopant can be formed on the initial selector layer 220 as the initial buffer layer 221. Here, a method for forming the amorphous silicon layer doped with the dopant can be implemented as a method of depositing an amorphous silicon layer doped with a first dopant. The first dopant can be an element of Group 13 of the periodic table, such as boron (B), aluminum (Al), gallium (Ga), or indium (In). Preferably, the first dopant can be boron (B).

[0062] The amorphous silicon layer with the first dopant can be formed by a low pressure chemical vapor deposition (LPCVD) process using a catalyst containing the first dopant and a silicon source gas. For example, the amorphous silicon layer with the first dopant can be formed by a low pressure chemical vapor deposition (LPCVD) process using silane gas (Si x H y ) (e.g., SiH4) and diborane (B2H6). The low pressure chemical vapor deposition process can provide a uniform thin layer and a low defect rate, thereby improving the performance of a semiconductor device.

[0063] When boron (B) is applied as the first dopant, the boron-containing catalyst can be selected from a group including trimethyl borate (B(Ome)3), boron trichloride (BC13), boron tribromide (BBr3), boron dibromide (BBr2), boron trifluoride (BF3), or diborane (B2H6). In a case where the boron (B)-containing catalyst itself does not contain hydrogen, it can be supplied together with hydrogen (H2).

[0064] Subsequently, referring to FIG. 2B, FIG. 6C A second dopant (e.g., arsenic (As)) can be ion-implanted into the amorphous silicon layer having the first dopant. The second dopant can include, in addition to arsenic (As), an element of Group 14 of the periodic table, such as carbon (C), silicon (Si), germanium (Ge), or tin (Sn), or an element of Group 15 of the periodic table, such as nitrogen (N), phosphorus (P), or antimony (Sb). Preferably, the first dopant can include boron (B), and the second dopant can include at least one selected from a group including carbon (C), silicon (Si), germanium (Ge), phosphorus (P), and arsenic (As). The ion-implantation of the second dopant can be performed in a direction substantially perpendicular to the surface of the substrate 200, and an angled ion-implantation can also be performed. Furthermore, the ion-implantation can be repeatedly performed several times. By ion-implanting the second dopant such as arsenic (As) into the amorphous silicon layer, an electrical characteristic can be provided to the manufactured semiconductor device. By changing the concentration of the ion-implanted second dopant, the characteristics of the semiconductor device can be appropriately changed. For example, the concentration of the ion-implanted second dopant can be adjusted in a range of about 10% to 50% depending on the implantation conditions.

[0065] The amorphous silicon layer in which the second dopant is additionally ion-implanted can be easily secured, and due to the influence of the second dopant during the ion-implantation process, a conductive path in the amorphous silicon layer can be easily secured.

[0066] The ion-implantation process can be performed by high energy and high ion-implantation amount, and since the ion such as arsenic (As) is a heavy component having a large mass, the ion-implantation process can be performed under conditions that the layer material can hardly endure. According to an embodiment of the present disclosure, the second dopant can be absorbed into a vacancy between silicon (Si) and hydrogen (H) in the amorphous silicon layer including the first dopant. Thus, the layer material is able to endure such harsh conditions during the ion-implantation process. This can prevent defects such as microvoids from being formed inside. Furthermore, since the initial buffer layer 221 serves as a buffer layer, damage to the first electrode layer 210 can be minimized. The initial buffer layer 221 serving as a buffer can be completely removed during the ion-implantation process and be absorbed into the selector layer 230. After the ion-implantation process is completed, the initial buffer layer 221 can not exist.

[0067] During the formation of the selector layer 230, the buffer layer 222 can be formed as a portion of the initial buffer layer 221 that remains after the ion implantation process. Subsequently, referring to FIG. 6D A second electrode layer 240 can be formed over the buffer layer 222. The second electrode layer 240 can be formed by depositing a conductive material. The second electrode layer 240 can be implemented as a single layer of TiN, or the second electrode layer 240 can be implemented by stacking a thin layer of carbon (C) and a layer of TiN. Herein, the thin layer of carbon (C) can be formed at an interface between the amorphous silicon layer and the layer of TiN.

[0068] A semiconductor device according to an embodiment of the disclosure can be manufactured by the above-described processes.

[0069] Referring back to FIG. 6D A semiconductor device according to an embodiment of the disclosure can include a substrate 200, a first electrode layer 210 over the substrate 200, and a selector layer 230, a buffer layer 222, and a second electrode layer 240 sequentially formed over the first electrode layer 210.

[0070] FIGS. 7A-7D A method for manufacturing a semiconductor device according to another embodiment of the disclosure is illustrated. By the manufacturing method according to an embodiment of the disclosure, a semiconductor memory having a structure in which a buffer layer 131 is formed in a lower portion of a selector layer 140 can be manufactured. Except for the formation of the buffer layer 131 in the lower portion of the selector layer 140, FIGS. 7A-7D The illustrated method for manufacturing a semiconductor device is similar to the method for manufacturing a semiconductor device illustrated in FIGS. 6A-6D The illustrated method for manufacturing a semiconductor device is similar to the method for manufacturing a semiconductor device illustrated in FIGS. 6A-6D For the similar content to the embodiment of the disclosure illustrated in

[0071] Referring to FIG. 7A An amorphous silicon layer doped with a first dopant can be formed over the first electrode layer 210 as an initial buffer layer 221.

[0072] Subsequently, referring to FIG. 7B and FIG. 7C An initial selector layer 220 can be formed over the initial buffer layer 221, and a second dopant (e.g., arsenic (As)) can be ion-implanted into an upper portion of the initial selector layer 220.

[0073] According to an embodiment of the disclosure, even if the initial buffer layer 221 is disposed under the initial selector layer 220, the initial buffer layer 221 can serve as a buffer layer when ions of the second dopant are implanted. The initial buffer layer 221 serving as a buffer can be completely removed and absorbed into the selector layer 230 during the ion implantation process. The initial buffer layer 221 can not exist after the ion implantation process is completed.

[0074] Subsequently, referring to FIG. 7D A second electrode layer 240 can be formed over the ion-implanted selector layer 230.

[0075] A semiconductor device according to an embodiment of the disclosure can be manufactured through the above-described processes.

[0076] Referring back to FIG. 7D FIG. 7D A semiconductor device according to an embodiment of the disclosure can include a substrate 200, a first electrode layer 210 positioned over the substrate 200, and a buffer layer 222, a selector layer 230, and a second electrode layer 240 sequentially formed over the first electrode layer 210.

[0077] According to an embodiment of the disclosure, by minimizing scattering that can be caused by metal ions implanted into the selector layer during the ion implantation process, the selector characteristics of the memory cell can be improved, and damage to the lower electrode can be reduced.

[0078] While the embodiments of the disclosure have been described with respect to specific embodiments, various changes and modifications can be suggested to one skilled in the art, and it is intended that the disclosure encompass such changes and modifications as fall within the scope of the technical concept and scope of the disclosure as defined by the appended claims. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Multiple storage units, Each storage unit in the storage unit includes: Storage layer; A selector layer, formed above or below the storage layer, is used to select the storage layer; and A buffer layer, the buffer layer being directly coupled to the upper or lower portion of the selector layer, wherein the buffer layer includes an amorphous silicon layer, the amorphous silicon layer including at least one dopant selected from the group consisting of elements of Group 13, Group 14 and Group 15 of the periodic table.

2. The semiconductor device as claimed in claim 1, wherein, The dopant includes elements from group 13 of the periodic table.

3. The semiconductor device as claimed in claim 1, wherein, The dopants include elements from Group 13 and Group 14 of the periodic table.

4. The semiconductor device as claimed in claim 1, wherein, The dopants include elements from Group 13 and Group 15 of the periodic table.

5. The semiconductor device as claimed in claim 1, wherein, The dopant includes boron (B).

6. The semiconductor device of claim 1, wherein, The dopant includes at least one of phosphorus (P) and arsenic (As) and boron (B).

7. The semiconductor device of claim 1, wherein, The dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), and boron (B).

8. The semiconductor device of claim 1, wherein, The dopant has a concentration of about 10 wt% to 30 wt% in the doped amorphous silicon layer.

9. The semiconductor device of claim 1, wherein, The storage unit further includes: A first electrode layer, wherein the first electrode layer is disposed below the selector layer, and The second electrode layer is disposed on top of the selector layer.

10. The semiconductor device of claim 9, wherein, The first electrode layer and the second electrode layer comprise a thin TiN layer.

11. The semiconductor device of claim 9, further comprising: A SiN thin layer, wherein the SiN thin layer is located at the interface between the first electrode layer and the selector layer, and A carbon C thin layer is located at the interface between the selector layer and the second electrode layer.

12. The semiconductor device of claim 1, wherein, The buffer layer has approximately to The thickness.

13. A method for manufacturing a semiconductor device comprising a plurality of memory cells, the method comprising: Form a selector layer; as well as An amorphous silicon layer containing dopant is formed in the upper or lower part of the selector layer as a buffer layer. The buffer layer includes an amorphous silicon layer, which includes at least one dopant selected from the group consisting of elements from Group 13, Group 14 and Group 15 of the periodic table.

14. The method of claim 13, wherein, The steps for forming the amorphous silicon layer include: An amorphous silicon layer doped with a first dopant is deposited.

15. The method of claim 14, wherein, The first dopant has a concentration of about 10 wt% to 30 wt% in the doped amorphous silicon layer.

16. The method of claim 13, further comprising: An electrode layer is formed on top of the selector layer.

17. The method of claim 13, wherein, The steps for forming the amorphous silicon layer include: Deposited amorphous silicon layer doped with a first dopant; and The second dopant ions are implanted into the amorphous silicon layer doped with the first dopant.

18. The method of claim 17, wherein, The first dopant includes elements from Group 13 of the periodic table, and The second dopant includes a Group 14 or Group 15 element of the periodic table.

19. The method of claim 17, wherein, The first dopant includes boron (B), and The second dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), phosphorus (P), and arsenic (As).

20. The method of claim 14, wherein, The step of depositing the amorphous silicon layer doped with the first dopant is performed using a low-pressure chemical vapor deposition (LPCVD) process with SiH4 and diborane (B2H6).

21. The method of claim 13, wherein, The buffer layer has approximately to The thickness.

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