Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is located above the substrate. The drift region is in the substrate and below the gate structure. The source region and the drain region are located on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and is located between the drain region and the gate structure. The doped region is spaced apart from the bottom surface of the drain region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increase in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes primarily from shrinking semiconductor process nodes (e.g., shrinking process nodes to nodes less than 20nm). As semiconductor devices shrink in size, new technologies are expected to maintain the performance of electronic components from one generation to another. For example, low on-resistance and high breakdown voltage of transistors are required for various high-power applications.

[0003] With the development of semiconductor technology, metal oxide semiconductor field effect transistor (MOSFET) has been widely used in today's integrated circuits. MOSFET is a voltage controlled device. When a control voltage is applied to the gate of the MOSFET and the control voltage is greater than the threshold of the MOSFET, a conductive channel is established between the drain and source of the MOSFET. Therefore, current flows between the drain and source of the MOSFET. On the other hand, when the control voltage is lower than the threshold of the MOSFET, the MOSFET is turned off accordingly.

[0004] According to the difference in polarity, MOSFET can include two major categories. One is n-channel MOSFET and the other is p-channel MOSFET. On the other hand, according to the difference in structure, MOSFET can be further divided into three subcategories: planar MOSFET, lateral diffused MOS (LDMOS) FET and vertical diffused MOSFET. Summary of the invention

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a gate structure located above the substrate; a drift region in the substrate and located below the gate structure; a source region and a drain region located on opposite sides of the gate structure, wherein the drain region is in the drift region and the source region is outside the drift region; and a doped region in the drift region and located between the drain region and the gate structure.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a substrate; a drift region in the substrate; a gate structure located above the drift region; a source region and a drain region located on opposite sides of the gate structure, wherein the drain region is in the drift region; an isolation structure in contact with the drain region and the drift region; and a doped region in the drift region and between the drain region and the gate structure, wherein the doped region and the drain region have the same conductivity type.

[0007] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a drift region in a substrate; forming a gate structure above the drift region; forming a doped region in the drift region; and forming a source region and a drain region on the opposite side of the gate structure and in the drift region, wherein the doped region is formed between the gate structure and the drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0009] FIG. 1A to FIG. 1O A method of manufacturing a semiconductor device at different stages according to some embodiments is illustrated.

[0010] Figure 2 In various embodiments Fig.1O Top view of a semiconductor device.

[0011] Figure 3 is a cross-sectional view of a semiconductor device according to various embodiments.

[0012] Figure 4 is a curve of drain voltage (Vd) versus drain current (Id) of a semiconductor device in an off state according to some embodiments of the present disclosure.

[0013] Figure 5 is a curve of Vd versus Id of a semiconductor device in an on-state according to some embodiments of the present disclosure.

[0014] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor device according to various embodiments.

[0015] Fig. 7A and Figure 7B is a cross-sectional view of a semiconductor device according to various embodiments.

[0016] Figure 8 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0019] As used herein, "about," "approximately," or "substantially" generally means within 20%, within 10%, or within 5% of a given value or range. The values ​​given herein are approximate, which means that the term "about," "approximately," "approximately," or "substantially" can be inferred in the absence of explicit statement.

[0020] Laterally diffused (LD) MOS transistors have many advantages. For example, since the asymmetric structure of the LDMOS transistor provides a short channel between the drain and source of the LDMOS transistor, the LDMOS transistor can transmit more current per unit area. The present disclosure will be described with respect to an embodiment in a specific context, i.e., a laterally diffused (LD) metal oxide semiconductor field effect transistor (MOSFET) having a doped region between the drain and gate structure for improving the Kirk effect. However, embodiments of the present disclosure may also be applied to various metal oxide semiconductor transistors. In the following, various embodiments will be described in detail with reference to the accompanying drawings.

[0021] FIG. 1A to FIG. 1O1 and 2. The method of manufacturing a semiconductor device at different stages according to some embodiments is illustrated. FIG. 1A to FIG. 1O has been simplified. In addition, the semiconductor device can be configured as a system-on-chip (SoC) device having various PMOS and NMOS transistors that are manufactured to operate at different voltage levels. PMOS and NMOS transistors can provide low-voltage functions including logic / memory devices and input / output devices, as well as high-voltage functions including power management devices. For example, a transistor providing low-voltage functions can have an operating (or drain) voltage of 1.1V when using standard CMOS technology, or a voltage of 1.8 / 2.5 / 3.3V when using special (input / output) transistors in standard CMOS technology. In addition, transistors providing medium / high voltage functions can have an operating (or drain) voltage of 5V or higher (e.g., 20-35V). It will be understood that FIG. 1A to FIG. 1O The semiconductor devices in the embodiment may also include resistors, capacitors, inductors, diodes, and other suitable microelectronic devices that may be implemented in an integrated circuit.

[0022] refer to Figure 1A , a semiconductor substrate 110 is provided. The semiconductor substrate 110 may include a semiconductor wafer, such as a silicon wafer. Alternatively, the semiconductor substrate 110 may include other basic semiconductors, such as germanium. The semiconductor substrate 110 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In addition, the semiconductor substrate 110 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, the semiconductor substrate 110 includes an epitaxial layer (epi layer) covering the bulk semiconductor. In addition, the semiconductor substrate 110 may include a semiconductor on insulator (SOI) structure. For example, the semiconductor substrate 110 may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX). In various embodiments, the semiconductor substrate 110 may include a buried layer, such as an n-type buried layer (NBL), a p-type buried layer (PBL), and / or a buried dielectric layer including a buried oxide (BOX) layer. In some embodiments, the n-type MOS is shown, and the semiconductor substrate 110 includes a p-type silicon substrate (p substrate). For example, p-type dopants are introduced into semiconductor substrate 110 to form a p-substrate. To form a complementary MOS, an n-type buried layer (ie, deep n-well (DNW)) may be implanted deeply below the active region of the p-type MOS of p-substrate 110 as described below.

[0023] Specifically, a deep n-type well (DNW) 120' is formed in the semiconductor substrate 110. In some embodiments, the DNW 120' is formed by ion implantation. In some embodiments, arsenic or phosphorus ions are implanted to form the DNW 120'. In some other embodiments, the DNW 120' is formed by selective diffusion. The DNW 120' functions to electrically isolate the p-substrate.

[0024] refer to Figure 1B . Isolation structures 142, 144, and 146 including isolation features, such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS) (or field oxidation (FOX)), can be formed in the semiconductor substrate 110 to define and electrically isolate various active regions, thereby preventing leakage current from flowing between adjacent active regions. As an example, the formation of STI features can include dry etching trenches in the substrate and filling the trenches with an insulator material such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trenches can have a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In some other embodiments, the STI structure can be created using a process sequence such as: growing a liner oxide; forming a low pressure chemical vapor deposition (LPCVD) nitride layer; patterning an STI opening using a photoresist and a mask; etching a trench in the substrate; optionally growing a thermal oxide trench liner to improve the trench interface; filling the trench with a CVD oxide; using a chemical mechanical polishing (CMP) process for etch back and planarization; and using a nitride strip process to remove silicon nitride. In some embodiments, isolation structures 142, 144, and 146 have a depth D1 in the range of about 200 nm to about 400 nm.

[0025] In some embodiments, an annealing process may be performed during the formation of the isolation structures 142, 144, and 146, and the DNW 120' (see Figure 1A ) diffuses during the annealing process, so that the depth of DNW 120 increases. In some embodiments, the depth D2 of DNW 120 is in the range of about 2 um to about 6 um, and the doping concentration of DNW 120 is about 10 μm per cubic centimeter. 15 To about 10 17 Isolation structures 142 and 144 are formed in DNW 120. Isolation structure 146 is located at the interface of DNW 120 and the p-substrate.

[0026] refer to Figure 1CIn some embodiments, a deep p-type well (DPW) 130 is formed in the DNW 120. In some embodiments, the DPW 130 is formed by ion implantation. In some other embodiments, boron ions and / or boron difluoride (BF2) ions are implanted to form the DPW 130. In some other embodiments, the DPW 130 is formed by selective diffusion. Therefore, the isolation structure 142 is deposited in the DPW 130. The DPW 130 functions to electrically isolate the p-substrate. In some embodiments, the depth D3 of the DPW 130 is in the range of about 2 um to about 3 um, and the doping concentration of the DPW 130 is about 10 μm per cubic centimeter. 15 To about 10 17 In some embodiments, DPW 130 and DNW 120 have substantially the same or similar dopant concentrations.

[0027] refer to Figure 1D An n-type doped region (NDD) (or n-type drift region) 152 is formed in the semiconductor substrate 110 and near the top surface 112 of the semiconductor substrate 110. Specifically, the NDD 152 is formed in the DPW 130 and adjacent to the isolation structure 142. Figure 1D In the embodiment of the present invention, the bottom of NDD 152 is surrounded by DPW 130. In some embodiments, NDD 152 is formed by ion implantation, diffusion technology, or other suitable technology. For example, an N-well mask is used to pattern a photoresist layer in a photolithography process or other suitable process. An exemplary photolithography process may include the following process steps: photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. Ion implantation using an n-type dopant (e.g., arsenic or phosphorus) may be performed to form NDD 152 in semiconductor substrate 110. In some embodiments, the doping concentration of NDD 152 is about 10 N / cm3. 16 To about 10 17 The doping concentration of NDD 152 may be greater than the doping concentration of DPW 130 (or DNW 120). In some embodiments, the depth D4 of NDD 152 is greater than the depth D1 of isolation structures 142, 144, and / or 146 (see Figure 1B ). The depth D4 may be in the range of about 0.5 um to about 1 um.

[0028] Then, a shallow low-voltage n-type well (SHN) 154 is formed in the semiconductor substrate 110 and near the top surface 112 of the semiconductor substrate 110. Specifically, the SHN 154 is formed in the DNW 120 and between the isolation structures 144 and 146. Figure 1D, the bottom of SHN 154 is surrounded by DNW 120. In some embodiments, SHN 154 is formed by ion implantation, diffusion technology, or other suitable technology. For example, another N-well mask is used to pattern the photoresist layer in a photolithography process or other suitable process. An exemplary photolithography process may include the following process steps: photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. Ion implantation using an n-type dopant (e.g., arsenic or phosphorus) may be performed to form SHN 154 in semiconductor substrate 110. In some embodiments, the doping concentration of SHN 154 is about 10 N / cm3. 17 To about 10 18 The doping concentration of the SHN 154 may be greater than the doping concentration of the NDD 152 .

[0029] Subsequently, shallow low voltage p-type wells (SHPs) 156a, 156b, and 156c are formed in the semiconductor substrate 110 and near the top surface 112 of the semiconductor substrate 110. Specifically, SHPs 156a and 156b are formed in the DPW 130, and SHP 156c is formed in the p-substrate. SHP 156a is configured to suppress parasitic BJT action. NDD 152 is formed between SHPs 156a and 156b. SHP 156b is formed between isolation structures 142 and 144, and SHP 156c is formed adjacent to isolation structure 146. Figure 1D In the embodiment, the bottom of SHP 156a and 156b is surrounded by DPW 130, and the bottom of SHP 156c is surrounded by p-substrate. In some embodiments, SHP 156a, 156b and 156c are formed by ion implantation, diffusion technology or other suitable technology. For example, the P-well mask is used to pattern the photoresist layer in a photolithography process or other suitable process. An exemplary photolithography process may include the following process steps: photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development and hard baking. Ion implantation with p-type dopants (e.g., boron and / or boron difluoride (BF2)) may be performed to form SHP 156a, 156b and 156c in semiconductor substrate 110. In some embodiments, the doping concentration of each of SHP 156a, 156b and 156c may be about 10 to 10 cm3. 17 To about 10 18 The doping concentration of each of the SHPs 156 a , 156 b , and 156 c may be greater than the doping concentration of the NDD 152 .

[0030] In some embodiments, SHN 154 and SHP 156a, 156b, and 156c have substantially the same or similar depth D5. In some embodiments, depth D5 is greater than depth D1 of isolation structures 142, 144, and / or 146 (see Figure 1B ). The depth D5 may be in the range of about 1 um to about 2 um. In addition, it should be noted that the above-mentioned formation order of the NDD 152, the SHN 154, and the SHPs 156a, 156b, and 156c is an example and should not limit the present disclosure. In some other embodiments, the NDD 152 may be formed after forming the SHN 154 and / or the SHPs 156a, 156b, and 156c, and / or the SHN 154 may be formed after forming the SHPs 156a, 156b, and 156c.

[0031] refer to Figure 1E . A gate dielectric film 162' and a conductive film 164' are subsequently formed over the semiconductor substrate 110. The gate dielectric film 162' may include a silicon oxide layer. Alternatively, the gate dielectric film 162' may optionally include a high-k dielectric material, silicon oxynitride, other suitable materials, or a combination thereof. The high-k material may be selected from: metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, hafnium oxide, or a combination thereof. The gate dielectric film 162' may have a multilayer structure, such as a layer of silicon oxide and another layer of high-k material. The gate dielectric film 162' may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, other suitable processes, or a combination thereof.

[0032] The conductive film 164' may include doped polysilicon (i.e., polysilicon). Alternatively, the conductive film 164' may include a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or other suitable conductive materials, or a combination thereof. The conductive film 164' may be formed by CVD, PVD, electroplating, or other suitable processes. The conductive film 164' may have a multi-layer structure and may be formed in a multi-step process using a combination of different processes.

[0033] refer to Figure 1F. An opening 166 is formed in the gate dielectric film 162' and the conductive film 164', and the opening 166 exposes the SHP 156a. The opening 166 can be formed by using a process including photolithography patterning and etching. An exemplary method for patterning the gate dielectric film 162' and the conductive film 164' is described below. A layer of photoresist is formed on the conductive film 164' by a suitable process (e.g., spin coating), and then patterned by a suitable photolithography patterning method to form patterned photoresist features. The pattern of the photoresist can then be transferred to the underlying conductive film 164' and the gate dielectric film 162' by a dry etching process in multiple processing operations and various appropriate sequences. Thereafter, the photoresist layer can be stripped. In yet other embodiments, a hard mask layer can be used and formed on the conductive film 164'. The patterned photoresist layer is formed on the hard mask layer. The pattern of the photoresist layer is transferred to the hard mask layer and then to the conductive film 164'. The hard mask layer may include silicon nitride, silicon oxide, silicon carbide, and / or other suitable dielectric materials, and may be formed using methods such as CVD or PVD.

[0034] Then, high voltage p-type implant regions (HVPBs) 158 are formed in DPW 130 such that each of HVPBs 158 is formed between SHP 156a and NDD 152. That is, NDD 152 is formed between HVPB 158 and isolation structure 142. Gate dielectric film 162' and conductive film 164' serve as implantation masks. Figure 1F The implantation in the HVPB 158 may be tilted, and its tilt angle is greater than the tilt angle of the SHP, SHN and LDD implants, so that the HVPB 158 is formed below the gate dielectric film 162' and the conductive film 164'. In some embodiments, the depth D6 of the HVPB 158 is in the range of about 1.5um to about 2.5um. In some embodiments, the doping concentration of each of the HVPBs 158 may be about 10 μm per cubic centimeter. 17 To about 10 18 The doping concentration of each of the HVPBs 158 may be greater than the doping concentration of the SHPs 156a, 156b, and / or 156c.

[0035] refer to Figure 1G .right Figure 1FThe gate dielectric film 162' and the conductive film 164' in the semiconductor substrate 110 are further patterned to form a gate structure 160 on the semiconductor substrate 110. In some embodiments, the gate structure 160 includes a gate dielectric layer 162 formed on the semiconductor substrate 110 and a gate electrode 164 formed on the gate dielectric layer 162. In addition, the gate structure 160 covers a portion of the NDD 152 and the HVPB 158. The gate electrode 164 may be configured to be coupled to a metal interconnection and may be disposed on an upper layer of the gate dielectric layer 162. Then, the gate dielectric layer 162 and the gate electrode 164 formed on the semiconductor substrate 110 are patterned using a process including photolithography patterning and etching to form a plurality of gate structures.

[0036] refer to Figure 1H An N-type lightly doped region (NLDD) 182 is formed in the NDD 152. Specifically, the NLDD 182 is formed in the NDD 152 and is separated from the isolation structure 142. Figure 1H , the bottom of NLDD 182 is surrounded by NDD 152. Depth D7 of NLDD 182 is less than depth D4 of NDD 152 and depth D1 of isolation structure 142, and depth D7 is in the range of about 0.2 um to about 0.4 um. In other words, bottom surface 182 b of NLDD 182 is higher than bottom surface 142 b of isolation structure 142.

[0037] In some embodiments, NLDD 182 is formed by ion implantation, diffusion technology, or other suitable technology. Figure 1G Another N-well mask 105 is deposited over the structures in the NDD 152 (i.e., over the NDD 152, SHN 154, SHP 156a-156c, gate structure 160, and isolation features 142, 144, and 146). The N-well mask 105 has an opening 106 that exposes a portion of the NDD 152. Ion implantation with an n-type dopant (e.g., arsenic or phosphorus) may be performed to form a NLDD 182 in the NDD 152. In some embodiments, the NLDD implant may be tilted or vertical, with a tilt angle θ between about 0 degrees and about 45 degrees. The vertical implant (i.e., the tilt angle θ is 0 degrees) forms the NLDD 182 directly below the opening 106, and the width W of the NLDD 182 is substantially the same as the width of the opening 106. In some other embodiments, the NLDD 182 is formed offset from the opening 106 by tilted implantation (i.e., the tilt angle θ is greater than 0 degrees), and the width W of the NLDD 182 is greater than the width of the opening 106. In the case of tilted implantation, the size of the opening 106 can be reduced so that the opening 106 does not expose the region where the drain region of the semiconductor device should be formed. In addition, the NLDD 182 can be formed according to the relationship between the drain region (i.e., Figure 1J The desired width W and / or distance d1 between the N-type source / drain regions 184a in FIG. Figure 1J ) to adjust the injection tilt angle.

[0038] In some embodiments, the doping concentration of NLDD 182 is about 10 17 To about 10 19 The doping concentration of NLDD 182 is greater than the doping concentration of NDD 152. In some embodiments, the width W of NLDD 182 is greater than 0um and equal to or less than about 1um. NLDD 182 improves the Kirk effect of the semiconductor device and further improves the drain voltage (Vd)-drain current (Id) tailing performance, and a detailed description will be discussed in the following paragraphs.

[0039] refer to Fig. 1I . Removed Figure 1H The N-well mask 105 in the gate structure 160 is formed, and a sidewall spacer 170 is formed on the opposite side of the gate structure 160. The sidewall spacer 170 may include a dielectric material such as silicon oxide. Alternatively, the sidewall spacer 170 may optionally include silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiC x O y N z Or a combination thereof. In some embodiments, the sidewall spacer 170 may have a multilayer structure. The sidewall spacer 170 may be formed using the following deposition methods, for example: plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), etc. The formation of the sidewall spacer 170 may include blanket forming a spacer layer, and then performing an etching operation to remove a horizontal portion of the spacer layer. The remaining vertical portion of the spacer layer forms the sidewall spacer layer 170.

[0040] refer to Figure 1J . The N-type source / drain region 184a, the N-type pick-up region 184b, and the N-type source / drain region 184c are formed in the N-well or P-well. The N-type source / drain regions 184a, 184c, and the N-type pick-up region 184b are N+ or heavily doped regions. In some embodiments, the N-type source / drain regions 184a, 184c, and the N-type pick-up region 184b include N-type dopants, such as P or As. The N-type source / drain regions 184a, 184c, and the N-type pick-up region 184b may be formed by methods such as ion implantation or diffusion. A rapid thermal annealing (RTA) process may be used to activate the implanted dopants. In various embodiments, the N-type source / drain regions 184a, 184c, and the N-type pick-up region 184b may have different doping profiles formed by multi-process implantation.

[0041] N-type source / drain region 184a is formed in NDD 152 and adjacent to isolation structure 142, and N-type source / drain region 184a is referred to as a drain region of a semiconductor device. In addition, N-type source / drain region 184a is formed between NLDD 182 and isolation structure 142. N-type pickup region 184b is formed in SHN 154 and located between isolation structures 144 and 146, and N-type source / drain region 184c is formed in SHP 156a (outside NDD 152) and is spaced apart from each other. In some embodiments, N-type source / drain region 184c is referred to as a source region of a semiconductor device. A depth D8 of each of N-type source / drain regions 184a, 184c, and N-type pickup region 184b is less than a depth D4 of NDD 152 and a depth D1 of isolation structure 142, and the depth D8 is in a range of about 0.2um to about 0.3um. In some embodiments, the doping concentration of each of the N-type source / drain regions 184a, 184c and the N-type pickup region 184b may be about 10 N / cm3. 20 To about 10 21 The doping concentration of each of the N-type source / drain regions 184 a , 184 c and the N-type pickup region 184 b may be greater than the doping concentration of the NLDD 182 .

[0042] NLDD 182, NDD 152, and N-type source / drain region 184a have the same conductivity type (i.e., N-type in this case). NLDD 182 improves the Kirk effect on the surface on the drain side. The Kirk effect occurs at the N / N+ junction (i.e., the interface between NDD 152 and N-type source / drain region 184a) due to a sharper field and enhanced avalanche multiplication at the junction. The Kirk effect can be suppressed by implementing NLDD 182 near the N-type source / drain region 184a. NLDD 182 can prevent strong impact ionization near the surface 112 and modify the electric field near the N-type source / drain region 184a so that the electric field on the drain side is no longer strong / sharp. In addition, NLDD 182 provides good drain voltage (Vd)-drain current (Id) tailing performance (such as Figure 4 and Figure 5 In addition, the NLDD 182 is not formed below the N-type source / drain region 184a, and the NDD 152 surrounds the bottom of the NLDD 182, so that the NLDD 182 does not reduce the off-state breakdown voltage of the semiconductor device.

[0043] In some embodiments, Figure 1JAs shown, NLDD 182 is spaced apart from N-type source / drain region 184a. A distance d1 between NLDD 182 and N-type source / drain region 184a may be greater than 0 and equal to or less than about 0.5 um. In some other embodiments, NLDD 182 is in contact with N-type source / drain region 184a, such as Figure 3 As shown, Figure 3 1 is a cross-sectional view of a semiconductor device according to various embodiments. Since the drain region (N-type source / drain region 184a) is between NLDD 182 and isolation structure 142, ie, NLDD 182 does not diffuse outside NDD 152, NLDD 182 does not reduce the off-state breakdown voltage of the semiconductor device.

[0044] In addition, the doping concentration of NLDD 182 is lower than the doping concentration of N-type source / drain region 184a and higher than the doping concentration of NDD 152. If the doping concentration of NLDD 182 is equal to or higher than the N-type source / drain region 184a, NLDD 182 will become the drain region of the semiconductor device, so that the channel length is shortened and the Kirk effect still exists. If the doping concentration of NLDD 182 is equal to or lower than the doping concentration of NDD 152, NLDD 182 will not suppress the Kirk effect.

[0045] refer to Figure 1K . P-type pickup regions 192a-192c are formed in SHP 156a-156c. P-type pickup regions 192a-192c are P+ or heavily doped regions. In some embodiments, P-type pickup regions 192a-192c include P-type dopants, such as boron or boron difluoride (BF2). P-type pickup regions 192a-192c may be formed by methods such as ion implantation or diffusion. A rapid thermal annealing (RTA) process may be used to activate the implanted dopants. A depth D9 of the P-type pickup regions 192a-192c is less than a depth D4 of the NDD 152 and a depth D1 of the isolation structure 142, and the depth D9 is in a range of about 0.2um to about 0.3um. In some embodiments, the doping concentration of each of the P-type pickup regions 192a-192c may be about 10 μm per cubic centimeter. 20 To about 10 21 The doping concentration of each of the P-type pickup regions 192 a - 192 c may be greater than the doping concentration of the SHPs 156 a - 156 c and the doping concentration of the NLDD 182 .

[0046] A P-type pickup region 192a is formed in SHP 154b and is located between isolation structures 142 and 144, a P-type pickup region 192b is formed in SHP 156c and is adjacent to isolation structure 146, and a P-type pickup region 192c is formed in SHP 156a and is located between N-type source / drain regions 184c. P-type pickup region 192c is spaced apart from HVPB 158. In some embodiments, P-type pickup regions 192a-192c may be formed before forming N-type source / drain regions 184a, 184c and N-type pickup region 184b and / or NLDD 182.

[0047] It should be noted that the doping technique used in the previous example was chosen purely for exemplary purposes and is not intended to limit the various embodiments to any particular doping technique. Those skilled in the art will recognize that alternative embodiments may be employed (eg, employing diffusion techniques).

[0048] refer to Figure 1L The RP layer 210' is formed on Figure 1K , namely, gate structure 160, sidewall spacers 170, N-type source / drain regions 184a, 184c and N-type pickup region 184b, NLDD 182, P-type pickup regions 192a-192c, and isolation structures 142, 144, and 146. In some embodiments, RP layer 210' is formed of a dielectric layer such as silicon dioxide using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof.

[0049] refer to Figure 1M RP layer 210' (see Figure 1L ) is partially etched away so that the RP layer 210 remains over at least a portion of the gate structure 160 and over the sidewall spacers 170, extending over a portion of the N-type source / drain region 184a. That is, the RP layer 210 covers and contacts the NLDD 182. The RP layer 210 can act as a silicide barrier during a subsequent self-aligned silicide process discussed below. Device areas where the silicide process is not used are covered by the RP layer 210. The RP layer 210 can be defined by applying, for example, an oxide wet etch that partially removes the RP layer 210'. This protects the area below the RP layer 210 from the formation of silicide.

[0050] refer to Figure 1N. The metal alloy layer 220 can be formed by silicidation (e.g., salicide), in which a metal material is formed near a Si structure, and then the temperature is raised for annealing and a reaction is induced between the underlying silicon and the metal to form silicide, and the unreacted metal is etched away. The salicide material can be self-aligned to form on various features, such as the N-type source / drain regions 184a, 184c and the N-type pickup region 184b, the P-type pickup regions 192a-192c and / or the gate 160a, to reduce contact resistance. In addition, one of the metal alloy layers 220 contacts the N-type source / drain region 184a and the edge of the RP layer 210.

[0051] refer to Fig.1O and Figure 2 ,in Figure 2 In various embodiments Fig.1O Top view of a semiconductor device. Fig.1O The cross-sectional view shown in FIG. Figure 2 For clarity, Figure 2 The metal alloy layer 220 and the well are omitted. The interlayer dielectric (ILD) 230 is formed on Figure 1N The dielectric layer 230 may include silicon oxide. Alternatively or additionally, the ILD 230 includes a material having a low dielectric constant (e.g., a dielectric constant of less than about 3.5). In some embodiments, the dielectric layer includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluorine-doped silicate glass (FSG), carbon-doped silicon oxide, Black (Applied Materials, Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (benzocyclobutene), SiLK (Dow Chemical, Midland, Mich.), polyimide, and / or other suitable materials. The dielectric layer may be formed by techniques including spin coating, CVD, or other suitable processes.

[0052] Then, a plurality of contacts 242, 244, 246, 248, 252, and 254 are formed in the ILD 230. For example, a plurality of openings are formed in the ILD 230, and a conductive material is filled in the openings. Excess portions of the conductive material are removed to form the contacts 242, 244, 246, 248, 252, and 254. The contacts 242, 244, 246, 248, 252, and 254 may be made of tungsten, aluminum, copper, or other suitable materials. In some embodiments, contact 242 is connected to gate structure 160, contact 244 is connected to P-type pickup region 192c and N-type source / drain region 184c (i.e., the source region of the semiconductor device), contact 246 is connected to N-type source / drain region 184a (i.e., the drain region of the semiconductor device), contact 248 is connected to P-type pickup region 192a, contact 252 is connected to N-type pickup region 184b, and contact 254 is connected to P-type pickup region 192b.

[0053] The semiconductor device includes a gate structure 160, a drain region (i.e., an N-type source / drain region 184a), a source region (i.e., an N-type source / drain region 184c), an NDD 152, and a NLDD 182. The source region and the drain region are located on opposite sides of the gate structure 160 and on opposite sides of the NLDD 182. The NDD 152 is located below the gate structure 160. The NLDD 182 and the drain region are both in the NDD 152. The depth D7 of the NLDD 182 is less than the depth D4 of the NDD 152, and the depth D7 is in a range of about 0.2um to about 0.4um. In some embodiments, the width W of the NLDD 182 is greater than 0um and equal to or less than about 1um. If the width W of the NLDD 182 is greater than about 1um, the NLDD 182 may be close to the gate structure 160, thereby possibly reducing the off-state breakdown voltage of the semiconductor device. In some embodiments, the NLDD 182 does not overlap the gate structure 160 . That is, the gate structure 160 does not cover the NLDD 182 , and the gate structure 160 is spaced apart from the sidewall 182 s of the NLDD 182 .

[0054] NLDD 182 is formed in NDD 152 and is located between N-type source / drain region 184a and gate structure 160. NLDD 182, NDD 152, and N-type source / drain region 184a have substantially coplanar top surfaces (i.e., top surface 112 of substrate 110). In some embodiments, bottom surface 182b of NLDD 182 is laterally spaced from bottom surface 184ab of N-type source / drain region 184a to define distance d1. Distance d1 between NLDD 182 and N-type source / drain region 184a may be greater than 0 and equal to or less than about 0.5um. If distance d1 is greater than about 0.5um, NLDD 182 is close to gate structure 160 and may reduce off-state breakdown voltage of semiconductor device. Since the drain region (N-type source / drain region 184 a ) is between the NLDD 182 and the isolation structure 142 , ie, the NLDD 182 does not diffuse outside the NDD 152 , the NLDD 182 does not reduce the off-state breakdown voltage of the semiconductor device.

[0055] In some embodiments, a distance d2 referred to as a drift region length is formed between the N-type source / drain region 184a and the edge of the NDD 152 adjacent to the HVPB 152. The sum of the width W and the distance d1 is about 10% to 50% of the distance d2. If the sum (W+d1) is less than about 10%, the NLDD 182 is too short to effectively suppress the Kirk effect; if the sum (L+d1) is greater than about 50%, the NLDD 182 may be close to the gate structure 160, resulting in a low off-state breakdown voltage.

[0056] The semiconductor device further includes a RP layer 210 over the gate structure 160 and the drift region 152. The RP layer 210 extends over a portion of the gate structure 160 and over the drain region. The RP layer 210 contacts the NLDD 182. Fig.1O and Figure 3The substrate device further includes SHN 154, SHP156a-156c, HVPB 158, and isolation structures 142, 144, and 146. Isolation structures 142, 144, and 146, SHN 154, and SHP 156a-156c are annular. SHP 156 surrounds isolation structure 146, isolation structure 146 surrounds SHN 154, SHN 154 surrounds isolation structure 144, isolation structure 144 surrounds SHP 156b, SHP 156b surrounds isolation structure 142, and isolation structure 142 surrounds NDD 152, SHP 156a, HVPB 158, and structures formed thereon. The drain region contacts isolation structure 142, and NLDD 182 is spaced apart from isolation structure 142. In some embodiments, the depths of NLDD 182 and the drain region are both less than the depth of isolation structure 142. That is, the bottom surface 182 b of the NLDD 182 is higher than the bottom surface 142 b of the isolation structure 142 .

[0057] Since NLDD 182 is formed between gate structure 160 and N-type source / drain region 184a, the Kirk effect occurring on the drain side can be suppressed. In addition, NLDD 182 also provides good Vd-Id tailing performance. In addition, NLDD 182 does not complicate the manufacturing process for forming the semiconductor device.

[0058] Figure 3 is a cross-sectional view of a semiconductor device according to various embodiments. Figure 3 and Fig.1O The difference between the semiconductor devices is the location of NLDD 182. Figure 3 In the embodiment, NLDD 182 is in contact with N-type source / drain region 184a. That is, the distance d1 (see Figure 1J ) is 0. Figure 3 Other relevant structural details of the semiconductor device in Fig.1O The semiconductor device is similar to that in the embodiment of the present invention, and therefore, the description in this regard will not be repeated hereinafter.

[0059] Figure 4 is a drain voltage (Vd)-drain current (Id) curve of a semiconductor device in an off state according to some embodiments of the present disclosure, Figure 5 is a Vd-Id curve of a semiconductor device in a conducting state according to some embodiments of the present disclosure. Figure 4 In the off state, the breakdown voltage (BV 关断 ) is about 33V. Figure 5 The breakdown voltage (BV 导通 ) is about 32V. In addition, Figure 5 Shows good Id-Vd tailing performance.

[0060] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor device according to various embodiments. Fig. 6A and Fig.1O The difference between semiconductor devices in the well is the conductivity type. Fig. 6A and Figure 6B , the semiconductor device includes a semiconductor substrate 310, a DPW 320, and a DNW 330. The semiconductor substrate 310 is an n-substrate. In some embodiments, the semiconductor device further includes a gate structure 160, isolation structures 142, 144, and 146, a PDD 352, a SHP 354, SHN 356a, 356b, and 356c, and a HVNB 358. In some embodiments, the semiconductor device further includes a PLDD 382, ​​P-type source / drain regions 384a and 384c, a P-type pickup region 384b, and N-type pickup regions 392a, 392b, and 392c. The semiconductor device further includes a RP layer 210, a metal alloy layer 220, an ILD 230, and contacts 242, 244, 246, 248, 252, and 254. In some embodiments, as Fig. 6A As shown, PLDD 382 is spaced apart from P-type source / drain region 384a. In some other embodiments, as shown in FIG. Figure 6B As shown, PLDD 382 is in contact with P-type source / drain regions 384a. Fig. 6A and Figure 6B Other relevant structural details of the semiconductor device are similar to Fig.1O Therefore, the description in this regard will not be repeated hereinafter.

[0061] Fig. 7A and Figure 7B is a cross-sectional view of a semiconductor device according to various embodiments. Fig. 7A and Fig.1O The difference between semiconductor devices is the presence of pocket (doped) regions. Fig. 7A and Figure 7B In the embodiment, the P-type pocket region 186 is formed below the NLDD 182. That is, the P-type pocket region 186 and the NLDD 182 have different conductivity types. The P-type pocket region 186 is configured to isolate the NLDD 182. In some embodiments, the P-type pocket region 186 may be formed below the NLDD 182. Figure 1HThe P-type pocket region 186 and the NLDD 182 may have substantially the same width. In some embodiments, the depth D10 of the P-type pocket region 186 is in the range of about 0.4 um to about 0.6 um, and the doping concentration of the P-type pocket region 186 is about 10 μm per cubic centimeter. 17 To about 10 19 In some embodiments, the P-type pocket region 186 and the NLDD 182 have substantially the same or similar doping concentrations. Fig. 7A and 7B Other relevant structural details of the semiconductor device are similar to Fig.1O Therefore, the description of this aspect will not be repeated below. In some other embodiments, Fig. 6A An N-type pocket region is formed under the PLDD 382 in FIG. 6B , and the detailed description is not repeated hereinafter.

[0062] Figure 8 is a flow chart of a method M1 for forming a semiconductor device according to some embodiments of the present disclosure. Although method M1 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from that shown, and / or the actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0063] At block S12 , DNW, DPW, and isolation structures are formed in the substrate. Figures 1A-1C Perspective and cross-sectional views of some embodiments corresponding to the actions in block S12 are shown.At block S14, NDD, SHN, and SHP are formed in the substrate. Figure 1D Perspective and cross-sectional views of some embodiments corresponding to the actions in block S14 are shown. At block S16, a HVPB is formed in the substrate. Figure 1E-1F Perspective and cross-sectional views of some embodiments corresponding to the actions in block S16 are shown.At block S18, a gate structure is formed over the substrate. Figure 1G Perspective and cross-sectional views of some embodiments corresponding to the actions in block S18 are shown. At block S20, a NLDD is formed in the NDD. Figure 1HPerspective and cross-sectional views of some embodiments corresponding to the actions in block S20 are shown. At block S22, N-type source / drain regions and P-type source / drain regions are formed in the substrate. Figures 1J-1K Perspective and cross-sectional views of some embodiments corresponding to the actions in block S22 are shown. At block S24, a RP layer is formed over the gate structure and the NLDD. Figure 1L-1M Perspective and cross-sectional views of some embodiments corresponding to the actions in block S24 are shown. At block S26, a metal alloy layer is formed over the gate structure, the N-type source / drain region, and the P-type source / drain region, respectively. Figure 1N Perspective and cross-sectional views of some embodiments corresponding to the actions in block S26 are shown. At block S28, contacts are formed over the metal alloy layers, respectively. Fig.1O Perspective and cross-sectional views of some embodiments corresponding to the actions in block S28 are shown. In some embodiments, the following process is performed between blocks S18 and S20: forming a pocket region in the NDD.

[0064] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and specific advantages are not required for all embodiments. One advantage is that NLDD improves the Kirk effect occurring on the drain side. Thereby improving the off-state breakdown voltage, on-state breakdown voltage, and Id-Vd tailing performance. Another advantage is that NLDD does not complicate the manufacturing process for forming the semiconductor device.

[0065] According to some embodiments, a semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is located above the substrate. The drift region is located in the substrate and below the gate structure. The source region and the drain region are located on opposite sides of the gate structure. The drain region is in the drift region and the source region is outside the drift region. The doped region is in the drift region and is located between the drain region and the gate structure. The doped region is spaced apart from the bottom surface of the drain region.

[0066] According to some embodiments, a semiconductor device includes a substrate, a drift region, a gate structure, a source region, a drain region, an isolation structure, and a doped region. The drift region is in the substrate. The gate structure is located above the drift region. The source region and the drain region are located on opposite sides of the gate structure. The drain region is located in the drift region. The isolation structure contacts the drain region and the drift region. The doped region is in the drift region and is located between the drain region and the gate structure. The doped region and the drain region have the same conductivity type, and the bottom surface of the doped region is located above the bottom surface of the isolation structure.

[0067] According to some embodiments, a method for manufacturing a semiconductor device includes forming a drift region in a substrate. Forming a gate structure above the drift region. Forming a doped region in the drift region. Forming a source region and a drain region on opposite sides of the gate structure and in the drift region. The doped region is formed between the gate structure and the drain region.

[0068] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0069] Example 1. A semiconductor device, comprising: a substrate; a gate structure located above the substrate; a drift region in the substrate and located below the gate structure; a source region and a drain region located on opposite sides of the gate structure, wherein the drain region is in the drift region and the source region is outside the drift region; and a doped region in the drift region and located between the drain region and the gate structure.

[0070] Example 2. The semiconductor device of Example 1, wherein the drift region, the doped region, and the drain region have the same conductivity type.

[0071] Example 3. The semiconductor device of Example 1, wherein a doping concentration of the doping region is lower than a doping concentration of the drain region.

[0072] Example 4. The semiconductor device of Example 1, wherein a doping concentration of the doping region is higher than a doping concentration of the drift region.

[0073] Example 5. The semiconductor device of Example 1, wherein the doped region is in contact with the drain region.

[0074] Example 6. The semiconductor device of Example 1, wherein the doped region is spaced apart from the drain region.

[0075] Example 7. The semiconductor device of Example 1, wherein the doped region is spaced apart from a bottom surface of the drain region.

[0076] Example 8. The semiconductor device of Example 1, wherein a depth of the doped region is less than a depth of the drift region.

[0077] Example 9. The semiconductor device of Example 1, wherein the gate structure is spaced apart from a sidewall of the doped region facing the source region.

[0078] Example 10. The semiconductor device according to Example 1 further includes: a pocket region located below the doped region.

[0079] Example 11. A semiconductor device comprising: a substrate; a drift region in the substrate; a gate structure located above the drift region; a source region and a drain region located on opposite sides of the gate structure, wherein the drain region is in the drift region; an isolation structure in contact with the drain region and the drift region; and a doped region in the drift region and located between the drain region and the gate structure, wherein the doped region and the drain region have the same conductivity type.

[0080] Example 12. The semiconductor device of Example 11, wherein a doping concentration of the doping region is between a doping concentration of the drain region and a doping concentration of the drift region.

[0081] Example 13. The semiconductor device according to Example 11 further includes: an anti-etching protection layer, the anti-etching protection layer extending over a portion of the gate structure and over the drain region, wherein the anti-etching protection layer is in contact with the doped region.

[0082] Example 14. The semiconductor device of Example 11, wherein a bottom surface of the doped region is above a bottom surface of the isolation structure.

[0083] Example 15. A method for manufacturing a semiconductor device, comprising: forming a drift region in a substrate; forming a gate structure above the drift region; forming a doped region in the drift region; and forming a source region and a drain region on the opposite side of the gate structure and in the drift region, wherein the doped region is formed between the gate structure and the drain region.

[0084] Example 16. The method of Example 15, wherein the doped region and the drain region have the same conductivity type.

[0085] Example 17. The method of Example 15, wherein a doping concentration of the doping region is between a doping concentration of the drain region and a doping concentration of the drift region.

[0086] Example 18. The method of Example 15, further comprising: forming a dielectric layer over the gate structure and the doped region.

[0087] Example 19. The method of Example 15 further includes: after forming the doped region, forming a gate spacer on a sidewall of the gate structure.

[0088] Example 20. The method of Example 19, wherein the source region and the drain region are formed after forming the gate spacer.

Claims

1. A semiconductor device, comprising: substrate; A gate structure located above the substrate; a drift region in the substrate and below the gate structure; a source region and a drain region located on opposite sides of the gate structure, wherein the drain region is in the drift region and the source region is outside the drift region; a doped region in the drift region and between the drain region and the gate structure; and A pocket region is located in the drift region and below the doped region, the pocket region having substantially the same width as the doped region and having a different conductivity type than the doped region.

2. The semiconductor device according to claim 1, wherein The drift region, the doped region, and the drain region have the same conductivity type.

3. The semiconductor device according to claim 1, wherein The doping concentration of the doping region is lower than the doping concentration of the drain region.

4. The semiconductor device according to claim 1, wherein: The doping concentration of the doping region is higher than the doping concentration of the drift region.

5. The semiconductor device according to claim 1, wherein The doped region contacts the drain region.

6. The semiconductor device according to claim 1, wherein The doped region is spaced apart from the drain region.

7. The semiconductor device according to claim 1, wherein The doped region is spaced apart from a bottom surface of the drain region.

8. The semiconductor device according to claim 1, wherein The depth of the doped region is less than the depth of the drift region.

9. The semiconductor device according to claim 1, wherein: The gate structure is spaced apart from a sidewall of the doped region facing the source region.

10. A semiconductor device comprising: substrate; a drift region in the substrate; A gate structure located above the drift region; a source region and a drain region located on opposite sides of the gate structure, wherein the drain region is in the drift region; an isolation structure in contact with the drain region and the drift region; a doped region in the drift region and between the drain region and the gate structure, wherein the doped region and the drain region have the same conductivity type; and A pocket region is located in the drift region and below the doped region, the pocket region having substantially the same width as the doped region and having a different conductivity type than the doped region.

11. The semiconductor device according to claim 10, wherein: The doping concentration of the doping region is between the doping concentration of the drain region and the doping concentration of the drift region.

12. The semiconductor device according to claim 10, further comprising: An etch-resistant protection layer is over a portion of the gate structure and extends over the drain region, wherein the etch-resistant protection layer contacts the doped region.

13. The semiconductor device according to claim 12, wherein: A bottom surface of the doped region is above a bottom surface of the isolation structure.

14. A method for manufacturing a semiconductor device, comprising: forming a drift region in the substrate; forming a gate structure above the drift region; forming a pocket region in the drift region; After forming the pocket region, forming a doped region in the drift region and above the pocket region, wherein the pocket region has substantially the same width as the doped region and has a different conductivity type than the doped region; and A source region and a drain region are formed on opposite sides of the gate structure and in the drift region, wherein the doped region is formed between the gate structure and the drain region.

15. The method according to claim 14, wherein: The doped region and the drain region have the same conductivity type.

16. The method according to claim 14, wherein: The doping concentration of the doping region is between the doping concentration of the drain region and the doping concentration of the drift region.

17. The method according to claim 14, further comprising: A dielectric layer is formed over the gate structure and the doped region.

18. The method according to claim 14, further comprising: After forming the doped regions, gate spacers are formed on sidewalls of the gate structure.

19. The method according to claim 18, wherein: The source region and the drain region are formed after forming the gate spacer.

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