A technique for scheduling instructions in compiled source code

Abstract

Examples described herein generally involve generating a plurality of basic blocks from a list of source code for compiling the source code into an intermediate language; determining, for a first basic block of the plurality of basic blocks, a first heuristic associated with applying a first plurality of optimizations to the first basic block; determining, for a second basic block of the plurality of basic blocks, a second heuristic associated with applying a second plurality of optimizations to the second basic block; and based on the first heuristic and the second heuristic, applying one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block and applying one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the field of computer technology, and more particularly to a technique for scheduling instructions in compiled source code. Background Art

[0002] Nowadays, the use of computing devices is becoming increasingly common. Computing devices range from standard desktop computers to gaming systems to wearable computing technologies, etc. Programming languages ​​can be used to develop software for computing devices, and generally provide an environment for writing source code instructions. By using a compiler, source code instructions can be compiled into an intermediate language that can be understood by a computing device operating system or a processor for executing instructions based on the source code. When compiling the source code, the compiler can group the intermediate language instructions representing the source code into instruction basic blocks, which are executed sequentially and without branches. When the compiler encounters a branch statement in the source code (such as a loop, a conditional clause, a function or a procedure call, etc.), the compiler can generate another instruction basic block for the branch, and so on, until all source codes are compiled. The instruction basic block for the program can then be scheduled in the intermediate language to generate compiled software code, which can be executed on a computing device operating system or a processor. Summary of the invention

[0003] A simplified overview of one or more examples is presented below to provide a basic understanding of these examples. The content of the present invention is not an extensive overview of all contemplated examples, nor is it intended to identify the key or important elements of all examples, nor is it intended to describe the scope of any or all examples. Its sole purpose is to present some concepts of one or more examples in a simplified form as a preface to the specific embodiments presented later.

[0004] In an example, a computer-implemented method for scheduling instructions in compiling source code is provided. The method includes generating a plurality of basic blocks for compilation into an intermediate language from a source code list; for a first basic block of the plurality of basic blocks, determining a first heuristic related to applying a first plurality of optimizations to the first basic block; for a second basic block of the plurality of basic blocks, determining a second heuristic related to applying a second plurality of optimizations to the second basic block; based on the first heuristic and the second heuristic, applying one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block, and applying one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block.

[0005] In another example, a computing device for scheduling instructions in compiling source code is provided. The device includes a memory storing one or more parameters or instructions for compiling source code, and at least one processor coupled to the memory. The at least one processor is configured to generate a plurality of basic blocks for compiling into an intermediate language from a source code list; for a first basic block of the plurality of basic blocks, determine a first heuristic related to applying a first plurality of optimizations to the first basic block; for a second basic block of the plurality of basic blocks, determine a second heuristic related to applying a second plurality of optimizations to the second basic block; and based on the first heuristic and the second heuristic, apply one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block, and apply one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block.

[0006] In another example, a non-transitory computer-readable medium is provided, which includes code executable by one or more processors for scheduling instructions in compiled source code. The code includes: code for generating a plurality of basic blocks for compilation into an intermediate language from a source code list; code for determining, for a first basic block of the plurality of basic blocks, a first heuristic related to applying a first plurality of optimizations to the first basic block; code for determining, for a second basic block of the plurality of basic blocks, a second heuristic related to applying a second plurality of optimizations to the second basic block; code for applying one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block, and applying one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block based on the first heuristic and the second heuristic.

[0007] To achieve the above and related purposes, one or more examples include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more examples. However, these features are only indicative of some of the various ways in which the principles of the various examples can be employed, and this description is intended to include all such examples and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an example of a computing device for compiling source code according to examples described herein.

[0009] Figure 2 is a flow diagram of an example of selecting instructions for optimizing source code compilation according to examples described herein.

[0010] Figure 3 is a flow chart of a process for optimizing basic blocks in an intermediate language according to examples described herein.

[0011] Figure 4 is a schematic diagram of an example of a computing device for performing the functions described herein. DETAILED DESCRIPTION

[0012] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, known components are shown in block diagram form to avoid confusing these concepts.

[0013] Described herein are various examples related to optimizing instruction scheduling in compiled source code. In one example, a compiler can generate multiple basic blocks of instructions in an intermediate language, wherein each basic block can include a set of intermediate language instructions corresponding to a source code instruction sequence without branches. For each basic block of intermediate language instructions, the compiler can determine a set of heuristics to schedule the corresponding instructions in the basic block, and the set of heuristics corresponds to each of the multiple possible optimizations that can be performed for a given basic block. For example, the set of heuristics can correspond to an estimated performance metric based on an instruction scheduling for a given optimization of a basic block. Based on the set of heuristics, the compiler can schedule the instruction sequence in each basic block.

[0014] Some compilers can provide optimizations implemented by instruction scheduling, but a given optimization is applied to all basic blocks of instructions for a software application. According to the examples described herein, optimizations can be evaluated and applied for each of a plurality of basic blocks of a software application to obtain a more optimized software application. For example, using the heuristics determined for each of a plurality of basic blocks, the heuristics for all basic blocks (or at least a subset of a plurality of basic blocks) can be considered together (e.g., added) to determine a combination of heuristics to obtain the most desired overall heuristic, which can be used for a given optimization or other for the overall software application. The corresponding optimizations for the heuristics determined for each basic block can be applied to the instruction sequence of the scheduling basic block to optimize the overall source code in compiling the software application.

[0015] Now turn Figures 1 to 4 , with reference to one or more components and one or more method examples that can perform the actions and operations described herein are depicted, where the components and / or actions / operations in dashed lines are optional. Figure 2The described operations are presented in a particular order and / or performed by example components, and in some examples, the arrangement of these actions and the components that perform the actions may vary depending on the implementation. In addition, in some examples, one or more of the following actions, functions, and / or described components may be performed by a specially programmed processor, a processor that executes specially programmed software or computer-readable media, or by any other combination of hardware components and / or software components that are capable of performing the described actions or functions.

[0016] Figure 1 Schematic diagram of an example computing device 100 and / or related components for scheduling instructions in compiled source code according to various aspects described herein. For example, computing device 100 may include or may be otherwise coupled to processor 104 and / or memory 106, wherein processor 104 and / or memory 106 may be configured to execute or store instructions or other parameters related to associating interactive data with media content as described herein. For example, processor 104 and memory 106 may be independent components coupled via bus communication (such as, on a motherboard or other part of a computing device, on an integrated circuit (such as a system on a chip SOC), etc.), components integrated with each other (such as, processor 104 may include memory 106 as an onboard component 101), etc. Memory 106 may store instructions, parameters, data structures, etc. for use / execution by processor 104 to perform the functions described herein.

[0017] In an example, the computing device 100 may execute an operating system 108 (e.g., via the processor 104 and / or the memory 106) to provide an environment for executing one or more applications, such as an optional development environment 110 for providing an interface to support source code development, a compiler 112 for compiling source code generated using the development environment 110 or otherwise received at the computing device 100, and / or an optional application 114 generated from an intermediate language compiled based on the source code, where the application can be executed via the operating system 108 and / or on other computing devices via other operating systems (not shown).

[0018] The compiler 112 may include a basic block generation component 120 for generating basic blocks of intermediate language instructions from a source code listing. For example, the source code may include text written in a programming language according to a specified syntax, wherein the compiler 112 may interpret the source code and generate corresponding machine language understood by the processor 104 and / or the operating system 108 (or the processor 104 and / or the operating system 108 of another device, wherein the compiler 112 may be executed on a computing device to generate software applications for other types of devices). Thus, the basic block generation component 120 may use an interpreter of the programming language that can process the source code to generate basic blocks of machine language instructions from the source code.

[0019] As described above, each basic block can be a collection of machine language instructions generated without branches (such as machine language corresponding to the source code within the branch). The source code without branches can include a sequential list of source code that does not reference or jump to different source code locations, such as loops, conditional clauses, source code within a function or procedure call, etc. For each branch, the basic block generation component 120 can generate a new basic block of machine language instructions until the next branch, and so on, until the source code is compiled into multiple basic blocks of machine language instructions. The machine language can then be used to create an application 114 to execute on the processor 104 and / or the operating system 108 (or another processor 104 and / or operating system 108 as described above).

[0020] The compiler 112 also includes a heuristic determination component 122 for determining a heuristic associated with applying an optimization to each basic block generated from the source code. For example, the heuristic determination component 122 can determine the heuristic as one or more performance metrics related to applying one of a plurality of possible optimizations to a basic block to schedule corresponding machine language instructions. The compiler 112 can also include an instruction scheduling component 124 for scheduling machine language instructions within a basic block (e.g., scheduling a sequence of instructions in a basic block) based on determining which optimizations for a given basic block result in the best optimization for all basic blocks (or at least a subset of a plurality of basic blocks).

[0021] Figure 2 is an example flow chart of a method 200 for scheduling instructions in compiled source code. For example, the method 200 may be performed by the computing device 100, and thus reference is made to Figure 1 Described is a non-limiting example of an environment for implementing method 200 .

[0022] In method 200, at action 202, a plurality of basic blocks for compiling into an intermediate language may be generated from a source code list. In an example, a basic block generation component 120 (e.g., in conjunction with a processor 104, a memory 106, an operating system 108, a compiler 112, etc.) may generate a plurality of basic blocks for compiling into an intermediate language from a source code list. For example, a source code list may be received from a development environment 110 as a source code written by an application developer using an interface of the development environment 110. In another example, the source code may be received from another application or computing device. The source code may include one or more files having a command list in a grammar of a programming language. The compiler 112 may obtain the list and may use an interpreter to parse the list of source code. As described above, the basic block generation component 120 may generate one or more basic blocks from the source code by converting the programming language grammar into machine language instructions, and each basic block may be generated as a sequence of instructions corresponding to the source code until a branch is reached, at which point the basic block generation component 120 may generate another basic block, and so on.

[0023] In the method 200, at 204, a first heuristic may be determined for a first basic block related to applying a first plurality of optimizations to the first basic block. In an example, the heuristic determination component 122 (e.g., in conjunction with the processor 104, the memory 106, the operating system 108, the compiler 112, etc.) may determine for the first basic block a first heuristic related to applying a first plurality of optimizations to the first basic block. For example, the heuristic determination component 122 may determine the first heuristic to include at least one heuristic for each possible optimization for the first basic block. For example, the optimization may involve reducing register pressure (e.g., reducing the number of registers required to execute the machine language corresponding to the basic block), reducing the latency associated with executing the basic language of the basic block, reducing the size of the machine language for the basic block, etc. In this example, the heuristic may accordingly include a register pressure metric for each possible optimization (e.g., the number or percentage of registers used), a latency metric for each possible optimization, a code size for each possible optimization, etc. In an example, as further described herein, in this regard, the compiler 112 may ultimately apply different optimizations in scheduling machine language instructions corresponding to the source code to achieve the selected optimization.

[0024] In the method 200, at act 206, a second heuristic can be determined for the second basic block related to applying the second plurality of optimizations to the second basic block. In an example, the heuristic determination component 122 (e.g., in conjunction with the processor 104, the memory 106, the operating system 108, the compiler 112, etc.) can determine for the second basic block a second heuristic related to applying the second plurality of optimizations to the second basic block. For example, the heuristic determination component 122 can determine the second heuristic to include at least one heuristic for each possible optimization for the second basic block. For example, the heuristic determination component 122 can determine the first heuristic and the second heuristic based on the same set of possible optimizations or different sets of possible optimizations.

[0025] In addition, the heuristic determination component 122 can determine heuristics for additional basic blocks and / or all basic blocks of the source code listing. Thus, in an example, the heuristic determination component 122 can generate a table of basic blocks and possible optimizations, where the values ​​in the table can correspond to a heuristic for each possible optimization for each basic block in the table. In this example, multiple heuristics can be evaluated together to determine which optimization to apply to each basic block to achieve a particular optimization in the machine language.

[0026] In the method 200, at 208, based on the first heuristic and the second heuristic, one of the first plurality of optimizations can be applied to the first basic block to schedule a first instruction for the first basic block, and one of the second plurality of optimizations can be applied to the second basic block to schedule a second instruction for the second basic block. In an example, the instruction scheduling component 124 (e.g., in conjunction with the processor 104, the memory 106, the operating system 108, the compiler 112, etc.) can apply one of the first plurality of optimizations to the first basic block to schedule the first instruction for the first basic block based on the first heuristic and the second heuristic, and apply one of the second plurality of optimizations to the second basic block to schedule the second instruction for the second basic block. As described above, in this regard, scheduling instructions can refer to scheduling a sequence of instructions to be executed within each given basic block, wherein the sequence of scheduled instructions is scheduled to implement a corresponding optimization. Thus, for example, the instruction scheduling component 124 can schedule the first instruction by generating a sequence of first instructions that implement one of the first plurality of optimizations. In addition, for example, the instruction scheduling component 124 can schedule the second instruction by generating a sequence of second instructions that implement one of the second plurality of optimizations.

[0027] In one example, the instruction scheduling component 124 can analyze the first heuristic and the second heuristic together (e.g., and / or other heuristics for other basic blocks) to determine a combination of optimizations to apply to each basic block. In a specific example, the instruction scheduling component 124 can sum the heuristics for each basic block for each corresponding optimization to determine which optimization achieves the most desirable heuristic for all basic blocks (e.g., minimum register pressure, minimum latency, minimum code size, etc.) for that particular basic block. For example, different optimizations applied to each basic block may achieve better overall optimization of the source code for one or more purposes.

[0028] In an example, in applying the optimization to the basic block at act 208, optionally at act 210, the one of the first plurality of optimizations may be selected as a different optimization than the one of the second plurality of optimizations. In an example, the instruction scheduling component 124 (e.g., in conjunction with the processor 104, the memory 106, the operating system 108, the compiler 112, etc.) may select the one of the first plurality of optimizations to be a different optimization than the one of the second plurality of optimizations. As described above, for example, the instruction scheduling component 124 may apply a first optimization related to reducing register pressure to the first basic block and a second optimization related to reducing latency to the second basic block to achieve overall optimization for the source code listing.

[0029] In another example, before applying the optimization to the basic block at act 208, optionally at act 212, the optimization in the first plurality of optimizations and the optimization in the second plurality of optimizations may be selected based on the optimization goal determined for the source code list. In an example, the instruction scheduling component 124 (e.g., in conjunction with the processor 104, the memory 106, the operating system 108, the compiler 112, etc.) may select the optimization in the first plurality of optimizations and the optimization in the second plurality of optimizations based on the optimization goal determined for the source code list. As described above, the overall optimization goal for the source code may be different from the goal selected for a given basic block, and selecting different optimizations for each basic block may allow the overall goal to be better achieved. Therefore, the instruction scheduling component 124 may determine which combination of optimizations for each basic block allows the overall optimization goal to be achieved, and may accordingly select the optimization for generating or reordering the scheduling instructions for the basic block.

[0030] In method 200, optionally at act 214, an intermediate language may be generated that includes a first instruction for a first basic block and a second instruction for a second basic block. In an example, compiler 112 (e.g., in conjunction with processor 104, memory 106, operating system 108, compiler 112, etc.) may generate an intermediate language that includes a first instruction for the first basic block and a second instruction for the second basic block. In this regard, instruction scheduling component 124 may apply optimization to each basic block to generate a sequence of scheduling instructions to achieve the optimization, and compiler 112 may combine the basic blocks into the intermediate language for executing the corresponding software application.

[0031] Figure 3 An example of a flow chart for compiling source code 302 into an optimized intermediate language 308 according to aspects described herein is illustrated. In an example, source code 302 may be compiled into an initial intermediate language 304, as described above, including a plurality of basic blocks (e.g., basic block 1, basic block 2, ..., basic block n). As described herein, a plurality of heuristics may include methods for applying possible optimizations to each basic block. As shown, the heuristics may include a heuristic for optimization 1 for basic block 1, a heuristic for optimization 2 for basic block 1, ... a heuristic for optimization m for basic block 1, ... a heuristic for optimization m for basic block 1, ... a heuristic for optimization 1 for basic block n, a heuristic for optimization 2 for basic block n, ... a heuristic for optimization m for basic block n, substantially for any values ​​of n and m.

[0032] By determining all heuristics for each optimization for each basic block, a combination of optimizations applied to the basic blocks (e.g., one optimization for each basic block) can be determined, and as described in one example, the determination can be based on an overall optimization goal for the software application. In one example, the heuristics can be summed, and it can be determined which combination of the summed optimization metrics obtains the lowest expected optimization metric for the entire set of n basic blocks. These optimizations can then be applied to the corresponding basic blocks to generate an optimized intermediate language 308. In the example shown, the optimized intermediate language 308 can include basic block 1 to which optimization 1 is applied, basic block 2 to which optimization m is applied, ... basic block n to which optimization 1 is applied.

[0033] Figure 4 An example of a computing device 100 is shown, which includes Figure 1 Additional optional component details are shown. In one example, computing device 100 may include a processor 104 for implementing processing functions associated with one or more components and functions described herein. Processor 104 may include a single or multiple processors or a multi-core processor. In addition, processor 104 may be implemented as an integrated processing system and / or a distributed processing system.

[0034] The computing device 100 may also include a memory 106, for example, for storing a local version of an application program (which is executed by the processor 104), related instructions, parameters, etc. The memory 106 may include any type of memory that can be used by a computer, such as random access memory (RAM), read-only memory (ROM), tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and any combination thereof. In addition, the processor 104 and the memory 106 may include an operating system, one or more application programs, such as the development environment 110, the compiler 112, the application 114, and / or components thereof, as described herein, and / or other components of the computing device 100, which are executed on the processor 104.

[0035] Further, the computing device 100 may include a communication component 402 that provides for establishing and maintaining communications with one or more other devices, parties, entities, etc. using the hardware, software, services described herein. The communication component 402 may carry communications between the components of the computing device 100 and between the computing device 100 and external devices, such as devices located across a communication network and / or devices connected serially or locally to the computing device 100. For example, the communication component 402 may include one or more buses and also include a transmission chain component and a reception chain component associated with a wireless or wired transmitter and receiver, which are operable to interface with external devices, respectively. For example, the communication component 402 may carry communications between the development environment 110, the compiler 112, an application 114 executed on another device (or the same device), etc., as described in various examples herein.

[0036] Additionally, computing device 100 may include data storage 404, which may be any suitable combination of hardware and / or software, that provides mass storage of information, databases, and programs employed in conjunction with the examples described herein. For example, data storage 404 may be or may include a data repository for applications and / or related parameters that are not currently being executed by processor 104. Furthermore, data storage 404 may be a data repository for an operating system, applications, such as development environment 110, compiler 112, applications 114, and / or components thereof, etc., executing on processor 104, and / or one or more other components of computing device 100.

[0037] The computing device 100 may also include a user interface 406 that is operable to receive input from a user of the computing device 100 and further operate to generate output for presentation to the user (e.g., via a display interface to the display device 100). The user interface 406 may include one or more input devices, including, but not limited to, a keyboard, a numeric keypad, a mouse, a touch-sensitive display, navigation keys, function keys, a microphone, a speech recognition component, a gesture recognition component, a depth sensor, a gaze tracking sensor, any other device capable of receiving input from a user, or any combination thereof. In addition, the user interface 406 may include one or more output devices, including, but not limited to, a display interface, a speaker, a tactile feedback device, a printer, any other device capable of presenting output to a user, or any combination thereof.

[0038] The computing device 100 may also include a development environment 110 for providing one or more interfaces for developing application source code, a compiler 112 for compiling the source code into machine code for execution on the computing device 100 or other devices, and / or an application 114, which may be a software representation of the compiled source code that can be executed on the computing device 100 or sent to another device or medium for execution therein.

[0039] As an example, an element, or any part of an element, or any combination of elements may be implemented by a "processing system" comprising one or more processors. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other hardware that is suitably configured to perform the various functions disclosed herein. One or more processors in a processing system may execute software. Software should be broadly interpreted to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable code, execution threads, processes, functions, etc., whether referring to software, firmware, middleware, microcode, hardware description languages, or other.

[0040] Accordingly, in one or more examples, one or more of the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the function may be stored or encoded as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media. Storage media may be any available medium accessed by a computer. As an example and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store required program code in the form of an instruction or data structure and can be accessed by a computer. The optical disk and disk used herein include a compact disk (CD), a laser disk, an optical disk, a digital versatile disk (DVD disk) and a floppy disk, wherein the optical disk usually magnetically copies data, and the disk uses a laser to optically copy data. The above combination should also be included in the scope of computer-readable media.

[0041] The description provided above enables those skilled in the art to implement various examples of this invention. Various modifications to these examples are obvious to those skilled in the art, and the general principles defined herein can be applied to other examples. Therefore, the claims are not intended to be limited to the examples shown herein, but to conform to the full scope consistent with the language claims, wherein the elements mentioned in the singular form, unless otherwise specified, are not intended to mean "one and only one", but to mean "one or more". Unless otherwise specified, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various examples described herein known or to be known later by those of ordinary skill in the art are intended to be covered by the claims. In addition, regardless of whether such disclosure is explicitly cited in the claims, anything disclosed herein is not intended to be exclusively for public use. Unless the element is explicitly described using the phrase "device for...", any claim element shall not be interpreted as a method plus function.

Claims

1. A computer-implemented method for scheduling instructions in compiled source code, comprising: generating a plurality of basic blocks for compilation into an intermediate language from a source code listing; determining, for a first basic block of the plurality of basic blocks, a first heuristic related to applying a first plurality of optimizations to the first basic block; determining, for a second basic block of the plurality of basic blocks, a second heuristic related to applying a second plurality of optimizations to the second basic block; as well as Based on the first heuristic and the second heuristic, applying one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block, and applying one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block, wherein applying comprises: selecting the one of the first plurality of optimizations for the first basic block to achieve an overall optimization based on the first heuristic and the second heuristic; as well as The one of the second plurality of optimizations for the second basic block is selected to achieve the overall optimization based on the first heuristic and the second heuristic. 2 . The computer-implemented method of claim 1 , wherein the first plurality of optimizations are the same as the second plurality of optimizations. 3 . The computer-implemented method of claim 1 , wherein the first plurality of optimizations comprises at least one of: minimizing register pressure, minimizing program size, or minimizing memory latency.

4. The computer-implemented method of claim 1 , wherein the first heuristics each correspond to an estimated optimization metric for a given one of the first plurality of optimizations, and wherein the second heuristics each correspond to an estimated optimization metric for a given one of the second plurality of optimizations.

5. The computer-implemented method of claim 1 , wherein the application comprises: The one of the first plurality of optimizations is selected to be a different optimization than the one of the second plurality of optimizations.

6. The computer-implemented method of claim 1, wherein the overall optimization is determined for at least a portion of the source code listing.

7. The computer-implemented method of claim 1 , further comprising: The intermediate language including the first instruction for the first basic block and the second instruction for the second basic block is generated.

8. A computing device for scheduling instructions in a compiled source code, comprising: A memory storing one or more parameters or instructions for compiling source code; as well as at least one processor coupled to the memory, wherein the at least one processor is configured to: generating a plurality of basic blocks for compilation into an intermediate language from a source code listing; determining, for a first basic block of the plurality of basic blocks, a first heuristic related to applying a first plurality of optimizations to the first basic block; determining, for a second basic block of the plurality of basic blocks, a second heuristic related to applying a second plurality of optimizations to the second basic block; as well as Based on the first heuristic and the second heuristic, applying one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block, and applying one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block, wherein applying comprises: selecting the one of the first plurality of optimizations for the first basic block to achieve an overall optimization based on the first heuristic and the second heuristic; as well as The one of the second plurality of optimizations for the second basic block is selected to achieve the overall optimization based on the first heuristic and the second heuristic.

9. The computing device of claim 8, wherein the first plurality of optimizations are the same as the second plurality of optimizations.

10. The computing device of claim 8, wherein the first plurality of optimizations comprises at least one of: minimizing register pressure, minimizing program size, or minimizing memory latency.

11. The computing device of claim 8, wherein the first heuristics each correspond to an estimated optimization metric for a given optimization in the first plurality of optimizations, and wherein the second heuristics each correspond to an estimated optimization metric for a given optimization in the second plurality of optimizations.

12. The computing device of claim 8, wherein the at least one processor is configured to select the one of the first plurality of optimizations as a different optimization than the one of the second plurality of optimizations.

13. The computing device of claim 8, wherein the at least one processor is further configured to determine the overall optimization for at least a portion of the source code listing. 14 . The computing device of claim 8 , wherein the at least one processor is further configured to generate the intermediate language including the first instruction for the first basic block and the second instruction for the second basic block.

15. A non-transitory computer readable medium comprising code executable by one or more processors for scheduling instructions in compiled source code, the code comprising code for: generating a plurality of basic blocks for compilation into an intermediate language from a source code listing; determining, for a first basic block of the plurality of basic blocks, a first heuristic related to applying a first plurality of optimizations to the first basic block; determining, for a second basic block of the plurality of basic blocks, a second heuristic related to applying a second plurality of optimizations to the second basic block; as well as Based on the first heuristic and the second heuristic, applying one of the first plurality of optimizations to the first basic block to schedule a first instruction for the first basic block, and applying one of the second plurality of optimizations to the second basic block to schedule a second instruction for the second basic block, wherein applying comprises: selecting the one of the first plurality of optimizations for the first basic block to achieve an overall optimization based on the first heuristic and the second heuristic; as well as The one of the second plurality of optimizations for the second basic block is selected to achieve the overall optimization based on the first heuristic and the second heuristic.

16. The non-transitory computer readable medium of claim 15, wherein the first plurality of optimizations are the same as the second plurality of optimizations. 17 . The non-transitory computer readable medium of claim 15 , wherein the first plurality of optimizations comprises at least one of: minimizing register pressure, minimizing program size, or minimizing memory latency.

18. The non-transitory computer-readable medium of claim 15, wherein the first heuristics each correspond to an estimated optimization metric for a given one of the first plurality of optimizations, and wherein the second heuristics each correspond to an estimated optimization metric for a given one of the second plurality of optimizations.

19. The non-transitory computer-readable medium of claim 15, wherein the code for applying selects the one of the first plurality of optimizations to be a different optimization than the one of the second plurality of optimizations.

20. The non-transitory computer-readable medium of claim 15, wherein the code for applying selects the one of the first plurality of optimizations and the one of the second plurality of optimizations based on an overall optimization goal for the source code listing.

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