Direct Input Redundancy Scheme Using Adaptive Syndrome Decoder

Abstract

The present application relates to a direct input redundancy scheme utilizing an adaptive syndrome decoder. A device having read data from a data plane may replace data from one of the planes with redundant data from a data plane storing redundant data. The device may then provide the redundant data to an error correction circuit coupled to the data plane storing the redundant data. The output of the error correction circuit may be used to generate syndrome bits that may be decoded by a syndrome decoder. The syndrome decoder may indicate whether bits of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bits to be corrected are regular data bits, and react to a second set of inputs if the data bits to be corrected are redundant data bits.

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 063393, filed by Nakai on November 26, 2019, entitled “DIRECT-INPUT REDUNDANCY SCHEME WITH ADAPTIVE SYNDROME DECODER,” which claims priority to U.S. Patent Application No. 16 / 212,017, filed by Nakai on December 6, 2018, entitled “DIRECT-INPUT REDUNDANCY SCHEME WITH ADAPTIVE SYNDROME DECODER,” each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to a direct input redundancy scheme using an adaptive syndrome decoder. Background Art

[0004] The following relates generally to operating a memory array, and more particularly to a direct-input redundancy scheme utilizing an adaptive syndrome decoder.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device has two states, usually represented by a logical "1" or a logical "0". In other systems, more than two states can be stored. To access the stored information, a component of the electronic device may perform a read operation to sense the stored state in the memory device. To store information, a component of the electronic device may perform a write operation to program the state into the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM, PCM, RRAM) can maintain its stored logic state for a long time, even if no external power source is present. Volatile memory devices (e.g., DRAM) may lose their stored state over time unless they are periodically refreshed by an external power source.

[0007] During a retrieval operation, a memory device may read data bits stored in the memory and perform error correction thereon. Prior to error correction, the device may replace some of the data bits with substitute data bits, which may be referred to as redundant data bits. However, the data path between the memory location of the redundant bits and the error correction circuitry may add unnecessary and costly delays to the error correction operation, which may increase the latency of the retrieval operation, among other disadvantages. Summary of the invention

[0008] An apparatus is described. The apparatus may include an error correction code (ECC) circuit coupled to a data plane and configured to receive data bits from the data plane, a redundant ECC circuit coupled to a redundant data plane and configured to receive redundant data corresponding to data stored by at least one of the data planes, and a syndrome decoder circuit for a first one of the data planes, the syndrome decoder circuit coupled to the redundant ECC circuit and the ECC circuit and configured to adjust its output based at least in part on whether the redundant data received by the redundant ECC circuit corresponds to data stored by the first data plane.

[0009] An apparatus is described. The apparatus may include a bit flipping circuit configured to invert data bits; and a syndrome decoder for a first data plane, the syndrome decoder coupled to the bit flipping circuit and comprising: a first decoder configured to receive a first set of bits, the first set of bits comprising syndrome bits generated at least in part based on a set of data, inverted syndrome bits, or a combination thereof; and a second decoder configured to receive a second set of bits comprising an inverted version of the first set of bits.

[0010] A method is described. The method may include generating syndrome bits for data stored by data planes; selecting data bits from the data for an error correction operation; communicating a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for the error correction operation; and decoding the syndrome bits at the syndrome decoder based at least in part on the control signal.

[0011] A method is described. The method may include performing a first bitwise operation on a first set of redundant data for a first data plane using an ECC circuit, the first set of redundant data corresponding to data stored by the first data plane; transferring a result of the first bitwise operation to a combination of logic gates; performing a second bitwise operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transferring a result of the second bitwise operation to the combination of logic gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An example memory array supporting a direct-input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is described.

[0013] Figure 2 An example of a memory architecture supporting a direct-input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is described.

[0014] Figure 3 An example Hamming matrix supporting a direct-input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is illustrated.

[0015] Figure 4 An example ECC module supporting a direct input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is described.

[0016] Figure 5 An example ECC module supporting a direct input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is described.

[0017] Figure 6 Example redundant ECC circuits and enabling circuitry supporting a direct input redundancy scheme utilizing dedicated ECC circuits according to various embodiments of the present disclosure are described.

[0018] Figure 7 An example Hamming matrix supporting a direct-input redundancy scheme utilizing an adaptive syndrome decoder circuit is illustrated in accordance with various embodiments of the present disclosure.

[0019] Figure 8An example ECC module supporting a direct-input redundancy scheme utilizing adaptive syndrome decoder circuitry according to various embodiments of the present disclosure is described.

[0020] Fig. 9 An example redundant ECC circuit supporting a direct-input redundancy scheme utilizing adaptive decoder circuitry according to various embodiments of the present disclosure is described.

[0021] Fig.10 An example error correction module supporting a direct-input redundancy scheme utilizing adaptive decoder circuitry according to various embodiments of the present disclosure is described.

[0022] Fig.11 A block diagram illustrating a memory array supporting a direct-input redundancy scheme utilizing adaptive decoder circuitry in accordance with various embodiments of the present disclosure.

[0023] Fig.12 A system supporting a direct-input redundancy scheme utilizing adaptive decoder circuitry in accordance with various embodiments of the present disclosure is described.

[0024] Fig.13 and 14 One or more methods for utilizing a direct-input redundancy scheme for adaptive decoder circuitry according to various embodiments of the present disclosure are described. DETAILED DESCRIPTION

[0025] A memory device may increase the reliability of stored data bits by performing error correction on the data bits during a retrieval operation, for example, using error correction codes (ECC). In some cases, a memory device may further increase reliability by replacing some of the data bits with replacement bits, which may be referred to as redundant data bits. For example, a device may replace data bits from one of the data planes involved in a read operation with redundant data bits stored at a redundant data plane. However, the error correction circuitry that transfers the redundant data to the replacement data plane may increase the latency of the error correction operation, which may be proportional to the length of the data path along which the redundant data travels to the error correction circuitry.

[0026] According to the first technology described herein, a memory device can reduce the length of a data path and thus reduce propagation delay by directly inputting redundant data bits into an error correction circuit dedicated to a redundant data plane. The error correction circuit can be coupled with an adaptive enabling circuit system that can selectively transmit the output of the error correction circuit to other error correction components based on the data plane replaced by the redundant data. For example, when the redundant data is used for the xth data plane, the enabling circuit system can transmit the output of the error correction circuit to one combination of error correction components, but when the redundant data is used for the yth data plane, the enabling circuit system can transmit the output of the error correction circuit to a different combination of error correction components. Therefore, even if the redundant data is directly passed to the error correction circuit of the redundant data plane (rather than the error correction circuit of the replaced data plane), the error correction component can operate without interference.

[0027] Features of the first technique are further described herein in the context of a memory system. Specific examples of apparatus and methods for inputting redundant data directly into an error correction circuit dedicated to redundant data are described. These and other features of the present disclosure are further illustrated and described with reference to apparatus diagrams, system diagrams, and flow charts related to generating syndrome bits for codewords containing redundant data.

[0028] According to the second technology described herein, a memory device can reduce the length of a data path, and thus reduce propagation delay, by directly inputting redundant data bits into an error correction circuit system dedicated to a redundant data plane. The error correction circuit system for redundant data can perform operations on redundant data that contribute to the generation of syndrome bits for the read data bits. Once the syndrome bits are generated, the device can decode the syndrome bits using an adaptive syndrome decoder. The syndrome decoder can be adaptive because it selectively reacts to inputs based on the type of data being decoded (e.g., redundant data versus regular data). For example, when the data being decoded is redundant data, the syndrome decoder can react to a first set of inputs, but can substantially ignore a second set of inputs. The output of the syndrome decoder can indicate to the bit flip circuit whether a data bit (e.g., a regular data bit or a redundant data bit) is incorrect and should be flipped (e.g., inverted).

[0029] Features of the second technique are further described herein in the context of a memory system. Specific examples of apparatus and methods for directly inputting redundant data into an error correction circuit system are described. These and other features of the present disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flow charts relating to an adaptive syndrome decoder.

[0030] Figure 1An example memory array 100 supporting a direct input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is illustrated. The memory array 100 may be used to store digital information (e.g., binary information) and may also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 is programmable to store two states represented as a logic 0 and a logic 1. In some cases, the memory cells 105 are configured to store more than two logic states.

[0031] The memory cell 105 may include a memory element having a programmable state. The memory cell 105 in a DRAM or FeRAM architecture may store a charge representing a programmable state in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. The DRAM architecture may typically use this design and may use a capacitor comprising a dielectric material and having a linear electrical polarization property as a memory element. The FeRAM architecture may also use this design, but the capacitor used as the memory element may include a ferroelectric material having a nonlinear polarization property. The memory cell 105 in a PCM architecture may change the resistivity (e.g., resistance or threshold voltage) of the material, where different resistivities may represent different logic states. The PCM architecture may use a chalcogenide material having an electrically programmable resistance as a memory element.

[0032] Operations such as reading and writing can be performed on the memory cell 105 by activating or selecting the appropriate access line 110 and digit line 115. The access line 110 may also be referred to as a word line 110, and the digit line 115 may also be referred to as a bit line 115. Activating or selecting a word line 110 or a digit line 115 may include applying a voltage to the corresponding line. The word line 110 and the digit line 115 are made of conductive materials. For example, the word line 110 and the digit line 115 may be made of metal (e.g., copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, etc. According to Figure 1 1, each row of memory cells 105 is connected to a single word line 110, and each column of memory cells 105 is connected to a single digit line 115. By activating one word line 110 and one digit line 115 (e.g., applying a voltage to the word line 110 or the digit line 115), a single memory cell 105 can be accessed at their intersection. Accessing a memory cell 105 can include reading or writing the memory cell 105. The intersection of a word line 110 and a digit line 115 can be referred to as the address of the memory cell.

[0033] In some architectures, the logical storage device of a cell (e.g., a capacitor) can be electrically isolated from a digit line by a selection component. A word line 110 can be connected to and can control the selection component. For example, the selection component can be a transistor, and the word line 110 can be connected to the gate of the transistor. Activating the word line 110 results in an electrical connection or closed circuit between the capacitor of the memory cell 105 and its corresponding digit line 115. The digit line can then be accessed to read or write to the memory cell 105.

[0034] Access to memory cells 105 may be controlled by row decoders 120 and column decoders 130. In some examples, row decoders 120 receive row addresses from memory controller 140 and activate appropriate word lines 110 based on the received row addresses. Similarly, column decoders 130 receive column addresses from memory controller 140 and activate appropriate digit lines 115. For example, memory array 100 may include a plurality of word lines 110 labeled WL_1 to WL_M, and a plurality of digit lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by activating a word line 110 and a digit line 115, such as WL_3 and DL_N, a memory cell 105 at their intersection may be accessed.

[0035] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, after accessing the memory cell 105, the capacitor of the memory cell 105 can be discharged onto its corresponding digit line 115. Discharging the capacitor can be based on biasing or applying a voltage to the capacitor. The discharge can induce a change in the voltage of the digit line 115, which the sensing component 125 can compare to a reference voltage (not shown) in order to determine the stored state of the memory cell 105. For example, if the digit line 115 has a higher voltage than the reference voltage, the sensing component 125 can determine that the stored state in the memory cell 105 is a logic 1, and vice versa.

[0036] The reliability of the sensing operation may depend on the sensing window produced by reading the memory cell 105. For example, a larger sensing window may be associated with fewer bit errors than a smaller sensing window. The sensing window may be determined as the difference between the voltage of the digit line 115 caused by reading the memory cell 105 when storing a logic 1 and the voltage of the digit line 115 caused by reading the memory cell 105 when storing a logic 0. The sensing component 125 may include various transistors or amplifiers in order to detect and amplify the difference in the signal, which may be referred to as latching. The detected logic state of the memory cell 105 may then be output as output 135 by the column decoder 130.

[0037] Memory cells 105 may be set or written to by activating associated word lines 110 and digit lines 115. As discussed herein, activating a word line 110 electrically connects the corresponding memory cell row 105 to its corresponding digit line 115. By controlling the associated digit line 115 when the word line 110 is activated, the memory cell 105 may be written to, i.e., a logical value may be stored in the memory cell 105. In some cases, a memory array 100 storing a data bit corresponding to a logical value at a first memory cell 105 may store another data bit corresponding to a logical state at another memory cell 105 (e.g., for reliability purposes). The data bit stored at the second memory cell 105 may be referred to as a redundant data bit. Column decoder 130 may accept data to be written to the memory cell 105, such as input 135.

[0038] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, etc.) of the memory cells 105 through various components such as the row decoder 120, the column decoder 130, and the sensing components 125. The memory controller 140 may generate row and column address signals in order to activate the desired word lines 110 and digit lines 115. The memory controller 140 may also generate and control various voltage potentials used during the operation of the memory array 100. In general, the amplitude, shape, or duration of the applied voltages discussed herein may be adjusted or varied and may be different for the various operations used to operate the memory array 100. Furthermore, one, multiple, or all memory cells 105 within the memory array 100 may be accessed simultaneously; for example, multiple or all cells of the memory array 100 may be accessed simultaneously during a reset operation, wherein all memory cells 105 or groups of memory cells 105 are set to a single logical state.

[0039] In some cases, the memory array 100 may be partitioned into sets of memory cells. For example, the memory array 100 may be partitioned into memory segments referred to as data planes, at least some of which may include multiple memory cells 105. The data planes may be configured so that different groups of data planes may be accessed by different word lines 110. For example, a group of data planes may be accessed by the same word lines 110, which may also be shared with redundant data planes configured to store redundant data bits corresponding to data bits stored by the data planes (e.g., the redundant data bits may be based on the same logical state as the data bits stored at the data planes). The digit lines 115 of the memory cells in each data plane may be coupled with corresponding error correction circuitry (e.g., an error correction code (ECC) module).

[0040] Before storing the data in a set of data planes, the memory array 100 may generate a certain amount of parity bits for the data for error correction purposes. The parity bits may be based on the data to be stored (e.g., as defined by an error correction code (e.g., a Hamming code)). Once one or more parity bits are generated, they may be appended to the original data bits and stored in the set of data planes along with the original data bits. The combination of the original data bits and the appended parity bits may be referred to herein as a codeword. In some cases, some of the original data bits that are intended to be stored at the respective data planes may also be stored at the redundant data planes. For example, a device having x logical states for storage may store data bits corresponding to those x logical states not only in memory cells of the data planes, but also in memory cells of the redundant data planes.

[0041] When reading a codeword, but before error correction, the set of redundant data bits can replace a set of original bits in a process called redundancy repair. Redundancy repair can increase the reliability of the codeword, but also increase the latency of the read operation, especially when the propagation path of the redundant data is long.

[0042] In some examples, information stored in the memory array 100 (e.g., one or more codewords) may be requested by another device (e.g., a memory component such as a buffer or an external processor). Upon receiving the request for information, the memory array 100 may identify the location of the information within the memory array 100 (e.g., the memory array 100 may identify the location of the one or more codewords within one or more sets of data planes). For example, the memory array 100 may determine that the information is located within a set of memory cells that are located within a particular set of data planes. The memory array 100 may access the set of data planes via associated word lines 110 so that the data bits stored by the memory cells and the corresponding parity bits are output on the corresponding digital lines 115.

[0043] However, before providing the information to the requesting device, the memory array 100 may first process the information, performing redundancy repair and error correction for the information bits stored in the set of memory planes. For example, after replacing a portion of the original data bits with redundant bits, the memory array 100 may determine whether any of the bits are erroneous (e.g., inverted as compared to the original stored state), and flip the incorrect bit to return it to the stored state expected by the requesting device.

[0044] During error correction (e.g., during an error correction operation), the memory array 100 may generate syndrome bits that can be used to detect errors in the read data bits and identify the locations of those errors. For example, the syndrome bits for a codeword may be compared to the parity bits for the codeword to determine whether the codeword contains errors. If no errors are detected (e.g., if the syndrome bits match the parity bits), the data bits may be passed to the requesting device without error correction (e.g., without inverting any of the bits). However, if errors are detected (e.g., if the syndrome bits do not match the parity bits), the memory array 100 may decode the syndrome bits to identify the locations of the errors within the codeword so that the errors may be corrected (e.g., inverted) before the codeword is transmitted to the requesting device.

[0045] To perform error correction, data bits from each data plane involved in the read operation may be input into a corresponding error correction circuit, which may be positioned near the data plane. When redundant repair is used for bits in a data plane, the redundant data bits, rather than the original data bits, may be input into the error correction circuit for the data plane (or at least undergo an operation comparable to that performed by the error correction circuit for the data plane). However, delivering the redundant bits to the appropriate error correction circuit (e.g., the error correction circuit for the data plane to be replaced) may be associated with a propagation delay, for example, due to the propagation path from the redundant data plane to the error correction circuit. According to the techniques described herein, the propagation path of the redundant data may be shortened compared to other architectures by inputting the redundant data into an additional error correction circuit positioned near the redundant data plane. The additional error correction circuit may replicate the output of the error correction circuit for the data plane to be replaced, thereby ensuring that the error correction operation is not disturbed.

[0046] Figure 2 An example of a memory architecture 200 supporting a direct input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure is illustrated. The memory architecture 200 may support a column redundancy scheme in which redundant data for a data plane is stored at a separate data plane (or "column") reserved for redundant data. For example, in a column redundancy scheme, redundant data corresponding to data in data plane 0 may be stored at redundant data plane 205.

[0047] The redundant data plane 205 may include multiple memory cells and may have the ability to store redundant data for (e.g., corresponding to) multiple data planes. For example, the redundant data plane 205 may be part of a global column redundancy architecture, wherein the redundant data plane 205 is configured to store redundant data for any or all of the data planes accessed by the same word line as the redundant data plane 205. A data plane that does not store redundant data may be referred to herein as a regular data plane or a non-redundant data plane. The redundant data may be data representing a logical state that serves as a basis for data bits stored in a regular data plane. Thus, when the data bits in the regular data plane are not damaged, the redundant data bits corresponding to those data bits may be the same as those data bits. However, if the data bits in the regular data plane are damaged, the redundant data bits corresponding to those data bits may include one or more different data bits.

[0048] Memory architecture 200 may include multiple conventional data planes (e.g., data plane 0 to data plane 15), each of which is configured to store data bits and each of which is coupled to a common word line (e.g., word line 210). Thus, non-redundant data planes may be accessed with or selected by the same word line. Word line 210 may also be coupled to redundant data plane 205 and parity data plane 215. Parity data plane 215 may be configured to store parity bits of a codeword whose data bits are stored by the conventional data planes. Alternatively, the parity bits may be stored in one or more of the conventional data planes. Although shown as having sixteen conventional data planes, the redundancy repair and error correction techniques described herein may be implemented using any number of conventional data planes.

[0049] At least some, if not each, of the regular data planes, the redundant data plane 205, and the parity data plane 215 may include one or more digital lines for outputting the stored logic states as signals. The signals may pass through one or more processing components, such as sense amplifiers, before being passed to a data selector as data bits. The data selector may select between regular data and redundant data for ECC operations. When the data selector selects redundant data, the redundant data bits corresponding to the regular data bits may be used to replace those regular data bits for ECC operations.

[0050] In some examples, the data selector can select regular data for ECC operation by establishing a conductive path between the ECC circuit and the digital line from the regular data plane. Alternatively, the data selector can select redundant data for ECC operation by establishing a conductive path between the ECC circuit and the digital line from the redundant data plane 205. The data selector can establish a conductive path by activating and deactivating one or more switching components such as transistors. Therefore, the memory architecture 200 can include a certain number of digital lines, at least some of which can be coupled to corresponding data planes and corresponding ECC circuits. In addition, the memory architecture 200 can include one or more digital lines coupled to the redundant data plane 205 and the redundant ECC circuit 235.

[0051] In some cases, each conventional data plane may be associated with a corresponding ECC circuit. For example, there may be a one-to-one correspondence between the ECC circuit and the conventional data plane. Therefore, the memory architecture 200 may include multiple ECC circuits, each of which is configured to receive data from a corresponding conventional data plane. For example, ECC circuit 0 may receive data from data plane 0 via data selector 0, ECC circuit 1 may receive data from data plane 1 via data selector 1, and so on. Each ECC circuit may be designed to operate on data bits from its corresponding data plane, for example, defined by a Hamming matrix. Therefore, different ECC circuits may be used for different conventional data planes.

[0052] As described above, the conventional data planes may be used to store information, such as codewords (or data portions of codewords). In such cases, the parity data plane 215 may store parity bits for the codewords (or the parity bits may be distributed among the memory cells of one or more conventional data planes). For example, each of the conventional data planes may store a portion (e.g., eight bits) of the requested data (e.g., a total of 128 bits), and the parity data plane 215 may store the corresponding parity bits (e.g., eight parity bits). In some cases, an uncorrupted version of the codeword data may be stored in the redundant data plane 205 as redundant data. For example, the redundant data plane 205 may store eight redundant bits corresponding to eight logical values ​​represented (or expected to be represented) by the eight data bits stored in the data plane 0. Thus, the redundant data plane 205 may be configured to store redundant data that is the same as (or expected to be the same as) the data stored at the conventional data plane 0. When one or more bits of the regular data are corrupted (eg, during a corresponding write operation or between a write operation and a read operation), a deviation between the regular data and the corresponding redundant data may occur.

[0053] When the stored information is requested by another device or component, the memory architecture 200 may perform a retrieval operation that involves reading the memory cells storing the information, performing ECC operations on the read data, correcting errors in the read data, and transferring the corrected data to the output bus 230 for transfer to the requesting device. To begin the retrieval operation, the requested information may be passed from the regular plane (e.g., as a certain amount of data bits) to the data selector. However, if redundancy repair is in play (e.g., if one of the regular data planes is selected for redundancy repair), the redundant data from the redundant data plane 205 must be passed to the data selector corresponding to that data plane so that the redundant data (rather than the replaced regular data) is subjected to the ECC operation.

[0054] But passing redundant data from redundant data plane 205 to the appropriate data selector (or ECC circuit) can increase the latency of the system because the travel time of the redundant data can be proportional to the length of the propagation path between the redundant data plane and the data selector. For example, when redundant data replaces data from conventional data plane 0, the latency of the system can increase (compared to a non-redundant repair) because the redundant data travels along propagation path 225-a, which in some cases can be as high as 1 mm or more. In some cases, because error correction cannot occur until all relevant data has undergone the ECC operation, any delay in providing data to the ECC circuit can cause a delay in the retrieval operation.

[0055] According to the techniques described herein, the latency of a retrieval operation can be reduced by directly inputting redundant data into an ECC circuit corresponding to the redundant data plane 205. The ECC circuit corresponding to the redundant data plane 205 can be referred to as a redundant ECC circuit 235, and the redundant ECC circuit 235 can be configured to receive redundant data from the redundant data plane 205. Thus, each data plane, conventional or unconventional, can have a corresponding ECC circuit. When the redundant data is transmitted to the ECC module 220, the redundant data can follow a propagation path 225-b, which can be shorter than the propagation path 225-a. Thus, the latency associated with transmitting the redundant data to the ECC module can be reduced.

[0056] In a first embodiment, redundant ECC circuit 235 may be coupled to an enabling circuit system that selectively transmits the output of redundant ECC circuit 235 to certain components of ECC circuit system 245. The components to which the output is transmitted may be based on the data plane replaced by the redundant data. Figure 6 , describing the relationship of redundant ECC circuit 235 to the enabling circuitry in additional detail.

[0057] In a second embodiment, redundant ECC circuit 235 may be coupled with an adaptive syndrome decoder. The syndrome decoder may be adaptive in that it may consider certain inputs (eg, and ignore other inputs) when decoding the syndrome bits of a codeword. Fig.10 The adaptive syndrome decoder is described in additional detail and reference is made to Fig. 9 An ECC circuit coupled to a syndrome decoder is described in additional detail.

[0058] A retrieval operation using redundant ECC circuit 235 is now described. For purposes of illustration, the retrieval operation is described with reference to a codeword comprising 128 data bits and eight parity bits. However, the techniques described herein may be implemented for codewords of any length.

[0059] During a write operation, the data of the codeword may have been distributed across the regular data planes. For example, each of the regular data planes may have been used to store eight bits of the codeword (yielding 128 bits stored by sixteen regular data planes). Eight parity bits may have been stored at parity data plane 215, and eight bits stored (or expected to be stored) at data plane 0 may have been stored as redundant data at redundant data plane 205.

[0060] During the retrieval process, each of the data planes (e.g., data planes 0 to 15) may be selected (e.g., using word lines 210) and read. Thus, eight data bits may be transferred from data plane 0 (e.g., via eight digit lines) to data selector 0, eight bits may be transferred from data plane 1 to data selector 1, and so on. Each of the data selectors (except data selector 0) may establish a conductive path between the digit lines and the corresponding ECC circuit so that data from each plane is input into the respective ECC circuit. However, instead of transferring data bits from data plane 0, data selector 0 may transfer null data bits (e.g., all zeros) so that the operation of ECC module 220 is not impaired (because data plane 0 has been selected for redundancy repair). Copies of the data bits input into ECC module 220 (except for the null data bits output by data selector 0) may also be transferred to error correction module 240.

[0061] For the eight redundant data bits stored by redundant data plane 205, these bits may be transferred directly to redundant ECC circuit 235 (e.g., as a replacement for the eight bits of data plane 0). A copy of the redundant data bits may also be transferred to error correction module 240 (e.g., via data selector 0 or some other component). Thus, all of the data bits that make up the requested codeword may be present for correction at error correction module 240.

[0062] The ECC circuit can perform initial ECC operations on the data bits received from the data plane, such as reference Figure 4 and 7 Furthermore, the redundant ECC circuit 235 may perform an initial ECC operation on the redundant data received from the redundant data plane 205, as shown in FIG. Figure 5 and 8 245 for further processing (e.g., additional ECC operations). The output of ECC module 220 may be a certain amount of syndrome bits that may be used for error correction. In some cases, the syndrome bits are derived from a bitwise operation (e.g., an exclusive-or operation) performed on the parity bits and the bits output from ECC circuitry 245.

[0063] After the syndrome bits are generated by the ECC module 220, they can be compared to the parity bits to determine whether there is an error in the corresponding codeword. For example, if the syndrome bits do not match the parity bits, an error can be detected. If an error is detected, the syndrome bits can be decoded (e.g., by a syndrome decoder included in the error correction module 240) to determine the location of the error. Once the location of the error is determined, the erroneous bits can be inverted (e.g., by a bit flipping circuit included in the error correction module 240) to correct the error. After error correction has been performed, the codeword can be transmitted to other components or devices via the output bus 230.

[0064] Figure 3 An example Hamming matrix 300 is illustrated that supports a direct input redundancy scheme utilizing a dedicated ECC circuit according to various embodiments of the present disclosure. The Hamming matrix 300 may represent a (136, 128) Hamming code corresponding to 128 data bits, eight parity bits, and 136 total bits. The Hamming matrix 300 may be compared to, for example, a reference Figure 2 Although described with reference to (136, 128) Hamming codes, any type of error correction code may be used to implement the techniques described herein.

[0065] Hamming matrix 300 may illustrate the relationship between parity bits, syndrome bits, and data bits across multiple data planes, e.g., sixteen data planes spanning from data plane 0 to data plane 15. For example, Hamming matrix 300 may show how parity bits of a codeword encompass data from different data planes and how corresponding syndrome bits may be generated from the data in those data planes.

[0066] The Hamming matrix 300 can be used to detect errors in codewords, as well as indicate the location of the errors. For example, if the syndrome bits generated for the codeword do not match the parity bits of the codeword, the mismatch can indicate that the codeword contains an error. However, in order to locate the error, the device must know the data plane and bit storing the error. In order to determine the location of the error at the bit level within a particular data plane, the syndrome bits can be effectively compared to the syndrome pattern that makes up each column of the Hamming matrix 300. The syndrome pattern that matches the syndrome bits can indicate the data plane (via syndrome bits S3 to S7) and the bit position (via syndrome bits S0 to S2) storing the error. For example, if the generated syndrome bits match the syndrome pattern 320, the device can determine that the error is in data bit D1 (indicated by syndrome bits S0 to S2) in data plane 0 (indicated by syndrome bits S3 to S7).

[0067] Hamming matrix 300 may include a common matrix pattern 305 and a different matrix pattern 310. Common matrix pattern 305 shows data bits covered by parity bits P0, P1, and P2. For example, as shown in Hamming matrix 300, parity bit P0 covers (e.g., is based on) data bits D1, D3, D5, and D7 of all data planes, parity bit P1 covers data bits D2, D3, D6, and D7 of all data planes, and parity bit P2 covers data bits D4, D5, D6, and D7 of all data planes.

[0068] Common matrix pattern 305 also shows the data bits used to generate syndrome bits S0, S1, and S2 (which together indicate the location of the error at the bit level). Common matrix pattern 305 is called "common" because it is the same for each data plane (because each data plane stores eight data bits, in this example, only three bits are needed to indicate which of the eight bits is an error). According to Hamming matrix 300, syndrome bit S0 can be generated by XORing data bits D1, D3, D5, and D7 from all data planes, syndrome bit S1 can be generated by XORing data bits D2, D3, D6, and D7 from all data planes, and syndrome bit S2 can be generated by XORing data bits D4, D5, D6, and D7 from all data planes.

[0069] Different matrix patterns 310 show data bits covered by parity check bits P3, P4, P5, P6, and P7. For example, according to the Hamming matrix 300, check bit P3 covers (e.g., based on) all data bits in data planes 0, 2, 5, 6, 8, 11, 12, and 15, check bit P4 covers all data bits in data planes 0, 3, 4, 6, 9, 10, 12, and 15, check bit P5 covers all data bits in data planes 1, 2, 4, 6, 9, 11, 13, and 14, check bit P6 covers all data bits in data planes 1, 3, 5, 7, 8, 10, 12, and 14, and check bit P7 covers all data bits in data planes 1, 3, 5, 7, 9, 11, 13, and 15.

[0070] The different matrix patterns also show the data bits used to generate the syndrome bits S3, S4, S5, S6, and S7. The different matrix patterns 310 are called "different" because the matrix for each data plane is different or unique. For example, the syndrome matrix for data plane 0 is different from the syndrome matrices for all other data planes. This is because the syndrome bits S3 to S7 indicate the data planes storing errors. For example, syndrome pattern 11000 of S3 to S7 may indicate data plane 0 storing errors, while syndrome pattern 11001 of S3 to S7 may indicate data plane 15 storing errors. According to the Hamming matrix 300, syndrome bit S3 may be generated by performing an XOR operation on all data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15, syndrome bit S4 may be generated by performing an XOR operation on all data bits from data planes 0, 3, 4, 6, 9, 10, 12, and 15, syndrome bit S5 may be generated by performing an XOR operation on all data bits from data planes 1, 3, 5, 7, 8, 10, 12, and 14, and syndrome bit S7 may be generated by performing an XOR operation on all data bits from data planes 1, 3, 5, 7, 9, 11, 13, and 15.

[0071] For ease of illustration, the Hamming matrix 300 is presented in a compressed form. However, it should be understood that a different syndrome matrix for each data plane can be expanded, as shown in the partial enlarged view 315-a of data plane 0. Similarly, a complete syndrome matrix for a data plane can be expanded, as shown in the complete enlarged view 315-b of data plane 0.

[0072] Figure 4 An example ECC module 400 is illustrated that supports a direct input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure. The ECC module 400 may be a reference Figure 24. The ECC module 400 is an example of an ECC module described herein. The ECC module 400 may be configured to generate and output a set of syndrome bits for a codeword that includes data bits from multiple data planes, such as data planes 0 to 15. The ECC module 400 may perform the operations described using any combination of logic gates, such as OR, XOR, NOR, NAND, AND, NOT, and XNOR logic gates.

[0073] ECC module 400 may include multiple ECC circuits (e.g., one ECC for each data plane participating in the retrieval operation). For example, ECC module 400 may include sixteen ECC circuits, such as ECC circuits 0 through 15. ECC module 400 may also include: ECC circuit system 405, which may be a reference Figure 2 and redundant ECC circuit 420, which may be referenced Figure 2 An example of redundant ECC circuit 235 is described.

[0074] Each ECC circuit may be configured to perform one or more bitwise operations on a set of data. A bitwise operation may be an operation that operates on one or more bit patterns at the bit level to return a one-bit result. For example, each ECC circuit may include a certain number of logic gates, such as XOR logic gates, that receive one or more bits as input and output a single bit.

[0075] Thus, each ECC circuit may be configured to perform a bitwise operation on data from a corresponding data plane. For example, ECC circuit 0 may be configured to perform a bitwise operation on data from data plane 0 (e.g., eight data bits). Thus, ECC circuit 0 may include a certain amount of logic gates (or "bitwise operators"). The logic gates may operate on the data bits to output the results of one or more XOR operations to logic level 410. For example, ECC circuit 0 may output the results of an XOR operation on data bits D1, D3, D5, D7 of data plane 0. The results of the XOR operation on data bits Dx, Dy, Dt, and Dz may be represented herein as and referred to as Dxytz. Thus, the results of the operation performed by the ECC circuit on data bits D1, D3, D5, and D7 may be represented as and referred to as D1357. Similarly, ECC circuit 0 may output D2367, D4567, and D_ALL (which refers to the results of the XOR operation on all data bits D0 to D8).

[0076] Other ECC circuits may also be configured to output results similar to the XOR operation of ECC circuit 0. For example, all ECC circuits may be configured to output D1357, D2367, D4567, and D_ALL of their respective data bits. The ECC circuits may transmit D1357, D2367, D4567, and D_ALL to logic level 410. Thus, as indicated by Hamming matrix 300, each ECC circuit may transmit its respective D1357 to S0 circuitry (“S0 Cir.”), D2367 to S1 circuitry (“S1 Cir”), and D4567 to S2 circuitry (“S2 Cir.”).

[0077] The S0 circuit system may operate on its inputs to obtain the results of an XOR operation on those inputs. Thus, the S0 circuit system may effectively output the results of an XOR operation on data bits D1, D3, D5, D7 from each of the data planes (referred to as D1357_ALL). Similarly, the S1 circuit system may operate on its inputs to obtain the results of an XOR operation on those inputs. Thus, the S1 circuit system may effectively output the results of an XOR operation on data bits D2, D3, D6, D7 from each of the data planes (referred to as D1357_ALL). Similarly, the S2 circuit system may operate on its inputs to obtain the results of an XOR operation on those inputs. Thus, the S2 circuit system may effectively output the results of an XOR operation on data bits D4, D5, D6, D7 from each of the data planes (referred to as D4567_ALL). The outputs of the S0 circuit system, the S1 circuit system, and the S2 circuit system may be transmitted to the logic level 415 for additional operations.

[0078] Although each ECC circuit may output its respective D_ALL to logic stage 410, the D_ALL of each ECC circuit may be directed only to certain components of logic stage 410. For example, only ECC circuits 0, 2, 5, 6, 8, 11, 12, and 15 may communicate their respective D_ALL to S3 circuitry, as indicated by Hamming matrix 300. This is because syndrome bits S3 are based on all data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15. Similarly, only ECC circuits 0, 3, 4, 6, 9, 10, 12, and 15 may communicate their respective D_ALLs to S4 circuitry, only ECC circuits 1, 2, 4, 6, 9, 11, 13, and 14 may communicate their respective D_ALLs to D5 circuitry, only ECC circuits 1, 3, 5, 7, 8, 10, 12, and 14 may communicate their respective D_ALLs to S6 circuitry, and only ECC circuits 1, 3, 5, 7, 9, 11, 13, and 15 may communicate their respective D_ALLs to S7 circuitry. Thus, logic stage 410 may communicate the result of an XOR operation on all data from a selected data plane (referred to as D_ALL_Select) to logic stage 415.

[0079] The redundant ECC circuit 420 may be configured to receive the corresponding redundant data plane (eg, reference Figure 2 The redundant data plane 205 described above receives redundant data (e.g., eight bits of redundant data). The redundant ECC circuit 420 may perform a bit-by-bit operation on the redundant data to effectively obtain the result of an XOR operation on the redundant data. For example, the redundant ECC circuit 420 may perform a bit-by-bit operation on the redundant data to obtain the result of an XOR operation on the redundant data bits RD1, RD3, RD5, and RD7 (expressed as RD1357). The redundant ECC circuit 420 may also obtain the result of an XOR operation on the redundant data bits RD2, RD3, RD6, and RD7 (expressed as RD2367), and the result of an XOR operation on the redundant data bits RD4, RD5, RD6, and RD7 (expressed as RD4567). In addition, the redundant ECC circuit 420 may obtain the result of an XOR operation on all redundant data bits (expressed as RD_ALL).

[0080] Redundant ECC circuit 420 may transmit RD1357, RD2367, and RD4567 to corresponding circuitry in logic stage 415 to generate syndrome bits S0, S1, and S2. For example, redundant ECC circuit 420 may transmit RD1357 to logic stage 415 via conductive path 425-a, may transmit RD2367 to logic stage 415 via conductive path 425-b, and may transmit RD4567 to logic stage 415 via conductive path 425-c. Redundant ECC circuit 420 may transmit RD1357, RD2367, and RD4567 regardless of which data plane is selected for redundant repair (because S0, S1, and S2 are based on selected data bits from all data planes).

[0081] However, the redundant ECC circuit 420 may selectively transmit RD_ALL to a subset of components (e.g., logic gates) in the logic stage 415 based on which data plane is selected for redundant repair. This is because only certain syndrome bits are based on data of a given data plane. For example, as indicated by the Hamming matrix 300, syndrome bit S3 is based on data in data planes 0, 2, 5, 6, 8, 11, 12, and 15, but not based on data from data planes 1, 3, 4, 7, 9, 10, 13, and 14. Therefore, if data plane 1 is selected for redundant repair, the redundant ECC circuit 420 may not pass RD_ALL to the component responsible for generating S3 because S3 does not depend on data from data plane 1 (which has been replaced by redundant data). Therefore, the redundant ECC circuit 420 may selectively transmit RD_ALL (e.g., the result of a bitwise operation on the redundant data) to the logic stage 415 through the conductive path 425-d, which may be a conductive path between the output of the redundant ECC circuit 420 and the logic stage 415.

[0082] Logic stage 415 may receive the output from logic stage 410 and redundant ECC circuit 420 and generate syndrome bits for the codeword. The syndrome bits may be generated according to Hamming matrix 300. The syndrome bits may be used in subsequent error correction operations to correct errors in the codeword.

[0083] Figure 5 An example ECC module 500 is illustrated that supports a direct input redundancy scheme utilizing dedicated ECC circuitry according to various embodiments of the present disclosure. The ECC module 500 may be a reference Figure 2 and 4 An example of an ECC module is described. The ECC module 500 may be configured to generate and output a set of syndrome bits for a codeword that includes data bits from multiple data planes (eg, data planes 0-15).

[0084] The ECC module 500 may include as reference Figure 2 and4 1 and 2. The ECC module 500 may also include an ECC circuit system 505 and a redundant ECC circuit 520, which may be as described in reference to FIG. Figure 2 and 4 Although described with reference to XOR gates, the functionality of the ECC circuitry and ECC circuitry 505 may be implemented using any type and combination of logic gates.

[0085] In this example, each ECC circuit may receive a certain amount of data bits from its respective data plane and perform a bit-by-bit operation on the amount of data bits before outputting a single resulting bit to the ECC circuitry 505. Since the syndrome bits for the (136, 128) Hamming code are derived from XORing various combinations of the data bits in the codeword, the ECC circuits may perform XOR operations on their respective data bits. For example, ECC circuit n may include a certain amount of XOR logic gates configured to perform XOR operations on the data bits received from data plane n. The XOR operation may include performing an XOR operation on data bits D1, D3, D5, and D7 (from data plane n) using a first logic gate, performing an XOR operation on data bits D2, D3, D6, and D7 (from data plane n) using a second logic gate, performing an XOR operation on data bits D4, D5, D6, and D7 (from data plane n) using a third logic gate, and performing an XOR operation on data bits D0, D1, D2, and D3 (from data plane n) using a fourth logic gate. The ECC circuit n may also include an additional (e.g., fifth) logic gate configured to perform an XOR operation on the results of the XOR operations performed by the third and fourth logic gates.

[0086] Thus, as an example, ECC circuit 0 for data plane 0 may XOR data bits D1, D3, D5, and D7 (from data plane 0) using logic gate 515-a, XOR data bits D2, D3, D6, and D7 (from data plane 0) using logic gate 515-b, XOR data bits D4, D5, D6, and D7 (from data plane 0) using logic gate 515-c, and XOR data bits D0, D1, D2, and D3 (from data plane 0) using logic gate 515-d. ECC circuit 0 may also XOR the results of the XOR operations of logic gates 515-c and 515-d using logic gate 515-e to effectively obtain the result of a single XOR operation on all data bits from data plane 0. Therefore, the output of logic gate 515-a may be D1357, the output of logic gate 515-b may be D2367, the output of logic gate 515-c may be D4567, the output of logic gate 515-d may be D0123, and the output of logic gate 515-e may be D_ALL.

[0087] The results of the XOR operations performed by the different ECC circuits may be input into additional logic gates (e.g., included in logic state 510) to effectively obtain the result of a single XOR operation on those data bits. For example, according to Hamming matrix 300, data bits D1, D3, D5, and D7 from each data plane may be effectively XORed by logic gate 515-f. This is because the result of each XOR operation on the selected data bits (D1, D3, D5, D7) of each data plane may be input into logic gate 515-f. For example, D1357 for each data plane 0 through 15 may be input into logic gate 515-f.

[0088] Regardless of the exact inputs, the output of logic gate 515-f may be the result of an XOR operation on data bits D1, D3, D5, and D7 from all data planes involved in the read operation. Similarly, the output of logic gate 515-g may be the result of an XOR operation on data bits D2, D3, D6, and D7 from all data planes involved in the read operation. And the output of logic gate 515-h may be the result of an XOR operation on data bits D4, D5, D6, and D7 from all data planes involved in the read operation. However, the data bits from the data planes may have been invalidated (e.g., set to zero) prior to insertion into the corresponding ECC circuit for the data plane selected for redundancy repair. For example, when data plane 0 is selected for redundancy repair, the data bits D0 to D7 inserted into ECC circuit 0 may be all zeros. This technique prevents the replaced data bits from interfering with the syndrome generation process.

[0089] Unlike logic gates 515-f to 515-h, logic gates 515-i to 515-u may not output the result of an XOR operation performed on selected data bits from all data planes. Instead, logic gates 515-i to 515-u may output the result of an XOR operation performed on all data bits from the selected data plane. For example, logic gate 515-i may actually perform an XOR operation on all data from data planes 0, 2, 5, 6, 8, 11, 12, and 15 (as specified by Hamming matrix 300). The result of this XOR operation may be represented as and referred to as D_ALL S3 because it represents the XOR of all relevant non-redundant data bits used to generate S3. However, as described above, the data from the replaced data plane (e.g., in this case, data plane 0) may be invalid (e.g., set to zero) prior to insertion into ECC module 500.

[0090] As reference Figure 4 As described, redundant ECC circuit 520 may also communicate signals to ECC circuit system 505 (e.g., to logic stage 525). For example, redundant ECC circuit 520 may communicate RD1 357 to logic gate 515-n, RD2 367 to logic gate 515-o, and RD4 567 to logic gate 515-p. Thus, the result of an XOR operation on redundant data bits D1, D3, D5, and D7 may be communicated to logic gate 515-n, the result of an XOR operation on redundant data bits D2, D3, D6, and D7 may be communicated to logic gate 515-o, and the result of an XOR operation on redundant data bits D4, D5, D6, and D7 may be communicated to logic gate 515-p.

[0091] The redundant ECC circuit 520 may also selectively transmit the XOR result of all redundant data bits to certain components of the logic stage 525. For example, when the data plane selected for redundant repair is one of the data planes on which the generation of the syndrome bit S3 is based, the redundant ECC circuit 520 may pass RD_ALL to the logic gate 515-q. When RD_ALL is passed to the logic gate 515-q, it may be represented as and referred to as RD_ALL_S3. Thus, when data plane 0 is selected for redundant repair, RD_ALL_S3 may be passed to the logic gate 515-q (because S3 is generated based on all data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15, and the redundant data represents data from data plane 0). However, if data plane 1 is selected for redundant repair, RD_ALL may not be passed to the logic gate 515-q (because S3 is generated based on all data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15, and the redundant data represents data from data plane 1).

[0092] In a similar manner, when the data plane selected for redundancy repair is one of the data planes on which the generation of syndrome bits S4 is based, RD_ALL may be passed to logic gate 515-r. When RD_ALL is passed to logic gate 515-r, it may be represented as and referred to as RD_ALL_S4. Thus, when data plane 0 is selected for redundancy repair, RD_ALL_S4 may be passed to logic gate 515-r (because S4 is generated based on all data bits from data planes 0, 3, 4, 5, 8, 9, 12, and 15, and the redundant data represents data from data plane 0). However, if data plane 1 is selected for redundancy repair, RD_ALL may not be passed to the logic gate (because S4 is generated based on all data bits from data planes 0, 3, 4, 5, 8, 9, 12, and 15, and the redundant data represents data from data plane 1). Thus, the result of the XOR operation on all redundant data bits may be passed from redundant ECC circuit 520 to ECC circuit system 505 based on the data plane selected for redundancy repair. To complete the example of data plane 0, none of RD_ALL_S5, RD_ALL_S6, or RD_ALL_S7 may be passed to the ECC circuitry 505 because none of these data planes are used to generate syndrome bits S5, S6, or S7 when data plane 0 is selected for redundancy repair.

[0093] Thus, logic gates 515-q to 515-u can each be described as a logic gate coupled to an ECC circuit and configured to receive the result of a bitwise operation on a data bit from a selected data plane. For a given logic gate, the result of the bitwise operation can be transmitted on a conductive path between the output of redundant ECC circuit 520 and the input of the logic gate. For example, as shown in FIG. Figure 4 As described, the result of the bitwise operation may be transmitted via conductive path 425-d. In some cases, another logic gate may be coupled to ECC circuit 520 and may form part of the conductive path. Figure 6 The depicted logic gate 620 may form part of a conductive path.

[0094] The logic gates in the logic level 525 may receive the result of the XOR operation on the regular data and the result of the XOR operation on the redundant data. Each logic gate in the logic level 525 may perform an XOR operation on its inputs to output a syndrome bit (or a bit that serves as the basis for the syndrome bit). For example, the logic gate 515-n may perform an XOR operation on D1357_ALL and RD1357 to obtain S0. Similarly, the logic gate 515-o may perform an XOR operation on D2367_ALL and RD2367 to obtain S1. And the logic gate 515-p may perform an XOR operation on D4567_ALL and RD4567 to obtain S2.

[0095] Other logic gates in logic level 525 may also perform XOR operations on their respective inputs, one of which may be passed through redundant ECC circuit 520 (see reference 524). Figure 6 515-s, 515-t, and 515-u may operate on null data bits (e.g., logical zeros) instead of operating on RD_ALL_S5, RD_ALL_S6, and RD_ALL_S7. This is because syndrome bits S5, S6, and S7 are not based on data from data plane 0. Therefore, logic gate 515-s may perform an XOR operation on D_ALL_S5 and a logical zero to obtain syndrome bit S5. Similarly, logic gate 515-t may perform an XOR operation on D_ALL_S6 and a logical zero to obtain syndrome bit S6. Furthermore, logic gate 515 - u may perform an XOR operation on D_ALL_S6 and logic zero to obtain syndrome bit S7 .

[0096] Figure 6 An example redundant ECC circuit 600 and enabling circuitry 605 are illustrated to support a direct input redundancy scheme utilizing a dedicated ECC circuit in accordance with various embodiments of the present disclosure. The redundant ECC circuit 600 may be a reference Figure 2 , 4 5. Thus, the redundant ECC circuit 600 can be coupled to the redundant data plane via digital lines and can be configured to perform an XOR operation on the redundant data received from the redundant data plane. In conjunction with the enabling circuit system 605, the redundant ECC circuit 600 can selectively transmit the result of the XOR operation on the redundant data to other components (e.g., to the reference circuit system). Figure 5 ECC circuit system 505 described).

[0097] Redundant ECC circuit 600 may include a certain number of logic gates configured to output RD1 357, RD2 367, RD4 567, and RD_ALL. However, RD_ALL may be appropriately passed to certain selection components of ECC circuitry 505. For example, when data plane 0 is selected for redundancy, RD_ALL may be appropriately passed to logic gates 515-q and 515-r, but not to logic gates 515-s through 515-u (because in some cases only syndrome bits S3 and S4 are based on data from data plane 0).

[0098] According to the techniques described herein, RD_ALL may be selectively passed or deasserted using enable circuitry 605. Enable circuitry 605 may include an enable circuit for each of the syndrome sub-bits S3 to S7. For example, enable circuitry 605 may include an S3 enable circuit for syndrome sub-bit S3, an S4 enable circuit for syndrome sub-bit S4, an S5 enable circuit for syndrome sub-bit S5, an S6 enable circuit for syndrome sub-bit S6, and an S7 enable circuit for syndrome sub-bit S7. Each enable circuit may be coupled to a corresponding one. For example, the output of the S3 enable circuit may be coupled to logic gate 515-q, the output of the S4 enable circuit may be coupled to logic gate 515-r, the output of the S5 enable circuit may be coupled to logic gate 515-s, the output of the S6 enable circuit may be coupled to logic gate 515-t, and the output of the S7 enable circuit may be coupled to logic gate 515-u.

[0099] Each enable circuit can be configured to pass or disable the output of the redundant ECC circuit 600. For example, the S3 enable circuit can be configured to pass RD_ALL (e.g., as RD_ALL_S3) or a logical zero based on the data plane selected for redundancy repair. Each enable circuit can include a number of OR logic gates 615 coupled to an AND gate 620.

[0100] Each enable circuit can receive RD_ALL and a corresponding control signal as input. The control signal can be a control bit CredEn <x>A combination of CredEn, each of which indicates whether the corresponding data plane x has been selected for redundancy repair. <0> may indicate when a logical one that data plane 0 has been selected for redundancy repair, and may indicate when a logical zero that data plane 0 has not been selected for redundancy repair. Thus, in some cases, the control signal may indicate that redundant data is related to (or a substitute for) data stored by the data plane corresponding to the enabling circuit that received the control signal.

[0101] Each control bit of the control signal may represent the redundancy repair state of the data plane whose bit serves as the basis for the corresponding syndrome bit. Thus, the control bit for the S3 enabling circuit may be CredEn <0> 、CredEn <2> 、CredEn <5> 、CredEn <6> 、CredEn <8> 、CredEn <11> 、CredEn <12> CredEn <15> (Since S3 is generated based on the XOR of the data bits in data planes 0, 2, 5, 6, 8, 11, 12, and 15 as defined by the Hamming matrix 300.) As another example, the control bit for the S4 enable circuit may be CredEn <0> 、CredEn <3> 、CredEn <4> 、CredEn <6> 、CredEn <9> 、CredEn <10> 、CredEn <12> CredEn <15> (Since S4 is generated based on the XOR of the data bits in data planes 0, 3, 4, 6, 9, 10, 12, and 15 as defined by the Hamming matrix 300).

[0102] According to the example that data plane 0 has been selected for redundancy repair, the control bits for the S3 enable circuit may be 10000000 (in CredEn <0> Start with CredEn <15> End). Thus, OR logic gate 615-a may output a logic one, and OR logic gate 615-b may output a logic zero. The outputs of logic gates 615-a and 615-b may drive OR logic gate 615-c. Thus, in this example, OR logic gate 615-c may output a logic one. The output of OR logic gate 615-c may, in turn, (and together with RD_ALL) drive AND logic gate 620 (e.g., in response to a control signal). Thus, AND logic gate 620 may output RD_ALL (e.g., output to logic gate 515-q as RD_ALL_S3) when the output of OR logic gate 615-c is one (as in this case), or output a logic zero when the output of OR logic gate 615-c is zero (e.g., if data plane 3 is selected for redundancy repair instead of data plane 0, this would be the case).

[0103] Thus, AND logic gate 620 will be described as an AND logic gate coupled to the output of the redundant ECC circuit and configured to output a signal based at least in part on a control signal (e.g., a control signal consisting of control bits CredEn<*>), the signal representing the result of an XOR operation on redundant data (e.g., RD_ALL). The signal can be passed to a logic gate coupled to both the output of AND logic gate 620 and a set of conventional data planes. For example, the signal can be passed to a logic gate as shown in reference Figure 5 One or more of the logic gates 515-q through 515-u depicted.

[0104] In some cases, redundant ECC circuit 600 and enabling circuitry 605 may be operated as follows. Redundant ECC circuit 600 may perform a first bitwise operation (e.g., an XOR operation) on a first set of redundant data (e.g., redundant data bits 0 to 7 for a first codeword). The first set of redundant data may be the same as data stored (or expected to be stored) at a first data plane (e.g., data plane 0). The result of the first bitwise operation may be communicated to a first set of logic gates (e.g., logic gates 515-q and 515-r for syndrome bits S3 and S4) based on the redundant data being for the first data plane (e.g., data plane 0). In some cases, a first control signal may indicate that the redundant data is for the first data plane. A first set of syndrome bits for the first codeword may be generated based on the result of the first bitwise operation.

[0105] The redundant ECC circuit 600 may also perform a second bitwise operation (e.g., an XOR operation) on a second set of redundant data (e.g., redundant data bits 0 to 7 for a second codeword). The second set of redundant data may be the same as data stored (or expected to be stored) at a second data plane (e.g., data plane 1). The redundant ECC circuit 600 may transmit the result of the second bitwise operation to a second set of logic gates (e.g., logic gates 515-q and 515-r corresponding to syndrome bits S5, S6, and S7) that is different from the first set of logic gates (e.g., logic gates 515-q and 515-r corresponding to S3 and S4). The result of the second bitwise operation may be transmitted to the second set of logic gates based on the redundant data being used for the second data plane (e.g., data plane 1). In some cases, the second control signal may indicate that the redundant data is used for the second data plane. A second set of syndrome bits for the second codeword may be generated based on the result of the second bitwise operation.

[0106] Figure 7 An example Hamming matrix 700 is illustrated that supports a direct-input redundancy scheme utilizing an adaptive syndrome decoder circuit according to various embodiments of the present disclosure. The Hamming matrix 700 may represent a (144, 136) Hamming code corresponding to 136 data bits, eight parity bits, and 144 total bits. The Hamming matrix 700 may be used with an ECC circuit (e.g., reference Figure 8 Those ECC circuits described in Fig. 9 Although described with reference to (144, 136) Hamming codes, any type of error correction code may be used to implement the techniques described herein.

[0107] Hamming matrix 700 may differ from Hamming matrix 300 because it includes an additional matrix for redundant data. This additional matrix may be referred to as redundant data matrix 705. Adding redundant data matrix 705 may affect the generation of syndrome bits. For example, by adding redundant data matrix 705, S3 is calculated by XORing the data bits from data planes 0, 2, 5, 6, 8, 11, 12, 15 and the redundant data plane (compared to XORing only the data bits from data planes 0, 2, 5, 6, 8, 11, 12, 15). If an error occurs in the redundant data, the fact that an error occurs in the redundant data plane will be indicated by the last four syndrome bits S3 to S7 matching the pattern 01110. As previously described, the location of the erroneous data bit is indicated by the first three syndrome bits. Therefore, when the syndrome bits generated by the ECC module are 11001110 (and do not match the parity bits), the location of the error in data bit 3 from the redundant data plane can be detected.

[0108] For ease of illustration, the Hamming matrix 700 is presented in a compressed form. However, it should be understood that different matrices for each data plane (and redundant data plane) may be expanded, as shown in FIG. Figure 3 Discussed.

[0109] Figure 8 An example ECC module 800 is illustrated that supports a direct-input redundancy scheme utilizing an adaptive syndrome decoder circuitry according to various embodiments of the present disclosure. The ECC module 800 may be a reference Figure 2 An example of an ECC module is described. ECC module 800 may be configured to generate and output a set of syndrome bits for a codeword that includes data bits from multiple data planes (eg, data planes 0-15).

[0110] In the configuration of the circuit system for generating syndrome bits S3 to S7, ECC module 800 may be different from ECC module 500. Also, redundant ECC circuit 810 may be different from (eg, referring to Fig. 9 810 may be used to generate the syndrome bits S3 and S7. In some cases, the syndrome bits S4, S5, and S6 are based on the redundant data.

[0111] Fig. 9 An example redundant ECC circuit 900 is illustrated that supports a direct input redundancy scheme utilizing an adaptive decoder circuit system according to various embodiments of the present disclosure. The redundant ECC circuit 900 may be a reference Figure 2 900 can transmit the result of the XOR operation on the redundant data to other components regardless of which data plane is selected for redundancy repair. This scheme may be different from the scheme for redundant ECC circuit 600. In the scheme for redundant ECC circuit 600, the result of the XOR operation on the redundant data can be selectively transmitted to certain components based on the data plane that has been selected for redundancy repair.

[0112] For example, the redundant ECC circuit 900 may transmit the result of an XOR operation for error correction of two different codewords (e.g., a first codeword and a second codeword) as follows. In order to perform error correction on the first codeword, the redundant ECC circuit 900 may perform a first bitwise operation (e.g., an XOR operation) on a first set of redundant data for a first data plane. The first set of redundant data may be data included in the first codeword and corresponding to data stored by the first data plane. The redundant ECC circuit 900 may then transmit the result of the first bitwise operation (e.g., RD_ALL) to a combination of logic gates (e.g., logic gates 815-a, 815-b, and 815-c corresponding to syndrome bits S4, S5, and S6). The result of the first bitwise operation may be transmitted to the combination of logic gates independently of the first set of redundant data being used for the first data plane. Next, a first set of syndrome bits for the first codeword may be generated based on the result of the first bitwise operation. In some cases, at least one of the syndrome bits of the first set may be generated by performing an XOR operation on a result of the first bitwise operation (eg, syndrome bit S4 may be generated by logic gate 815 - a performing an XOR operation on RD_ALL).

[0113] In order to perform error correction on the second codeword, the redundant ECC circuit 900 may perform a second bitwise operation (e.g., an XOR operation) on a second set of redundant data for a second data plane different from the first data plane. The second set of redundant data may be data included in the second codeword and corresponding to data stored by the second data plane. The redundant ECC circuit 900 may then transmit the result of the second bitwise operation (e.g., RD_ALL) to the same combination of logic gates (e.g., logic gates 815-a, 815-b, and 815-c corresponding to syndrome bits S4, S5, and S6). The result of the second bitwise operation may be transmitted to the combination of logic gates independently of the second set of redundant data for the first data plane. Therefore, a second set of syndrome bits for the second codeword may be generated based on the result of the second bitwise operation. In some cases, at least one of the syndrome bits of the second set may be generated by performing an XOR operation on the result of the first bitwise operation (e.g., syndrome bit S4 may be generated by logic gate 815-a performing an XOR operation on RD_ALL).

[0114] Fig.10 An example error correction module 1000 is illustrated that supports a direct input redundancy scheme utilizing an adaptive decoder circuit system according to various embodiments of the present disclosure. The error correction module 1000 may be a reference Figure 2 1000 is an example of an error correction module 240 described herein. Error correction module 1000 may include syndrome decoder circuit 1005, data selector 1010, bit flip circuit 1015, and inverter 1020. Although shown as including a single syndrome decoder circuit, error correction module 1000 may include multiple syndrome decoders (e.g., one for each data plane). In this example, syndrome decoder circuit 1005 may be used for a first data plane (e.g., data plane 0). Error correction module 1000 may perform error correction on data bits that make up, for example, a codeword.

[0115] The syndrome decoder circuit 1005 may include multiple decoders, and each decoder may be composed of one or more logic gates. In this example, the decoder circuit includes a NAND logic gate. However, other types of logic gates can be used to implement the techniques described herein.

[0116] During an error correction operation, the data selector 1010 may receive data bits (eg, from a reference Figure 2 During the same error correction operation, inverter 1020 may receive a control signal (eg, CredEn) indicating whether data plane x corresponding to syndrome decoder circuit 1005 has been selected for redundancy repair. <x>For example, when the syndrome decoder circuit 1005 corresponds to data plane 0, the inverter 1020 may receive a control signal CredEn indicating whether data plane 0 has undergone redundancy repair. <0> .

[0117] The data selector 1010 may also receive a control signal (eg, CredEn <x>) and uses the control signal as the basis for selecting redundant data or standard data for error correction. After selecting the data, the data selector 1010 may transmit the selected data to the bit flip circuit 1015. However, if the syndrome decoder circuit 1005 instructs to do so, the bit flip circuit 1015 may invert the data bits. Otherwise, the data bits may be transmitted to the output bus 1025 without inversion, which may be a reference bus. Figure 2 An example of an output bus 230 is described.

[0118] Upon receiving the control signal CredEn <x>Afterwards, the inverter 1020 may invert the control signal to produce an inverted (or "complemented") version of the control signal, which may be referred to as CredEn. <x>In the example of data plane 0, inverter 1020 may output CredEn <0> '. In general, the inverted version of the bit or control signal n can be represented as n'.

[0119] The syndrome decoder circuit 1005 may receive the control signal and the inverted version of the control signal as input. For example, the redundant decoder 1035 may receive the control signal and the standard decoder 1030 may receive the inverted version of the control signal. In the example of data plane 0, the redundant decoder 1035 (e.g., logic gate 1045-b) may receive CredEn <0> And the standard decoder 1030 (eg, logic gate 1045-a) may receive CredEn <0> Given the relationship between redundant decoder 1035, standard decoder 1030 and logic gate 1050, using the control signal and the inverted control signal as inputs to redundant decoder 1035 and standard decoder 1030, respectively, ensures that the output of redundant decoder 1035 or standard decoder 1030 is effectively invalidated.

[0120] Each of the decoders in the syndrome decoder circuit 1005 may receive as input a certain amount of syndrome-based bits (e.g., syndrome bits or inverted syndrome bits). These inputs may change based on the position of the bit undergoing error correction. For example, different inputs may be used depending on whether the bit is the first bit (e.g., data bit 0) or the last bit (e.g., data bit 7) stored by the data plane undergoing an error correction operation. Thus, in addition to receiving control signals, the redundant decoder 1035 may also receive a certain amount of syndrome-based inputs. And, in addition to receiving inverter control signals, the standard decoder 1030 may receive a set of syndrome-based inputs. According to the techniques described herein, the syndrome-based bits received by the standard decoder 1030 may be an inverted version (or "complement") of the syndrome-based bits received by the redundant decoder 1035. The reasons for this are explained below.

[0121] In the example of data plane 0, common decoder 1040 may receive S0', S1', and S2' at logic gate 1045-c-1, and S4 and S7' at logic gate 1045-c-2. Common decoder 1040 may be referred to as "common" because it receives as input the syndrome bits that are common (according to Hamming matrix 700) to data plane 0 and the redundant data plane. This can be easily seen by placing the two matrices next to each other in comparison matrix 1055, which shows that syndrome bit S4 (equal to 1) and syndrome bit S7 (equal to 0) are the same for both data plane 0 and the redundant data plane. Because they are part of the common matrix, S0, S1, and S2 are also the same for data plane 0 and the redundant data plane. Therefore, in the example where data plane 0 has undergone redundancy repair, common decoder 1040 may receive versions of syndrome bits S0, S1, S2, S4, and S7.

[0122] A determination is made whether the syndrome bits are inverted prior to insertion into the error correction module 1000 based on the expected value of the syndrome bits given by the Hamming matrix 700. For example, the syndrome bits may be processed (e.g., inverted) such that only logic ones are input to the syndrome decoder circuit 1005 if they are true with respect to the Hamming matrix 700. For example, when performing an operation to detect an error in data bit 0 of data plane 0, syndrome bits S0, S1, S2, S5, S6, and S7 may be inverted such that they appear as logic ones to the syndrome decoder circuit 1005. Similarly, when performing an operation to detect an error in data bit 0 of a redundant data plane, syndrome bits S3 and S7 may be inverted such that they appear as logic ones to the syndrome decoder circuit 1005.

[0123] Since the syndrome bits S3, S5, and S6 are different between the matrices for data plane 0 and the redundant data plane (e.g., 100 for data plane 0 compared to 011 for the redundant data plane), the syndrome bits must be processed differently and input to different decoders. In the data plane 0 example, syndrome bits S5 and S6 may be inverted so that S3, S5', and S6' (e.g., 111) may be input to the standard decoder 1030. And syndrome bit S3 may be inverted so that S3', S5, and S6 (111) may be input to the redundant decoder 1035. Thus, the redundant decoder 1035 may receive as input the complement (S3', S5, S6) of the syndrome-based input (S3, S5', S6') received by the standard decoder 1030 (and vice versa).

[0124] After receiving their respective inputs, the standard decoder 1030, the redundant decoder 1035, and the common decoder 1040 may transmit the results of the NAND operation on those inputs to the other components of the syndrome decoder circuit 1005. In the example of data plane 0, the standard decoder 1030 may transmit the results of the NAND operation on S3, S5', and S6'. If all inputs to the standard decoder 1030 are logic ones, the standard decoder 1030 may output a logic zero. Otherwise, the standard decoder 1030 may output a logic one. Similarly, if all inputs to the redundant decoder 1035 are logic ones, the redundant decoder 1035 may output a logic zero. Otherwise, the redundant decoder 1035 may output a logic zero.

[0125] Logic gate 1050 may be an AND logic gate (or perform an AND logic gate operation). Logic gate 1050 may receive the outputs of standard decoder 1030 and redundant decoder 1035 as inputs. Logic gate 1050 may perform an AND operation on its inputs and output the result of the AND operation (e.g., to logic gate 1060). Thus, logic gate 1050 may be configured so that the output of standard decoder 1030 or redundant decoder 1035 is actually passed to the next stage (e.g., to logic gate 1060).

[0126] Because logic gate 1050 is driven by the output of standard decoder 1030 or redundant decoder 1035, and because the driven output is determined based on the control signal, syndrome decoder circuit 1005 is configured to adjust its output based at least in part on whether redundant data received by the redundant ECC circuit corresponds to data stored by the first data plane.

[0127] In other words, the output of syndrome decoder circuit 1005 may be based on a first set of inputs (e.g., inputs to standard decoder 103) and a second set of inputs (e.g., inputs to redundant decoder 1035). According to the techniques described herein, syndrome decoder circuit 1005 may control its output by invalidating the first set of inputs when redundant data is for (e.g., corresponds to) a first data plane, and invalidating the second set of inputs when redundant data is for (e.g., corresponds to) a data plane other than the first data plane. A set of inputs may be referred to as invalid if it does not change the output of syndrome decoder circuit 1005.

[0128] Logic gate 1060 may be a NOR logic gate (or perform the function of a NOR logic gate). Logic gate 1060 may receive as input the output of common decoder 1040 and the output of logic gate 1050. In the example of data plane 0, the output of common decoder 1040 may be 1) the result of a NAND operation on S0', S1', and S2, and 2) the result of a NAND operation on S4 and S7'. Logic gate 1060 may perform a NOR operation on its inputs and output the result of the NOR operation to, for example, inverter 1065 and / or bit flip circuit 1015. Inverter 1065 may invert the output of logic gate 1060 and transmit an inverted version of the output of logic gate 1060 to bit flip circuit 1015. Thus, syndrome decoder circuit 1005 may be configured to output a control signal indicating whether the selected data bit is to be inverted.

[0129] The bit flip circuit 1015 may also receive selected data from the data selector 1010. For example, the bit flip circuit 1015 may receive a regular data bit from data plane 0 (e.g., when data plane 0 is not selected for redundancy repair), or a redundant data bit from a redundant data plane (e.g., when data plane 0 is selected for redundancy repair). Based on the output of the syndrome decoder circuit 1005 (e.g., the control signal and the control signal '), the bit flip circuit 1015 may flip the data bit. After flipping the data bit, or after preventing the flipped data bit from being flipped, the bit flip circuit 1015 may output the data bit (or the flipped data bit) to the output bus 1025 for communication with other components. Thus, the error correction module 1000 may perform error correction on data bits from the regular data plane or the redundant data plane.

[0130] Fig.11 A block diagram 1100 is shown that illustrates a memory array supporting a direct input redundancy scheme utilizing an adaptive decoder circuitry according to various embodiments of the present disclosure. The block diagram 1100 may include a memory array 100-a, which may be as described in reference to Figure 1 An example of a memory array 100 is discussed. The memory array 100-a may be referred to as an electronic memory device and may include a memory controller 140-a, word lines 110-a, bit lines 115-a, and sensing components 125-a, which may be referenced. Figure 1 An example of a memory controller 140, word lines 110, bit lines 115, and sensing components 125 are depicted. The memory array 100-a may include data planes 1125, which may include a normal data plane, a redundant data plane, and a parity data plane.

[0131] The memory array 100-a may also include a reference component 1120, an ECC module 220-a, and an error correction module 240-a. The components of the memory array 100-a may electronically communicate with each other and may perform reference Figures 1 to 10 Functionality as described.

[0132] The memory controller 140-a may combine other components to apply voltages throughout the memory array 100-a, write data to the memory cells 105-a, read data from the data plane 1125, and generally operate the memory array 100-a, such as Figures 1 to 10 Memory controller 140 - a may include bias component 1110 and timing component 1115 . Memory controller 140 - a may be in electronic communication with data plane 1125 , sense component 125 - a , and reference component 1120 .

[0133] The bias component 1110 may be configured (e.g., by the memory controller 140-a) to activate the word line 110-a or the digit line 115-a by applying voltages to those various nodes. For example, the bias component 1110 may be configured to apply voltages to read or write memory cells as described herein. In some cases, the memory controller 140-a may include a memory controller as described in reference to FIG. Figure 1 The described row decoder, column decoder, or both. This can enable the memory controller 140-a to access one or more memory cells within the data plane 1125. The bias component 1110 can also provide a voltage potential to the reference component 1120 to generate a reference signal for the sensing component 125-a. In addition, the bias component 1110 can provide a voltage potential for the operation of the sensing component 125-a.

[0134] Timing component 1115 can be configured to control the timing of various word line selections, plate biases, or component activation / deactivation. For example, timing component 1115 can control the timing of voltage application to perform the memory functions discussed herein, such as reading and writing, and error correction. In some cases, timing component 1115 can control the operation of bias component 1110.

[0135] Reference component 1120 may include various components for generating a reference signal for sensing component 125-a. Reference component 1120 may include circuitry configured to generate a reference signal.

[0136] The sensing component 125-a may compare the signal from the memory cell with the reference signal from the reference component 1120. After determining the logic state stored by the memory cell, the sensing component 125-a may transmit a signal representing the logic state to other components of the memory array 100-a. In some cases, the signal representing the logic state may be transmitted to a data selector, such as a reference Figure 2 As described, it, in turn, may communicate signals to ECC module 220-a and / or error correction module 240-a. In some cases, reference component 1120 and sense component 125-a may be components of memory controller 140-a.

[0137] In some cases, in conjunction with the ECC module 220-a and the error correction module 240-a, the memory controller 140-a may perform error correction on the codewords retrieved from the data plane 1125. As part of the error correction operation, the memory array 100-a may generate (e.g., via the ECC module 220-a) syndrome bits for the data stored by the data plane 1125. The memory array 100-a may then select data bits from the data for the error correction operation. The memory array 100-a may transmit a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for the error correction operation. Based on the control signal, the memory array 100-a may decode the syndrome bits to determine whether the data bit should be corrected (e.g., inverted).

[0138] Fig.12 A system 1200 is illustrated that supports a direct input redundancy scheme utilizing an adaptive decoder circuit system according to various embodiments of the present disclosure. The system 1200 includes a device 1205, which may be or include a printed circuit board to connect or physically support various components. The device 1205 includes a memory array 100-b, which may be a reference Figure 1 and 11 1. The memory array 100-b may contain a memory controller 140-b and a data plane 1125-a, which may be as described in reference to FIG. Figure 1 and 11 The depicted examples of memory controller 140 and data plane 1125. Device 1205 may also include processor 1210, BIOS component 1215, peripheral component 1220, and input / output control component 1225. The components of device 1205 may electronically communicate with each other via bus 1230.

[0139] The processor 1210 may be configured to operate the memory array 100-b through the memory controller 140-b. In some cases, the processor 1210 may execute reference Figure 1 and 11 The functions of the memory controller 140 described herein. In other cases, the memory controller 140-b may be integrated into the processor 1210. The processor 1210 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components, and the processor 1210 may perform the various functions described herein. The processor 1210 may, for example, be configured to execute computer readable instructions stored in the memory array 100-b to cause the device 1205 to perform various functions or tasks.

[0140] BIOS component 1215 may be a software component including a basic input / output system (BIOS) operating as firmware that may initialize and run the various hardware components of system 1200. BIOS component 1215 may also manage the flow of data between processor 1210 and various components such as peripheral components 1220, input / output control components 1225, etc. BIOS component 1215 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0141] Peripheral component 1220 may be any input or output device, or an interface to such a device, that may be integrated into device 1205. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0142] The input / output control component 1225 can manage data communications between the processor 1210 and the peripheral components 1220, the input device 1235, or the output device 1240. The input / output control component 1225 can also manage peripheral devices that are not integrated into the device 1205. In some cases, the input / output control component 1225 can represent a physical connection or port to an external peripheral device.

[0143] Input 1235 may represent a device or signal external to device 1205 that provides input to device 1205 or a component thereof. This may include a user interface or an interface with or between other devices. In some cases, input 1235 may be a peripheral device that interfaces with device 1205 via peripheral component 1220, or may be managed by input / output control component 1225.

[0144] Output 1240 may represent a device or signal external to device 1205 that is configured to receive output from device 1205 or any of its components. Examples of output 1240 may include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some cases, output 1240 may be a peripheral device that interfaces with device 1205 via peripheral component 1220 or may be managed by input / output control component 1225.

[0145] The components of memory controller 140-b, device 1205, and memory array 100-b may be comprised of circuitry designed to perform their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

[0146] Fig.13 A method 1300 is illustrated for utilizing a direct-input redundancy scheme for adaptive decoder circuitry in accordance with various embodiments of the present disclosure. The method 1300 may illustrate a portion of a retrieval operation that includes error correction.

[0147] At block 1305, the method may include generating syndrome bits for data stored by the data plane. Figures 1 to 10 The described method performs the operation of 1305. In some examples, the operation of 1305 can be performed as shown in reference Figure 2 , 8 and the ECC module described in 10 is executed.

[0148] At block 1310, the method may include selecting data bits from the data for error correction operations. Figures 1 to 10 The described method performs the operation of 1310. In some examples, the operation of 1310 can be performed as shown in reference Figure 1 and 11 The described memory controller performs.

[0149] At block 1315, the method may include transmitting a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for error correction operations. In some cases, transmitting the control signal includes transmitting the control signal to a first decoder of the syndrome decoder. In some cases, the method may also include transmitting an inverted version of the control signal to a second decoder of the syndrome decoder. Figures 1 to 10 The described method performs the operation of 1315. In some examples, the operation of 1315 can be performed as shown in reference Figure 1 and 11 The described memory controller performs.

[0150] At block 1320, the method may include decoding the syndrome bits at based at least in part on the control signal. Figures 1 to 10 The described method performs the operation of 1320. In some examples, the operation of 1320 can be performed as shown in reference Fig.10 The syndrome decoder circuit described performs.

[0151] In some cases, the method may include transferring the data bits to a bit flipping circuit configured for an error correction operation. In such cases, the method may include activating the bit flipping circuit based at least in part on a result of decoding the syndrome bits.

[0152] In some cases, the method may include decoding the syndrome bits based at least in part on input to a first decoder when the data bits are substitute data bits, and decoding the syndrome bits based at least in part on input to a second decoder when the data bits are not substitute data bits.

[0153] In some cases, the method may include: determining that a data bit is stored by a data plane configured to store data, the data representing a logical state that is a basis for data stored by one or more of the data planes; and detecting that the data bit is a substitute data bit based at least in part on the determination.

[0154] In some cases, portions of method 1300 may be performed by an apparatus. The apparatus may include an ECC circuit coupled to a data plane and configured to receive data bits from the data plane. Each of the ECC circuits may include a set of logic gates configured to perform bit-by-bit operations on data from a corresponding data plane. The apparatus may also include a redundant ECC circuit coupled to a redundant data plane and configured to receive redundant data corresponding to data stored by at least one of the data planes. The redundant ECC circuit may include a set of logic gates configured to perform bit-by-bit operations on the redundant data. The apparatus may also include a syndrome decoder circuit for a first data plane in the data planes, the syndrome decoder circuit coupled to the redundant ECC circuit and the ECC circuit and configured to adjust its output based at least in part on whether the redundant data received by the redundant ECC circuit corresponds to data stored at the first data plane.

[0155] In some cases, the output of the syndrome decoder circuit is based at least in part on a first set of inputs (e.g., inputs to standard decoder 1030) and a second set of inputs (e.g., inputs to redundant decoder 1035). In such cases, the syndrome decoder circuit may be configured to adjust its output by being configured to invalidate the first set of inputs when the redundant data corresponds to data stored at a first data plane, and to invalidate the second set of inputs when the redundant data corresponds to data stored at a data plane other than the first data plane.

[0156] In some cases, the syndrome decoder circuit includes a first logic gate (e.g., logic gate 1045-b) and a second logic gate (e.g., logic gate 1045-a), each of which is configured to receive a syndrome-based input including a syndrome bit and / or an inverted syndrome bit or a combination. In such cases, the apparatus may also include an inverter having an input coupled to the first logic gate and an output coupled to the second logic gate of the syndrome decoder circuit. The inverter may be configured to receive a signal indicating whether the redundant data corresponds to data stored at a first data plane. When the redundant data corresponds to data stored at the first data plane, the syndrome decoder circuit may be configured to output an indication of whether the bit is to be inverted based at least in part on the syndrome-based input for the first logic gate and independently of the syndrome-based input for the second logic gate. When the redundant data corresponds to data stored at a data plane other than the first data plane, the syndrome decoder circuit may be configured to output an indication of whether the bit is to be inverted based at least in part on the syndrome-based input for the second logic gate and independently of the syndrome-based input for the first logic gate.

[0157] In some cases, the apparatus also includes a bit flipping circuit coupled to the syndrome decoder circuit.The bit flipping circuit can be configured to flip bits from the first data plane or the redundant data plane based at least in part on an output of the syndrome decoder circuit.

[0158] In some cases, the apparatus may include a bit flipping circuit configured to invert data bits, and a syndrome decoder for a first data plane. The syndrome decoder may be coupled to the bit flipping circuit and may include a first decoder (e.g., a redundant decoder 1035) and a second decoder (e.g., a standard decoder 1030). The first decoder may be configured to receive a first set of bits, the first set of bits including syndrome bits and / or inverted syndrome bits generated at least in part based on a set of data. The second decoder may be configured to receive a second set of bits including an inverted version of the first set of bits. The first and second decoders may be configured to receive the first and second sets of bits, respectively, as part of the same decoding operation (e.g., a decoding operation of the same bit).

[0159] In some cases, the syndrome decoder also includes a third decoder configured to receive a third set of bits, the third set of bits including syndrome bits and / or inversion syndrome bits. The third set of bits may be different from the first and second sets of bits and may be generated based at least in part on the set of data.

[0160] In some cases, the apparatus may include an inverter coupled to the first decoder and the second decoder. The inverter may be configured to receive a control signal indicating whether the set of data includes redundant data corresponding to data stored at the first data plane. In such cases, the first decoder may be configured to receive the control signal from the memory controller, and the second decoder may be configured to receive an inverted version of the control signal from the inverter.

[0161] In some cases, the apparatus includes a data selector circuit configured to select a data bit based at least in part on a control signal. In such cases, the bit flip circuit may be configured to invert the selected data bit based at least in part on an output of a syndrome decoder.

[0162] Fig.14 A method 1400 is illustrated for utilizing a direct-input redundancy scheme for adaptive decoder circuitry in accordance with various embodiments of the present disclosure. The method 1400 may illustrate portions of two retrieval operations including error correction.

[0163] At block 1405, the method may include performing a first bitwise operation (eg, an XOR operation) on a first set of redundant data for a first data plane using an ECC circuit, the first set of redundant data corresponding to data stored by the first data plane. Figures 1 to 10 The method described herein performs the operation of 1405. In some examples, the operation of 1405 may be performed as described in reference Figure 2 , 6 , 8 and 9 are performed by the redundant ECC circuits described.

[0164] At block 1410, the method may include transferring the result of the first bitwise operation (e.g., RD_ALL) to a combination of logic gates (e.g., logic gates 815-a, 815-b, and 815-c). Transferring the result of the first bitwise operation to the combination of logic gates may be independent of the first set of redundant data for the first data plane. Figures 1 to 10 The described method performs the operation of 1410. In some examples, the operation of 1410 can be performed as shown in FIG. Figure 2 , 6 , 8 and 9 are performed by the redundant ECC circuits described.

[0165] At block 1415, the method may include performing a second bitwise operation (eg, an XOR operation) on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane. Figures 1 to 10 The described method performs the operation of 1415. In some examples, the operation of 1415 can be performed as shown in reference Figure 2 , 6 , 8 and 9 are performed by the redundant ECC circuits described.

[0166] At block 1420, the method may include transmitting the result of the second bitwise operation to the combination of logic gates. Transmitting the result of the second bitwise operation to the combination of logic gates may be used for the second data plane independently of the second set of redundant data. Figures 1 to 10 The described method performs the operation of 1420. In some examples, the operation of 1420 can be performed as described in reference Figure 2 , 6 , 8 and 9 are performed by the redundant ECC circuits described.

[0167] In some examples, the method may also include generating a first set of syndrome bits for a codeword, the codeword including a first set of redundant data. The first set of syndrome bits may be based at least in part on a result of the first bitwise operation. In some examples, the method may also include generating a second set of syndrome bits for a second codeword, the second codeword including a second set of redundant data. The second set of syndrome bits may be based at least in part on a result of the second bitwise operation.

[0168] In some cases, the method includes performing an XOR operation on a result of the first bitwise operation (e.g., by one of logic gates 815-a, 815-b, or 815-c), and performing an XOR operation on a result of the second bitwise operation (e.g., by one of logic gates 815-a, 815-b, or 815-c).

[0169] A method is described. The method may include: generating syndrome bits for data stored by data planes; selecting data bits from the data for an error correction operation; transmitting a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for the error correction operation; and decoding the syndrome bits at the syndrome decoder based on the control signal.

[0170] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: generate syndrome bits for data stored by a data plane; select data bits from the data for an error correction operation; transmit a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for the error correction operation; and decode the syndrome bits at the syndrome decoder based on the control signal.

[0171] Another apparatus is described. The apparatus may include: means for generating syndrome bits for data stored by data planes; means for selecting data bits from the data for an error correction operation; means for transmitting a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for the error correction operation; and means for decoding the syndrome bits at the syndrome decoder based on the control signal.

[0172] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to generate syndrome bits for data stored by a data plane; select data bits from the data for an error correction operation; transmit a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for the error correction operation; and decode the syndrome bits at the syndrome decoder based on the control signal.

[0173] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: transferring data bits to a bit flipping circuit configured for an error correction operation; and activating the bit flipping circuit based on a result of decoding the syndrome bits.

[0174] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, transmitting a control signal may include operations, features, means, or instructions for transmitting the control signal to a first decoder of a syndrome decoder; and wherein the method further includes transmitting an inverted version of the control signal to a second decoder of the syndrome decoder.

[0175] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: decoding syndrome bits based on input for a first decoder when the data bits may be substitute data bits; and decoding syndrome bits based on input for a second decoder when the data bits may not be substitute data bits.

[0176] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: determining that a data bit is stored by a data plane configured to store data, the data representing a logical state that may be a basis for data stored by one or more of the data planes; and detecting that the data bit may be an alternative data bit based on the determination.

[0177] A method is described. The method may include: performing a first bitwise operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; transferring a result of the first bitwise operation to a combination of logic gates; performing a second bitwise operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transferring a result of the second bitwise operation to the combination of logic gates.

[0178] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: perform a first bitwise operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; transmit a result of the first bitwise operation to a combination of logic gates; perform a second bitwise operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transmit a result of the second bitwise operation to the combination of logic gates.

[0179] Another apparatus is described. The apparatus may include: means for performing a first bitwise operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; means for transferring a result of the first bitwise operation to a combination of logic gates; means for performing a second bitwise operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and means for transferring a result of the second bitwise operation to the combination of logic gates.

[0180] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: perform a first bitwise operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; transfer a result of the first bitwise operation to a combination of logic gates; perform a second bitwise operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transfer a result of the second bitwise operation to the combination of logic gates.

[0181] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: generating a first set of syndrome bits for a codeword including a first set of redundant data, the first set of syndrome bits being based on a result of a first bitwise operation; and generating a second set of syndrome bits for a second codeword including a second set of redundant data, the second set of syndrome bits being based on a result of a second bitwise operation.

[0182] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: performing an exclusive OR (XOR) operation on a result of the first bitwise operation; and performing an XOR operation on a result of the second bitwise operation.

[0183] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: transmitting a result of a first bitwise operation to a combination of logic gates independently of a first set of redundant data for a first data plane; and transmitting a result of a second bitwise operation to a combination of logic gates independently of a second set of redundant data for a second data plane.

[0184] An apparatus is described. The apparatus may include: an error correction code (ECC) circuit coupled to a data plane and configured to receive data bits from the data plane; a redundant ECC circuit coupled to the redundant data plane and configured to receive redundant data corresponding to data stored by at least one of the data planes; and a syndrome decoder circuit for a first one of the data planes, coupled to the redundant ECC circuit and the ECC circuit and configured to adjust its output based on whether the redundant data received by the redundant ECC circuit corresponds to data received by the first data plane.

[0185] In some examples, the output may be based on a first set of inputs and a second set of inputs, and wherein the syndrome decoder circuit may be configured to adjust its output by being configured to invalidate the first set of inputs when the redundant data corresponds to data stored by a first data plane, and to invalidate the second set of inputs when the redundant data corresponds to data stored by a data plane other than the first data plane.

[0186] In some examples, a syndrome decoder circuit includes a first logic gate and a second logic gate that may each be configured to receive a syndrome-based input including syndrome bits or inverted syndrome bits, or a combination thereof.

[0187] Some instances of the apparatus may include an inverter including an input coupled to a first logic gate of a syndrome decoder circuit and an output coupled to a second logic gate of the syndrome decoder circuit, the inverter configured to receive a signal indicating whether the redundant data may correspond to data stored by the first data plane.

[0188] In some examples, when redundant data is available for the first data plane, the syndrome decoder circuit may be configured to output an indication of whether the bit may be inverted based on a syndrome-based input for the first logic gate and independently of a syndrome-based input for the second logic gate.

[0189] In some examples, when redundant data is available for a data plane other than the first data plane, the syndrome decoder circuit can be configured to output an indication of whether the invertible bit is available based on the syndrome-based input for the second logic gate and independently of the syndrome-based input for the first logic gate.

[0190] Some examples of the apparatus may include a bit flipping circuit coupled with the syndrome decoder circuit and configured to flip bits from the first data plane or the redundant data plane based on an output of the syndrome decoder circuit.

[0191] In some examples, the redundant ECC circuits include a set of logic gates configured to perform bit-by-bit operations on redundant data, and wherein each of the ECC circuits includes a set of logic gates configured to perform bit-by-bit operations on data from the data plane.

[0192] An apparatus is described. The apparatus may include a bit flipping circuit configured to invert data bits, and a syndrome decoder for a first data plane, the syndrome decoder coupled to the bit flipping circuit and including a first decoder configured to receive a first set of bits, the first set of bits including syndrome bits generated based on a set of data, inverted syndrome bits, or a combination thereof, and a second decoder configured to receive a second set of bits, the second set of bits including an inverted version of the first set of bits.

[0193] In some examples, the first and second decoders may be configured to receive the first and second sets of bits, respectively, as part of the same decoding operation.

[0194] In some examples, the syndrome decoder may further include operations, features, means, or instructions for a third decoder configured to receive a third set of bits including syndrome bits different from the first and second sets of bits and generated based on the set of data, inverted syndrome bits, or a combination thereof.

[0195] Some examples of the apparatus may include an inverter coupled to the first decoder and the second decoder, the inverter configured to receive a control signal indicating whether the set of data includes redundant data corresponding to the first data plane.

[0196] In some examples, the first decoder may be configured to receive a control signal from a memory controller, and the second decoder may be configured to receive an inverted version of the control signal from an inverter.

[0197] Some examples of the apparatus may include a data selector circuit configured to select a data bit based on a control signal, wherein the bit flipping circuit may be configured to invert the selected data bit based on an output of the syndrome decoder.

[0198] As used herein, the term "virtual ground" refers to a circuit node that is maintained at a voltage of approximately zero volts (0V) but is not directly connected to ground. Therefore, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a stable state. Virtual ground can be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" means connecting to approximately 0V.

[0199] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components that are in electronic communication or coupled to each other may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals as soon as the circuit is energized. For example, two components that are physically connected via a switch (e.g., a transistor) may be in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

[0200] The term "isolation" or "electrical isolation" refers to a relationship between components where electrons cannot flow between them; if there is an open circuit between the components, the components are isolated from each other. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

[0201] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to obtain the advantage of the characteristic.

[0202] The devices discussed herein, including memory array 100, may be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0203] One or more transistors discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as a metal. The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "started". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0204] The specific embodiments described above in conjunction with the accompanying drawings describe examples and do not represent the only examples that can be implemented or within the scope of the claims. When used in this specification, the terms "example" and "exemplary" mean "serving as an example, instance or illustration" and are not "preferred" or "superior to other examples". The specific embodiments include specific details for the purpose of providing an understanding of the described technology. However, these technologies can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0205] Information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0206] The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0207] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. As used herein, included in the claims, when used in a list of two or more items, the term "and / or" means that any of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a composition is described as containing components A, B, and / or C, the composition may contain: only A; only B; only C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Also, as used herein, including in the claims, "or" used in a list of items (e.g., a list of items that begins with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that a list such as "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C).

[0208] Computer-readable media include both computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, computer-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code devices in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. And, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0209] The previous description of the disclosure is provided to enable those skilled in the art to make or use the disclosure. Those skilled in the art will readily appreciate various modifications to the disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.< / x> < / x> < / x> < / x> < / x>

Claims

1. A device comprising: an error correction code (ECC) circuit coupled to the data plane and configured to receive data bits from the data plane and to generate first error correction information based at least on the received data bits; a redundant ECC circuit coupled to the redundant data plane and configured to receive redundant data from the redundant data plane corresponding to data stored by at least one of the data planes and to generate second error correction information based at least in part on the redundant data; and a syndrome decoder circuit for a first one of the data planes, the syndrome decoder circuit coupled to the redundant ECC circuit and the ECC circuit and configured to generate an output based at least in part on whether the redundant data received by the redundant ECC circuit corresponds to data stored by at least the first data plane and based at least in part on one or more of the first error correction information or the second error correction information.

2. The apparatus of claim 1 , wherein the output is based at least in part on a first set of inputs and a second set of inputs, and wherein the syndrome decoder circuit is configured to adjust the output by being configured to invalidate the first set of inputs when the redundant data corresponds to the data stored by the first data plane, and to invalidate the second set of inputs when the redundant data corresponds to data stored by a data plane other than the first data plane.

3. The apparatus of claim 1 , wherein the syndrome decoder circuit comprises a first logic gate and a second logic gate that can each be configured to receive a syndrome-based input, the syndrome-based input comprising syndrome bits or inverted syndrome bits, or a combination thereof.

4. The apparatus according to claim 3, further comprising: an inverter including an input coupled to the first logic gate of the syndrome decoder circuit and an output coupled to the second logic gate of the syndrome decoder circuit, the inverter being configured to receive a signal indicating whether the redundant data corresponds to the data stored by the first data plane.

5. The apparatus of claim 3 , wherein when the redundant data is for the first data plane, the output of the syndrome decoder circuit is configured to be based at least in part on the syndrome-based input for the first logic gate and independently of the syndrome-based input for the second logic gate to output an indication of whether a bit is to be inverted.

6. The apparatus of claim 3 , wherein when the redundant data is for a data plane other than the first data plane, the output of the syndrome decoder circuit is configured to be based at least in part on the syndrome-based input for the second logic gate and to be independent of the syndrome-based input for the first logic gate to output an indication of whether a bit is to be inverted.

7. The apparatus of claim 1, further comprising: A bit flip circuit is coupled to the syndrome decoder circuit and is configured to flip bits from the first data plane or the redundant data plane based at least in part on the output of the syndrome decoder circuit.

8. The apparatus of claim 1 , wherein the redundant ECC circuits comprise a first set of logic gates configured to perform a first bitwise operation on the redundant data, and wherein each of the ECC circuits comprises a second set of logic gates configured to perform a second bitwise operation on data from a corresponding one of the data planes.

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