Double doped source / drain region and method of forming the same

Abstract

The present disclosure relates to dual-doped source / drain regions and methods for forming the same. A method includes: forming a source / drain region in a semiconductor fin; after forming the source / drain region, injecting a first impurity into the source / drain region; and after injecting the first impurity, injecting a second impurity into the source / drain region. The first impurity has a lower enthalpy of formation than the second impurity. The method also includes: after injecting the second impurity, annealing the source / drain region.

Description

Technical Field

[0001] The present disclosure relates to dual-doped source / drain regions and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be integrated into a given area. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a source / drain region in a semiconductor fin; after forming the source / drain region, injecting a first impurity into the source / drain region; after injecting the first impurity, injecting a second impurity into the source / drain region, wherein the first impurity has a lower formation enthalpy than the second impurity; and after injecting the second impurity, annealing the source / drain region.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: etching a groove in a semiconductor fin; epitaxially growing a source / drain region in the groove; after epitaxially growing the source / drain region, implanting the source / drain region with arsenic; after implanting the source / drain region with arsenic, implanting the source / drain region with a phosphorus dimer; after implanting the source / drain region with the phosphorus dimer, activating the arsenic and the phosphorus dimer using an annealing process.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor substrate; a gate stack located at the top surface of the semiconductor substrate; a source / drain region adjacent to the gate stack, wherein the source / drain region includes a first epitaxial region containing a first impurity; a first doped region containing a second impurity in the first epitaxial region; and a second doped region containing a third impurity in the first epitaxial region, the second impurity having a lower formation enthalpy than the third impurity, and the first doped region surrounds the side of the second doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1When read together, various aspects of the present disclosure will be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.16 , Fig.17 , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig.23A and Fig. 23B A cross-sectional and top-down view of an intermediate stage in the FinFET manufacturing process.

[0010] Fig.15D Impurity concentrations in devices according to some embodiments are shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] Various embodiments include injecting two different types of dopants into the source / drain region for improved junction mutation (e.g., reduced leakage current) and reduced source / drain contact resistance. In an embodiment method, a first dopant is injected into the source / drain region and then a second dopant is injected. The first dopant is an element different from the second dopant, and the first dopant may have a lower formation enthalpy than the second dopant. For example, the first dopant may include arsenic, carbon, antimony, etc., and the second dopant may include phosphorus, etc. In a specific embodiment, arsenic is injected into the source / drain region and then a phosphorus dimer (P2) is injected. Due to its lower formation enthalpy, the first dopant is more easily attracted to the vacancies in the source / drain region and forms a more stable bond with the vacancies. For example, the first dopant can be used to reduce the diffusion of the second dopant and reduce the bonding of the second dopant to the vacancies. By reducing the diffusion of the second dopant, a higher concentration of the second dopant can be obtained in the contact region of the source / drain region, thereby reducing the source / drain contact resistance. Furthermore, using two different elements as dopants allows for a junction with improved abruptness and less diffusion, thereby providing improved short channel control (e.g., to combat the effects of drain-induced barrier lowering (DIBL) in advanced process nodes). Various embodiments may provide one or more of the following non-limiting advantages: improved junction abruptness, reduced diffusion of the second dopant, and reduced source / drain contact resistance.

[0014] Figure 1 An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is provided in the substrate 50, and the fin 52 protrudes above and between adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used only to refer to a semiconductor substrate or a semiconductor substrate containing an isolation region. In addition, although the fin 52 is illustrated as a single, continuous material as the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0015] A gate dielectric layer 92 is along the sidewalls and over the top surface of the fin 52, and a gate electrode 94 is located over the gate dielectric layer 92. The source / drain regions 82 are disposed in opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1Reference cross sections used in the following figures are further shown. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in a direction, for example, of current flow between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate last process. In other embodiments, a gate first process may be used. In addition, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructures (e.g., nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs), and the like.

[0017] Figures 2 to 23B is a cross-sectional view of an intermediate stage in the FinFET fabrication process according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA is shown, except for multiple fins / FinFETs. Fig. 8A , Fig. 9A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A and Fig.23A Along Figure 1 The reference section AA shown shows that Figure 8B , Fig. 9B , Fig.10 , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16 , Fig.17 , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B and Fig. 23B Along Figure 1 A similar section BB is shown. Fig. 12B , Fig. 12C , Fig. 15B and Fig. 15C Along Figure 1 Reference cross section CC shown in FIG. 1 shows, in addition to multiple fins / FinFETs.

[0018] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., using a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide layer (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium, aluminum gallium arsenide, gallium indium arsenide, gallium in phosphide and / or gallium indium arsenide phosphide; or a combination thereof.

[0019] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type FinFET. The p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by a separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0020] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic.

[0021] The fins may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) may be used to pattern the fins 52. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, a smaller spacing than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on the fins 52.

[0022] exist Figure 4In the embodiment, the insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material (e.g., oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material, such as those discussed above, may be formed over the liner.

[0023] exist Figure 5 In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a deep etching process, a combination thereof, etc. may be utilized. The planarization process exposes the fin 52 so that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed. In embodiments where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that the top surfaces of the mask or the fin 52, respectively, are flush with the insulating material 54 after the planarization process is completed.

[0024] exist Figure 6 In the embodiment of the present invention, the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed so that the upper portion of the fin 52 in the n-type region 50N and the p-type region 50P protrudes from between the adjacent STI regions 56. In addition, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof as shown. The top surface of the STI region 56 can be formed into a flat, convex surface, and / or a concave surface by appropriate etching. The STI region 56 can be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fin 52)). For example, the oxide can be removed using, for example, dilute hydrofluoric (dHF) acid.

[0025] about Figures 2 to 6The process described is only one example of how to form fin 52. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and a trench can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure can be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 can be recessed, and a material different from the fin 52 can be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, where a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid previous and subsequent implants, although in situ doping and implant doping can be used together.

[0026] Furthermore, it may be advantageous to epitaxially grow a different material in the n-type region 50N (eg, NMOS region) than in the p-type region 50P (eg, PMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon germanium (Si x Ge 1-x , where x may be in the range of 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0027] In addition, Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N, and an N-well may be formed in the P-type region 50P. In some embodiments, a P-well or an N-well may be formed in both the n-type region 50N and the P-type region 50P.

[0028] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be implemented using photoresists and / or other masks (not shown). For example, a photoresist may be formed over the fins 52 and STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the implantation of n-type impurities into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., and the n-type impurity concentration implanted into the region is equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 To about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0029] After the p-type region 50P is implanted, a photoresist is formed over the fin 52 and the STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., and the concentration of the p-type impurity implanted in the region is equal to or less than 10 18 cm -3 For example, in about 10 16 cm -3 To about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0030] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the material of the grown epitaxial fins may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0031] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 may be deposited on the dummy dielectric layer 60, and then planarized, for example, by CMP. The mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 may be made of other materials having high etch selectivity from etching of isolation regions (e.g., STI regions 56 and / or dummy dielectric layer 60). The mask layer 64 may include one or more layers of, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed on the n-type region 50N and the p-type region 50P. Note that the dummy dielectric layer 60 is shown as covering only the fin 52 for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56, extends above the STI region and between the dummy gate layer 62 and the STI region 56.

[0032] FIG. 8A to FIG. 23B Various additional steps in fabricating example devices are shown. FIG. 8A to FIG. 23B The characteristics of either the n-type region 50N or the p-type region 50P are shown. For example, FIG. 8A to FIG. 23B The structure shown may be applicable to both the n-type region 50N and the p-type region 50P. In the text accompanying each figure, the difference, if any, in the structure of the n-type region 50N and the p-type region 50P is described.

[0033] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 64 (see Figure 7 ) can be patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from an adjacent dummy gate. The dummy gate 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0034] In addition, Fig. 8A and Figure 8B In the embodiment, the gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 52. Thermal oxidation or deposition and anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0035] After forming the gate sealing spacer 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above, Figure 6 As discussed in the implantation, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into the exposed fins 52 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into the exposed fins 52 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a doping range from about 10 15 cm -3 To about 10 19 cm -3 Annealing may be performed to repair implantation damage and activate the implanted impurities.

[0036] exist Fig. 9A and Fig. 9B In the embodiment, the gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, etc.

[0037] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., before forming gate spacers 86, gate seal spacers 80 may not be etched, thereby producing "L-shaped" gate seal spacers), spacers may be formed and removed, and the like. In addition, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region of an n-type device may be formed before forming the gate seal spacer 80, while the LDD region of a p-type device may be formed after forming the gate seal spacer 80.

[0038] exist Figure 10 to Figure 1 5, epitaxial source / drain regions 82 are formed in the fins 52. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short out the subsequently formed gates of the resulting FinFETs. The material of the epitaxial source / drain regions 82 may be selected to exert stress in the corresponding channel regions 58, thereby improving performance.

[0039] The epitaxial source / drain regions 82 in the n-type region 50N may be formed differently and separately from the epitaxial source / drain regions 82 in the p-type region 50P. Fig.10 , Fig.11 , Fig. 12A , Fig.13A , Fig.14A and Fig.15A The process of forming epitaxial source / drain regions 82 in n-type region 50N is shown along Figure 1 When the p-type region 50P (not explicitly shown) is masked, it is possible to perform Figures 10 to 15A The steps described in Fig.10 In the embodiment, the source / drain region of the fin 52 in the n-type region 50N is patterned to form a recess 20 in the fin 52. For example, the recess 20 may be formed in the dummy gate 72 (eg, see Fig.19B ), such as between adjacent dummy gates 72. For example, patterning of the recess 20 can be achieved by a combination of photolithography and etching. In some embodiments, the fin 52 can be over-etched so that the recess 20 extends directly under the gate spacer 86.

[0040] exist Fig.11 In the embodiment of the present invention, an optional epitaxial region 22 is grown in the recess 20. The epitaxial region 22 may only partially fill the recess 20. For example, the epitaxial region 22 may grow to cover the sides and bottom of the recess 20. The epitaxial region 22 may be grown by any acceptable process and may include any acceptable material (e.g., suitable for n-type FinFETs). For example, if the fin 52 is silicon, the epitaxial region 22 may include silicon, silicon carbide, silicon phosphide, etc. In some embodiments, the material of the epitaxial region 22 in the n-type region 50N may be selected to apply tensile strain to the channel region 58. In some embodiments, the epitaxial region 22 has a thickness T1 in the range of about 3 nm to about 7 nm.

[0041] The epitaxial region 22 and / or the fin 52 may be implanted with dopants during epitaxy using an in-situ doping process. For example, a first n-type impurity may flow into a deposition chamber while the epitaxial region 22 is growing. The first n-type impurity implanted into the epitaxial region 22 may be phosphorus, arsenic, carbon, antimony, etc. For example, the epitaxial region 22 may have a dopant density of approximately 5×10 19 cm -3 About 2×10 20 cm -3 In other embodiments, the epitaxial region 22 may have a different impurity concentration. The impurity concentration in the epitaxial region 22 may remain constant throughout the epitaxial region 22 or may vary. For example, the epitaxial region 22 may have a gradient impurity concentration that increases in a direction away from the sidewall of the fin 52 where the epitaxial region 22 is grown.

[0042] exist Fig. 12A , the epitaxial growth process can continue to fill the remainder of the recess 20 with the epitaxial regions 24a and 24b. The growth of the epitaxial regions 24a and 24b can be performed in situ (e.g., in the same chamber) as the epitaxial region 22 and using the same process as the epitaxial region 22. In addition, the epitaxial regions 24a and 24b can include the same material as the epitaxial region 22, such as silicon, silicon carbide, silicon phosphide, etc. In some embodiments, the material of the epitaxial regions 24a and 24b in the n-type region 50N can be selected to apply the same type of stress (e.g., tensile) to the channel region 58 as the epitaxial region 22. In some embodiments, the epitaxial regions 24a and 24b have a combined thickness T2 in the range of about 50nm to about 70nm. The thickness T2 can be measured from the uppermost surface of the epitaxial region 24b to the lowermost point of the epitaxial region 24a.

[0043] Epitaxial region 24a, epitaxial region 24b, and / or fin 52 may be implanted with dopants using an in-situ doping process during epitaxy. For example, a second n-type impurity may flow into a deposition chamber while epitaxial region 22 is grown. The second n-type impurity implanted into epitaxial regions 24a and 24b may be phosphorus, arsenic, carbon, antimony, etc. In some embodiments, the second n-type may be an element different from the first n-type impurity implanted into epitaxial region 22. For example, in a particular embodiment, epitaxial region 22 may be implanted with arsenic, and epitaxial regions 24a and 24b may be implanted with phosphorus. In other embodiments, other combinations of n-type impurities may be used.

[0044] In addition, the dopant concentration of the second n-type impurity may be different in the epitaxial regions 24a and 24b. For example, the concentration of the second n-type impurity in the epitaxial region 24b may be greater than the second n-type impurity in the epitaxial region 24a. This may be achieved, for example, by changing the flow rate and / or concentration of the doping gas flowing into the process chamber during epitaxy. In some embodiments, the epitaxial region 24a has a dopant concentration of about 5×10 20 cm -3 to about 10 21 cm -3 The impurity concentration in the epitaxial region 24b is about 10 21 cm -3 About 3×10 21 cm -3 In other embodiments, the epitaxial regions 24a and / or 24b may have different impurity concentrations. The impurity concentration in the epitaxial regions 24a and / or 24b may remain constant throughout the respective epitaxial regions 24a / 24b, or may vary. For example, the epitaxial regions 24a / 24b may each have a gradient, impurity concentration that increases in a direction toward the top surface of the fin 52.

[0045] Thus, epitaxial source / drain regions 82 are formed. Epitaxial source / drain regions 82 include epitaxial regions 22, 24a, and 24b. Epitaxial region 22 includes a first impurity (e.g., arsenic, etc.), and epitaxial regions 24a and 24b include a second impurity (e.g., phosphorus, etc.). Epitaxial region 22 may epitaxially extend the sides and bottom of epitaxial regions 24a / 24b. Alternatively, one or more of epitaxial regions 22, 24a, or 24b may be omitted from epitaxial source / drain regions 82.

[0046] The epitaxial source / drain regions 82 may have surfaces that are raised from the corresponding surfaces of the fins 52 and may have facets. As a result of the epitaxial process used to form the epitaxial source / drain regions 82, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins 52. In some embodiments, as shown in FIG. Fig. 12BAs shown, these facets allow adjacent source / drain regions 82 of the same FinFET to merge. Fig. 12C As shown, adjacent source / drain regions 82 remain separated after the epitaxial process is completed. Fig. 12B and 12C In the illustrated embodiment, gate spacer 86 is formed to cover a portion of the sidewalls of fin 52 extending over STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacer 86 can be adjusted to remove spacer material to allow the area of ​​epitaxial growth to extend to the surface of STI region 56.

[0047] FIG. 13A to FIG. 14B An additional implantation step is shown formed on the epitaxial source / drain regions 82 after the epitaxial source / drain regions 82 are fully grown in some embodiments. Fig.13A and Fig. 13B In the embodiment of the present invention, a first implant 26 is performed on the epitaxial source / drain regions 82. The first implant 26 may be performed in-situ with the formation of the epitaxial source / drain regions 82, or may be performed ex-situ with the formation of the epitaxial source / drain regions 82.

[0048] In some embodiments, the first implant 26 implants a third n-type impurity into the epitaxial source / drain region 82. The third impurity may be selected to have a relatively low enthalpy of formation, and may be arsenic, antimony, carbon, etc. As will be explained in more detail below, due to its relatively low enthalpy of formation, the third impurity is more easily attracted to the vacancies (V) in the epitaxial source / drain region 82, and the third impurity may form an inactive cluster with the vacancies. For example, in an embodiment where the third impurity is arsenic, As4V may be formed as a relatively stable complex (e.g., deactivated from an inactive cluster). Therefore, the third impurity helps to reduce the diffusion of the fourth impurity subsequently implanted into the epitaxial source / drain region 82. For example, the vacancies in the silicon lattice are more attractive to the third impurity (e.g., arsenic) than the fourth impurity (e.g., phosphorus). Therefore, if the vacancies are consumed by forming a stable complex with the third impurity, the diffusion of the fourth impurity may be slowed down. Therefore, the source / drain contact resistance may be reduced. Furthermore, implanting the third impurity may provide improved junction abruptness and reduced diffusion compared to a junction formed by implanting only the fourth impurity described below. The third impurity implanted in the first implant 26 may be the same as or different from the first impurity in the epitaxial region 22 .

[0049] The first implant 26 may use arsenic, antimony, carbon, etc. as a doping gas. Other carrier gases (e.g., nitrogen, argon, helium, etc.) may also be present. The first implant 26 may be performed at an implant energy in the range of about 2 keV to about 20 keV (e.g., about 4 keV). The implant dose of the first implant 26 may be about 5×1014 cm -3 to about 10 22 cm -3 The implantation angle of the first implant 26 may be in the range of about 3° to about 15°, and the rotation angle of the first implant 26 may be in the range of 0° to 360°. For example, the implantation angle may refer to the angle at which the third impurity is implanted from above relative to the main surface of the substrate into the epitaxial source / drain region 82. In addition, the rotation angle may refer to the rotation of the wafer 10 around the process chamber during the first implant 26. For example, referring to Fig. 13B , showing a top-down view of the process chamber 200. The first implant 26 can be performed in the process chamber 200. The process chamber 200 includes a platen 202 that supports the wafer 10 during the first implant 26. The platen can also be connected to a motor that rotates the wafer 10 according to the rotation angle of the first implant 26 shown by arrow 28. The wafer 10 can be rotated any number of times. For example, in some embodiments, the wafer 10 is not rotated during the entire duration of the first implant 26. In other embodiments, the wafer 10 is rotated 90° twice. In other embodiments, the wafer 10 is rotated 45° four times. The angle and number of rotations of the wafer may affect the post-annealing implant profile of the complete structure (see, for example, Figures 15A to 17 ). Therefore, by adjusting the rotation angle and the rotation time during the first implant 26, different implant profiles can be obtained. Fig. 13B The process chamber 200 is shown with a particular configuration for processing a single wafer 10 , but other configurations are possible, and different numbers of wafers may be processed simultaneously in the process chamber 200 .

[0050] Next, in Fig.14A and Fig. 14B In the embodiment, a second implant 30 is performed on the epitaxial source / drain regions 82. The second implant 30 can be performed in-situ or ex-situ with the first implant 26. In some embodiments, no annealing process is performed between the first implant 26 and the second implant 30.

[0051] In some embodiments, the second implant 30 implants a fourth impurity into the epitaxial source / drain region 82. The fourth impurity is selected to have a relatively high enthalpy of formation compared to the third impurity implanted in the first implant 26. For example, the fourth impurity may include phosphorus (e.g., phosphorus dimer (P2)), etc. In some specific embodiments, the first implant 26 implants arsenic and the second implant 30 implants phosphorus dimer. Since the enthalpy of formation of the fourth impurity is relatively high compared to the third impurity, the fourth impurity is less likely to be attracted by the vacancy (V) in the epitaxial source / drain region 82. For example, the third impurity may form a stable complex with a vacancy, thereby reducing deactivation (e.g., by forming a complex of the fourth impurity and the vacancy) and diffusion of the fourth impurity. As a result, due to the higher concentration of the fourth impurity in the contact region of the epitaxial source / drain region 82 (e.g., the top portion of the epitaxial source / drain region 82), the contact resistance may be reduced. In addition, including the third impurity may provide improved junction abruptness and reduced diffusion compared to the junction formed by implanting only the fourth impurity.

[0052] The second implant 30 may use phosphorus (e.g., phosphorus dimer (P2)) or the like as a doping gas. Other carrier gases (e.g., nitrogen, argon, helium, etc.) may also be present. The second implant 30 may be performed at an implant energy in the range of about 2 keV to about 20 keV. The implant dose of the second implant 30 may be at least about 4×10 15 cm -3 , for example, at about 10 18 cm -3 to about 10 22 cm -3 range. It has been observed that by implanting the fourth impurity at a high dose (e.g., within the above range), the source / drain contact resistance can be reduced by providing increased dopants in the contact area of ​​the epitaxial source / drain region 82. The implantation angle of the second implant 30 can be in the range of about 3° to about 15°, and the rotation angle of the second implant 30 can be in the range of 0° to 360°. For example, the implantation angle can refer to the angle at which the fourth impurity is implanted into the epitaxial source / drain region 82 from above relative to the main surface of the substrate. In addition, the rotation angle can refer to the rotation of the wafer 10 around the process chamber during the second implant 30. For example, referring to Fig. 14B, showing a top-down view of the process chamber 200. The second implant 30 can be performed in the same process chamber 200 as the first implant 26. Alternatively, the second implant 30 can be performed in a different process chamber 200. The wafer 10 is rotated on the platen 202 according to the rotation angle of the second implant 30 indicated by arrow 32. The wafer 10 can be rotated any number of times. For example, in some embodiments, the wafer 10 is not rotated for the entire duration of the second implant 30. In other embodiments, the wafer 10 is rotated 90° twice during the second implant 30. In other embodiments, the wafer 10 is rotated 45° four times during the second implant 30. The angle and number of rotations of the wafer may affect the post-annealing implant profile of the complete structure (see, for example, Figures 15A to 17 ). Therefore, by adjusting the rotation angle and the rotation time during the first injection 26 and / or the second injection 30, different injection profiles can be obtained. Fig. 14B The process chamber 200 is shown with a particular configuration for processing a single wafer 10 , but other configurations are possible, and different numbers of wafers may be processed simultaneously in the process chamber 200 .

[0053] Subsequently, an annealing process may be performed to activate the third dopant and the fourth dopant. For example, in some embodiments, the annealing process may include a microsecond anneal (μSSA) followed by a laser spike anneal (LSA). In some embodiments, the junction profile of the fourth dopant (e.g., phosphorus) after the annealing process (e.g., after μSSA / LSA) may be the same as before the annealing process. Therefore, implanting low formation enthalpy elements helps to reduce diffusion during the annealing process. μSSA may be performed at a temperature in the range of about 1050°C to about 1150°C, and LSA may be performed at a temperature in the range of about 1100°C to about 1250°C. Other annealing processes may be used in other embodiments.

[0054] Fig.15A , Fig. 15B and Fig. 15C The resulting structure is shown after an annealing process in accordance with some embodiments. Fig.15A Shown along Figure 1 The structure of line BB; Fig. 15B The epitaxial source / drain region 82 is shown along Figure 1 The structure of the line CC; Fig. 15C The unmerged epitaxial source / drain regions 82 are shown along Figure 1As shown, doped regions 34 and 36 are formed at the top of the epitaxial source / drain regions 82 and the fin 52. Doped region 34 includes a third impurity having a relatively low enthalpy of formation, and doped region 36 includes a fourth impurity having a relatively high enthalpy of formation. Fig.15A , Fig. 15B and Fig. 15C In the embodiment of the present invention, the sides and bottom of the doped region 36 may be covered by the doped region 34. For example, the doped region 34 may separate the doped region 36 from the lower portion of the fin 52 and the epitaxial source / drain region 82. In addition, the doped regions 34 and 36 may further include additional impurities, such as the first and / or second impurities implanted in the epitaxial source / drain region 82 (e.g., implanted in situ into the corresponding epitaxial regions 22, 24A, and 24B). The original boundaries of the epitaxial regions 22, 24A, and 24B are shown with ghosts for reference.

[0055] The doped region 34 provides a steeper junction for improved short channel control (e.g., an improved DIBL with a channel length less than, for example, 10 nm, and reduced leakage current). For example, in experimental data, the off-current is reduced by at least 20% in the embodiment transistor in which the third impurity and the fourth impurity are implanted, compared to the transistor in which only the fourth impurity is implanted. In addition, the implantation of the third impurity reduces the diffusion of the fourth impurity and can increase the concentration of the fourth impurity in the doped region 36. Therefore, the contact resistance can be reduced. For example, in the experimental data, the source resistance (R s ) by at least 20%. For example, the additional As implant can increase Rs by 20% or more compared to a structure without such As implant.

[0056] Doped region 36 may include regions 36A, 36B, and 36C, and the dopant concentration of the fourth impurity in regions 36A, 36B, and 36C may be different. For example, the concentration of the fourth impurity in region 36B may be higher than the concentration in region 36A, and the concentration of the fourth impurity in region 36C may be higher than the concentration in region 36B. The concentration of the fourth impurity in each of regions 36A, 36B, and 36C may be variable or constant. For example, doped region 36 may have a gradient concentration of the fourth impurity that increases in a direction toward the top surface of epitaxial source / drain region 82 (as shown by arrow 38). Similarly, the concentration of the third impurity in region 34 may be constant or variable. For example, doped region 34 may have a gradient concentration of the third impurity that increases in the direction of arrow 38.

[0057] Fig.15DGraph 250 shows the concentration of impurities in epitaxial source / drain region 82 in an embodiment device, for example, along the center line of epitaxial source / drain region 82. Line 252 represents the concentration of a fourth impurity (e.g., phosphorus dimer), while line 254 represents the concentration of a third impurity (e.g., arsenic). As shown, in the contact region (e.g., doped region 36C) of epitaxial source / drain region 82, the post-annealing concentration of the fourth impurity (e.g., phosphorus dimer) may be greater than 10 22 cm -3 It has been observed that by providing a doped region with this concentration, the source / drain contact resistance is advantageously reduced. In other embodiments, other impurity concentration profiles are also possible.

[0058] As described above, the profiles of doped regions 34 and 36 may be adjusted by varying process parameters (eg, rotation angles) of implantation processes 26 and 30 . Fig.15A The profiles obtained without rotating the wafer 10 around the process chamber during the first implant process 26 and the second implant process 30 are shown. Fig.16 An alternative embodiment is shown in which the wafer 10 is rotated 90° twice during each of the first implant process 26 and the second implant process 30. Fig.16 In the present invention, similar reference numerals are used to indicate the use of Fig.15A Similar components are formed by similar processes as shown. Fig.16 As shown, doped regions 34 may be disposed on the sides of doped regions 36, and doped regions 34 may further extend under gate spacers 86 / dummy gates 72. Doped regions 36 may extend further into epitaxial source / drain regions 82 than doped regions 34. Fig.17 An alternative embodiment is shown in which the first implant 26 includes rotating the wafer 10 90° four times and the second implant 30 does not include rotating the wafer 10. Fig.17 In the present invention, similar reference numerals are used to indicate the use of Fig.15A Similar components are formed by similar processes as shown. Fig.17 As shown, the doped region 34 can be disposed on the side of the doped region 36, and the doped region 34 can further extend under the gate spacer 86 / dummy gate 72. The doped region 34 can also extend under the gate spacer 86 / dummy gate 72, and compared with the doped region 34, the doped region 36 can extend further into the epitaxial source / drain region 82. Fig.16 and Fig.17In each embodiment of the present invention, doped region 34 includes regions 34A and 34B, and the impurity concentration of the third impurity in region 34A may be greater than the impurity concentration in region 34B. The impurity concentration of each region in regions 34A and / or 34B may be constant or varied. Other configurations of doped regions 34 and 36 are also possible.

[0059] The epitaxial source / drain region 82 in the p-type region 50P may be formed by masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a recess in the fin 52. The epitaxial source / drain region 82 in the p-type region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P may include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 82 in the p-type region 50P may have a surface that protrudes from a corresponding surface of the fin 52 and may have a small facet.

[0060] exist Fig.18A and Fig.18B , depositing a first interlayer dielectric (ILD) 88. The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacer 86. The CESL 87 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having a lower etch rate than the material of the overlying first ILD 88.

[0061] exist Fig.19A and Fig.19BIn the process, a planarization process (e.g., CMP) may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and the portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0062] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in the etching step(s) to form the recess 90. The portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first region of the die (e.g., the core logic region) and remains in the recess 90 in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas (s) that selectively etches the dummy gate 72 without etching or etching less of the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. Then, the dummy dielectric layer 60 may be optionally removed after the dummy gate 72 is removed.

[0063] exist Fig.21A and Fig. 21B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed to form a replacement gate. Fig. 21C Shows Fig. 21BDetailed view of region 89 of . A gate dielectric layer 92 is deposited in the recess 90, such as on the top surface and sidewalls of the fin 52, and on the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 includes an interfacial layer of silicon oxide formed by thermal oxidation or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of the following metals: hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess 90 , the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (eg, SiO 2 ).

[0064] The gate electrode 94 is deposited on the gate dielectric layer 92 and fills the remaining portion of the recess 90. The gate electrode 94 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, and combinations thereof or multilayers thereof. Fig. 21B A single-layer gate electrode 94 is shown in FIG. 1 , but the gate electrode 94 may include any number of liner layers 94A, any number of work function tuning layers 94B, and filler materials 94C, such as Fig. 21C As shown. After filling the recess 90, a planarization process (e.g., CMP) may be performed to remove excess portions of the gate dielectric layer 92 and the material of the gate electrode 94, which are located above the top surface of the ILD 88. Thus, the gate electrode 94 and the remaining portion of the gate dielectric layer 92 form a replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack." The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0065] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, such that the gate dielectric layer 92 can be a different material, and / or the gate electrode 94 in each region can be formed by different processes, such that the gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose appropriate regions.

[0066] exist Fig.22A and Fig. 22B In the embodiment of the present invention, a gate mask 96 is formed on the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask can be disposed between the opposite portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack to form a groove directly above the gate stack and between the opposite portions of the gate spacers 86. The gate mask 96 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxide, etc.) is filled in the groove, and then a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 88.

[0067] Also like Fig.22A and Fig. 22B As shown, the second ILD 108 is deposited on the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD and PECVD. The gate contact 110 ( Fig.23A and Fig. 23B ) passes through the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0068] exist Fig.23A and Fig. 23BIn the embodiment, according to some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown) (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. As a result of the first implantation process 26 and the second implantation process 30, the concentration of the fourth impurity (e.g., phosphorus dimer, etc.) may be increased in the region where the source / drain contact 112 is connected to the epitaxial source / drain region 82. As a result, the contact resistance of the source / drain contact 112 may be advantageously reduced. The source / drain contact 112 and the gate contact 110 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contact 112 and the gate contact 110 may be formed in different cross sections, which may avoid shorting of the contacts.

[0069] The disclosed FinFET embodiments may also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, wraparound structures, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. A dummy gate stack and source / drain regions are formed in a manner similar to the above-described embodiments. After removing the dummy gate stack, the sacrificial layer in the channel region may be partially or completely removed. A replacement gate structure is formed in a manner similar to the above-described embodiments, the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contact portions of the replacement gate structure and the source / drain region may be formed in a manner similar to the above-described embodiments. A nanostructured device as disclosed in U.S. Patent Application Publication No. 2016 / 0365414 may be formed, the entire contents of which are incorporated herein by reference.

[0070] Various embodiments include injecting two different types of dopants into the source / drain region for improved junction mutation (e.g., reduced leakage current) and reduced source / drain contact resistance. In an embodiment method, a first dopant is injected into the source / drain region and then a second dopant is injected. The first dopant may have a lower enthalpy of formation than the second dopant. For example, the first dopant may include arsenic, carbon, antimony, etc., and the second dopant may include phosphorus, etc. In a specific embodiment, arsenic is injected into the source / drain region and then a phosphorus dimer (P2) is injected. Due to its lower enthalpy of formation, the first dopant is more easily attracted to vacancies in the source / drain region and forms a more stable bond with the vacancies. For example, the first dopant can be used to reduce the diffusion of the second dopant and reduce the bonding of the second dopant to the vacancies. By reducing the diffusion of the second dopant, a higher concentration of the second dopant can be obtained in the contact region of the source / drain region, thereby reducing the source / drain contact resistance. In addition, using two different elements as dopants allows for a junction with improved abruptness and less diffusion, thereby providing improved short channel control (e.g., to combat the effects of drain-induced barrier lowering (DIBL) in advanced process nodes), reduced leakage, and improved device performance. Various embodiments may provide one or more of the following non-limiting advantages: improved junction abruptness, reduced diffusion of the second dopant, and reduced source / drain contact resistance.

[0071] According to some embodiments, a method includes: forming a source / drain region in a semiconductor fin; after forming the source / drain region, implanting a first impurity into the source / drain region; after implanting the first impurity, implanting a second impurity into the source / drain region, wherein the first impurity has a lower enthalpy of formation than the second impurity; and after implanting the second impurity, annealing the source / drain region. In some embodiments, the first impurity includes arsenic, antimony, or carbon. In some embodiments, the second impurity includes phosphorus. In some embodiments, implanting the second impurity into the source / drain region includes: implanting a phosphorus dimer into the source / drain region. In some embodiments, forming the source / drain region includes: etching a recess in the semiconductor fin; epitaxially growing a first epitaxial region in the recess; in-situ doping the first epitaxial region with a third impurity while epitaxially growing the first epitaxial region; epitaxially growing a second epitaxial region in the recess and on the first epitaxial region; and in-situ doping the second epitaxial region with a fourth impurity while epitaxially growing the second epitaxial region, wherein the third impurity is an element different from the fourth impurity. In some embodiments, the third impurity is the same element as the first impurity. In some embodiments, annealing the source / drain region comprises: performing a microsecond anneal (μSSA) on the source / drain region; and performing a laser spike anneal (LSA) on the source / drain region after performing the μSSA.

[0072] According to some embodiments, a method includes: etching a recess in a semiconductor fin; epitaxially growing a source / drain region in the recess; after epitaxially growing the source / drain region, implanting the source / drain region with arsenic; after implanting the source / drain region with arsenic, implanting the source / drain region with a phosphorus dimer; after implanting the source / drain region with the phosphorus dimer, activating the arsenic and the phosphorus dimer using an annealing process. In some embodiments, implanting the source / drain region with the phosphorus dimer includes using a 18 cm -3 Up to 10 22 cm -3 In some embodiments, no annealing process is performed between implanting the source / drain region with arsenic and implanting the source / drain region with phosphorus dimer. In some embodiments, implanting the source / drain region with arsenic includes rotating the wafer containing the semiconductor fin by 90° twice. In some embodiments, implanting the source / drain region with arsenic includes rotating the wafer containing the semiconductor fin by 45° four times. In some embodiments, implanting the source / drain region with arsenic includes not rotating the wafer containing the semiconductor fin during the entire duration of implanting the source / drain region with arsenic.

[0073] According to some embodiments, a device includes: a semiconductor substrate; a gate stack located at the top surface of the semiconductor substrate; a source / drain region adjacent to the gate stack, wherein the source / drain region includes a first epitaxial region including a first impurity; a first doped region including a second impurity in the first epitaxial region; and a second doped region including a third impurity in the first epitaxial region, the second impurity having a lower enthalpy of formation than the third impurity, and the first doped region surrounds the side of the second doped region. In some embodiments, the source / drain region further includes a second epitaxial region surrounding the first epitaxial region, wherein the second epitaxial region includes a fourth impurity, and the fourth impurity is an element different from the first impurity. In some embodiments, the second doped region extends to below the first doped region. In some embodiments, the first doped region covers the bottom of the second doped region. In some embodiments, the second impurity is arsenic, and the third impurity is phosphorus. In some embodiments, the concentration of the third impurity increases in a direction toward the top surface of the source / drain region. In some embodiments, it also includes: a source / drain contact extending to the second doped region, wherein the concentration of the third impurity at the source / drain contact is at least 10 23 cm -3 .

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0075] Example 1 is a method for forming a semiconductor device, comprising: forming a source / drain region in a semiconductor fin; after forming the source / drain region, injecting a first impurity into the source / drain region; after injecting the first impurity, injecting a second impurity into the source / drain region, wherein the first impurity has a lower formation enthalpy than the second impurity; and after injecting the second impurity, annealing the source / drain region.

[0076] Example 2 is the method of Example 1, wherein the first impurity comprises arsenic, antimony, or carbon.

[0077] Example 3 is the method of Example 1, wherein the second impurity includes phosphorus.

[0078] Example 4 is the method of Example 3, wherein injecting the second impurity into the source / drain region includes injecting a phosphorus dimer into the source / drain region.

[0079] Example 5 is the method described in Example 1, wherein forming the source / drain region includes: etching a groove in the semiconductor fin; epitaxially growing a first epitaxial region in the groove; in-situ doping the first epitaxial region with a third impurity while epitaxially growing the first epitaxial region; epitaxially growing a second epitaxial region in the groove and on the first epitaxial region; and in-situ doping the second epitaxial region with a fourth impurity while epitaxially growing the second epitaxial region, wherein the third impurity is an element different from the fourth impurity.

[0080] Example 6 is the method of Example 5, wherein the third impurity is the same element as the first impurity.

[0081] Example 7 is the method of Example 1, wherein annealing the source / drain region comprises: performing a microsecond anneal (μSSA) on the source / drain region; and after performing the μSSA, performing a laser spike anneal (LSA) on the source / drain region.

[0082] Example 8 is a method for forming a semiconductor device, comprising: etching a groove in a semiconductor fin; epitaxially growing a source / drain region in the groove; after epitaxially growing the source / drain region, implanting arsenic into the source / drain region; after implanting the source / drain region with arsenic, implanting the source / drain region with a phosphorus dimer; after implanting the source / drain region with the phosphorus dimer, activating the arsenic and the phosphorus dimer using an annealing process.

[0083] Example 9 is the method of Example 8, wherein implanting the source / drain region with a phosphorus dimer comprises using 18 cm -3 Up to 10 22 cm -3 The implantation dose is within the range of

[0084] Example 10 is the method of Example 8, wherein no annealing process is performed between implanting the source / drain region with arsenic and implanting the source / drain region with phosphorus dimer.

[0085] Example 11 is the method of Example 8, wherein implanting the source / drain regions with arsenic includes rotating a wafer including the semiconductor fins 90° twice.

[0086] Example 12 is the method of Example 8, wherein implanting the source / drain regions with arsenic includes rotating a wafer including the semiconductor fins by 45° four times.

[0087] Example 13 is the method of Example 8, wherein implanting the source / drain regions with arsenic includes not rotating the wafer containing the semiconductor fins for the entire duration of implanting the source / drain regions with arsenic.

[0088] Example 14 is a semiconductor device comprising: a semiconductor substrate; a gate stack located at the top surface of the semiconductor substrate; a source / drain region adjacent to the gate stack, wherein the source / drain region comprises a first epitaxial region comprising a first impurity; a first doped region comprising a second impurity in the first epitaxial region; and a second doped region comprising a third impurity in the first epitaxial region, the second impurity having a lower enthalpy of formation than the third impurity, and the first doped region surrounds the side of the second doped region.

[0089] Example 15 is the device of Example 14, wherein the source / drain region further includes a second epitaxial region surrounding the first epitaxial region, wherein the second epitaxial region includes a fourth impurity, and the fourth impurity is an element different from the first impurity.

[0090] Example 16 is the device of Example 14, wherein the second doped region extends below the first doped region.

[0091] Example 17 is the device of Example 14, wherein the first doped region covers a bottom of the second doped region.

[0092] Example 18 is the device of Example 14, wherein the second impurity is arsenic and the third impurity is phosphorus.

[0093] Example 19 is the device of Example 14, wherein a concentration of the third impurity increases in a direction toward a top surface of the source / drain region.

[0094] Example 20 is the device of Example 14, further comprising: a source / drain contact extending to the second doped region, wherein the concentration of the third impurity at the source / drain contact is at least 10 23 cm -3 .

Claims

1. A method for forming a semiconductor device, comprising: forming source / drain regions in the semiconductor fin; After forming the source / drain region, implanting a first impurity into the source / drain region; After implanting the first impurity, implanting a second impurity into the source / drain region, wherein the first impurity has a lower enthalpy of formation than the second impurity; and After implanting the second impurity, annealing the source / drain region, Wherein, forming the source / drain region comprises: etching a recess in the semiconductor fin; epitaxially growing a first epitaxial region in the groove; In-situ doping the first epitaxial region with a third impurity during epitaxial growth of the first epitaxial region; epitaxially growing a second epitaxial region in the recess and over the first epitaxial region; and When epitaxially growing the second epitaxial region, the second epitaxial region is in-situ doped with a fourth impurity, wherein the third impurity is an element different from the fourth impurity.

2. The method according to claim 1, wherein: The first impurity includes arsenic, antimony or carbon.

3. The method according to claim 1, wherein: The second impurity includes phosphorus.

4. The method according to claim 3, wherein: Implanting the second impurity into the source / drain region includes implanting a phosphorus dimer into the source / drain region.

5. The method according to claim 1, wherein: The third impurity is the same element as the first impurity.

6. The method according to claim 1, wherein: Annealing the source / drain region includes: performing a microsecond annealing μSSA on the source / drain region; and After performing the μSSA, a laser spike annealing LSA is performed on the source / drain regions.

7. A method for forming a semiconductor device, comprising: etching grooves in semiconductor fins; epitaxially growing a source / drain region in the groove; After epitaxially growing the source / drain regions, implanting the source / drain regions with arsenic; After implanting the source / drain region with arsenic, implanting the source / drain region with phosphorus dimer; After implanting the source / drain region with phosphorus dimer, activating the arsenic and the phosphorus dimer with an annealing process, Wherein, epitaxially growing the source / drain region comprises: epitaxially growing a first epitaxial region in the groove; In-situ doping the first epitaxial region with a first impurity during epitaxial growth of the first epitaxial region; epitaxially growing a second epitaxial region in the recess and over the first epitaxial region; and When epitaxially growing the second epitaxial region, the second epitaxial region is in-situ doped with a second impurity, wherein the first impurity is an element different from the second impurity.

8. The method according to claim 7, wherein: Implanting the source / drain region with phosphorus dimers includes using a 10 18 cm -3 Up to 10 22 cm -3 The implantation dose is within the range of 9. The method according to claim 7, wherein: No annealing process is performed between implanting the source / drain regions with arsenic and implanting the source / drain regions with phosphorus dimer.

10. The method according to claim 7, wherein: Implanting the source / drain regions with arsenic includes rotating the wafer including the semiconductor fins 90° twice.

11. The method according to claim 7, wherein: Implanting the source / drain regions with arsenic includes rotating the wafer including the semiconductor fins by 45° four times.

12. The method according to claim 7, wherein: Implanting the source / drain regions with arsenic includes not rotating the wafer including the semiconductor fins for the entire duration of implanting the source / drain regions with arsenic.

13. A semiconductor device comprising: Semiconductor substrate; a gate stack located at a top surface of the semiconductor substrate; a source / drain region adjacent to the gate stack, wherein the source / drain region includes a first epitaxial region including a first impurity; a first doped region, comprising a second impurity in the first epitaxial region; and a second doped region, comprising a third impurity in the first epitaxial region, the second impurity having a lower formation enthalpy than the third impurity, the first doped region surrounding a side surface of the second doped region, The source / drain region further includes a second epitaxial region surrounding the first epitaxial region, wherein the second epitaxial region includes a fourth impurity, and the fourth impurity is an element different from the first impurity.

14. The device according to claim 13, wherein The second doped region extends below the first doped region.

15. The device according to claim 13, wherein The first doped region covers a bottom of the second doped region.

16. The device according to claim 13, wherein The second impurity is arsenic, and the third impurity is phosphorus.

17. The device according to claim 13, wherein: The concentration of the third impurity increases in a direction toward a top surface of the source / drain region.

18. The device according to claim 13, further comprising: A source / drain contact portion extending to the second doped region, wherein the concentration of the third impurity at the source / drain contact portion is at least 10 23 cm -3 .

Images