Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a memory cell capacitor for storing data. The memory cell capacitor includes a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate, an upper support pattern on an upper side surface of the plurality of bottom electrodes, and a lower support pattern on a lower side surface of the plurality of bottom electrodes. The lower support pattern is disposed between the substrate and the upper support pattern, a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0018452, filed on February 14, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a capacitor. Background Technology

[0004] As semiconductor devices become increasingly highly integrated, it is desirable for capacitors to have high capacitance within a limited area. The capacitance of a capacitor is directly proportional to the surface area of ​​the electrodes and the dielectric constant of the dielectric layer, and inversely proportional to the equivalent oxide thickness of the dielectric layer. The higher the aspect ratio of the bottom electrode of the capacitor, the greater the capacitance. Therefore, various processing techniques for forming capacitors with high aspect ratios have been studied. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a semiconductor device with improved electrical characteristics and a method for manufacturing the same.

[0006] Some exemplary embodiments of the present invention provide a highly integrated semiconductor device and a method for manufacturing the same.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes a memory cell capacitor for storing data. The memory cell capacitor includes: a plurality of bottom electrodes located on a substrate and extending in a vertical direction relative to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate; an upper support pattern located on an upper surface of the plurality of bottom electrodes; and a lower support pattern located on a lower surface of the plurality of bottom electrodes. The lower support pattern is disposed between the substrate and the upper support pattern, and a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to the bottom surface of the lower support pattern.

[0008] According to an example embodiment of the present invention, a semiconductor device includes: a plurality of bottom electrodes located on a substrate and extending in a vertical direction with respect to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate; a lower support pattern located on a lower side surface of the plurality of bottom electrodes; an upper support pattern located on the lower support pattern and on an upper side surface of the plurality of bottom electrodes; a top electrode filling a space between the plurality of bottom electrodes, a space between the substrate and the lower support pattern, and a space between the lower support pattern and the upper support pattern; and a dielectric layer located between the top electrode and each of the upper support pattern and the lower support pattern, and between the top electrode and each of the plurality of bottom electrodes. A first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern and a second recess adjacent to a top surface of the lower support pattern.

[0009] According to an example embodiment of the present invention, a method of manufacturing a semiconductor device includes: sequentially forming a first mold layer, a lower support layer, a second mold layer, and an upper support layer on a substrate; forming a plurality of bottom electrodes penetrating the first mold layer, the lower support layer, the second mold layer, and the upper support layer on the substrate; patterning the upper support layer to form an upper support pattern having at least one upper opening; removing the second mold layer via the at least one upper opening to partially expose an upper side surface of the plurality of bottom electrodes; patterning the lower support layer to form a lower support pattern having at least one lower opening; removing at least a portion of the first mold layer via the at least one lower opening to partially expose a lower side surface of the plurality of bottom electrodes; and after the removing of the at least a portion of the first mold layer, etching the exposed lower side surface of the plurality of bottom electrodes and the exposed upper side surface of the plurality of bottom electrodes. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A plan view of a semiconductor device according to some example embodiments of inventive concepts is shown.

[0011] Figure 2 A cross-sectional view taken along line I-I’ of Figure 1 is shown.

[0012] Figure 3A and Figure 3B Enlarged views of portions R1 and R2, respectively, of Figure 2 are shown.

[0013] Figures 4-9 and Figure 11 A cross-sectional view taken along line I-I’ of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts is shown. Figure 1 is shown.

[0014] Figure 10A and Figure 10Benlarged view of the portion R3 and the portion R4 of Figure 9

[0015] Figure 12 and Figure 13 shows a cross-sectional view taken along the line I-I' of the method of manufacturing a semiconductor device presenting some example embodiments in accordance with the inventive concept. Figure 1

[0016] Figure 14 shows a cross-sectional view taken along the line I-I' of the semiconductor device presenting some example embodiments in accordance with the inventive concept. Figure 1

[0017] Figure 15 shows an enlarged view of the portion R5 of Figure 14

[0018] Figures 16-21 shows a cross-sectional view taken along the line I-I' of the method of manufacturing a semiconductor device presenting some example embodiments in accordance with the inventive concept. Figure 1

[0019] Figure 22 shows a cross-sectional view taken along the line I-I' of the semiconductor device presenting some example embodiments in accordance with the inventive concept. Figure 1

[0020] Figure 23 shows a circuit diagram of a unit memory cell of the semiconductor device presenting some example embodiments in accordance with the inventive concept.

[0021] Figure 24 shows a plan view of the semiconductor device partially presenting some example embodiments in accordance with the inventive concept.

[0022] Figure 25 shows a cross-sectional view taken along the line II-II' of Figure 24 DETAILED DESCRIPTION

[0023] Some example embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings.

[0024] Figure 1 shows a plan view of the semiconductor device presenting some example embodiments in accordance with the inventive concept. Figure 2 shows a cross-sectional view taken along the line I-I' of Figure 1 Figure 3A and Figure 3B shows an enlarged view of the portion R1 and the portion R2 of Figure 2

[0025] Referring to​​​​​​​​​Figure 1 and Figure 2 An interlayer dielectric layer 102 can be disposed on the substrate 100. The substrate 100 can include a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. The interlayer dielectric layer 102 can include at least one selected, for example, from silicon oxide, silicon nitride, and silicon oxynitride.

[0026] Conductive contacts 110 and contact pads 115 can be disposed in the interlayer dielectric layer 102. Each of the conductive contacts 110 can penetrate a lower portion of the interlayer dielectric layer 102 and can be electrically connected with the substrate 100. The contact pads 115 can be disposed on corresponding conductive contacts 110. The contact pads 115 can penetrate an upper portion of the interlayer dielectric layer 102 and can be electrically connected with corresponding conductive contacts 110. The conductive contacts 110 and the contact pads 115 can include at least one selected from a semiconductor material (e.g., polysilicon), a metal semiconductor compound (e.g., tungsten silicide), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), and a metal (e.g., titanium, tungsten, and / or tantalum).

[0027] An insulating layer 120 can be disposed on the interlayer dielectric layer 102. The insulating layer 120 can cover at least a portion of a top surface of the interlayer dielectric layer 102 and at least some portions of top surfaces of the contact pads 115. For example, the insulating layer 120 can contact at least a portion of a top surface of the interlayer dielectric layer 102 and at least some portions of top surfaces of the contact pads 115. The insulating layer 120 can include at least one selected, for example, from oxides, nitrides, and oxynitrides.

[0028] A plurality of bottom electrodes BE can be disposed to be horizontally spaced apart from each other on the interlayer dielectric layer 102. For example, the plurality of bottom electrodes BE can be spaced apart from each other along a first direction D1 parallel to a top surface 100U of the substrate 100. The plurality of bottom electrodes BE can penetrate the insulating layer 120 and can be connected with corresponding contact pads 115. According to some example embodiments, each of the plurality of bottom electrodes BE can have a column shape.

[0029] The lower support pattern 130L can be disposed on the lower side surfaces (i.e., the first portions of the side surfaces) of the plurality of bottom electrodes BE. The lower support pattern 130L can contact the lower side surfaces of the plurality of bottom electrodes BE. The lower support pattern 130L can be vertically spaced apart from the interlayer dielectric layer 102 and the insulating layer 120 along the second direction D2 perpendicular to the top surface 100U of the substrate 100. The lower support pattern 130L can have at least one lower opening 180L. In an example embodiment, the plurality of bottom electrodes BE can include a plurality of first bottom electrodes BE1 exposed by the at least one lower opening 180L and a plurality of second bottom electrodes BE2 surrounded by the lower support pattern 130L. For example, the lower side surfaces of the plurality of first bottom electrodes BE1 can be partially exposed by the lower opening 180L and partially covered by the lower support pattern 130L, and the lower side surfaces of the plurality of second bottom electrodes BE2 can be surrounded by the lower support pattern 130L. When viewed in a planar view, the at least one lower opening 180L can extend along a third direction D3 parallel to the top surface 100U of the substrate 100 and intersecting the first direction D1, and can also extend along the lower side surfaces of the plurality of first bottom electrodes BE1. In an embodiment, the first direction D1 and the third direction D3 can form an acute angle therebetween. According to some example embodiments, the lower support pattern 130L can have a plurality of lower openings 180L horizontally spaced apart from each other. Each of the plurality of lower openings 180L can extend along the lower side surfaces of a corresponding ones of the plurality of first bottom electrodes BE1.

[0030] The upper support pattern 130U can be disposed on the upper side surfaces (i.e., the second portions of the side surfaces) of the plurality of bottom electrodes BE. The upper support pattern 130U can contact the upper side surfaces of the plurality of bottom electrodes BE. The upper support pattern 130U can be vertically spaced apart from the lower support pattern 130L along the second direction D2. The upper support pattern 130U can have at least one upper opening 180U. In an example embodiment, the plurality of first bottom electrodes BE1 can be exposed by the at least one upper opening 180U, and the plurality of second bottom electrodes BE2 can be surrounded by the upper support pattern 130U. For example, the upper side surfaces of the plurality of first bottom electrodes BE1 can be partially exposed by the upper opening 180U and partially covered by the upper support pattern 130U, and the upper side surfaces of the plurality of second bottom electrodes BE2 can be surrounded by the upper support pattern 130U. When viewed in a planar view, the at least one upper opening 180U can extend along the third direction D3, and can also extend along the upper side surfaces of the plurality of first bottom electrodes BE1. The at least one upper opening 180U can vertically overlap the at least one lower opening 180L along the second direction D2. According to some example embodiments, the upper support pattern 130U can have a plurality of upper openings 180U that are horizontally spaced apart from each other. Each of the plurality of upper openings 180U can extend along the upper side surfaces of a corresponding number of first bottom electrodes BE1 of the plurality of first bottom electrodes BE1. The plurality of upper openings 180U can vertically overlap the plurality of lower openings 180L, respectively, along the second direction D2.

[0031] The plurality of bottom electrodes BE can penetrate the upper support pattern 130U, the lower support pattern 130L, and the insulating layer 120, and can be connected with the corresponding contact pads 115. The uppermost surface BE_U of each of the plurality of bottom electrodes BE can be located at substantially the same height as the height of the top surface 130UU of the upper support pattern 130U, although the inventive concepts need not be limited thereto. Unlike as shown, the uppermost surface BE_U of each of the plurality of bottom electrodes BE can be located at a height lower than the height of the top surface 130UU of the upper support pattern 130U. In the present disclosure, the term "height" can be a distance measured from the top surface 100U of the substrate 100. Terms such as "same," "equal," "planar," or "co-planar" as used herein encompass approximately the same including variations that can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to emphasize this meaning, unless otherwise indicated by context or other statement.

[0032] The top electrode TE can be disposed on the interlayer dielectric layer 102 and can cover the plurality of bottom electrodes BE, the lower support pattern 130L, and the upper support pattern 130U. The top electrode TE can fill spaces between the plurality of bottom electrodes BE, spaces between the interlayer dielectric layer 102 and the lower support pattern 130L, and spaces between the lower support pattern 130L and the upper support pattern 130U. The insulating layer 120 can be interposed between the top electrode TE and the interlayer dielectric layer 102. The top electrode TE can penetrate the upper support pattern 130U and the lower support pattern 130L by passing through the at least one upper opening 180U and the at least one lower opening 180L. The top electrode TE can penetrate the upper support pattern 130U and the lower support pattern 130L by filling the at least one upper opening 180U and the at least one lower opening 180L. For example, the top electrode TE can completely fill the at least one upper opening 180U and the at least one lower opening 180L.

[0033] The dielectric layer 140 can be interposed between the top electrode TE and each of the plurality of bottom electrodes BE, between the top electrode TE and the lower support pattern 130L, and between the top electrode TE and the upper support pattern 130U. The dielectric layer 140 can extend between the top electrode TE and the insulating layer 120. The dielectric layer 140 can space the plurality of bottom electrodes BE from the top electrode TE.

[0034] The plurality of bottom electrodes BE and the top electrode TE can include at least one selected from polysilicon, metal, metal silicide, and metal nitride. The dielectric layer 140 can include at least one selected from oxide (e.g., a silicon oxide layer), nitride (e.g., a silicon nitride layer), oxynitride (e.g., a silicon oxynitride layer), and high-K dielectric (e.g., a hafnium oxide layer). Each of the lower support pattern 130L and the upper support pattern 130U can include a dielectric material. For example, each of the lower support pattern 130L and the upper support pattern 130U can include at least one selected from oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride). In an exemplary embodiment, the lower support pattern 130L and the upper support pattern 130U can be formed of the same material or different materials from each other. Hereinafter, the reference numeral "BE" can be used collectively to describe side surfaces of the plurality of first bottom electrodes BE1 and side surfaces of the plurality of second bottom electrodes BE2.

[0035] Referring to Figure 2 and Figure 3AAt least one of the plurality of bottom electrodes BE can include a first recess 150a adjacent to a bottom surface 130LL of the lower support pattern 130L. The first recess 150a can be a region recessed into the at least one bottom electrode BE from a side surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the bottom surface 130LL of the lower support pattern 130L and can fill at least a portion of the first recess 150a. The at least one bottom electrode BE can further include a second recess 150b adjacent to a top surface 130LU of the lower support pattern 130L. The second recess 150b can be a region recessed into the at least one bottom electrode BE from a side surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the top surface 130LU of the lower support pattern 130L and can fill at least a portion of the second recess 150b.

[0036] The at least one bottom electrode BE can include a first portion P1 in the lower support pattern 130L and a second portion P2 below the lower support pattern 130L. A maximum width W2 of the second portion P2 of the at least one bottom electrode BE can be greater than a maximum width W1 of the first portion P1 of the at least one bottom electrode BE. In the disclosure, the term "width" can be a distance measured in a direction parallel to the top surface 100U of the substrate 100 (e.g., the first direction D1). The at least one bottom electrode BE can include a third portion P3 between the upper support pattern 130U and the lower support pattern 130L. A maximum width W3 of the third portion P3 of the at least one bottom electrode BE can be greater than the maximum width W1 of the first portion P1 of the at least one bottom electrode BE. The first recess 150a can be located at a boundary between the first portion P1 and the second portion P2 of the at least one bottom electrode BE. The second recess 150b can be located at a boundary between the first portion P1 and the third portion P3 of the at least one bottom electrode BE. In an exemplary embodiment, the first portion P1 of the at least one bottom electrode BE can include a first part in contact with the lower support pattern 130L. The first part of the first portion P1 can be disposed between the first recess 150a and the second recess 150b. The first portion P1 of the at least one bottom electrode BE can further include a second part spaced apart from the lower support pattern 130L, and a portion of the dielectric layer 140 fills the first recess 150a between the second part and the lower support pattern 130L. The first portion P1 of the at least one bottom electrode BE can further include a third part spaced apart from the lower support pattern 130L, and a portion of the dielectric layer 140 fills the second recess 150b between the third part and the lower support pattern 130L.

[0037] Referring to Figure 2 and Figure 3BThe at least one bottom electrode BE can further include a third recess 150c adjacent to a bottom surface 130UL of the upper support pattern 130U. The third recess 150c can be a region recessed into the at least one bottom electrode BE from a side surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the bottom surface 130UL of the upper support pattern 130U and can fill at least a portion of the third recess 150c. The at least one bottom electrode BE can further include a fourth recess 150d adjacent to a top surface 130UU of the upper support pattern 130U. The fourth recess 150d can be a region recessed into the at least one bottom electrode BE from a top surface BE_U of the at least one bottom electrode BE. The fourth recess 150d can expose a boundary between the at least one bottom electrode BE and the upper support pattern 130U. The dielectric layer 140 can cover the top surface 130UU of the upper support pattern 130U and can fill at least a portion of the fourth recess 150d.

[0038] The at least one bottom electrode BE can include a fourth portion P4 in the upper support pattern 130U. A maximum width W3 of the third portion P3 of the at least one bottom electrode BE can be greater than a maximum width W4 of the fourth portion P4 of the at least one bottom electrode BE. The third recess 150c can be located at a boundary between the third portion P3 and the fourth portion P4 of the at least one bottom electrode BE. The fourth recess 150d can be disposed along a rounded corner of the top surface BE_U of the at least one bottom electrode BE. In an exemplary embodiment, the fourth portion P4 of the at least one bottom electrode BE can include a first portion contacting the upper support pattern 130U. The first portion of the fourth portion P4 can be disposed between the third recess 150c and the fourth recess 150d. The fourth portion P4 of the at least one bottom electrode BE can further include a second portion spaced apart from the upper support pattern 130U, and a portion of the dielectric layer 140 fills the third recess 150c between the second portion and the upper support pattern 130U. The fourth portion P4 of the at least one bottom electrode BE can further include a third portion spaced apart from the upper support pattern 130U, and a portion of the dielectric layer 140 fills the fourth recess 150d between the third portion and the upper support pattern 130U.

[0039] Referring back to Figure 1 and Figure 2 The capacitor can be composed of the plurality of bottom electrodes BE, the lower support pattern 130L, the upper support pattern 130U, the top electrode TE, and the dielectric layer 140.

[0040] The plurality of bottom electrodes BE can each have a relatively large aspect ratio to increase the capacitance of the capacitor, and the lower support pattern 130L and the upper support pattern 130U can be used to ensure structural stability of the plurality of bottom electrodes BE. In this case, during a process of forming the plurality of bottom electrodes BE, the plurality of bottom electrodes BE can be formed to have their relatively large widths between the upper support pattern 130U and the lower support pattern 130L and below the lower support pattern 130L, which can cause a leakage current between adjacent bottom electrodes BE.

[0041] According to the present inventive concept, between the upper support pattern 130U and the lower support pattern 130L and below the lower support pattern 130L, an etching process can be performed to partially etch side surfaces of the plurality of bottom electrodes BE. The etching process can reduce the widths of the plurality of bottom electrodes BE, and as a result, can minimize the leakage current between the plurality of bottom electrodes BE. In addition, during the etching process, at least one bottom electrode BE can be formed to include the first recess 150a, the second recess 150b, the third recess 150c, and the fourth recess 150d.

[0042] Figures 4-9 and Figure 11 A cross-sectional view taken along line I-I' of a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept is shown. Figure 1 Figure 10A and Figure 10B An enlarged view of portions R3 and R4 of Figure 9 , respectively, is shown. For the sake of brevity, the description of the semiconductor device discussed above with reference to Figure 1 , Figure 2 , Figure 3A and Figure 3B will be omitted.

[0043] With reference to Figure 4 , an interlayer dielectric layer 102 can be formed on the substrate 100, and a conductive contact 110 and a contact pad 115 can be formed in the interlayer dielectric layer 102. Forming the conductive contact 110 and the contact pad 115 can include forming a contact hole (not shown) to penetrate a lower portion of the interlayer dielectric layer 102, forming a pad hole (not shown) to penetrate an upper portion of the interlayer dielectric layer 102, and forming a conductive layer to fill the contact hole and the pad hole.

[0044] ​An insulating layer 120 can be formed on the interlayer dielectric layer 102, and then the first mold layer 162, the lower support layer 132, the second mold layer 164, and the upper support layer 134 can be sequentially formed on the insulating layer 120. The first mold layer 162 and the second mold layer 164 can be formed of, for example, a silicon oxide layer. The insulating layer 120, the lower support layer 132, and the upper support layer 134 can be formed of a material having etching selectivity with respect to the first mold layer 162 and the second mold layer 164. For example, the insulating layer 120, the lower support layer 132, and the upper support layer 134 can include at least one selected from SiN, SiCN, TaO, and TiO2. The upper support layer 134 can be formed to have a thickness substantially the same as or greater than that of the lower support layer 132. In the present disclosure, the term "thickness" can be a distance measured in a direction perpendicular to the top surface 100U of the substrate 100 (e.g., the second direction D2). A deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) can be performed to form each of the insulating layer 120, the first mold layer 162, the lower support layer 132, the second mold layer 164, and the upper support layer 134.

[0045] Referring to Figure 5 Vertical holes 170 can be formed in the stacked layers 120, 162, 132, 164, and 134. Each of the vertical holes 170 can penetrate the upper support layer 134, the second mold layer 164, the lower support layer 132, the first mold layer 162, and the insulating layer 120, and can expose a corresponding one of the contact pads 115. The vertical holes 170 can be horizontally spaced apart from each other on the interlayer dielectric layer 102. For example, forming the vertical holes 170 can include forming a mask pattern (not shown) having a plurality of openings on the upper support layer 134 to define regions in which the vertical holes 170 are to be formed, and sequentially etching the upper support layer 134, the second mold layer 164, the lower support layer 132, the first mold layer 162, and the insulating layer 120 using the mask pattern as an etching mask.

[0046] For example, a dry etching process can be employed to etch the upper support layer 134, the second molding layer 164, the lower support layer 132, the first molding layer 162, and the insulating layer 120. In the dry etching process, a bending phenomenon caused by ion dispersion can occur, such that the vertical holes 170 can be defined by concave side surfaces of the first and second molding layers 162 and 164. In some example embodiments, during the dry etching process, the first and second molding layers 162 and 164 can be etched more than the upper and lower support layers 134 and 132, and thus each of the vertical holes 170 can be formed to have a relatively large width in the first and second molding layers 162 and 164. For example, each of the vertical holes 170 formed in the lower support layer 132 can have a first maximum width 170W1, each of the vertical holes 170 formed in the first molding layer 162 can have a second maximum width 170W2 that is greater than the first maximum width 170W1. Each of the vertical holes 170 formed in the second molding layer 164 can have a third maximum width 170W3 that is greater than the first maximum width 170W1, and each of the vertical holes 170 formed in the upper support layer 134 can have a fourth maximum width 170W4 that is less than the third maximum width 170W3.

[0047] Referring to Figure 6 A plurality of bottom electrodes BE can be formed in the vertical holes 170. For example, forming the bottom electrodes BE can include forming a bottom electrode layer on the upper support layer 134 to fill the vertical holes 170, and planarizing the bottom electrode layer until the upper support layer 134 is exposed. The bottom electrodes BE can be horizontally spaced apart from each other on the interlayer dielectric layer 102, and can be connected to the contact pads 115. When the vertical holes 170 have side surfaces caused by the bending phenomenon as discussed with reference to Figure 5 When the vertical holes 170 have side surfaces caused by the bending phenomenon as discussed with reference to

[0048] Referring to Figure 1 and Figure 7The upper support layer 134 can be patterned to form an upper support pattern 130U having at least one upper opening 180U. The at least one upper opening 180U can expose upper side surfaces of the plurality of first bottom electrodes BE1 and can also expose a top surface of the second mold layer 164. The second mold layer 164 can be removed through the at least one upper opening 180U. Removing the second mold layer 164 can include selectively etching the second mold layer 164 relative to the upper support pattern 130U and the lower support layer 132. For example, the second mold layer 164 can be removed by performing an isotropic etch process using phosphoric acid. Removing the second mold layer 164 can partially expose a top surface of the lower support layer 132 and upper side surfaces of the bottom electrodes BE.

[0049] Referring to Figure 1 and Figure 8 The lower support layer 132 can be patterned to form a lower support pattern 130L having at least one lower opening 180L. The at least one lower opening 180L can expose lower side surfaces of the plurality of first bottom electrodes BE1 and can also expose a top surface of the first mold layer 162. An upper portion of the first mold layer 162 can be removed through the at least one lower opening 180L. Removing the upper portion of the first mold layer 162 can include selectively etching the first mold layer 162 relative to the upper support pattern 130U and the lower support pattern 130L. For example, the upper portion of the first mold layer 162 can be removed by performing an isotropic etch process using phosphoric acid. Removing the upper portion of the first mold layer 162 can partially expose side surfaces of the bottom electrodes BE and can allow a lower portion of the first mold layer 162 to remain on the interlayer dielectric layer 102.

[0050] Referring to Figure 9 , Figure 10A and Figure 10B The exposed side surfaces of the bottom electrodes BE can be partially etched. The exposed side surfaces of the bottom electrodes BE can be etched by an etch-selective wet etch process. During the wet etch process, the exposed side surfaces of the bottom electrodes BE can be etched relative to the upper support pattern 130U, the lower support pattern 130L, and the first mold layer 162. Thus, each of the bottom electrodes BE can have a reduced width between the upper support pattern 130U and the lower support pattern 130L and below the lower support pattern 130L. According to some example embodiments, as shown in FIG. 1C, the exposed side surfaces of the bottom electrodes BE can be etched to a depth of about 100 nm to about 200 nm. Figure 9 and Figure 10AAs shown in FIG. 1A, each of the bottom electrodes BE can include a first portion P1 in the lower support pattern 130L and a second portion P2 below the lower support pattern 130L. A maximum width W2 of the second portion P2 can be greater than a maximum width W1 of the first portion P1. Each of the bottom electrodes BE can include a third portion P3 between the upper support pattern 130U and the lower support pattern 130L, a maximum width W3 of the third portion P3 can be greater than the maximum width W1 of the first portion P1. As shown in FIG. 1A, each of the bottom electrodes BE can include a fourth portion P4 in the upper support pattern 130U. A maximum width W4 of the fourth portion P4 can be greater than the maximum width W3 of the third portion P3. Figure 9 and Figure 10B As shown in FIG. 1A, each of the bottom electrodes BE can include a first portion P1 in the lower support pattern 130L and a second portion P2 below the lower support pattern 130L. A maximum width W2 of the second portion P2 can be greater than a maximum width W1 of the first portion P1. Each of the bottom electrodes BE can include a third portion P3 between the upper support pattern 130U and the lower support pattern 130L, a maximum width W3 of the third portion P3 can be greater than the maximum width W1 of the first portion P1. As shown in FIG. 1A, each of the bottom electrodes BE can include a fourth portion P4 in the upper support pattern 130U. A maximum width W4 of the fourth portion P4 can be greater than the maximum width W3 of the third portion P3.

[0051] The wet etching process can form a first recess 150a adjacent to a bottom surface 130LL of the lower support pattern 130L, a second recess 150b adjacent to a top surface 130LU of the lower support pattern 130L, a third recess 150c adjacent to a bottom surface 130UL of the upper support pattern 130U, and a fourth recess 150d adjacent to a top surface 130UU of the upper support pattern 130U in each of the bottom electrodes BE. Each of the first recess 150a, the second recess 150b, the third recess 150c can be a region recessed into the bottom electrode BE from a side surface of the bottom electrode BE. The fourth recess 150d can be a region recessed into the bottom electrode BE from a top surface BE_U of the bottom electrode BE, and can expose a boundary between the bottom electrode BE and the upper support pattern 130U.

[0052] According to the present inventive concept, the wet etching process can allow each of the bottom electrodes BE to have a reduced width between the upper support pattern 130U and the lower support pattern 130L and below the lower support pattern 130L. Accordingly, a leakage current between the plurality of bottom electrodes BE can be minimized, or the leakage current due to an electrical short between the plurality of bottom electrodes BE can be avoided.

[0053] Referring to Figure 11 After the wet etching process is performed, a lower portion of the first mold layer 162 can be removed. Removing the lower portion of the first mold layer 162 can include etching the first mold layer 162 selectively with respect to the upper support pattern 130U, the lower support pattern 130L, and the insulating layer 120. For example, the lower portion of the first mold layer 162 can be removed by performing an isotropic etching process using phosphoric acid. Removing the lower portion of the first mold layer 162 can expose a top surface of the insulating layer 120.

[0054] Referring back to Figure 1 and Figure 2The dielectric layer 140 and the top electrode TE can be sequentially formed on the interlayer dielectric layer 102. The top electrode TE can fill spaces among the plurality of bottom electrodes BE, spaces between the interlayer dielectric layer 102 and the lower support pattern 130L, and spaces between the lower support pattern 130L and the upper support pattern 130U. The insulating layer 120 can be interposed between the top electrode TE and the interlayer dielectric layer 102. The dielectric layer 140 can be interposed between the top electrode TE and each of the plurality of bottom electrodes BE, between the top electrode TE and the lower support pattern 130L, and between the top electrode and the upper support pattern 130U. The dielectric layer 140 can extend between the top electrode TE and the insulating layer 120. The dielectric layer 140 and the top electrode TE can be conformally formed by using a layer deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In an example embodiment, the processing conditions of the layer deposition technique can be controlled such that the step coverage of the dielectric layer 140 is sufficient to conformally cover the exposed surfaces of the plurality of bottom electrodes BE, the exposed surfaces of the lower support pattern 130L, the exposed surfaces of the upper support pattern 130U, and the exposed surfaces of the insulating layer 120. In an example embodiment, the processing conditions of the layer deposition technique can be controlled such that the step coverage of the top electrode TE can fill the spaces among the plurality of bottom electrodes BE, the top electrode TE, the lower support pattern 130L, the upper support pattern 130U, and the insulating layer 120.

[0055] Figure 12 and Figure 13 shows a cross-sectional view taken along line I-I' of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts. For brevity of description, the following will focus on the differences from the method of manufacturing a semiconductor device discussed with reference to Figure 1 , Figures 4-9 , Figure 10A , Figure 10B and 11 .

[0056] As discussed with reference to Figure 7 and Figure 8 , the upper support layer 134 can be patterned to form the upper support pattern 130U having at least one upper opening 180U, and the second mold layer 164 can be removed through the at least one upper opening 180U. Thereafter, the lower support layer 132 can be patterned to form the lower support pattern 130L having at least one lower opening 180L.

[0057] Referring to Figure 12The first molding layer 162 can be removed through at least one lower opening 180L. Removing the first molding layer 162 may include selectively etching the first molding layer 162 relative to the upper support pattern 130U and the lower support pattern 130L. For example, the first molding layer 162 can be removed by performing an isotropic etching process using phosphoric acid. The removal of the first molding layer 162 may be performed until the insulating layer 120 is exposed. Removing the first molding layer 162 may expose some portions of the side surface of the bottom electrode BE and the top surface of the insulating layer 120.

[0058] Reference Figure 13 This allows for partial etching of the exposed side surface of the bottom electrode BE. This can be achieved by comparing it with a reference. Figure 9 , Figure 10A and Figure 10B The method discussed is the same as that used to etch the exposed side surface of the bottom electrode BE. Apart from the differences mentioned above, the method for manufacturing a semiconductor device according to this embodiment can be the same as that described in the reference. Figures 4-9 , Figure 10A , Figure 10B and Figure 11 The methods for manufacturing semiconductor devices discussed are basically the same.

[0059] Figure 14 The diagram illustrates some example embodiments of semiconductor devices based on the concept of the present invention. Figure 1 The cross-sectional view taken from line I-I'. Figure 15 The presentation is shown Figure 14 A magnified view of part R5. For brevity, the following will focus on the reference. Figure 1 , Figure 2 , Figure 3A and Figure 3B The differences in semiconductor devices are discussed.

[0060] Reference Figure 1 and Figure 14 According to some example embodiments, an intermediate support pattern 130M can be disposed on the intermediate side surface of a plurality of bottom electrodes BE. The intermediate support pattern 130M can contact the intermediate side surface of the plurality of bottom electrodes BE. The intermediate support pattern 130M can be disposed between a lower support pattern 130L and an upper support pattern 130U. The intermediate support pattern 130M can be vertically spaced from the lower support pattern 130L along a second direction D2, and the upper support pattern 130U can be vertically spaced from the intermediate support pattern 130M along the second direction D2.

[0061] The intermediate support pattern 130M may have at least one intermediate opening 180M. When viewed in a plane, the at least one intermediate opening 180M may extend along a third direction D3 and may also extend along the intermediate side surfaces of a plurality of first bottom electrodes BE1. The at least one intermediate opening 180M may vertically overlap with at least one lower opening 180L and at least one upper opening 180U along a second direction D2. According to some example embodiments, the intermediate support pattern 130M may have a plurality of intermediate openings 180M horizontally spaced apart from each other. Each of the plurality of intermediate openings 180M may extend along the intermediate side surfaces of corresponding first bottom electrodes BE1. The plurality of intermediate openings 180M may vertically overlap with a plurality of lower openings 180L along a second direction D2 and may also vertically overlap with a plurality of upper openings 180U along a second direction D2.

[0062] Each of the multiple bottom electrodes BE can penetrate the upper support pattern 130U, the middle support pattern 130M, the lower support pattern 130L and the insulating layer 120, and can be connected to a corresponding one of the contact pads 115.

[0063] A top electrode TE can be disposed on the interlayer dielectric layer 102 and can cover multiple bottom electrodes BE, a lower support pattern 130L, a middle support pattern 130M, and an upper support pattern 130U. The top electrode TE can fill the spaces between the multiple bottom electrodes BE, the spaces between the interlayer dielectric layer 102 and the lower support pattern 130L, the spaces between the lower support pattern 130L and the middle support pattern 130M, and the spaces between the middle support pattern 130M and the upper support pattern 130U. The top electrode TE can pass through at least one upper opening 180U, at least one middle opening 180M, and at least one lower opening 180L, and can penetrate the upper support pattern 130U, the middle support pattern 130M, and the lower support pattern 130L. In an example embodiment, the top electrode TE can fill at least one upper opening 180U, at least one middle opening 180M, and at least one lower opening 180L.

[0064] The dielectric layer 140 may be interposed between the top electrode TE and each of the plurality of bottom electrodes BE, between the top electrode TE and the lower support pattern 130L, between the top electrode TE and the intermediate support pattern 130M, and between the top electrode TE and the upper support pattern 130U. The intermediate support pattern 130M may include a dielectric material, for example, at least one selected from oxides, nitrides, and oxynitrides.

[0065] For reference Figure 3AAs discussed, at least one of the plurality of bottom electrodes BE can include a first recess 150a adjacent to a bottom surface 130LL of the lower support pattern 130L and a second recess 150b adjacent to a top surface 130LU of the lower support pattern 130L. The dielectric layer 140 can cover the bottom surface 130LL and the top surface 130LU of the lower support pattern 130L and can fill at least a portion of each of the first recess 150a and the second recess 150b. The at least one bottom electrode BE can include a first portion P1 in the lower support pattern 130L and a second portion P2 below the lower support pattern 130L. A maximum width W2 of the second portion P2 of the at least one bottom electrode BE can be greater than a maximum width W1 of the first portion P1 of the at least one bottom electrode BE.

[0066] As discussed with reference to FIG. 1, Figure 3B As discussed, the at least one bottom electrode BE can further include a third recess 150c adjacent to a bottom surface 130UL of the upper support pattern 130U and a fourth recess 150d adjacent to a top surface 130UU of the upper support pattern 130U. The dielectric layer 140 can cover the bottom surface 130UL and the top surface 130UU of the upper support pattern 130U and can fill at least a portion of each of the third recess 150c and the fourth recess 150d. The at least one bottom electrode BE can include a third portion P3 between the upper support pattern 130U and the middle support pattern 130M and a fourth portion P4 in the upper support pattern 130U. A maximum width W3 of the third portion P3 of the at least one bottom electrode BE can be greater than a maximum width W4 of the fourth portion P4 of the at least one bottom electrode BE.

[0067] As discussed with reference to FIG. 1, Figure 14 As discussed with reference to FIG. 1, Figure 15 As discussed, the at least one bottom electrode BE can further include a fifth recess 150e adjacent to a bottom surface 130ML of the middle support pattern 130M. The fifth recess 150e can be a region recessed into the at least one bottom electrode BE from a side surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the bottom surface 130ML of the middle support pattern 130M and can fill at least a portion of the fifth recess 150e. The at least one bottom electrode BE can further include a sixth recess 150f adjacent to a top surface 130MU of the middle support pattern 130M. The sixth recess 150f can be a region recessed into the at least one bottom electrode BE from a side surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the top surface 130MU of the middle support pattern 130M and can fill at least a portion of the sixth recess 150f.

[0068] The at least one bottom electrode BE can further include a fifth portion P5 between the lower support pattern 130L and the middle support pattern 130M and a sixth portion P6 in the middle support pattern 130M. A maximum width W5 of the fifth portion P5 of the at least one bottom electrode BE can be greater than a maximum width W1 of the first portion P1 of the at least one bottom electrode BE and can be greater than a maximum width W6 of the sixth portion P6 of the at least one bottom electrode BE. A maximum width W3 of the third portion P3 of the at least one bottom electrode BE can be greater than the maximum width W6 of the sixth portion P6 of the at least one bottom electrode BE.

[0069] Referring back to Figure 1 and Figure 14 , the capacitor can be constituted of the plurality of bottom electrodes BE, the lower support pattern 130L, the middle support pattern 130M, the upper support pattern 130U, the top electrode TE, and the dielectric layer 140.

[0070] Figures 16-21 A cross-sectional view taken along line I-I' of a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts is shown. For brevity of description, the following will focus on differences from the method of manufacturing a semiconductor device discussed above with reference to Figure 1 , Figures 4-9 , Figure 10A , Figure 10B and Figure 11 .

[0071] Referring to Figure 16 , the first molding layer 162, the lower support layer 132, the second molding layer 164, and the upper support layer 134 can be sequentially formed on the insulating layer 120. According to some example embodiments, a third molding layer 166 can be formed between the lower support layer 132 and the second molding layer 164, and a middle support layer 136 can be formed between the third molding layer 166 and the second molding layer 164. For example, the third molding layer 166 can be formed of a silicon oxide layer. The middle support layer 136 can be formed of a material having etching selectivity with respect to the first molding layer 162, the second molding layer 164, and the third molding layer 166. For example, the middle support layer 136 can include at least one selected from SiN, SiCN, TaO, and TiO2. A thickness of the middle support layer 136 can be substantially the same as or greater than a thickness of the lower support layer 132. A thickness of the upper support layer 134 can be substantially the same as or greater than a thickness of the middle support layer 136. The third molding layer 166 and the middle support layer 136 can be formed by performing a deposition process (e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD)).

[0072] Referring to Figure 17Vertical holes 170 can be formed in the stacked layers 120, 162, 132, 166, 136, 164, and 134. Each of the vertical holes 170 can penetrate the upper support layer 134, the second molding layer 164, the middle support layer 136, the third molding layer 166, the lower support layer 132, the first molding layer 162, and the insulating layer 120, and can expose a corresponding one of the contact pads 115.

[0073] The vertical holes 170 can be formed by substantially the same method as the method (e.g., dry etching process) discussed above with reference to Figure 5 During the dry etching process, the first molding layer 162, the second molding layer 164, and the third molding layer 166 can be etched more than the upper support layer 134, the middle support layer 136, and the lower support layer 132, and thus, each of the vertical holes 170 can be formed to have a relatively large width in the first molding layer 162, the second molding layer 164, and the third molding layer 166. For example, each of the vertical holes 170 formed in the lower support layer 132 can have a first maximum width 170W1, each of the vertical holes 170 formed in the first molding layer 162 can have a second maximum width 170W2 that is greater than the first maximum width 170W1. Each of the vertical holes 170 formed in the second molding layer 164 can have a third maximum width 170W3, and each of the vertical holes 170 formed in the upper support layer 134 can have a fourth maximum width 170W4 that is less than the third maximum width 170W3. Each of the vertical holes 170 formed in the third molding layer 166 can have a fifth maximum width 170W5 that is greater than the first maximum width 170W1, and each of the vertical holes 170 formed in the middle support layer 136 can have a sixth maximum width 170W6 that is less than the fifth maximum width 170W5. The third maximum width 170W3 of each of the vertical holes 170 can be greater than the sixth maximum width 170W6 of each of the vertical holes 170.

[0074] Referring to Figure 18 A bottom electrode BE can be formed in a corresponding vertical hole 170. The bottom electrode BE can be formed by substantially the same method as the method discussed above with reference to Figure 6 When the vertical hole 170 has a side surface caused by a bending phenomenon as discussed above with reference to Figure 5 adjacent bottom electrodes BE formed in the vertical hole 170 can have a reduced spacing in the first molding layer 162, the second molding layer 164, and the third molding layer 166. Thus, a leakage current can occur between the bottom electrodes BE.

[0075] Referring to Figure 1 and Figure 19The upper support layer 134 can be patterned to form an upper support pattern 130U having at least one upper opening 180U. The second molding layer 164 can be removed through the at least one upper opening 180U. Removing the second molding layer 164 can partially expose a top surface of the middle support layer 136 and a side surface of the bottom electrode BE.

[0076] Referring to Figure 1 and Figure 20 The middle support layer 136 can be patterned to form a middle support pattern 130M having at least one middle opening 180M. The at least one middle opening 180M can expose a middle side surface of the plurality of first bottom electrodes BE1 and can also expose a top surface of the third molding layer 166. The third molding layer 166 can be removed through the at least one middle opening 180M. Removing the third molding layer 166 can include selectively etching the third molding layer 166 relative to the upper support pattern 130U, the middle support pattern 130M, and the lower support layer 132. For example, the third molding layer 166 can be removed by performing an isotropic etching process using phosphoric acid. Removing the third molding layer 166 can partially expose a top surface of the lower support layer 132 and a side surface of the bottom electrode BE.

[0077] The lower support layer 132 can be patterned to form a lower support pattern 130L having at least one lower opening 180L. The at least one lower opening 180L can expose a lower side surface of the plurality of first bottom electrodes BE1 and can also expose a top surface of the first molding layer 162. An upper portion of the first molding layer 162 can be removed through the at least one lower opening 180L. Removing the upper portion of the first molding layer 162 can partially expose a side surface of the bottom electrode BE and can allow a lower portion of the first molding layer 162 to remain on the interlayer dielectric layer 102.

[0078] Referring to Figure 21 The exposed side surface of the bottom electrode BE can be partially etched. The exposed side surface of the bottom electrode BE can be etched by substantially the same method as discussed with reference to Figure 9 , Figure 10A and Figure 10B Accordingly, each of the bottom electrodes BE can have a reduced width between the upper support pattern 130U and the middle support pattern 130M, between the middle support pattern 130M and the lower support pattern 130L, and below the lower support pattern 130L. According to some example embodiments, when partially etching the exposed side surface of the bottom electrode BE in each of the bottom electrodes BE, the bottom electrode BE can be etched to a depth of about 100 nm to about 200 nm, such as about 150 nm. Figure 15The fifth recess 150e can be formed adjacent to the bottom surface 130ML of the middle support pattern 130M, and the sixth recess 150f can be formed adjacent to the top surface 130MU of the middle support pattern 130M, as discussed with reference to Figures 4-9 , Figure 10A , Figure 10B and Figure 11 the manufacturing semiconductor device method according to the present embodiment can be substantially the same as the manufacturing semiconductor device method discussed with reference to

[0079] According to the present inventive concept, when the middle support pattern 130M is disposed between the upper support pattern 130U and the lower support pattern 130L, each of the plurality of bottom electrodes BE can have a greater aspect ratio than the bottom electrode BE as described with reference to Figure 2 . Accordingly, the capacitance of the capacitor including the plurality of bottom electrodes BE can be increased by increasing the aspect ratio of the capacitor including the plurality of bottom electrodes BE. In addition, each of the bottom electrodes BE can have a reduced width between the upper support pattern 130U and the middle support pattern 130M, between the middle support pattern 130M and the lower support pattern 130L, and below the lower support pattern 130L. Accordingly, the leakage current between the plurality of bottom electrodes BE can be minimized, or the leakage current due to an electrical short between the plurality of bottom electrodes BE can be avoided.

[0080] Figure 22 A cross-sectional view taken along the line I-I’ of a semiconductor device embodying some example embodiments according to the present inventive concept is shown. For brevity of description, the following will focus on the differences from the semiconductor device discussed with reference to Figure 1 , Figure 1 , Figure 2 , Figure 3A and Figure 3B .

[0081] Referring to Figure 22 , each of the plurality of bottom electrodes BE can have a hollow cylindrical shape with one end portion (e.g., a bottom end) thereof closed. In this case, each of the plurality of bottom electrodes BE can have an inner surface and an outer surface opposite to each other.

[0082] The lower support pattern 130L can be disposed on and can be in contact with the lower outer surfaces of the plurality of bottom electrodes BE. The lower support pattern 130L can have at least one lower opening 180L which can extend along the lower outer surfaces of the plurality of first bottom electrodes BE1. The upper support pattern 130U can be disposed on and can be in contact with the upper outer surfaces of the plurality of bottom electrodes BE. The upper support pattern 130U can have at least one upper opening 180U which can extend along the upper outer surfaces of the plurality of first bottom electrodes BE1.

[0083] The top electrode TE can cover the outer surfaces of each of the plurality of bottom electrodes BE and can extend onto the inner surfaces of each of the plurality of bottom electrodes BE. The dielectric layer 140 can be interposed between the top electrode TE and the outer surfaces of each of the plurality of bottom electrodes BE and between the top electrode TE and the inner surfaces of each of the plurality of bottom electrodes BE. Except for the above-mentioned differences, the semiconductor device according to the present embodiment can be substantially the same as the semiconductor device discussed with reference to Figure 1 、 Figure 2 、 Figure 3A and Figure 3B .

[0084] Figure 23 A circuit diagram of a unit memory cell of a semiconductor device according to some example embodiments of the inventive concepts is shown.

[0085] Referring to Figure 23 , a memory cell MC can be disposed between a word line WL and a bit line BL which intersect each other and can electrically connect the word line WL and the bit line BL to each other. The memory cell MC can include a transistor TR connected to the word line WL and a capacitor CA connected to the transistor TR. The transistor TR can have a drain region connected to the bit line BL and a source region connected to the capacitor CA. The transistor TR can be configured to control a flow of electric charges between the bit line BL and the capacitor CA. The memory cell MC can store a data "0" or "1" according to whether the capacitor CA stores electric charges.

[0086] Figure 24 A plan view of a semiconductor device according to some example embodiments of the inventive concepts is shown. Figure 25 A cross-sectional view taken along Figure 24 line II-II' is shown.

[0087] Referring to Figure 24 and Figure 25The substrate 100 can have therein device isolation layers ST defining active regions ACT. The substrate 100 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. For example, the device isolation layers ST can include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. When viewed in a planar, the active regions ACT can have a strip shape, and can be disposed to allow their major axes to lie in an S direction that intersects the X direction and the Y direction. The X direction, the Y direction, and the S direction can intersect each other while being parallel to a top surface 100U of the substrate 100.

[0088] The substrate 100 can have therein word line structures WLS that span the active regions ACT. The word line structures WLS can extend in the Y direction, and can be arranged along the X direction. Each of the word line structures WLS can include a gate electrode GE buried in the substrate 100, a gate dielectric pattern GI located between the gate electrode GE and the active region ACT and between the gate electrode GE and the device isolation layer ST, and a gate cap pattern CAP located on a top surface of the gate electrode GE. A top surface of the gate cap pattern CAP can be substantially coplanar with the top surface of the substrate 100. According to some example embodiments, a bottom surface of the gate cap pattern CAP can be in contact with an uppermost surface of the gate dielectric pattern GI, and opposite sidewalls of the gate cap pattern CAP can be in contact with the active region ACT and / or the device isolation layer ST. According to some other embodiments, the gate dielectric pattern GI can extend between the gate cap pattern CAP and the active region ACT and / or between the gate cap pattern CAP and the device isolation layer ST.

[0089] The gate electrode GE can include a conductive material. For example, the conductive material can include one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). For example, the gate dielectric pattern GI can include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. For example, the gate cap pattern CAP can include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0090] The active region ACT can have first dopant regions SD1 and second dopant regions SD2 therein, where the second dopant regions SD2 are spaced apart from each other across the first dopant regions SD1. The first dopant regions SD1 can be disposed in the active region ACT between a pair of adjacent word line structures WLS. Each of the second dopant regions SD2 can be disposed in the active region ACT on a side of a corresponding one of the pair of word line structures WLS. For example, the second dopant regions SD2 can be spaced apart from each other across the pair of word line structures WLS. The first dopant regions SD1 can extend deeper into the substrate 100 than the second dopant regions SD2. The first dopant regions SD1 can include the same conductive impurities as the second dopant regions SD2.

[0091] The bit line structure BLS can be disposed on the substrate 100 and can span the word line structure WLS. The bit line structure BLS can extend in the X-direction. The bit line structure BLS can include a conductive contact 210 electrically connected to the first dopant region SD1, a conductive line 230 located on the conductive contact 210 and extending in the X-direction, and a barrier pattern 220 located between the conductive contact 210 and the conductive line 230. The conductive contact 210 can be in contact with the first dopant region SD1. A bottom surface of the conductive contact 210 can be located at a height lower than a height of the top surface 100U of the substrate 100. Opposing side surfaces of the conductive contact 210 can be aligned with corresponding side surfaces of the conductive line 230. The bit line structure BLS can include a capping pattern 240 located on a top surface of the conductive line 230 and a spacer pattern 250 located on side surfaces of the conductive line 230. The capping pattern 240 and the spacer pattern 250 can extend in the X-direction along the top surface and the side surfaces of the conductive line 230. The spacer pattern 250 can cover the side surfaces of the capping pattern 240, the side surfaces of the barrier pattern 220, and the side surfaces of the conductive contact 210, and can contact the first dopant region SD1.

[0092] For example, the conductive contact 210 can include one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). The conductive line 230 and the barrier pattern 220 can each include one of a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). For example, the capping pattern 240 and the spacer pattern 250 can each include one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0093] The interlayer dielectric layer 102 can be disposed on the substrate 100, and can cover the active region ACT, the device isolation layer ST, the word line structure WLS, and the bit line structure BLS. For example, the interlayer dielectric layer 102 can include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0094] The conductive contact 110 and the contact pad 115 can be disposed in the interlayer dielectric layer 102. The conductive contact 110 can penetrate a lower portion of the interlayer dielectric layer 102, and can be electrically connected with the corresponding second impurity region SD2. The contact pad 115 can be disposed on the corresponding conductive contact 110. The contact pad 115 can penetrate an upper portion of the interlayer dielectric layer 102, and can be electrically connected with the corresponding conductive contact 110.

[0095] The insulating layer 120 can be disposed on the interlayer dielectric layer 102, and the capacitor structure CAS can be disposed on the insulating layer 120. According to some example embodiments, the capacitor structure CAS can include a plurality of bottom electrodes BE, a lower support pattern 130L, an upper support pattern 130U, a top electrode TE, and a dielectric layer 140 as discussed with reference to Figure 1 、 Figure 2 、 Figure 3A and Figure 3B According to some other embodiments, the capacitor structure CAS can further include an intermediate support pattern 130M as discussed with reference to Figure 14 and Figure 15 According to some other embodiments, the plurality of bottom electrodes BE in the capacitor structure CAS can each have a hollow cylindrical shape with one end closed as discussed with reference to Figure 22

[0096] According to the inventive concept, a plurality of support patterns vertically spaced apart from each other can be used for structural stability of each of a plurality of bottom electrodes having a relatively large aspect ratio. Each of the bottom electrodes can have a reduced width between the plurality of support patterns and below a lowermost one of the plurality of support patterns, and thus, a leakage current between adjacent bottom electrodes can be minimized, or a leakage current due to an electrical short between the plurality of bottom electrodes BE can be avoided. Accordingly, a semiconductor device having improved electrical characteristics and a method of fabricating the same can be provided.

[0097] The foregoing description provides some example embodiments for explaining the inventive concept. Accordingly, the inventive concept is not limited to the above-described embodiments, and those of ordinary skill in the art will understand that changes in form and detail can be made therein without departing from the spirit and essential characteristics of the inventive concept.​

Claims

1. A semiconductor device comprising: a memory cell capacitor configured to store data, wherein the memory cell capacitor comprises: a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, wherein the plurality of bottom electrodes are spaced apart from each other in a first direction parallel to the top surface of the substrate; an upper support pattern on an upper side surface of the plurality of bottom electrodes; and a lower support pattern on a lower side surface of the plurality of bottom electrodes, wherein the lower support pattern is disposed between the substrate and the upper support pattern, and wherein a first bottom electrode of the plurality of bottom electrodes comprises a first recess adjacent to a bottom surface of the lower support pattern, the first recess being recessed into the first bottom electrode from a side surface of the first bottom electrode and spacing a portion of the first bottom electrode from the lower support pattern in the first direction.

2. The device of claim 1, wherein the first bottom electrode further comprising a second recess adjacent to a top surface of the lower support pattern.

3. The device of claim 2, wherein the first bottom electrode further comprising a third recess adjacent to a bottom surface of the upper support pattern.

4. The device of claim 3, further comprising: a top electrode covering the plurality of bottom electrodes, the upper support pattern, and the lower support pattern, and disposed between the substrate and the lower support pattern and between the lower support pattern and the upper support pattern; and a dielectric layer between the top electrode and each of the upper support pattern and the lower support pattern and between the top electrode and each of the plurality of bottom electrodes.

5. The device of claim 4, the first bottom electrode comprising a first portion surrounded by the lower support pattern and a second portion surrounded by the top electrode, wherein wherein the second portion is below the first portion in the vertical direction, wherein the first recess is at a boundary between the first portion and the second portion, and wherein a maximum width of the second portion is greater than a maximum width of the first portion.

6. The device of claim 5, the first bottom electrode comprising a third portion surrounded by the top electrode and a fourth portion surrounded by the upper support pattern, wherein, wherein the third portion is between the fourth portion and the first portion, wherein the second recess is at a boundary between the first portion and the third portion, wherein the third recess is at a boundary between the third portion and the fourth portion, and wherein a maximum width of the third portion is greater than a maximum width of the first portion.

7. The device of claim 4, the dielectric layer filling at least a portion of the first recess. wherein 8. The device of claim 4, further comprising: an interlayer dielectric layer between the substrate and the plurality of bottom electrodes; a plurality of conductive contacts in the interlayer dielectric layer and connected to the plurality of bottom electrodes; and a plurality of conductive contacts in the interlayer dielectric layer and connected to the plurality of bottom electrodes; and ​ an insulating layer between the ILD layer and the lower support pattern, wherein the plurality of bottom electrodes penetrate the insulating layer and are connected to the plurality of conductive contacts, wherein the top electrode is disposed between the lower support pattern and the insulating layer, and wherein the dielectric layer extends between the top electrode and the insulating layer.

9. The apparatus of claim 4, wherein, the upper support pattern includes at least one upper opening, the lower support pattern includes at least one lower opening, and the top electrode is configured to fill the at least one upper opening and the at least one lower opening.

10. The apparatus of claim 9, wherein the at least one upper opening and the at least one lower opening vertically overlap each other.

11. The apparatus of claim 1, wherein the first bottom electrode includes: a first portion in the lower support pattern; and a second portion below the lower support pattern in the vertical direction, wherein a maximum width of the second portion is greater than a maximum width of the first portion.

12. The apparatus of claim 11, wherein the first bottom electrode further includes: a second recess adjacent to a top surface of the lower support pattern; and a third recess adjacent to a bottom surface of the upper support pattern.

13. The apparatus of claim 12, wherein, the first bottom electrode further includes a third portion between the upper support pattern and the lower support pattern, and wherein a maximum width of the third portion is greater than a maximum width of the first portion.

14. The apparatus of claim 13, wherein the first bottom electrode further includes a fourth portion surrounded by the upper support pattern, wherein the third portion is between the fourth portion and the first portion, and wherein a maximum width of the third portion is greater than a maximum width of the fourth portion.

15. A semiconductor apparatus comprising: a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, wherein the plurality of bottom electrodes are spaced apart from each other in a first direction parallel to the top surface of the substrate; a lower support pattern on a lower side surface of the plurality of bottom electrodes; an upper support pattern on the lower support pattern and on an upper side surface of the plurality of bottom electrodes; a top electrode filling a space between the plurality of bottom electrodes, a space between the substrate and the lower support pattern, and a space between the lower support pattern and the upper support pattern; and a dielectric layer between the top electrode and each of the upper support pattern and the lower support pattern and between the top electrode and each of the plurality of bottom electrodes, wherein a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern and a second recess adjacent to a top surface of the lower support pattern, the first recess being recessed from a side surface of the first bottom electrode into the first bottom electrode and spacing a portion of the first bottom electrode from the lower support pattern in the first direction.

16. The apparatus of claim 15, wherein the dielectric layer covers a bottom surface of the lower support pattern and fills at least a portion of the first recess.

17. The apparatus of claim 16, wherein the dielectric layer covers a top surface of the lower support pattern and fills at least a portion of the second recess.

18. The apparatus of claim 15, wherein, the first bottom electrode further comprises a third recess adjacent to a bottom surface of the upper support pattern.

19. The apparatus of claim 18, wherein, the dielectric layer covers a bottom surface of the upper support pattern and fills at least a portion of the third recess.

20. The apparatus of claim 15, wherein the first bottom electrode comprises: a first portion surrounded by the lower support pattern; and a second portion surrounded by the top electrode, wherein the second portion is below the first portion in the vertical direction, and wherein a maximum width of the second portion is greater than a maximum width of the first portion.

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