Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The present disclosure relates to post-formation repair of dielectric features. Specifically, the present disclosure provides embodiments of semiconductor structures and methods of forming the same. An exemplary semiconductor structure includes a first source / drain feature and a second source / drain feature and a hybrid fin disposed between the first source / drain feature and the second source / drain feature and extending longitudinally in a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbon nitride, and the inner feature includes silicon carbon nitride.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 032,431, filed on May 29, 2020, entitled “POST-FORMATION REPAIR OF DIELECTRIC FEATURES,” which is incorporated herein by reference in its entirety. Background Art

[0003] The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the process of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the geometric size (i.e., the smallest component (or line) that can be produced using the manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down is also accompanied by an increase in the design and manufacturing complexity of the devices incorporated into these ICs. Parallel developments in the manufacturing industry have enabled increasingly complex designs to be manufactured accurately and reliably.

[0004] For example, hybrid fins can be used to isolate adjacent source / drain features. Since hybrid fins are formed of dielectric materials and do not form active areas, they may also be referred to as dielectric fins or dummy fins. In conventional techniques, a seam may be formed along the centerline of the hybrid fin. Such a seam may be widened in subsequent processes and produce a shallow concave profile in the overlying layer or feature. Therefore, although existing hybrid fins and their formation methods are generally adequate for their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0005] Some embodiments of the present invention relate to a semiconductor structure comprising: a first source / drain feature and a second source / drain feature; and a hybrid fin disposed between the first source / drain feature and the second source / drain feature and extending longitudinally along a first direction, wherein the hybrid fin comprises an inner feature and an outer layer disposed around the inner feature, wherein the outer layer comprises silicon oxycarbon nitride and the inner feature comprises silicon carbon nitride.

[0006] Some other embodiments of the present invention relate to a method, comprising: providing a workpiece, the workpiece comprising a substrate, a first fin structure on the substrate, and a second fin structure on the substrate; conformally depositing a first dielectric layer on the workpiece; conformally depositing a second dielectric layer on the first dielectric layer; after conformally depositing the second dielectric layer, flattening the workpiece to expose the first dielectric layer above the first fin structure and the second fin structure; selectively etching back the first dielectric layer until the second dielectric layer rises above the first dielectric layer to form a hybrid fin; and annealing the workpiece to selectively form an outer layer on the hybrid fin.

[0007] Still other embodiments of the present invention relate to a method comprising: providing a workpiece comprising a substrate, a first fin structure on the substrate, and a second fin structure on the substrate; conformally depositing a first dielectric layer on the workpiece; conformally depositing a second dielectric layer on the first dielectric layer; after conformally depositing the second dielectric layer, flattening the workpiece to expose the first dielectric layer on the first fin structure and the second fin structure; selectively etching back the first dielectric layer to form a hybrid fin rising above the first dielectric layer; and selectively oxidizing the hybrid fin to cause volume expansion of the hybrid fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a flow chart of a method of manufacturing a semiconductor device according to various aspects of the present disclosure.

[0010] Figure 2-12 According to various aspects of the present disclosure Figure 1 Partial cross-sectional views of a workpiece at various manufacturing stages of the method.

[0011] Fig.13 A schematic diagram of a deposition cycle for forming a hybrid fin in accordance with various aspects of the present disclosure is shown.

[0012] Fig.14 A schematic diagram of an annealing process for a hybrid fin according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments of components and arrangements are described below in order to simplify the present disclosure. Of course, these embodiments are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, in the following disclosure, the formation of a feature connected to or coupled to another feature may include an embodiment in which the feature is directly contacted, and may also include an embodiment in which an additional feature may be formed to be inserted between features so that the features may not be in direct contact.

[0014] In addition, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, when "about," "approximately," and the like are used to describe a number or a range of numbers, the term is intended to encompass numbers within + / - 10% of the number unless otherwise stated. For example, the term "about 5 nm" encompasses a size range of 4.5 nm to 5.5 nm.

[0015] In a multi-gate device, a hybrid fin (also referred to as a dielectric fin or pseudo fin) is implemented to define space for forming source / drain epitaxial features, thereby preventing undesired merging of adjacent source / drain epitaxial features. Exemplary multi-gate devices include fin field effect transistors (FinFETs) or multi-bridge channel (MBC) transistors. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors may also be referred to as surround gate transistors (SGTs) or all-around gate (GAA) transistors. The channel region of an MBC transistor may be formed by nanowires, nanosheets, or other nanostructures, and for this reason, MBC transistors may also be referred to as nanowire transistors or nanosheet transistors.

[0016] In order to form a hybrid fin on a workpiece having a fin structure (or fin-shaped structure) on a substrate, a first dielectric layer for an isolation layer is conformally deposited on the fin-shaped structure and the substrate, and a second dielectric layer for a hybrid fin is conformally deposited on the first dielectric layer. After the workpiece is planarized to expose the first dielectric layer, the first dielectric layer is selectively recessed to form an isolation feature, such as a shallow trench isolation (STI) feature. After the selective recess, the second dielectric layer that rises above the isolation feature forms a hybrid fin. When two conformal second dielectric layers merge seamlessly along the centerline of the hybrid fin, an ideal hybrid fin can be formed. However, it is possible that at least some hybrid fins are less than ideal and seams may appear along their centerlines. These intermediate seams are easy to etch and may be widened in subsequent processes. Once these intermediate seams are widened, shallow concave profiles may be produced in the overlying layers or features. The present disclosure includes methods for forming seamless hybrid fins or repairing seams therein after forming hybrid fins.

[0017] Hereinafter, various aspects of the present disclosure will be described in more detail with reference to the accompanying drawings. Figure 1 A flow chart illustrating a method 100 for fabricating a semiconductor structure according to one or more aspects of the present disclosure is shown. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly described in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional implementations of the method. For the sake of brevity, not all steps are described in detail herein. The following is a description of a workpiece 200 (in the example of FIG. 1 ) at different stages of fabrication according to an implementation of the method 100. Figure 2-12 1 and 2 ). The method 100 is described with reference to a partial cross-sectional view of a workpiece 200 (shown in FIG. 1 ). For the avoidance of doubt, in all the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It is noted that since the workpiece 200 can be manufactured into a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 as the context requires.

[0018] refer to Figure 1 and Figure 2 The method 100 includes a block 102 in which a workpiece 200 is received. Figure 2As shown in , workpiece 200 includes substrate 202 and fin structure 204 disposed on substrate 202. In various examples, substrate 202 includes elemental (single element) semiconductors, such as silicon (Si) or germanium (Ge) in a crystalline structure; compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or alloy semiconductors, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP). Substrate 202 may be uniform in composition, or may include various layers, some of which may be patterned to form fins. The layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates. In some such examples, the layers of substrate 202 may include insulators such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, and / or other suitable insulator materials. Figure 2 2 , but the substrate 202 may include doped regions such as wells. In this regard, some portions of the substrate 202 may be doped with p-type dopants (such as boron, BF2, or indium) to form p-type wells, while other portions of the substrate 202 may be doped with n-type dopants (such as phosphorus or arsenic) to form n-type wells.

[0019] The fin structure 204 may be formed by etching a portion of the substrate 202, by depositing various layers on the substrate 202 and etching the layers, and / or by other suitable techniques. For example, the fin structure 204 may be patterned using one or more photolithography processes (including double patterning or multiple patterning processes). Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate 202 and one or more fin top hard masks. The material layer is patterned using a photolithography process. Spacers are formed along the edges of the patterned material layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used to pattern one or more fin top hard masks. The substrate (and / or various layers deposited on the substrate 202, if formed) is then patterned into the fin structure 204 using the patterned one or more fin top hard masks.

[0020] In the depicted embodiments, the fin structure 204 is manufactured from a substrate 202 formed of silicon. In these embodiments, the fin structure 204 may form a channel region and a source / drain region of a FinFET. Although not shown, the fin structure 204 may also include one or more silicon germanium layers so that they can act as a channel region and a source / drain region of a p-type fully strained channel (PFSC) transistor. In addition, although not explicitly shown, the fin structure 204 may be a fin-shaped structure formed by an epitaxial layer stack disposed on the substrate 202, and may be formed as a vertical stack of channel components of an MBC transistor. In these embodiments, the epitaxial layer stack includes a plurality of second epitaxial layers and a plurality of first epitaxial layers that are staggered. The first epitaxial layer and the second epitaxial layer have different semiconductor compositions, thereby allowing selective removal or recessing of the second epitaxial layer. In some examples, the first epitaxial layer is formed of silicon (Si), and the second epitaxial layer is formed of silicon germanium (SiGe). The first epitaxial layer may be referred to as a channel layer, and the second epitaxial layer may be referred to as a sacrificial layer. For simplicity, the following uses a fin structure for a FinFET as an example to describe various aspects of the present disclosure. It will be understood by those skilled in the art that various aspects of the present disclosure may be applicable to other multi-gate transistors, such as MBC transistors.

[0021] exist Figure 2 In some embodiments presented herein, the fin structures 204 may be grouped in pairs to form dual fins or dual fin devices. Other configurations, such as single fin devices, are possible and are fully contemplated by the present disclosure. Figure 2 The two pairs of fin structures 204 in FIG. 2 are separated by a hybrid fin trench 205 . The hybrid fin trench 205 includes a first width W1 along the X direction. The first width W1 is selected so that a hybrid fin can be formed in the hybrid fin trench 205 .

[0022] refer to Figure 1 and Figure 3 , the method 100 includes a block 104, in which a first dielectric layer 206 is conformally deposited on the workpiece 200. In some embodiments, the first dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. To conformally deposit the first dielectric layer 206 on the fin structure 204 and the substrate 202, the first dielectric layer 206 may be deposited by a chemical vapor deposition (CVD) process, a sub-atmospheric pressure CVD (SACVD) process, a low pressure CVD (LPCVD) process, a high density plasma CVD (HDPCVD) process, an atomic layer deposition (ALD), and / or other suitable processes. Figure 3As shown in FIG. 1 , the conformal deposition of the first dielectric layer 206 completely fills the space between two adjacent fin structures 204, but does not completely fill the hybrid fin trench 205. Instead, the first dielectric layer 206 conformally lines the sidewalls and bottom surface of the hybrid fin trench 205. After the deposition of the first dielectric layer 206, the first width W1 of the hybrid fin trench 205 is reduced to a smaller second width W2, as shown in FIG. Figure 3 as shown in .

[0023] refer to Figure 1 and Figure 4 , the method 100 includes block 106, where a second dielectric layer 208 is conformally deposited over the workpiece 200, including over the first dielectric layer 206. In some embodiments, the second dielectric layer 208 includes hydrogenated silicon carbonitride (H:SiCN) and may be deposited using atomic layer deposition (ALD). Fig.13 An ALD cycle according to some implementations of the present disclosure is shown. Fig.13 As shown in FIG. 1 , the first dielectric layer 206 deposited at block 104 may include hydroxyl groups (—OH) on its surface. In an ALD process chamber, the first dielectric layer 206 is first exposed to an amine-containing precursor, such as Fig.13 The amine-containing precursor reacts with the hydroxyl group and chemically adsorbs to the first dielectric layer 206, thereby forming an amine group (-NH) on the surface of the first dielectric layer 206. Fig.13 , but then the ALD process chamber is purged with an inert gas such as nitrogen (N2), argon (Ar) or helium (He) to remove excess amine-containing precursors in the ALD process chamber. After the purge, a trichlorosilane derivative such as bis(trichlorosilyl)methane is supplied to the ALD process chamber. Fig.13 As shown in FIG. 2 , the trichlorosilane derivative in the ALD process chamber reacts and bonds with the amine groups on the surface of the first dielectric layer 206. After the trichlorosilane derivative is brought into contact with the workpiece 200, the ALD process chamber is purged again with an inert gas to remove excess trichlorosilane derivative that is not chemically adsorbed on the surface of the first dielectric layer 206. Then, the same amine-containing precursor ( Fig.13 Ammonia (shown in ) is supplied to the ALD process chamber again to replace the chlorine functional groups with amine functional groups. At the end of the ALD cycle, the ALD process chamber is purged to remove excess amine-containing precursors. In some implementations, the conformal deposition of the second dielectric layer 208 can be performed at a process temperature between about 500° C. and about 700° C., such as between about 620° C. and about 680° C. In some embodiments, Fig.13 The ALD cycle shown in FIG. 2 may be repeated multiple times to substantially fill the hybrid fin trench 205. The number of ALD cycles is determined by the second width W2 of the hybrid fin trench 205. Figure 4 As shown in FIG. 2 , the conformal second dielectric layer 208 may not merge seamlessly along the midline or centerline of the hybrid fin trench 205, thereby creating a seam 209. Due to its shape, the seam 209 may also be referred to as a gap 209. The seam 209 may extend downward in the Z direction, and at least a portion of the seam 209 is disposed between the two pairs of fin structures 204. Since the first dielectric layer 206 is conformally deposited along the sidewalls of the hybrid fin trench 205, a portion of the seam 209 is also disposed between two portions of the first dielectric layer 206 disposed on the sidewalls of the fin structure 204.

[0024] refer to Figure 1 and Figure 5 , the method 100 includes block 108, where the workpiece 200 is planarized. A chemical mechanical polishing (CMP) process is performed at block 108 to expose the first dielectric layer 206 above the fin structure 204. At the end of the operation at block 108, the top surfaces of the first dielectric layer 206 and the second dielectric layer 208 are coplanar. Figure 5 As shown in FIG. 1 , although the depth of the seam 209 in the second dielectric layer 208 is reduced by planarization at block 108 , the seam 209 still remains disposed between the two pairs of fin structures 204 .

[0025] refer to Figure 1 and Figure 6 , the method 100 includes a block 110, wherein the first dielectric layer 206 is selectively recessed to form an isolation feature 2060 and a hybrid fin 2080 that rises above the isolation feature 2060. In some embodiments, an isotropic wet etching process such as a diluted hydrofluoric acid (DHF) or a buffered hydrofluoric acid (BHF) etching process can be used to selectively recess the first dielectric layer 206. Here, the BHF etching process can include using hydrofluoric acid (HF), water, and ammonium fluoride (NH4F). In some alternative embodiments, an anisotropic dry etching process (such as a process using fluorocarbons and oxygen) can be used to selectively recess the first dielectric layer 206. Plasma can promote the anisotropic dry etching process. As Figure 6 As shown in FIG. 1 , the operation at block 106 selectively recesses the first dielectric layer 206 without substantially etching the fin structure 204 and the second dielectric layer 208. Thus, at the end of the operation at block 106, the fin structure 204 and the second dielectric layer 208 are raised above the recessed first dielectric layer 206. For ease of reference, the recessed first dielectric layer 206 is referred to as an isolation feature 2060, and the second dielectric layer 208 raised above the isolation feature 2060 is referred to as a hybrid fin 2080. Figure 6 As shown in , the seam 209 extends along the midline of the mixing fin 2080 .

[0026] refer to Figure 1 and Figure 7 , the method 100 includes a block 112, in which an annealing process 300 is performed to repair the hybrid fin 2080. In some embodiments, the annealing process 300 can be performed using a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. The annealing process 300 may include an annealing temperature between about 400° C. and about 1000° C. The annealing process 300 is performed in an oxygen-containing environment. As used herein, an oxygen-containing environment refers to an environment that includes an oxygen-containing substance such as water, oxygen (O2), or oxygen plasma. As Figure 7 As shown in FIG. 1 , at a macroscopic level, the annealing process 300 and the oxygen-containing environment selectively form the outer layer 210 on the exposed surface of the hybrid fin 2080 and the silicon oxide layer 212 on the exposed surface of the fin structure 204 at block 112. At a microscopic level, the annealing process 300 causes the oxygen-containing environment to react with the hybrid fin 2080. Referring now to FIG. Fig.14 Available Fig.13 The hybrid fin 2080 (or the second dielectric layer 208) is formed by performing multiple ALD cycles as shown in FIG. Fig.14 The hybrid fin 2080 in FIG. 1 includes two atomic layers formed using two ALD cycles. During the annealing process 300, some silicon-nitrogen bonds and amine functional groups are oxidized and replaced with silicon-oxygen bonds in an outside-to-inside manner. This outside-to-inside oxidation at block 112 converts the exposed outer portion of the hybrid fin 2080 into an oxygen-containing outer layer 210. Figure 7 As shown in , at the end of the operation at box 112, an outer layer 210 is formed on the hybrid fin 2080. The outer layer 210 does not extend to the surface of the hybrid fin 2080 covered by the isolation feature 2060, which remains unchanged during the annealing process 300. In some embodiments, the outer layer 210 includes hydrogenated silicon oxycarbon nitride (H:SiOCN) and the hybrid fin 2080 includes hydrogenated silicon carbon nitride (H:SiCN). In these embodiments, if the hydrogen atoms are considered unimportant, the outer layer 210 includes silicon oxycarbon nitride and the hybrid fin 2080 includes silicon carbon nitride. In other words, the hybrid fin 2080 can be considered to have an outer layer 210 and an inner feature 211 surrounded by the outer layer 210. It is observed that such selective oxidation of the hybrid fin 2080 may cause local volume expansion and close the seam 209. As Figure 7As shown in , the outer layer 210 extends not only along the top surface and sidewalls of the hybrid fin 2080, but also extends into the hybrid fin 2080 along its midline. That is, the outer layer 210 can fill the seam 209, close the seam 209, make the seam 209 shallower, or otherwise make the seam 209 smaller. In embodiments where the seam 209 still exists after the outer layer 210 is formed, the seam 209 is defined in the outer layer 210 and is spaced apart from the internal feature 211 by the outer layer 210. That is, when the seam 209 is not completely filled by the outer layer 210, the surface of the seam is lined with the outer layer 210. Since the hybrid fin 2080 is substantially formed at frame 110, the operation at frame 112 repairs the hybrid fin 2080 by reducing or eliminating the seam 209. In some embodiments, the outer layer 210 may account for about 5% to about 20% of the total thickness of the hybrid fin 2080 as measured from the surface of the hybrid fin 2080. This thickness range is critical. On the one hand, if the outer layer 210 does not reach at least 5% of the total thickness, the seam 209 may not be substantially closed. On the other hand, if the outer layer 210 accounts for more than 20% of the total thickness, its inclusion of oxygen atoms may reduce the etch selectivity required to etch silicon oxide-containing features. Since the outer layer 210 is not formed on the isolation feature 2060, the outer layer 210 is selectively formed on the hybrid fin 2080 during the annealing process 300.

[0027] refer to Figure 1 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 , method 100 includes block 114, where additional processing is performed. Such additional processing may include Figure 8 The formation of the dummy gate stack 214 shown in Fig. 9 The formation of the gate spacer 216 shown in Fig.10 The recessed source / drain regions shown in Fig.10 , deposition of source / drain features 218 - 1 and 218 - 2 over the source / drain regions, deposition of a contact etch stop layer (CESL) 220, Fig.11 The deposition of the interlayer dielectric (ILD) layer 222 shown in FIG. Fig.11 The selective removal of the dummy gate stack 214 shown in FIG. Fig.11 The formation of the gate structure 224 shown in FIG. Fig.12 2 is a partial cross-sectional view of the workpiece 200 with the viewing direction along the X direction.

[0028] refer to Figure 8 , in the channel region 204C of the fin structure 204 ( Fig.12The dummy gate stack 214 is formed on the source / drain region 204SD (shown in FIG. 2 ). Since the dummy gate stack 214 is not disposed on the source / drain region 204SD ( Fig.12 ), so Figure 8 The dummy gate stack 214 in the fin structure 204 is out of plane and is shown in dashed lines. In some embodiments, a gate replacement process (or gate last process) is used, in which the dummy gate stack 214 acts as a placeholder for the functional gate structure. Other processes and configurations are possible. In some embodiments, the dummy gate stack 214 is formed over the isolation feature 2060 and is at least partially disposed in the channel region 204C ( Fig.12 As shown in Figure 8 As shown in FIG. 1 , the pseudo gate stack 214 extends longitudinally along the X direction to wrap over the fin structure 204 extending longitudinally along the Y direction. The portion of the fin structure 204 overlapping the pseudo gate stack 214 is the channel region 204C ( Fig.12 ), and the portion of the fin structure 204 not covered by the dummy gate stack 214 constitutes the source / drain region 204SD (as shown in Fig.12 ). Figure 8 As shown in FIG. 2 , a dummy gate stack 214 is disposed over the outer layer 210 of the silicon oxide layer 212 , the isolation features 2060 , and the hybrid fins 2080 .

[0029] In some embodiments, the dummy gate stack 214 is formed by various process steps, such as layer deposition, patterning, etching, and other suitable process steps. Exemplary layer deposition processes include low pressure CVD, CVD, plasma enhanced CVD (PECVD), ALD, or other suitable deposition techniques or combinations thereof. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In an exemplary process, a polysilicon layer and a gate top hard mask layer (not shown) for the dummy gate stack 214 are sequentially deposited on the workpiece 200, including on the fin structure 204 and the hybrid fin 2080. The deposition may be accomplished by the aforementioned deposition process. The deposited layers are then patterned using a photolithography process to form a dummy gate stack 214. The gate top hard mask layer may include a silicon oxide layer and a nitride layer. The patterning of the dummy gate stack 214 may also remove the silicon oxide layer 212 not covered by the dummy gate stack 214.

[0030] refer to Fig. 9, and then gate spacers 216 are deposited over the workpiece 200 , including over the sidewalls of the dummy gate stack 214 . Fig. 9 In FIG. 1 , the deposited gate spacer 216 blocks the direct view of the dummy gate stack 214. Since the gate spacer 216 on the sidewalls of the dummy gate stack 214 is also out of plane, Fig. 9 . In some embodiments, the formation of the gate spacer 216 includes conformally depositing one or more dielectric layers on the workpiece 200. In an exemplary process, the one or more dielectric layers are deposited using CVD, SACVD, ALD, or other suitable methods. The gate spacer 216 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbonitride, and / or combinations thereof. Fig. 9 As shown in FIG. 1 , the gate spacer 216 is formed along the sidewalls of the dummy gate stack 214, the source / drain region 204SD of the fin structure 204 ( Fig.12 The gate spacer 216 is deposited on the outer layer 210 of the hybrid fin 2080 .

[0031] Reference now Fig.10 . Etch back the source / drain region 204SD of the fin structure 204 ( Fig.12) to expose the fin structure 204. In some embodiments, the etch back may include a suitable dry etching process. An exemplary dry etching process may include hydrogen, oxygen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, C3F8, NF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. The etch back removes the gate spacers 216 on the top surface of the source / drain region of the fin structure 204 and exposes the fin structure 204. In some cases, the etch back may also remove a portion of the fin structure 204. After the etch back, a first source / drain feature 218-1 and a second source / drain feature 218-2 are epitaxially grown from the source / drain region of the fin structure 204. In some embodiments, the first source / drain features 218-1 and the second source / drain features 218-2 may be formed using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the composition of the fin structure 204. Depending on the design of the semiconductor device 200, the first source / drain features 218-1 and the second source / drain features 218-2 may be n-type source / drain features or p-type source / drain features. When the first source / drain features 218-1 and the second source / drain features 218-2 are n-type, they may include silicon (Si) and may be doped with n-type dopants, such as phosphorus (P) or arsenic (As). When the first source / drain feature 218-1 and the second source / drain feature 218-2 are p-type, they may include silicon germanium (SiGe) and may be doped with a p-type dopant, such as boron (B). When the first source / drain feature 218-1 and the second source / drain feature 218-2 are doped, they may be doped in situ during the epitaxial process, or may be doped ex situ by an implantation process (i.e., a junction implantation process). In some alternative embodiments, the first source / drain feature 218-1 and the second source / drain feature 218-2 may be epitaxial features of different types. For example, the first source / drain feature 218-1 is n-type and the second source / drain feature 218-2 is p-type. In some further embodiments, each of the first source / drain feature 218-1 and the second source / drain feature 218-2 includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer. In these embodiments, the doping concentration of the second epitaxial layer may be greater than the doping concentration of the first epitaxial layer. Fig.11As shown in FIG. 2 , each of the first source / drain feature 218 - 1 and the second source / drain feature 218 - 2 is in direct contact with the outer layer 210 and is spaced apart from the inner feature 211 of the hybrid fin 2080 .

[0032] Reference now Fig.11 After forming the first source / drain feature 218-1 and the second source / drain feature 218-2, CESL 220 is deposited on the first source / drain feature 218-1 and the second source / drain feature 218-2. CESL 220 may include silicon nitride, silicon oxynitride, and / or other materials known in the art. CESL 220 may be deposited using ALD, PECVD, and / or other suitable deposition processes. Fig.11 As shown in , the CESL 220 can be deposited on the top surface of the first source / drain feature 218-1, the second source / drain feature 218-2, the hybrid fin 2080, and along the sidewalls of the gate spacer 216 (not explicitly shown). Then, an ILD layer 222 is deposited on the CESL 220. In some embodiments, the ILD layer 222 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG)), and / or other suitable dielectric materials. The ILD layer 222 can be deposited by spin coating, PECVD process, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 222, the workpiece 200 can be annealed to improve the integrity of the ILD layer 222. To remove excess material and expose the top surface of the dummy gate stack 214 , a planarization process, such as a CMP process, may be performed.

[0033] Still refer to Fig.10 The exposed dummy gate stack 214 is then removed from the workpiece 200 and replaced with the gate structure 224. The removal of the dummy gate stack 214 results in a channel region 204C ( Fig.12) above the gate trench. Removal of the dummy gate stack 214 may include one or more etching processes that are selective to the material in the dummy gate stack 214. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 214. After removing the dummy gate stack 214, the gate structure 224 is then deposited into the gate trench to wrap over the channel region of the fin structure. In some embodiments, the gate structure 224 includes a gate dielectric layer (not shown) and a gate electrode (not shown) formed on the gate dielectric layer. In some embodiments, the gate dielectric layer may include an interfacial layer and a high-k dielectric layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant, for example, a dielectric material having a dielectric constant greater than the dielectric constant of thermal silicon oxide (approximately 3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. In some embodiments, if the silicon oxide layer 212 is not completely removed with the dummy gate stack 214, the interface layer may include the silicon oxide layer 212 on the channel region of the fin structure 204. The interface layer may be deposited using chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K dielectric layer may include a high-K dielectric layer such as hafnium oxide. Alternatively, the high-K dielectric layer may include other high-K dielectrics, such as hafnium oxide (HfO), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0034] The gate electrode of the gate structure 224 may include a single layer or alternatively a multilayer structure, such as various combinations of a metal layer (work function metal layer) with a selected work function that enhances device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. By way of example, the gate electrode may be titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode of the gate structure 224 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a planarization process, such as a CMP process, may be performed to remove excess material to provide a substantially planar top surface of the gate structure 224. At this point, the transistor 230 is substantially formed. In the illustrated embodiment, the transistor 230 is a FinFET.

[0035] Although not explicitly shown in the accompanying drawings, in some alternative embodiments, method 100 may also be applicable to the formation and repair of hybrid fins in MBC transistors. In these alternative embodiments, the fin structure 204 on the workpiece 200 may be replaced by a fin-shaped structure including a plurality of interlaced sacrificial layers and a plurality of channel layers. In addition to the fin structure 204, the operations at frames 102-112 may be substantially the same. When an MBC transistor is intended, the operation at frame 114 may be changed. For example, the depression of the source / drain region may remove the portion of the fin-shaped structure formed by the epitaxial stack, thereby forming a source / drain groove. The sidewalls of the channel layer and the sacrificial layer are exposed in the source / drain groove. The exposed sacrificial layer is selectively and partially etched to form an internal spacer groove. Then an internal spacer feature is formed in the internal spacer feature. The source / drain feature is epitaxially grown from the sidewalls of the channel layer and the remaining fin-shaped structure in the source / drain region. After depositing the CESL 220 and the ILD layer 222, the workpiece 200 is planarized to expose the dummy gate stack 214. After removing the dummy gate stack 214, the sacrificial layer in the channel region is selectively removed to release the channel layer as a channel member. The channel members are vertically stacked one on top of another. The gate structure 224 is disposed above and surrounds each channel member.

[0036] Although not intended to be limiting, one or more embodiments of the present disclosure provide benefits. For example, the method of the present disclosure forms a silicon carbonitride hybrid fin including an amine functional group. By using an annealing process in the presence of an oxygen-containing environment, the silicon carbonitride hybrid fin can be oxidized from the outside to the inside, resulting in a volume expansion of the silicon oxycarbonitride outer layer and the hybrid fin. The formation of the outer layer and the volume expansion can close the seams or cracks in the hybrid fin. In other words, the annealing process can repair the hybrid fin after the hybrid fin is formed.

[0037] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first source / drain feature and a second source / drain feature and a hybrid fin disposed between the first source / drain feature and the second source / drain feature and extending longitudinally along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature, and the outer layer includes silicon oxycarbon nitride, and the inner feature includes silicon carbon nitride.

[0038] In some embodiments, the hybrid fin includes a middle seam. In some implementations, the middle seam is defined in the outer layer. In some cases, the middle seam is separated from the internal features by the outer layer. In some embodiments, the first source / drain feature and the second source / drain feature contact the outer layer of the hybrid fin, but are separated from the internal features of the hybrid fin. In some embodiments, the semiconductor structure may further include a second fin structure and a first fin structure extending longitudinally in a first direction. The first source / drain feature is disposed above the first fin structure, and the second source / drain feature is disposed above the second fin structure. In some embodiments, the semiconductor structure may further include an isolation feature disposed between the first fin structure and the second fin structure. The internal features of the hybrid fin extend into the isolation features, and the outer layer is disposed above the isolation features. In some cases, the hybrid fin includes a first thickness, the outer layer includes a second thickness, and the second thickness is between about 5% and about 20% of the first thickness.

[0039] In another exemplary aspect, the present disclosure is directed to a method. The method includes providing a workpiece, the workpiece including a substrate, a first fin structure on the substrate, and a second fin structure on the substrate; conformally depositing a first dielectric layer on the workpiece; conformally depositing a second dielectric layer on the first dielectric layer; after conformally depositing the second dielectric layer, planarizing the workpiece to expose the first dielectric layer on the first fin structure and the second fin structure; selectively etching back the first dielectric layer until the second dielectric layer rises above the first dielectric layer to form a hybrid fin, and annealing the workpiece to selectively form an outer layer on the hybrid fin.

[0040] In some embodiments, conformally depositing the second dielectric layer comprises using ammonia and bis(trichlorosilyl)methane. In some embodiments, conformally depositing the second dielectric layer comprises using atomic layer deposition. In some implementations, conformally depositing the second dielectric layer comprises a process temperature between about 500° C. and about 700° C. In some cases, the first dielectric layer comprises silicon oxide. In some embodiments, annealing comprises annealing in the presence of an oxygen-containing species at an annealing temperature between about 400° C. and about 500° C. In some embodiments, the oxygen-containing species comprises water or oxygen.

[0041] In yet another exemplary aspect, the present disclosure relates to a method. The method includes providing a workpiece, the workpiece including a substrate, a first fin structure on the substrate, and a second fin structure on the substrate; conformally depositing a first dielectric layer on the workpiece; conformally depositing a second dielectric layer on the first dielectric layer; after conformally depositing the second dielectric layer, planarizing the workpiece to expose the first dielectric layer on the first fin structure and the second fin structure; selectively etching back the first dielectric layer to form a hybrid fin rising above the first dielectric layer, and selectively oxidizing the hybrid fin to cause a volume expansion of the hybrid fin.

[0042] In some embodiments, prior to selectively oxidizing the hybrid fin, the hybrid fin includes a seam extending along the length of the hybrid fin, and after selectively oxidizing the hybrid fin, the seam becomes smaller. In some embodiments, conformally depositing the second dielectric layer includes using ammonia and bis(trichlorosilyl)methane. In some cases, conformally depositing the second dielectric layer includes using atomic layer deposition. In some implementations, the selective oxidation includes annealing the workpiece at an annealing temperature between about 400° C. and about 500° C. in the presence of an oxygen-containing species.

[0043] The foregoing summarizes the features of multiple embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a first source / drain characteristic and a second source / drain characteristic; as well as a hybrid fin disposed between the first source / drain feature and the second source / drain feature and extending longitudinally in a first direction, wherein the hybrid fin comprises an inner feature and an outer layer disposed around the inner feature, wherein the outer layer comprises silicon oxycarbonitride and the inner feature comprises silicon carbonitride, Wherein the hybrid fin comprises a central seam.

2. The semiconductor structure of claim 1, wherein the intermediate seam and a portion of the outer layer extend into the interior feature. The semiconductor structure of claim 1 , wherein the intermediate seam is defined in the outer layer. 4 . The semiconductor structure of claim 1 , wherein the intermediate seam is separated from the interior feature by the outer layer. 5 . The semiconductor structure of claim 1 , the first source / drain feature and the second source / drain feature contacting the outer layer of the hybrid fin but spaced apart from the inner features of the hybrid fin.

6. The semiconductor structure according to claim 1, further comprising: a first fin structure and a second fin structure extending longitudinally along the first direction, The first source / drain feature is disposed on the first fin structure, and the second source / drain feature is disposed on the second fin structure.

7. The semiconductor structure according to claim 6, further comprising: an isolation feature disposed between the first fin structure and the second fin structure, wherein the inner feature of the hybrid fin extends into the isolation feature, Wherein the outer layer is disposed over the isolation features.

8. The semiconductor structure according to claim 1, wherein the hybrid fin comprises a first thickness, wherein the outer layer comprises a second thickness, The second thickness is between 5% and 20% of the first thickness.

9. A method for manufacturing a semiconductor structure, comprising: providing a workpiece comprising a substrate, a first fin structure on the substrate, and a second fin structure on the substrate; conformally depositing a first dielectric layer over the workpiece; conformally depositing a second dielectric layer over the first dielectric layer; After said conformally depositing said second dielectric layer, planarizing said workpiece to expose said first dielectric layer over said first fin structure and said second fin structure; selectively etching back the first dielectric layer until the second dielectric layer rises above the first dielectric layer to form a hybrid fin; as well as The workpiece is annealed to selectively form an outer layer on the hybrid fin.

10. The method of claim 9, wherein the conformally depositing the second dielectric layer comprises using ammonia and bis(trichlorosilyl)methane. The method of claim 9 , wherein the conformally depositing the second dielectric layer comprises using atomic layer deposition.

12. The method of claim 9, wherein said conformally depositing said second dielectric layer comprises a process temperature between 500°C and 700°C. The method of claim 9 , wherein the first dielectric layer comprises silicon oxide.

14. The method of claim 9, wherein the annealing comprises annealing at an annealing temperature between 400°C and 500°C in the presence of an oxygen-containing species.

15. The method of claim 14, wherein the oxygen-containing species comprises water or oxygen.

16. A method of manufacturing a semiconductor structure, comprising: providing a workpiece comprising a substrate, a first fin structure on the substrate, and a second fin structure on the substrate; conformally depositing a first dielectric layer over the workpiece; conformally depositing a second dielectric layer over the first dielectric layer; After said conformally depositing said second dielectric layer, planarizing said workpiece to expose said first dielectric layer over said first fin structure and said second fin structure; selectively etching back the first dielectric layer to form a hybrid fin raised above the first dielectric layer; as well as The hybrid fins are selectively oxidized to cause volume expansion of the hybrid fins.

17. The method according to claim 16, in, Prior to the selectively oxidizing the hybrid fin, the hybrid fin includes a seam extending along a length of the hybrid fin, Wherein, after the selective oxidation of the hybrid fin, the seam becomes smaller.

18. The method of claim 16, wherein the conformally depositing the second dielectric layer comprises using ammonia and bis(trichlorosilyl)methane.

19. The method of claim 16, wherein the conformally depositing the second dielectric layer comprises using atomic layer deposition.

20. The method of claim 16, wherein the selectively oxidizing comprises annealing the workpiece at an annealing temperature between 400°C and 500°C in the presence of an oxygen-containing species.

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