Display devices

Abstract

The display device includes: a display panel comprising a plurality of pixels; a timing controller for generating a transmission start signal; a transmission driver for supplying transmission control signals to the plurality of pixels based on the transmission start signal received from the timing controller; a first scan driver for supplying a first scan signal to the plurality of pixels; a second scan driver for supplying a second scan signal to the plurality of pixels; and a data driver for supplying data signals to the plurality of pixels. The timing controller adjusts the timing of supplying the transmission start signal based on changes in the driving frequency.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0020319, filed on February 19, 2020, and all benefits derived from that application, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to display devices, and more specifically, to pixels and display devices including such pixels. Background Technology

[0003] With the development of information technology, the importance of display devices as the connection medium between users and information has increased. Therefore, the use of display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays is increasing.

[0004] Each pixel of a display device may include a transistor containing a driving transistor and may emit light with a brightness corresponding to the data voltage supplied through a data line. The display device may use the combination of pixel emission to display image frames. Summary of the Invention

[0005] Recently, high-speed driving for display screens operating at high frequencies (e.g., 120 Hz) has been desired to improve image quality. However, with high-speed driving, the threshold voltage charging time of the driving transistor for each pixel can be shortened.

[0006] Embodiments of this disclosure provide a display device in which the threshold voltage of the driving transistor can be effectively compensated even when the display device is driven at a high driving frequency.

[0007] According to an embodiment of the present invention, a display device includes: a display panel including a plurality of pixels; a timing controller for generating a transmission start signal; a transmission driver for supplying transmission control signals to the plurality of pixels based on the transmission start signal received from the timing controller; a first scan driver for supplying a first scan signal to the plurality of pixels; a second scan driver for supplying a second scan signal to the plurality of pixels; and a data driver for supplying data signals to the plurality of pixels. In such an embodiment, the timing controller adjusts the duration of supplying the transmission start signal based on a change in the driving frequency.

[0008] In one embodiment, the timing controller may increase the duration of the transmission start signal supply as the drive frequency increases.

[0009] In one embodiment, the timing controller may adjust the period of the clock signal supplied to the transmit driver based on changes in the drive frequency.

[0010] In an embodiment, the supply period of the transmit control signal output by the transmit driver when the drive frequency is the first drive frequency can be the same as the supply period of the transmit control signal output by the transmit driver when the drive frequency is the second drive frequency, wherein the second drive frequency can be greater than the first drive frequency.

[0011] In an embodiment, each of the plurality of pixels may include: a first transistor; a light-emitting element including a first electrode electrically connected to a second electrode of the first transistor and a second electrode connected to a second power supply; and a third transistor connected between the second electrode of the first transistor and the gate electrode of the first transistor, wherein the third transistor may include a gate electrode for receiving a second scan signal.

[0012] In an embodiment, each of the plurality of pixels may include: a fifth transistor connected between a first power source and a first electrode of a first transistor, wherein the fifth transistor may include a gate electrode for receiving a transmission control signal; and a sixth transistor connected between a second electrode of a first transistor and a first electrode of a light-emitting element, wherein the sixth transistor may include a gate electrode for receiving a previously transmitted transmission control signal.

[0013] In an embodiment, each of the plurality of pixels may include: a second transistor connected between a data line receiving a data signal and a third node, wherein the second transistor may include a gate electrode for receiving a first scan signal; a fourth transistor connected between a first power supply and the third node, wherein the fourth transistor may include a gate electrode for receiving a transmit control signal; a first capacitor connected between a second electrode of the first transistor and the third node; a second capacitor connected between the first power supply and the gate electrode of the first transistor; and a seventh transistor connected between a first electrode of the light-emitting element and an initialization power supply, wherein the seventh transistor may include a gate electrode for receiving a second scan signal.

[0014] In an embodiment, during the period when the second scan signal is at the gate on level, the period during which the previous transmit control signal was at the gate on level may not overlap with the period during which the transmit control signal was at the gate on level.

[0015] In an embodiment, during a first time period, the voltage of the initialization power supply can be supplied to the gate electrode of the first transistor and the first electrode of the light-emitting element; during a second time period, the voltage of the first power supply can be supplied to the first electrode of the first transistor; during a third time period, the first transistor can be connected by a diode based on the voltage of the first power supply; and during a fourth time period, the second transistor can be turned on and the data signal can be supplied to the third node.

[0016] In an embodiment, the third transistor may be turned on during the first, third, and fourth time periods, and may be turned off during the second time period.

[0017] In one embodiment, during a first time period, the fourth and fifth transistors can be turned off, and the sixth transistor can be turned on.

[0018] In one embodiment, during the third time period, the fourth and fifth transistors can be turned on, and the sixth transistor can be turned off.

[0019] In one embodiment, the transmit driver may include: a first transmit driver that supplies transmit control signals to a plurality of pixels; and a second transmit driver that supplies the previously transmitted control signals to the plurality of pixels via a line independent of the transmit control signals.

[0020] In an embodiment, the first scan driver or the second scan driver may be located on opposite sides of the display panel for bilateral driving operation, and the first transmit driver or the second transmit driver may be located on one side of the display panel for unilateral driving operation.

[0021] In an embodiment, a first scan driver can shift a first scan signal and supply the shifted scan signal to pixels in a row of the display panel; a second scan driver can simultaneously supply a second scan signal to pixels in two or more consecutive rows of the display panel; a first transmit driver can simultaneously supply transmit control signals to pixels in two or more consecutive rows of the display panel; and a second transmit driver can simultaneously supply previously transmitted control signals to pixels in two or more consecutive rows of the display panel.

[0022] In an embodiment, each of the plurality of pixels may include: a second transistor connected between a data line receiving a data signal and a third node, wherein the second transistor may include a gate electrode for receiving a first scan signal; a fourth transistor connected between a reference power supply set differently based on a driving frequency and the third node, wherein the fourth transistor may include a gate electrode for receiving a transmit control signal; a first capacitor connected between a second electrode of the first transistor and the third node; a second capacitor connected between the first power supply and the gate electrode of the first transistor; and a seventh transistor connected between a first electrode of the light-emitting element and an initialization power supply, wherein the seventh transistor may include a gate electrode for receiving a second scan signal.

[0023] In an embodiment, each of the plurality of pixels may further include: a second transistor connected between a data line receiving a data signal and a first electrode of a first transistor, wherein the second transistor may include a gate electrode for receiving a first scan signal; a fifth transistor connected between a first power supply and a first electrode of the first transistor, wherein the fifth transistor may include a gate electrode for receiving a transmit control signal; and a sixth transistor connected between a second electrode of the first transistor and a first electrode of a light-emitting element, wherein the sixth transistor may include a gate electrode for receiving a transmit control signal.

[0024] In one embodiment, as the driving frequency increases, the second scan driver can extend the time period for supplying the second scan signal.

[0025] In an embodiment, each of the plurality of pixels may further include: a fourth transistor connected between the gate electrode of the first transistor and an initialization power supply, wherein the fourth transistor may include a gate electrode that receives a previous first scan signal; a seventh transistor connected between the initialization power supply and a first electrode of the light-emitting element, wherein the seventh transistor may include a gate electrode that receives the first scan signal; and a storage capacitor connected between the first power supply and the gate electrode of the first transistor.

[0026] In an embodiment, the period during which the first scan signal was at the gate on level may not overlap with the period during which the first scan signal was at the gate on level.

[0027] In embodiments of the pixel and display device including the pixel according to the present disclosure, the threshold voltage of the driving transistor is effectively compensated by providing a second emission control signal to the pixel via a separate emission driver.

[0028] In such an embodiment, the threshold voltage of the driving transistor can be compensated using the voltage of the first power supply, which serves as a constant voltage source, or the data voltage.

[0029] In such an embodiment, by adjusting the transmit start signal differently based on the drive frequency of the display device, sufficient time can be ensured for compensating the threshold voltage of the drive transistor, even in high-speed driving. Attached Figure Description

[0030] The above and other features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in a further detailed manner:

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0032] Figure 2 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure;

[0033] Figure 3 It is used to describe Figure 2 The signal timing diagram for pixel operations;

[0034] Figure 4 It is a graph showing the change in brightness as a function of the driving frequency of the display device.

[0035] Figure 5 This is a conceptual diagram of lines used to describe a transmit driver according to embodiments of the present disclosure;

[0036] Figure 6 This is a block diagram illustrating a display device according to an alternative embodiment of the present disclosure;

[0037] Figure 7 This is a signal timing diagram illustrating the transmission control signal according to the driving frequency variation in the display device according to an embodiment of the present disclosure;

[0038] Figure 8 This is a diagram illustrating the range of data voltage varying according to the driving frequency according to an embodiment of the present disclosure;

[0039] Figure 9 This is a circuit diagram illustrating pixels according to alternative embodiments of the present disclosure; and

[0040] Figure 10 It is used to describe Figure 9 The signal timing diagram for the operation of pixels. Detailed Implementation

[0041] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0042] It should be understood that when a component is referred to as being "on" another component, the component may be directly "on" the other component, or there may be an intermediate component between the component and the other component. Conversely, when a component is referred to as being "directly" "on" another component, there is no intermediate component.

[0043] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second area, second layer, or second part.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms that include “at least one”, unless the context clearly indicates otherwise. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or “including” as used in this specification specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0045] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “below” the other elements will be oriented as being “above” the other elements. Thus, depending on the specific orientation of the drawing, the exemplary term “below” can cover both “below” and “above” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented as being “above” the other elements. Thus, the exemplary terms “below” and “under” can cover both “above” and “below” orientations.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless specifically defined herein.

[0047] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0049] refer to Figure 1 An embodiment of the display device DD may include a display panel 100, a timing controller 200, a first scan driver 300, a second scan driver 400, a transmit driver 500, a data driver 600, and a power manager 700.

[0050] The timing controller 200 can generate a first drive control signal SCS1, a second drive control signal SCS2, a third drive control signal ECS, and a fourth drive control signal DCS in response to a synchronization signal supplied from an external source. The first drive control signal SCS1 can be supplied to a first scan driver 300, the second drive control signal SCS2 can be supplied to a second scan driver 400, the third drive control signal ECS can be supplied to a transmit driver 500, and the fourth drive control signal DCS can be supplied to a data driver 600. In an embodiment, the timing controller 200 can rearrange or convert externally supplied input image data into RGB image data to supply the RGB image data to the data driver 600.

[0051] The first drive control signal SCS1 may include a first scan start signal and a clock signal. The first scan start signal can control the first timing of the first scan signal. The clock signal can be used to shift the first scan start signal.

[0052] The second drive control signal SCS2 may include a second scan start signal and a clock signal. The second scan start signal can control the first timing of the second scan signal. The clock signal can be used to shift the second scan start signal.

[0053] The third drive control signal (ECS) can include a transmit start signal and a clock signal. The transmit start signal controls the initial timing of the transmit signal. The clock signal can be used to shift the transmit start signal.

[0054] The fourth drive control signal (DCS) may include a source start pulse and a clock signal. The source start pulse controls the start time of data sampling. The clock signal can be used to control the sampling operation.

[0055] The clock signal can be a frequency signal corresponding to the driving frequency of the display device DD. Therefore, the timing controller 200 can adjust the period of the clock signal supplied to the transmitter driver 500 in response to changes in the driving frequency.

[0056] In one embodiment, the timing controller 200 can generate a transmit start signal corresponding to the drive frequency of the display device DD. In one embodiment, for example, as the drive frequency increases, the timing controller 200 can increase the duration of supplying the transmit start signal.

[0057] The first scan driver 300 can receive a first drive control signal SCS1 from the timing controller 200, and based on the first drive control signal SCS1, sequentially supply the first scan signal to the first scan lines SL1[0], SL1[1], ... and SL1[p]. When the first scan signal is supplied sequentially, pixels can be selected (or turned on) in units of horizontal lines (or pixel row units), and data signals can be supplied to the selected pixels.

[0058] The first scan signal can be set to a gate on level (e.g., a low voltage). A transistor in the pixel that receives the first scan signal (e.g., described later) Figure 2 The second transistor T2 can be turned on or in the on state when the first scan signal is supplied.

[0059] The second scan driver 400 can receive the second drive control signal SCS2 from the timing controller 200, and supply the second scan signal sequentially to the second scan lines SL2[0], SL2[1], ... and SL2[p] based on the second drive control signal SCS2.

[0060] The second scan signal can be set to a gate on level (e.g., a low-level voltage). A transistor in the pixel that receives the second scan signal (e.g., Figure 2 The third transistor T3 and the seventh transistor T7 can be turned on or in the on state when the second scan signal is supplied.

[0061] The first scan driver 300 and the second scan driver 400 may include scan stages in the form of shift registers. The first scan driver 300 and the second scan driver 400 can generate a first scan signal and a second scan signal by sequentially transmitting a scan start signal in the form of pulses including an on level to the next scan stage under the control of a clock signal.

[0062] The transmitter driver 500 can receive the third drive control signal ECS (or the transmitter start signal in the third drive control signal ECS) from the timing controller 200, and supply the transmitter control signal sequentially to the transmitter control lines EL[0], EL[1], ... and EL[p] based on the third drive control signal ECS (or the transmitter start signal).

[0063] The transmit control signal can be set to a gate on level (e.g., a low voltage). A transistor in a pixel that receives the transmit control signal can be turned on or in an on state when the transmit control signal is supplied, and can be turned off or in an off state when the transmit control signal is not supplied.

[0064] The transmit control signal can control the transmit time of pixel PX[i,j]. In an embodiment, the transmit control signal can be set to a width wider than the width of the scan signal. In an embodiment, the transmit control signal can have multiple gate cutoff level (e.g., high-level voltage) periods during a frame period.

[0065] The display panel 100 may include a plurality of pixels PX[i,j]. The plurality of pixels PX[i,j] may be arranged in a matrix having p rows (p being natural numbers) and q columns (q being natural numbers), and pixels PX[i,j] located in the same row may be connected to the same first scan line, the same second scan line, and the same transmit control line. In such an embodiment, pixels PX[i,j] located in the same column may be connected to the same data line.

[0066] In one embodiment, for example, the pixel PX[i,j] located in the i-th row and j-th column can be connected to the first scan line SL1[i] corresponding to the i-th row (or horizontal line), the second scan line SL2[i] corresponding to the i-th row, the emission control line EL[i] corresponding to the i-th row, and the data line DL[j] corresponding to the j-th column.

[0067] Alternatively, the first scan lines SL1[0], SL1[1], ..., and SL1[p], the second scan lines SL2[0], SL2[1], ..., and SL2[p], the transmit control lines EL[0], EL[1], ..., and EL[p], and the data lines DL[1], DL[2], ..., and DL[q] can be modified in various ways depending on the circuit configuration. In one embodiment, for example, the pixel PX[i,j] located in the i-th row and j-th column can be connected to the transmit control line EL[ik] corresponding to the ik-th row (k is a natural number equal to or less than 10).

[0068] The data driver 600 can receive a fourth drive control signal DCS and image data RGB from the timing controller 200. The data driver 600 can supply data signals to data lines DL[1], DL[2], ..., and DL[q] in response to the fourth drive control signal DCS. The data signals supplied to the data lines DL[1], DL[2], ..., and DL[q] can be supplied to the pixel PX[i,j] selected by the first scan signal. In such an embodiment, the data driver 600 can supply data signals to the data lines DL[1], DL[2], ..., and DL[q] to synchronize with the first scan signal.

[0069] The power manager 700 can supply the voltage of the first power supply VDD, the voltage of the second power supply VSS, and the voltage of the initialization power supply Vint to the display panel 100. In an embodiment, the power manager 700 can further supply the voltage of the reference power supply Vref (reference... Figure 2 The voltage (as described in the description) is supplied to the display panel 100.

[0070] The power manager 700 can supply low and high power supplies corresponding to the gate on and gate off levels of the first scan signal, the second scan signal, and / or the transmit control signal to the first scan driver 300, the second scan driver 400, and / or the transmit driver 500. The low power supply can have a voltage level lower than that of the high power supply. However, this is merely exemplary, and alternatively, at least one selected from the first power supply VDD, the second power supply VSS, the initialization power supply Vint, the low power supply, and the high power supply can be supplied from the timing controller 200 or the data driver 600.

[0071] A first power supply VDD and a second power supply VSS can generate voltages for driving the light-emitting elements in each pixel of the display panel 100. In one embodiment, the voltage of the second power supply VSS may be lower than the voltage of the first power supply VDD. In one embodiment, for example, the voltage of the first power supply VDD may be a positive voltage, and the voltage of the second power supply VSS may be a negative voltage.

[0072] The initialization power supply Vint can be a power supply that initializes each pixel in the display panel 100. In one embodiment, for example, the driving transistors and / or light-emitting elements in a pixel can be initialized by the voltage of the initialization power supply Vint. The initialization power supply Vint can be a negative voltage.

[0073] In the following text, for ease of description, the pixel located in the i-th row and j-th column can be referred to as pixel PX[i,j], the first scan line corresponding to the i-th row can be referred to as the first scan line SL1[i], the second scan line corresponding to the i-th row can be referred to as the second scan line SL2[i], the emission control line corresponding to the i-th row can be referred to as the emission control line EL[i], and the data line corresponding to the j-th column can be referred to as the data line DL[j]. Additionally, the emission control line corresponding to the ik-th row (k is a natural number equal to or less than 10) can be referred to as the previous emission control line EL[ik].

[0074] In such an embodiment, a first scan signal can be supplied to a first scan line SL1[i], a second scan signal can be supplied to a second scan line SL2[i], a transmit control signal can be supplied to a transmit control line EL[i], and a previous transmit control signal can be supplied to a previous transmit control line EL[ik].

[0075] Figure 2 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure.

[0076] exist Figure 2 In the diagram, for ease of illustration and description, pixel PX[i,j] located in the i-th row (or horizontal line) and j-th column is shown, but other pixels may have the same configuration as pixel PX[i,j].

[0077] refer to Figure 2 An embodiment of pixel PX[i,j] may include a light-emitting element LD, a first transistor T1 to a seventh transistor T7, a first capacitor C1 and a second capacitor C2.

[0078] The light-emitting element LD may include a first electrode electrically connected to a second electrode (e.g., a drain electrode) of a first transistor T1 and a second electrode connected to a second power supply VSS. In an embodiment, the first electrode of the light-emitting element LD may be electrically connected to the second electrode of the first transistor T1 via a sixth transistor T6.

[0079] The light-emitting element (LD) can generate light of a predetermined brightness corresponding to the amount of current (drive current) supplied from the first transistor T1. In an embodiment, the light-emitting element (LD) can be an organic light-emitting diode (OLED) including an organic light-emitting layer. In an embodiment, the first electrode of the light-emitting element (LD) can be an anode electrode, and the second electrode can be a cathode electrode. Alternatively, the first electrode of the light-emitting element (LD) can be a cathode electrode, and the second electrode can be an anode electrode.

[0080] In an alternative embodiment, the light-emitting element LD may be an inorganic light-emitting element comprising or formed of inorganic materials. Alternatively, the light-emitting element LD may have a structure in which a plurality of inorganic light-emitting elements are connected in parallel and / or in series between the second power supply VSS and the second electrode of the first transistor T1.

[0081] The first transistor T1 may include a first electrode electrically connected to a first power supply VDD, a second electrode electrically connected to a first electrode of a light-emitting element LD, and a gate electrode connected to a first node N1. In an embodiment, the first electrode of the first transistor T1 may be connected to the first power supply VDD via a fifth transistor T5. The second electrode of the first transistor T1 may be connected to the light-emitting element LD via a sixth transistor T6. The first transistor T1 may supply drive current to the light-emitting element LD. The first transistor T1 may serve as a drive transistor for pixel PX[i,j]. In such an embodiment, the first transistor T1 may control the amount of current flowing from the first power supply VDD through the light-emitting element LD to the second power supply VSS in accordance with the voltage applied to the first node N1.

[0082] The first capacitor C1 can be connected between the second node N2 and the third node N3, which correspond to the second electrode of the first transistor T1. The first capacitor C1 can be charged with the differential voltage between the second node N2 and the third node N3.

[0083] The second capacitor C2 can be connected between the first power supply VDD and the first node N1 corresponding to the gate electrode of the first transistor T1. The second capacitor C2 can be charged with the differential voltage between the first power supply VDD and the first node N1.

[0084] A second transistor T2 can be connected between the data line DL[j] and the third node N3. The second transistor T2 may include a gate electrode for receiving a first scan signal. In one embodiment, for example, the gate electrode of the second transistor T2 may be connected to the first scan line SL1[i]. The second transistor T2 can be turned on when the first scan signal is supplied to the first scan line SL1[i] to electrically connect the data line DL[j] and the third node N3 to each other. Therefore, the data voltage (or data signal) supplied to the data line DL[j] can be transmitted to the third node N3.

[0085] In one embodiment, when the second transistor T2 is turned on corresponding to the first scan signal supplied to the first scan line SL1[i], the data signal supplied through the data line DL[j] can be written to the pixel PX[i,j]. In such an embodiment, by sharing charge between the first capacitor C1 and the second capacitor C2, the first node N1 and the second node N2 can have voltages corresponding to the capacitance ratio between the first capacitor C1 and the second capacitor C2.

[0086] A third transistor T3 can be connected between the first node N1 and the second node N2. The third transistor T3 may include a gate electrode for receiving a second scan signal. In one embodiment, for example, the gate electrode of the third transistor T3 may be connected to the second scan line SL2[i]. The third transistor T3 can be turned on when the second scan signal is supplied to the second scan line SL2[i] to electrically connect the first node N1 and the second node N2 to each other. When the first node N1 and the second node N2 are electrically connected to each other, the first transistor T1 may have a diode-equivalent form or become a diode-connected transistor. When the first transistor T1 has a diode-equivalent form, the threshold voltage of the first transistor T1 can be compensated by the charge charged into the first electrode of the first transistor T1.

[0087] The first transistor T1 can supply driving current to the light-emitting element LD based on the data signal supplied from the data line DL[j], the first capacitor C1, and the second capacitor C2. The driving current can satisfy the following formula 1.

[0088] [Formula 1]

[0089]

[0090] In Formula 1, Id refers to the drive current, ρ refers to the inherent characteristics of the first transistor T1, Vdd refers to the voltage of the first power supply VDD, Vdata refers to the data signal, CC1 refers to the capacitance of the first capacitor C1, and CC2 refers to the capacitance of the second capacitor C2. The light-emitting element LD can emit light with a brightness corresponding to the drive current Id.

[0091] A fourth transistor T4 can be connected between the first power supply VDD and the third node N3. The fourth transistor T4 may include a gate electrode for receiving a transmit control signal (the transmit control signal corresponding to the i-th pixel row). The gate electrode of the fourth transistor T4 can be connected to the transmit control line EL[i] (or the transmit control line corresponding to the i-th pixel row). The fourth transistor T4 can be turned on when the transmit control signal is supplied to the transmit control line EL[i] to supply the voltage of the first power supply VDD to the third node N3. Therefore, the voltage of the third node N3 can be initialized to the voltage of the first power supply VDD.

[0092] In one embodiment, a fourth transistor T4 may be coupled between a reference power supply Vref, which is different from the first power supply VDD, and the third node N3. In such an embodiment, when the fourth transistor T4 is turned on, it can supply the voltage of the reference power supply Vref to the third node N3. In this embodiment, since the reference power supply Vref initializes the voltage of the third node N3, it can be set differently according to the driving frequency of the display device DD to compensate for the increased brightness during high-speed driving. In one embodiment, for example, as the driving frequency of the display device DD increases, the voltage of the reference power supply Vref is set low, and therefore the light-emitting element LD can emit light with a constant brightness, regardless of the change in driving frequency.

[0093] A fifth transistor T5 may be connected between the first power supply VDD and the first electrode of the first transistor T1. The fifth transistor T5 may include a gate electrode for receiving a transmit control signal. In one embodiment, for example, the gate electrode of the fifth transistor T5 may be connected to the transmit control line EL[i]. The fifth transistor T5 may be turned on when the transmit control signal is supplied through the transmit control line EL[i] to connect the first electrode of the first transistor T1 to the first power supply VDD. Therefore, when the transmit control signal is supplied through the transmit control line EL[i], the voltage or DC voltage of the first power supply VDD connected to the first electrode of the first transistor T1 may be used to compensate for the threshold voltage of the first transistor T1.

[0094] The sixth transistor T6 may be connected between the second node N2 corresponding to the second electrode of the first transistor T1 and the fourth node N4 corresponding to the first electrode of the light-emitting element LD. The sixth transistor T6 may include a gate electrode that receives a previously emitted control signal. In one embodiment, for example, the gate electrode of the sixth transistor T6 may be connected to the previously emitted control line EL[ik].

[0095] The previous emission control signal may be the emission control signal corresponding to the ik-th pixel row. In an embodiment, the previous emission control line EL[ik] may be a line branching from the emission control line corresponding to the ik-th pixel row. In such an embodiment, the emission control signal may be a signal in which the previous emission control signal is shifted by k horizontal time intervals. In an embodiment, k may be 3 or 6, but this is merely exemplary and not limited thereto. In an alternative embodiment, for example, the previous emission control line EL[ik] or the previous emission control signal may be determined based on the time used for threshold voltage compensation, the number of pixel rows controlled simultaneously, the resolution, the length of a horizontal time interval (1H), and its relationship to the emission control signal supplied through the emission control line EL[i].

[0096] The sixth transistor T6 can be turned on when a previous emission control signal is supplied to the previous emission control line EL[ik] to electrically connect the second node N2 and the fourth node N4 to each other. In an embodiment, the sixth transistor T6 can be turned off when the previous emission control signal is not supplied to the previous emission control line EL[ik]. In such an embodiment, even when an emission control signal is supplied through the emission control line EL[i], threshold voltage compensation of the first transistor T1 can be performed while maintaining the non-emission state of the light-emitting element LD.

[0097] The seventh transistor T7 can be connected between the fourth node N4, corresponding to the first electrode of the light-emitting element LD, and the initialization power supply Vint. The seventh transistor T7 may include a gate electrode for receiving the second scan signal. Therefore, the gate electrode of the seventh transistor T7 can be connected to the second scan line SL2[i] for supplying the second scan signal.

[0098] The seventh transistor T7 can be turned on when the second scan signal is supplied to the second scan line SL2[i] to initialize the voltage of the fourth node N4 (or the voltage of the first electrode of the light-emitting element LD) to the voltage of the initialization power supply Vint.

[0099] In an embodiment, Figure 2 The transistors T1, T2, T3, T4, T5, T6, and T7 shown can be p-type transistors, such as p-channel metal-oxide-semiconductor (“PMOS”) transistors. In one embodiment, for example, Figure 2 The transistors T1, T2, T3, T4, T5, T6, and T7 shown may be low-temperature polycrystalline silicon (“LTPS”) thin-film transistors. However, this disclosure is not limited thereto, and alternatively, transistors T1, T2, T3, T4, T5, T6, and T7 may be n-type transistors, such as n-channel metal-oxide-semiconductor (“NMOS”) transistors.

[0100] Figure 3 It is used to describe Figure 2 The signal timing diagram for the operation of pixels. Figure 4 It is a graph showing the change in brightness as the driving frequency of the display device changes.

[0101] because Figure 2 The pixel PX[i,j] shown includes a p-type transistor, when Figure 3 When signals EM[i], EM[ik], GW[i], and GW2[i] are high, signals EM[i], EM[ik], GW[i], and GW2[i] can have gate cutoff voltages, and when Figure 3When signals EM[i], EM[ik], GW[i], and GW2[i] are at a low level, signals EM[i], EM[ik], GW[i], and GW2[i] may have gate turn-on voltages. However, this disclosure is not limited thereto. In alternative embodiments in which pixels PX[i,j] include n-type transistors, this can be reversed.

[0102] Figure 3 The timing diagram shows some waveforms of the signal within a frame period. Additionally, Figure 3 It is shown that a first scan signal GW[i] is supplied to a first scan line SL1[i], a second scan signal GW2[i] is supplied to a second scan line SL2[i], a transmit control signal EM[i] is supplied to a transmit control line EL[i], and a previous transmit control signal EM[ik] is supplied to a previous transmit control line EL[ik].

[0103] Pixel PX[i,j] can emit light during periods when both the transmit control signal EM[i] and the previous transmit control signal EM[ik] are at the gate on level (e.g., the fifth period P5), and pixel PX[i,j] (or light-emitting element LD) can not emit light during periods when at least one of the transmit control signal EM[i] and the previous transmit control signal EM[ik] is at the gate off level (e.g., the first period P1, the second period P2, the third period P3, and the fourth period P4, etc.).

[0104] The second scan signal GW2[i] may include a time period in which the second scan signal GW2[i] is at a gate-on level during the period when pixel PX[i,j] (or light-emitting element LD) is not emitting light. During the time period when the second scan signal GW2[i] is at a gate-on level, the first electrode of the light-emitting element LD and / or the gate electrode of the first transistor T1 may be initialized, or the threshold voltage of the first transistor T1 may be compensated. In addition, the second scan signal GW2[i] may include a time period in which the second scan signal GW2[i] is at a gate-off level (the time period overlapping with the second time period P2), which overlaps with the time period in which the transmit control signal EM[i] is at a gate-on level.

[0105] In such an embodiment, during the period when the second scan signal GW2[i] is at the gate on level, the period when the previous transmit control signal EM[ik] is at the gate on level may not overlap with the period when the transmit control signal EM[i] is at the gate on level, so as to maintain a non-transmit state (or to prevent incorrect transmission).

[0106] In one embodiment, at the first time point t1, when the transmit control signal EM[i] changes from a gate-on level to a gate-off level, the fifth transistor T5 and the fourth transistor T4 can be turned off. Additionally, at the first time point t1, when the previous transmit control signal EM[ik] changes from a gate-off level to a gate-on level, the sixth transistor T6 can be turned on. In this embodiment, when the second scan signal GW2[i] maintains a gate-on level, the seventh transistor T7 can be turned on. Therefore, during the period between the first time point t1 and the second time point t2, when the voltage of the initialization power supply Vint is supplied to the fourth node N4 (or the first electrode of the light-emitting element LD), the first electrode (or anode electrode) of the light-emitting element LD can be initialized. Furthermore, when the voltage of the initialization power supply Vint supplied to the fourth node N4 is supplied to the first node N1 through the sixth transistor T6 and the third transistor T3, the gate electrode of the first transistor T1 (or the first node N1) can be initialized. That is, the time period between the first time point t1 and the second time point t2 can be the first time period P1 in which the first electrode of the light-emitting element LD and the gate electrode of the first transistor T1 are initialized.

[0107] At the second time point t2, when the transmit control signal EM[i] changes from gate off level to gate on level, the fourth transistor T4 and the fifth transistor T5 can be turned on. Additionally, at the second time point t2, when the previous transmit control signal EM[ik] changes from gate on level to gate off level, the sixth transistor T6 can be turned off. Furthermore, when the second scan signal GW2[i] changes from gate on level to gate off level, the third transistor T3 and the seventh transistor T7 can be turned off at the second time point t2. Therefore, the voltage of the first power supply VDD can be supplied to the first electrode of the first transistor T1 through the fifth transistor T5. Additionally, the voltage of the first power supply VDD or the reference power supply Vref can be supplied to the third node N3 through the fourth transistor T4. Therefore, the period between the second time point t2 and the third time point t3 can be a second period P2 used to eliminate the bias deviation of the first transistor T1 caused by the grayscale difference between adjacent frames and / or adjacent pixel rows.

[0108] At the third time point t3, when the transmit control signal EM[i] changes from the gate on level to the gate off level, the fifth transistor T5 and the fourth transistor T4 can be turned off. Additionally, at the third time point t3, when the previous transmit control signal EM[ik] changes from the gate off level to the gate on level, the sixth transistor T6 can be turned on. Furthermore, at the third time point t3, when the second scan signal GW2[i] changes from the gate off level to the gate on level, the seventh transistor T7 can be turned on. Therefore, the time period between the third time point t3 and the fourth time point t4 can be a first time period P1 in which the first electrode of the light-emitting element LD and the gate electrode of the first transistor T1 are initialized, similar to the time period between the first time point t1 and the second time point t2.

[0109] At the fourth time point t4, when the transmit control signal EM[i] changes from the gate cutoff level to the gate on level, the fourth transistor T4 and the fifth transistor T5 can be turned on. Additionally, when the previous transmit control signal EM[ik] changes from the gate on level to the gate cutoff level, the sixth transistor T6 can be turned off. Furthermore, when the second scan signal GW2[i] is held at the gate on level, the charge supplied by the voltage of the first power supply VDD to the first electrode of the first transistor T1 can be supplied to the gate electrode of the first transistor T1 through the third transistor T3. Therefore, the threshold voltage of the first transistor T1 can be compensated. That is, the period between the fourth time point t4 and the fifth time point t5 can be a third period P3 for compensating the threshold voltage of the first transistor T1.

[0110] In this embodiment, during the third time period P3, the first transistor T1 can be in a diode-connected configuration. The voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the second capacitor C2. Furthermore, during the third time period P3, threshold voltage compensation can be performed using the voltage of the first power supply VDD, which serves as a constant voltage source. Therefore, since the threshold voltage compensation operation is performed based on a fixed or constant voltage, rather than a data signal (data voltage) that can change according to pixel rows and / or frames, the change in bias applied to the first transistor T1 is minimal, and the hysteresis variation of the first transistor T1 can be minimized.

[0111] Subsequently, the time period between the fifth time point t5 and the sixth time point t6 can be a first time period P1 in which the first electrode of the light-emitting element LD and the gate electrode of the first transistor T1 are initialized. The time period between the sixth time point t6 and the seventh time point t7 can be a third time period P3 in which the threshold voltage of the first transistor T1 is compensated.

[0112] At time point t8, when the transmit control signal EM[i] and the previous transmit control signal EM[ik] are held at the gate cutoff level, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off. Additionally, when the second scan signal GW2[i] is held at the gate on level, the third transistor T3 and the seventh transistor T7 can be turned on. At time point t8, when the first scan signal GW[i] changes from the gate cutoff level to the gate on level, the second transistor T2 can be turned on, and the data voltage (or data signal) supplied to the data line DL[j] can be transmitted to the third node N3. Therefore, the threshold voltage (Vth) and the voltage corresponding to the data signal (data voltage) can be stored in the first capacitor C1 and the second capacitor C2 respectively according to the charge-sharing principle. That is, the time period between time point t8 and time point t9 can be the fourth time period P4 in which the data signal is written to pixel PX[i,j].

[0113] In the fifth time period P5, when the transmit control signal EM[i] and the previous transmit control signal EM[ik] become gate-on, the drive current can be supplied from the first transistor T1 to the light-emitting element LD through the sixth transistor T6. Here, the drive current can be defined or determined based on Equation 1 described above.

[0114] In the embodiments, as described above, Figure 2 The pixel PX[i,j] shown can experience a first time period P1 in which the first electrode of the light-emitting element LD and the gate electrode of the first transistor T1 are initialized, and a second time period P2 for eliminating the conduction bias deviation of the first transistor T1. In such an embodiment, Figure 2 Pixel PX[i,j] can further experience a fourth period P4 in which data is written and a fifth period P5 in which the light-emitting element LD emits light after the first period P1 and the third period P3, which is used to compensate for the threshold voltage of the first transistor T1, are repeated at least once. In such an embodiment, the first period P1 and the third period P3 can be repeated two or more times during the period in which the second scan signal GW2[i] is at the gate on level.

[0115] In the embodiments, as described above, Figure 2 Pixel PX[i,j] can use the voltage of the first power supply VDD, which is a constant voltage source, to compensate for the threshold voltage of the first transistor T1. In such an embodiment, the conduction bias deviation of the first transistor T1 can be eliminated. In such an embodiment, the threshold voltage compensation operation (i.e., the third time period P3) and the data writing operation (i.e., the fourth time period P4) of the first transistor T1 (i.e., the driving transistor) can be performed separately from each other.

[0116] In this embodiment, the threshold voltage compensation period P3 can be effectively adjusted by modifying the waveform of the transmit control signal EM[i]. Therefore, the time available for compensating the threshold voltage of the display device DD, which operates at a high drive frequency, can be ensured.

[0117] When the driving frequency of the display device DD increases, it can be reduced Figure 3 The third time period P3 is used to compensate for the threshold voltage. When the third time period P3 is reduced, since insufficient threshold voltage compensation is not performed, the current supplied to the light-emitting element LD by the first transistor T1, which is a p-type transistor, can increase, and therefore the brightness can increase. Specifically, refer to... Figure 4 As the driving frequency of the display device DD increases, the brightness of the light-emitting element LD can be increased.

[0118] Therefore, the period in which the transmit control signal EM[i] controlling the third period P3 has a gate on level is expected to be longer or long enough to ensure sufficient threshold voltage compensation time even at high drive frequencies (e.g., 240 Hz).

[0119] Furthermore, the time period in which the transmit control signal EM[i] has a gate-on level and the time period in which the previously transmitted control signal EM[ik] had a gate-on level can be controlled to not overlap with each other to prevent incorrect transmission. However, when adjusting the time period in which the transmit control signal EM[i] has a gate-on level based on the drive frequency, the time period in which the previously transmitted control signal EM[ik] had a gate-on level may not be effectively controlled to allow the time period in which the previously transmitted control signal EM[ik] had a gate-on level to not overlap with the time period in which the transmit control signal EM[i] had a gate-on level. Therefore, the time period in which the previously transmitted control signal EM[ik] had a gate-on level is expected to be controlled independently.

[0120] Figure 5 This is a conceptual diagram of a line for changing the transmit driver according to an embodiment of the present disclosure.

[0121] refer to Figure 5 In the left figure, in an embodiment, the previous emission control line EL[ik] can be branched and connected to the current pixel PX[i,j]. In such an embodiment with the line connection state described above, when the emission control signal supplied to the emission control line EL[i] of the current pixel PX[i,j] is adjusted according to the change in driving frequency, the previous emission control signal supplied from the previous emission control line EL[ik] can also be changed.

[0122] Therefore, in such embodiments, the period in which the previously transmitted control signal EM[ik] has a gate-on level may not be effectively controlled to allow the period in which the previously transmitted control signal EM[ik] has a gate-on level to not overlap with the period in which the transmitted control signal EM[i] has a gate-on level.

[0123] refer to Figure 5 As shown in the right figure, in an embodiment, the transmit driver 500 may include a first transmit driver 510 and a second transmit driver 520. In such an embodiment, the first transmit driver 510 can supply a first transmit control signal to pixel PX[i,j] via a first transmit control line EL1[i], and the second transmit driver 520 can supply a second transmit control signal to pixel PX[i,j] via a second transmit control line EL2[i].

[0124] In such an embodiment, the first transmit control line EL1[i] and the first transmit control signal can be respectively connected to... Figure 5 The transmit control line EL[i] and transmit control signal shown in the left figure are the same. In such an embodiment, the second transmit control line EL2[i] and the second transmit control signal can be respectively connected to... Figure 5 The previous transmit control line EL[ik] shown in the left figure is the same as the previous transmit control signal.

[0125] In such an embodiment, instead of branching the previous transmit control line EL[ik] as described above, when the individual second transmit driver 520 independently supplies the second transmit control signal to the pixel PX[i,j] via the second transmit control line EL2[i], the period in which the second transmit control signal has a gate-on level can be effectively controlled to allow the period in which the second transmit control signal has a gate-on level to not overlap with the period in which the first transmit control signal has a gate-on level.

[0126] Figure 6 This is a block diagram illustrating a display device according to an alternative embodiment of the present disclosure.

[0127] like Figure 5 As shown in the right figure, in an embodiment where the transmitter driver 500 includes a first transmitter driver 510 and a second transmitter driver 520, it can be based on, as Figure 6 The display panel 100 shown is equipped with a first scan driver 300, a second scan driver 400, a first transmit driver 510, and a second transmit driver 520.

[0128] exist Figure 6In this context, the first direction DR1 can be a direction corresponding to a horizontal line on which pixels are arranged, and the second direction DR2 can be a direction opposite to the first direction DR1.

[0129] refer to Figure 6 The first scan driver 300 can be located on the first direction DR1 and the second direction DR2 (or opposite sides) based on the display panel 100. That is, the first scan driver 300 can be located on the first direction DR1 and the second direction DR2 based on the pixel PX[i,j] located in the i-th row of the display panel 100, and can be operated by driving from both sides.

[0130] Similar to the first scan driver 300, the second scan driver 400 can be located on the first direction DR1 and the second direction DR2 (or opposite sides) based on the display panel 100. That is, the second scan driver 400 can be located on the first direction DR1 and the second direction DR2 based on the pixel PX[i,j] located in the i-th row of the display panel 100, and can be operated by driving from both sides.

[0131] The first transmitter driver 510 can be located on the second direction DR2 based on the display panel 100. That is, the first transmitter driver 510 can be located on the second direction DR2 based on the pixel PX[i,j] located in the i-th row of the display panel 100, and can be operated in a single-sided drive.

[0132] The second transmitter driver 520 can be located on the first direction DR1 based on the display panel 100. That is, the second transmitter driver 520 can be located on the first direction DR1 based on the pixel PX[i,j] located in the i-th row of the display panel 100, and can be operated in a single-sided drive.

[0133] In an embodiment, each of the first scan driver 300, the second scan driver 400, the first transmit driver 510, and the second transmit driver 520 can be mounted on a substrate using a thin-film process.

[0134] The first scan driver 300 can supply corresponding first scan signals (by shifting the first scan signals) in rows of pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] in which the display panel 100 is arranged. In one embodiment, for example, the first scan line SL1[i] corresponding to the i-th row can be connected to the pixel PX[i,j] located in the i-th row of the display panel 100, and the first scan signal can be supplied through the connected first scan line SL1[i]. In addition, the first scan line SL1[i+d] corresponding to the i+d-th row can be connected to the pixel PX[i+d,j], and the first scan signal can be supplied through the connected first scan line SL1[i+d].

[0135] The second scan driver 400 can simultaneously supply a second scan signal to pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] arranged in two or more consecutive rows of the display panel 100. In one embodiment, for example, the second scan driver 400 can simultaneously supply the same second scan signal from pixel PX[i,j] located in the i-th row to pixel PX[i+d,j] located in the i+d-th row (d is a natural number). That is, the second scan driver 400 can supply the second scan signal by shifting the second scan signal in two or more row units where pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] of the display panel 100 are located, and pixels can share the same second scan signal in two or more row units. In addition, pixels PX[i,j] in the i-th row to pixels PX[i+d,j] in the i+d-th row can be connected to the same second scan line (SL2[i / d]). In such an embodiment, the number of stages in the second scan driver 400 may be less than the number of stages in the first scan driver 300.

[0136] The first transmit driver 510 can simultaneously supply a first transmit control signal to pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] located in two or more consecutive rows of the display panel 100. In one embodiment, for example, the first transmit driver 510 can simultaneously supply the first transmit control signal from pixel PX[i,j] located in the i-th row to pixel PX[i+d,j] located in the i+d-th row (d is a natural number). That is, the first transmit driver 510 can supply the first transmit control signal by shifting the first transmit control signal in two or more row units where pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] of the display panel 100 are located, and pixels can share the same first transmit control signal in two or more row units. In addition, pixels PX[i,j] in the i-th row to pixels PX[i+d,j] in the i+d-th row can be connected to the same first transmit control line (EL1[i / d]). In such an embodiment, the number of stages in the first transmit driver 510 may be less than the number of stages in the first scan driver 300.

[0137] The second transmit driver 520 can simultaneously supply a second transmit control signal (or the current transmit control signal) to pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] located in two or more consecutive rows of the display panel 100. In one embodiment, for example, the second transmit driver 520 can simultaneously supply the second transmit control signal from pixel PX[i,j] located in the i-th row to pixel PX[i+d,j] located in the i+d-th row (d is a natural number). That is, the second transmit driver 520 can supply the second transmit control signal by shifting the second transmit control signal in two or more row units where pixels PX[i,j], ..., PX[i+d,j] and PX[i+d+1,j] of the display panel 100 are located, and pixels can share the same second transmit control signal in two or more row units. Additionally, pixels PX[i,j] in row i to PX[i+d,j] in row i+d can be connected to the same second transmit control line (EL2[i / d]). In such an embodiment, the number of stages in the second transmit driver 520 can be less than the number of stages in the first scan driver 300.

[0138] In embodiments, as described above, pixels located in two or more consecutive rows can be jointly controlled by the same first transmit control signal. Pixels located in two or more consecutive rows can be jointly controlled by the same second transmit control signal. Pixels located in two or more consecutive rows can be jointly controlled by the same second scan signal. In such embodiments, the corresponding first scan signals can be shifted and supplied in rows of pixels in the display panel 100. Therefore, a display device DD operating at a high driving frequency (e.g., 120Hz or higher) can be easily implemented.

[0139] Figure 6 The connection relationships shown and described above are merely exemplary, and alternatively, all of the first transmit control signal, the second transmit control signal, the first scan signal, and the second scan signal may be shifted row by row and may be sequentially supplied to the pixels located in each row.

[0140] Figure 7 This is a signal timing diagram illustrating the transmission control signal according to the driving frequency variation in the display device according to an embodiment of the present disclosure.

[0141] In this embodiment, the transmit start signal EM_FLM includes the signal generated by the transmitter. Figure 1 The timing controller 200 of the display device DD provides the third drive control signal ECS to the transmit driver 500. When the transmit start signal EM_FLM is supplied to the transmit driver 500, the transmit control signal can be sequentially shifted based on the clock signals EM_CLK1 and EM_CLK2 and output from each stage circuit of the transmit driver 500.

[0142] exist Figure 7 In this process, the transmit start signal EM_FLM, the first clock signal EM_CLK1, and the second clock signal EM_CLK2 are configured to be supplied when their levels are low. Figure 7 The transmit control signal EM[i] of the i-th stage circuit (i is a natural number) and the transmit control signal EM[i+1] of the (i+1)-th stage circuit are shown. However, the transmit start signal EM_FLM, the first clock signal EM_CLK1 and the second clock signal EM_CLK2 can be modified in various ways depending on the type and configuration of the stage circuits in the transmit driver 500.

[0143] refer to Figure 7 The operation of the transmit driver 500 in the display device DD will be described in detail below when the drive frequency is 60Hz.

[0144] In this embodiment, at a first time point c1, a transmit start signal EM_FLM is supplied to the transmit driver 500. At a second time point c2 following the first time point c1, when the first clock signal EM_CLK1 is supplied, a transmit control signal EM[i] from the i-th stage circuit can be supplied to the pixel (e.g., the pixel corresponding to the i-th row).

[0145] At the third time point c3, when the second clock signal EM_CLK2 is supplied, the transmit control signal EM[i+1] from the (i+1)th stage circuit can be applied to the pixel (e.g., the pixel corresponding to the (i+1)th row). In such an embodiment, the transmit control signal EM[i+1] supplied from the (i+1)th stage circuit can be a signal that has been shifted since the transmit control signal EM[i] supplied by the (i)th stage circuit began to be shifted (by the time period between the second time point c2 and the third time point c3).

[0146] At the fourth time point c4, when the supply of the transmit start signal EM_FLM stops, at the fifth time point c5, after the fourth time point c4, when the second clock signal EM_CLK2 is supplied, the supply of the transmit control signal EM[i] output from the i-th stage circuit stops.

[0147] At the sixth time point c6, after the fifth time point c5 when the supply of the first clock signal EM_CLK1 stops, the supply of the transmit control signal EM[i+1] output from the i+1 stage circuit stops.

[0148] In such an embodiment, when the transmit start signal EM_FLM is supplied with a drive frequency of 60Hz for 4H (H is the first level time period), the transmit control signal EM[i] of the i-th stage circuit is supplied with 6H.

[0149] When the driving frequency of the display device DD increases from 60Hz to 120Hz, the periods of the first clock signal EM_CLK1 and the second clock signal EM_CLK2 are halved. Therefore, if the transmit start signal EM_FLM is supplied with 4H at a driving frequency of 120Hz, the supply period of the transmit control signal EM[i] supplied by the i-th stage circuit is reduced and shorter than 6H, as is the case at a driving frequency of 60Hz. That is, since the supply period of the transmit control signal EM[i] decreases with increasing driving frequency, the period used to compensate the driving transistor ( Figure 2 The threshold voltage of the first transistor T1 decreases during a certain period.

[0150] In embodiments of this disclosure, the supply period of the transmit start signal EM_FLM supplied by the timing controller 200 may be increased based on the drive frequency to ensure sufficient time for compensating the threshold voltage even if the drive frequency is increased (or to keep the time for compensating the threshold voltage constant).

[0151] In one embodiment, for example, referencing Figure 7 When the driving frequency of the display device DD is 120Hz, the supply period of the transmit control signal EM[i] can be 12H' (H' is a second horizontal period whose absolute time is less than the absolute time of the first horizontal period (H)). In one embodiment, for example, H' can satisfy the following formula: 2H' = H. In such an embodiment, compared to the case where the driving frequency is 60Hz, the supply period of the transmit start signal EM_FLM can be increased to supply the transmit start signal EM_FLM during 10H'. In such an embodiment, as Figure 7 As shown, when the driving frequency is 120Hz, the supply period 10H' of the transmit start signal EM_FLM can be greater than the supply period 4H of the transmit start signal EM_FLM when the driving frequency is 60Hz.

[0152] In the embodiments, as described above, when the supply period of the transmit start signal EM_FLM increases with the increase of the drive frequency, the supply period of the transmit control signal EM[i] can remain relatively constant. In one embodiment, for example, as... Figure 7 As shown, the supply period 6H of the transmit control signal EM[i] when the drive frequency is 60Hz and the supply period 12H' of the transmit control signal EM[i] when the drive frequency is 120Hz can be the same or similar to each other.

[0153] Therefore, as the driving frequency increases from 60Hz to 120Hz or 240Hz, the supply period of the transmit control signal EM[i] can be kept constant as the supply period of the transmit start signal EM_FLM increases, and thus the supply period for the threshold voltage compensation can be ensured.

[0154] Figure 8 This is a diagram illustrating the range of data voltage varying according to the driving frequency, based on an embodiment of the present disclosure.

[0155] As described above, when the driving frequency increases, if the time period used to compensate for the threshold voltage decreases, the brightness value can gradually increase. Figure 4 As shown in the diagram. Therefore, even as the brightness value increases, it is desirable to gradually increase the swing range of the data voltage corresponding to each grayscale value (data swing range) to ensure seamless driving of the display device DD, as shown in the diagram. Figure 8 As shown in the image.

[0156] However, if the swing range of the data voltage gradually increases with the increase of the driving frequency, the power consumption of the display device DD may increase due to the increase in the data voltage used to express each gray value.

[0157] However, as mentioned above... Figure 7 In the embodiment described, in which the timing controller 200 increases the supply period of the transmit start signal EM_FLM according to the increase of the drive frequency of the display device DD, so as to ensure the period for compensating the threshold voltage even when the drive frequency increases, the increase in brightness value can be suppressed and the increase in power consumption can be prevented by not increasing the swing range of the data voltage.

[0158] In such an embodiment, the data voltage swing range (data swing range) can be set to a target range by appropriately adjusting the supply period of the transmit start signal EM_FLM according to the change in drive frequency.

[0159] Figure 9 This is a circuit diagram illustrating pixels according to an alternative embodiment of the present disclosure.

[0160] In the embodiments, as referenced above Figure 2 The described pixel can have a driving transistor that is compensated by using a first power supply VDD as a constant voltage source. Figure 2 The structure of the threshold voltage of the first transistor T1.

[0161] In alternative embodiments of this disclosure, such as Figure 9 As shown, the pixel circuit used to compensate for the threshold voltage of the driving transistor can use the data voltage (or data signal) supplied through the data line.

[0162] and Figure 2 Similarly, for ease of illustration and description, Figure 9 The image shows pixel PX[i,j] located in row i (or horizontal line) and column j, but other pixels can have the same pixel structure as pixel PX[i,j]. Figure 9 In, such as in Figure 1 In the display device DD shown, a first scan line SL1[i] from the first scan driver 300 can be connected to a pixel PX[i,j], a second scan line SL2[i] from the second scan driver 400 can be connected to a pixel PX[i,j], and an emission control line EL[i] from the emission driver 500 can be connected to a pixel PX[i,j].

[0163] refer to Figure 9 Pixel PX[i,j] may include light-emitting element LD, first transistor M1 to seventh transistor M7 and storage capacitor Cst.

[0164] In one embodiment, the light-emitting element LD may include a first electrode electrically connected to a second electrode (e.g., a drain electrode) of the first transistor M1 and a second electrode connected to a second power supply VSS. In such an embodiment, the first electrode of the light-emitting element LD may be electrically connected to the second electrode of the first transistor M1 via a sixth transistor M6.

[0165] The first transistor M1 may include a first electrode electrically connected to a first power supply VDD, a second electrode electrically connected to a first electrode of a light-emitting element LD, and a gate electrode connected to a first node ND1. In such an embodiment, the first electrode of the first transistor M1 may be connected to the first power supply VDD via a fifth transistor M5. The second electrode of the first transistor M1 may be connected to the light-emitting element LD via a sixth transistor M6. The first transistor M1 may supply driving current to the light-emitting element LD. The first transistor M1 may serve as the driving transistor for pixel PX[i,j]. That is, the first transistor M1 may control the amount of current flowing from the first power supply VDD through the light-emitting element LD to the second power supply VSS in accordance with the voltage applied to the first node ND1.

[0166] The storage capacitor Cst can be connected between the first power supply VDD and the first node ND1 corresponding to the gate electrode of the first transistor M1. The storage capacitor Cst can be charged with the differential voltage between the voltage of the first power supply VDD and the voltage of the first node ND1.

[0167] A second transistor M2 can be connected between the data line DL[j] and the first electrode of the first transistor M1. The second transistor M2 may include a gate electrode for receiving a first scan signal. In one embodiment, for example, the gate electrode of the second transistor M2 may be connected to the first scan line SL1[i]. The second transistor M2 can be turned on when the first scan signal is supplied to the first scan line SL1[i] to electrically connect the data line DL[j] to the first electrode of the first transistor M1. Therefore, the data voltage (or data signal) supplied to the data line DL[j] can be transmitted to the first electrode of the first transistor M1.

[0168] In such an embodiment, when the second transistor M2 is turned on corresponding to the first scan signal supplied to the first scan line SL1[i], the data signal supplied through the data line DL[j] can be written to the pixel PX[i,j], and the differential voltage between the voltage of the first power supply VDD and the data voltage can be stored in the storage capacitor Cst.

[0169] A third transistor M3 can be connected between the first node ND1 and the second electrode of the first transistor M1. The third transistor M3 may include a gate electrode for receiving a second scan signal. In one embodiment, for example, the gate electrode of the third transistor M3 may be connected to the second scan line SL2[i]. The third transistor M3 can be turned on when the second scan signal is supplied to the second scan line SL2[i] to electrically connect the first node ND1 and the second electrode of the first transistor M1 to each other. When the first node ND1 and the second electrode of the first transistor M1 are electrically connected to each other, the first transistor M1 may have a diode-equivalent form or become a diode-connected transistor. When the first transistor M1 has a diode-equivalent form, the threshold voltage of the first transistor M1 can be compensated by the charge charged into the first electrode of the first transistor M1. In such an embodiment, since the data voltage through the data line DL[j] is supplied to the first electrode of the first transistor M1 through the second transistor M2, the threshold voltage of the first transistor M1 can be compensated by the data voltage.

[0170] A fourth transistor M4 can be connected between the first node ND1 and the initialization power supply Vint. The fourth transistor M4 may include a gate electrode that receives the previous first scan signal. The gate electrode of the fourth transistor M4 can be connected to the previous first scan line SL1[ik]. The fourth transistor M4 can be turned on when the previous first scan signal is supplied to the previous first scan line SL1[ik] to supply the voltage of the initialization power supply Vint to the first node ND1. Therefore, the voltage of the first node ND1 can be initialized to the voltage of the initialization power supply Vint.

[0171] The first scan signal can be the first scan signal corresponding to the ik-th pixel row (k is a natural number, for example, k is 1). Therefore, the first scan line SL1[ik] can be a line branching from the first scan line corresponding to the ik-th pixel row. However, this disclosure is not limited thereto. In alternative embodiments, such as in Figure 5 In the emitter driver 500, the previous first scan line SL1[ik] may be a line provided independently or separately (or disconnected) from the first scan line corresponding to the ik-th pixel row. In one embodiment, for example, the first scan driver 300 may include a first sub-scan driver that supplies the first scan signal described above (e.g., the first scan signal corresponding to the i-th pixel row) to the pixel (e.g., the pixel located in the i-th row) and a second sub-scan driver that supplies the previous first scan signal (e.g., the first scan signal corresponding to the ik-th pixel row) to the pixel (e.g., the pixel located in the i-th row).

[0172] A fifth transistor M5 may be connected between the first power supply VDD and the first electrode of the first transistor M1. The fifth transistor M5 may include a gate electrode for receiving a transmit control signal. In one embodiment, for example, the gate electrode of the fifth transistor M5 may be connected to the transmit control line EL[i]. The fifth transistor M5 may be turned on when the transmit control signal is supplied through the transmit control line EL[i] to connect the first electrode of the first transistor M1 to the first power supply VDD.

[0173] The sixth transistor M6 can be connected between the second electrode of the first transistor M1 and the first electrode of the light-emitting element LD. The sixth transistor M6 may include a gate electrode for receiving a transmission control signal. In one embodiment, for example, the gate electrode of the sixth transistor M6 may be connected to the transmission control line EL[i].

[0174] The sixth transistor M6 can be turned on when the transmit control signal is supplied to the transmit control line EL[i], so as to electrically connect the second electrode of the first transistor M1 and the first electrode of the light-emitting element LD to each other.

[0175] The seventh transistor M7 can be connected between the first electrode of the light-emitting element LD and the initialization power supply Vint. The seventh transistor M7 may include a gate electrode for receiving the first scan signal. Therefore, the gate electrode of the seventh transistor M7 can be connected to the first scan line SL1[i] that supplies the first scan signal.

[0176] The seventh transistor M7 can be turned on when the first scan signal is supplied to the first scan line SL1[i] to initialize the first electrode of the light-emitting element LD to the voltage of the initialization power supply Vint.

[0177] In an embodiment, Figure 9 The transistors M1, M2, M3, M4, M5, M6, and M7 shown can be p-type transistors, such as PMOS transistors. In one embodiment, for example, Figure 9 The transistors M1, M2, M3, M4, M5, M6, and M7 shown may be LTPS thin-film transistors. However, this disclosure is not limited thereto, and transistors M1, M2, M3, M4, M5, M6, and M7 may be n-type transistors, such as NMOS transistors.

[0178] Figure 10 It is used to describe Figure 9 The signal timing diagram for the operation of pixels.

[0179] because Figure 9 The pixel PX[i,j] shown is configured as a p-type transistor, when Figure 10When signals EM[i], GW[ik], GW[i], and GW2[i] are high, signals EM[i], GW[ik], GW[i], and GW2[i] can have gate cutoff voltages, and when Figure 10 When signals EM[i], GW[ik], GW[i], and GW2[i] are at a low level, signals EM[i], GW[ik], GW[i], and GW2[i] may have gate turn-on voltages. However, this disclosure is not limited thereto. In alternative embodiments in which pixel PX[i,j] comprises an n-type transistor, this may be reversed.

[0180] Figure 10 The timing diagram shows some waveforms of the signal within a frame period. Additionally, Figure 10 It is shown that a first scan signal GW[i] is supplied to a first scan line SL1[i], a second scan signal GW2[i] is supplied to a second scan line SL2[i], a transmit control signal EM[i] is supplied to a transmit control line EL[i], and a previous first scan signal GW[ik] is supplied to a previous first scan line SL1[ik].

[0181] Pixel PX[i,j] can emit light during the period when the transmit control signal EM[i] is at the gate on level (e.g., the fifth period Q5), and pixel PX[i,j] can not emit light during the period when the transmit control signal EM[i] is at the gate off level (e.g., the first period Q1, the second period Q2, the third period Q3, and the fourth period Q4, etc.).

[0182] The second scan signal GW2[i] may include a time period in which the second scan signal GW2[i] is at the gate-on level during the period when pixel PX[i,j] is not emitting light. During the time period when the second scan signal GW2[i] is at the gate-on level, the first electrode of the light-emitting element LD and / or the gate electrode of the first transistor T1 can be initialized, or the threshold voltage of the first transistor T1 can be compensated.

[0183] In such an embodiment, during the period when the second scan signal GW2[i] is at the gate on level, the period when the first scan signal GW[i] has the gate on level and the period when the previous scan signal GW[ik] has the gate on level may not overlap with each other.

[0184] In an embodiment, such as Figure 10As shown, at the first time point t1, when the second scan signal GW2[i] changes from a gate cutoff level to a gate on level, the third transistor M3 can be turned on. At the first time point t1, when the previous first scan signal GW[ik] changes from a gate cutoff level to a gate on level, the fourth transistor M4 can be turned on. Therefore, when the voltage of the initialization power supply Vint is supplied to the first node ND1 corresponding to the gate electrode of the first transistor M1 (or the driving transistor), the gate electrode of the first transistor M1 can be initialized. The time period between the first time point t1 and the second time point t2 can be a first time period Q1 for initializing the gate electrode of the first transistor M1. In one embodiment, for example, the first time period Q1 can be the same as a horizontal time period (1H).

[0185] At the second time point t2, when the first scan signal GW[i] changes from the gate cutoff level to the gate on level, the second transistor M2 and the seventh transistor M7 can be turned on. When the second transistor M2 is turned on, the cutoff bias deviation of the first transistor M1 can be removed. Additionally, when the seventh transistor M7 is turned on, the voltage of the initialization power supply Vint is supplied to the first electrode of the light-emitting element LD, and therefore, the first electrode (or anode electrode) of the light-emitting element LD can be initialized to the voltage of the initialization power supply Vint. The period between the second time point t2 and the third time point t3 can be a second period Q2 in which the first electrode of the light-emitting element LD is initialized and the cutoff bias deviation of the first transistor M1 is removed.

[0186] At the third time point t3, when the previous first scan signal GW[ik] transitions from gate cutoff level to gate on level, the fourth transistor M4 can be turned on. Therefore, when the voltage of the initialization power supply Vint is supplied to the first node ND1 corresponding to the gate electrode of the first transistor M1, the gate electrode of the first transistor M1 can be initialized. The period between the third time point t3 and the fourth time point t4 can be the first time period Q1 for initializing the gate electrode of the first transistor M1.

[0187] At the fourth time point t4, when the first scan signal GW[i] changes from the gate cutoff level to the gate on level, the second transistor M2 and the seventh transistor M7 can be turned on. Therefore, similar to the period between the second time point t2 and the third time point t3, the period between the fourth time point t4 and the fifth time point t5 can be the second period Q2 in which the first electrode of the light-emitting element LD is initialized and the cutoff bias deviation of the first transistor M1 is removed.

[0188] Similar to the time period between the first time point t1 and the second time point t2, the time period between the fifth time point t5 and the sixth time point t6 can be the first time period Q1 used to initialize the gate electrode of the first transistor M1.

[0189] At time point t6, when the first scan signal GW[i] changes from gate cutoff to gate on, the second transistor M2 and the seventh transistor M7 can be turned on. When the seventh transistor M7 is turned on, the data voltage Vdata can be transmitted to the first electrode of the first transistor M1. Furthermore, since the second scan signal GW2[i] remains at the gate on level, the first transistor M1 maintains a diode-like form while the third transistor M3 remains on. Therefore, the data voltage Vdata transmitted to the first electrode of the first transistor M1 can be used to compensate for the threshold voltage of the first transistor M1. Additionally, data can be written to pixel PX[i,j] via the data voltage Vdata transmitted through the data line DL[j]. The period between time point t6 and time point t7 can be the third period Q3, in which the threshold voltage of the first transistor M1 is compensated and data is written to pixel PX[i,j].

[0190] At the seventh time point t7, since the first scan signal GW[i] and the previous first scan signal GW[ik] are at the gate cutoff level, no data writing and initialization of the light-emitting element LD are performed. However, during the period between the sixth time point t6 and the seventh time point t7, the threshold voltage of the first transistor M1 can be further compensated using the charge supplied by the data voltage Vdata to the first electrode of the first transistor M1. That is, the period between the seventh time point t7 and the eighth time point t8 can be a fourth period Q4 for further compensating the threshold voltage of the first transistor M1. In one embodiment, for example, the fourth period Q4 can be longer than a horizontal period (1H) or the first period Q1.

[0191] At the ninth time point t9, when the transmit control signal EM[i] changes from the gate cutoff level to the gate on level, the fifth transistor M5 and the sixth transistor M6 can be turned on, and the drive current can be supplied to the light-emitting element LD through the first transistor M1. Therefore, the light-emitting element LD can emit light with a brightness corresponding to the drive current. The period after the ninth time point t9 can be the fifth period Q5 in which the light-emitting element LD emits light.

[0192] In the embodiment, as described above, data can be written during the third time period Q3 while compensating for the threshold voltage of the first transistor M1. Figure 9The pixel PX[i,j]. In such an embodiment, even if the first scan signal GW[i] and / or the previous first scan signal GW[ik] are at the gate cut-off level, the pixel PX[i,j] can further have a fourth time period Q4 for additional compensation of the threshold voltage of the first transistor M1 because the second scan signal GW2[i] further maintains the gate on level.

[0193] As the driving frequency of the display device DD increases, the fourth time period Q4 decreases, and therefore the time period used to compensate for the threshold voltage of the first transistor M1 decreases. Therefore, as referenced... Figure 8 As described, as the driving frequency increases, the brightness can increase and the swing range of the data voltage can increase.

[0194] In embodiments of this disclosure, the display device DD can be controlled to increase the fourth time period Q4 as the driving frequency increases. In one embodiment, for example, Figure 1 The timing controller 200 shown can increase the time period in which the transmit start signal EM_FLM is not supplied according to the drive frequency. When the time period in which the transmit start signal EM_FLM is not supplied is increased according to the drive frequency, the time period in which the transmit control signal EM[i] of the transmit driver 500 is not supplied ( Figure 10 The time period between the first time point t1 and the ninth time point t9 can be increased. Additionally, the second scan driver 400 can increase the time period supplied to the second scan signal GW2[i] according to the drive frequency. Figure 10 (The time period between the first time point t1 and the eighth time point t8).

[0195] In such an embodiment, the transmit start signal EM_FLM can be set differently depending on the drive frequency. In one embodiment, for example, the period during which the transmit start signal EM_FLM is not supplied can be set to increase with increasing drive frequency. In such an embodiment, the second scan signal GW2[i] can be set differently depending on the drive frequency. In one embodiment, for example, the period during which the second scan signal GW2[i] is supplied can be set to increase with increasing drive frequency.

[0196] This invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0197] While the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made in the invention without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels; The timing controller generates a transmit start signal; The transmit driver supplies transmit control signals to the plurality of pixels based on the transmit start signal received from the timing controller; A first scan driver supplies a first scan signal to the plurality of pixels; The second scan driver supplies the second scan signal to the plurality of pixels; as well as The data driver supplies data signals to the plurality of pixels. The timing controller adjusts the duration of the transmission start signal supply based on changes in the drive frequency, and Each of the plurality of pixels includes: First transistor; The light-emitting element includes a first electrode electrically connected to the second electrode of the first transistor and a second electrode connected to a second power supply; A second transistor is connected between the data line receiving the data signal and the third node, wherein the second transistor includes a gate electrode that receives the first scan signal; A third transistor is connected between the second electrode of the first transistor and the gate electrode of the first transistor, wherein the third transistor includes a gate electrode for receiving the second scan signal; A fourth transistor is connected between the first power supply and the third node, wherein the fourth transistor includes a gate electrode for receiving the transmit control signal; A fifth transistor is connected between the first power supply and the first electrode of the first transistor, wherein the fifth transistor includes a gate electrode for receiving the transmit control signal; A sixth transistor is connected between the second electrode of the first transistor and the first electrode of the light-emitting element, wherein the sixth transistor includes a gate electrode for receiving a previously emitted control signal; A first capacitor is connected between the second electrode of the first transistor and the third node; A second capacitor is connected between the first power supply and the gate electrode of the first transistor; and A seventh transistor is connected between the first electrode of the light-emitting element and the initialization power supply, wherein the seventh transistor includes a gate electrode for receiving the second scan signal.

2. The display device according to claim 1, wherein, The timing controller increases the time period for supplying the transmission start signal as the driving frequency increases.

3. The display device according to claim 2, wherein, The timing controller adjusts the period of the clock signal supplied to the transmit driver based on the change in the drive frequency.

4. The display device according to claim 2, wherein, When the driving frequency is a first driving frequency, the supply period of the transmission control signal output by the transmission driver is the same as the supply period of the transmission control signal output by the transmission driver when the driving frequency is a second driving frequency, wherein the second driving frequency is greater than the first driving frequency.

5. The display device according to claim 1, wherein, During the period when the second scan signal is at the gate on level, the period during which the previous transmit control signal is at the gate on level does not overlap with the period during which the transmit control signal is at the gate on level.

6. The display device according to claim 1, wherein, During the first time period, the voltage of the initialization power supply is supplied to the gate electrode of the first transistor and the first electrode of the light-emitting element. During the second time period, the voltage of the first power supply is supplied to the first electrode of the first transistor. During the third time period, the first transistor is connected to the diode based on the voltage of the first power supply, and During the fourth time period, the second transistor is turned on and the data signal is supplied to the third node.

7. The display device according to claim 6, wherein, The third transistor is turned on during the first time period, the third time period, and the fourth time period, and The third transistor is turned off during the second time period.

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