Memory device with row repair mechanism and operation method thereof

Abstract

The present invention describes a memory device having a row repair mechanism and an operating method thereof. A memory device includes a plurality of memory banks, each of which includes (1) a plurality of memory cells and (2) a plurality of redundant cells, the plurality of redundant cells being configured to replace one or more target memory cells in the plurality of memory cells. A set of shared fuses and latches can be used to store a row address for each repair that can be implemented in one of the plurality of memory banks. A shared matching circuit coupled to the shared latch set and the plurality of memory banks can be configured to at least partially implement a row repair of the row address of the memory bank associated with a command operation.

Description

Technical Field

[0001] The disclosed embodiments relate to devices, and in particular, to semiconductor memory devices having a row repair mechanism and methods of operating the same. Background Art

[0002] A memory device may include semiconductor circuits configured to store and access information utilizing electrical energy. Some examples of memory devices include volatile memory devices, nonvolatile memory devices, or a combination device.

[0003] Some memory devices, such as random access memory (RAM), such as dynamic RAM (DRAM), may include circuits configured to repair bit failures. Figure 1 1 is a partial block diagram of a memory device 100 that includes a set of repairable memory cells. The memory device 100 includes repair circuitry that is coupled to and / or integral with the memory cells 102 and is configured to repair / replace one or more defective cells 104 within the corresponding set of memory cells 102. The memory cells 102 include repair or redundant cells that are designated to replace the defective cells 104 as part of the repair circuitry. In other words, the repair cells are configured as spare memory cells that are not utilized in normal operation unless they are used to replace the actual / primary memory cells 102. Similar to the other memory cells 102, the repair cells are arranged in rows and columns (e.g., arranged in redundant rows 112 and redundant columns 114).

[0004] When replacing defective cells 104, the memory device 100 may perform row repair and / or column repair. For row repair, the memory device 100 may deploy and utilize redundant rows 112 to replace rows including defective cells 104. Figure 1 As illustrated in FIG. 1 , the memory device 100 may replace the row R0, which contains the defective cell 104, with the redundant row RR0. For column repair, the memory device 100 may deploy and utilize the redundant column 114 to replace the column including the defective cell 104. Figure 1 As illustrated in FIG. 1 , the memory device 100 may replace column C0 , which contains a defective cell 104 , with a redundant column RC1 .

[0005] The repair circuit includes a fuse block configured to facilitate memory cell replacement. Each of the blocks including a set of fuse latches is directly coupled (i.e., one-to-one dedicated and fixed electrical and functional connection) to a redundant row or redundant column. The memory device 100 includes fuses or non-volatile memory (not shown) located in a fuse array on the die. The information stored in the fuse array is broadcast upon initialization and loaded into the fuse block in each memory bank.

[0006] As in Figure 1 1, the fuse blocks include: row fuse blocks 122, each of which is directly coupled to one of the redundant rows 112; and column fuse blocks 124, each of which is directly coupled to one of the redundant columns 114. Each fuse block is configured to store the address of the row / column that includes the defective cell 104. For example, when a redundant column is used to replace a defective cell, the fuse block of the corresponding redundant column can be programmed (e.g., by blowing / setting a fuse latch and / or associated fuse) to store the address of the defective column. The defective column can be effectively removed from the operation of the memory device 100. Subsequently, the redundant column is used to store data in place of the replaced defective column and provide access to the data. Summary of the invention

[0007] In one aspect, the present invention relates to a memory device comprising: a memory array comprising a plurality of memory banks, each of the plurality of memory banks comprising (1) a plurality of memory cells and (2) a plurality of redundant cells, the plurality of redundant cells being configured to replace one or more target memory cells among the plurality of memory cells; a shared latch configured to latch a latched row address (RA) for row repair, wherein the latched RA identifies a target row comprising the target memory cell; a shared matching circuit coupled to the shared latch group and the plurality of memory banks, the shared matching circuit being configured to--receive an external RA and an external BA associated with an operation; and identify a repair row based on the external RA, the external BA and the latched RA, wherein the repair row corresponds to the target row within the memory bank for implementing row repair of the plurality of memory banks, and wherein the repair row comprises at least a portion of the plurality of redundant cells.

[0008] In another aspect, the present invention relates to a method for operating a memory device, wherein the memory device includes a plurality of memory cells and a plurality of redundant cells, wherein the plurality of redundant cells are configured to replace one or more target memory cells among the plurality of memory cells, the method comprising: obtaining a latched row address (RA) representing the location of the one or more target memory cells within a memory body; receiving an operation address for a memory operation, wherein the operation address includes (1) an external BA identifying a memory body associated with the memory operation and (2) an external RA identifying a row within the memory body associated with the memory operation; identifying a repair row based on comparing the external RA with the latched RA, wherein the repair row corresponds to a row for implementing a row repair of the plurality of memory bodies, and wherein the repair row includes at least a portion of the plurality of redundant cells; and using the identified repair row to replace the target row according to the external BA. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a portion of a memory device including a set of repairable memory cells.

[0010] Figure 2 is a block diagram of an example memory device in accordance with an embodiment of the present technology.

[0011] Figure 3A According to an embodiment of the present invention Figure 2 A block diagram of a portion of a memory device.

[0012] Figure 3B is a detailed block diagram of memory bank logic according to an embodiment of the present technology.

[0013] Figure 4A According to an embodiment of the present invention Figure 2 A block diagram of a portion of a memory device.

[0014] Figure 4B is a detailed block diagram of shared logic according to an embodiment of the present technology.

[0015] Figure 5 is a flow chart illustrating an example method of operating a device according to an embodiment of the present technology.

[0016] Figure 6 is a schematic diagram of a system including devices according to embodiments of the present technology. DETAILED DESCRIPTION

[0017] As described in more detail below, the technology disclosed herein relates to an apparatus for repairing a memory cell, such as a memory device, a memory system, a system having one or more memory devices, related methods, etc. The apparatus includes a shared logic circuit that controls a repair operation (e.g., a row repair) of a set of multiple memory banks. In some embodiments, each shared logic circuit may include a set of fuses / latches and a control circuit for controlling the repair of multiple memory banks. The fuse / latch set can be used to store a memory bank address and a latched row address for each repair. The shared logic circuit may include a memory bank selection circuit configured to apply / direct the repair to one of the memory banks indicated by the memory bank address.

[0018] Conventional devices have repair fuse latch sets that are hardwired (i.e., dedicated one-to-one electrical and functional connections) directly to corresponding redundant memory cells. Therefore, the repair capabilities of such conventional devices are limited by the worst performing repair area (e.g., a portion within the memory array). Because of the unpredictability of failures, a repair fuse latch set is included for each redundant element on the die (e.g., for each redundant column and each redundant row).

[0019] In contrast, for the embodiments described below, repairs may be assigned to different rows or columns within a group of memory cells (e.g., across banks). To assign repair cells, the device may include shared logic that can decode bank addresses (BA) and / or bank groups (BG). Although the shared logic is shared between multiple row elements, the matching circuit can still be reused to point to any of the remaining bank addresses when a redundant row is defective in one bank. In addition, since fuses / latches are shared between multiple banks, the device can reduce the overall circuit size. In addition, the device can reduce or eliminate situations where bad redundancy in one bank results in the loss of matching redundancy resources in all banks that replicate repairs (e.g., for row repairs). For example, the shared logic can connect repairs to individual banks, thereby preventing one defective redundant row from eliminating multiple (e.g., four) potential repairs.

[0020] Figure 2 2 is a block diagram of an example memory device 200 (e.g., a semiconductor die assembly, including a three-dimensional integration (3DI) device or a die stack package) according to an embodiment of the present technology. For example, the memory device 200 may include a DRAM or portion thereof including one or more dies / chips.

[0021] The memory device 200 may include an array of memory cells, such as the memory array 250. The memory array 250 may include a plurality of memory banks (e.g., memory banks 0 to 15), and each memory bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The memory cells may include any of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, or the like. The selection of the word lines WL may be performed by the row decoder 240, and the selection of the bit lines BL may be performed by the column decoder 245. A sense amplifier (SAMP) may be provided for the corresponding bit lines BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that may act as a switch. The memory array 250 may also include plate lines and corresponding circuitry for managing their operation.

[0022] The memory device 200 may employ a plurality of external terminals, including a command terminal and an address terminal coupled to a command bus and an address bus to receive a command signal (CMD) and an address signal (ADDR), respectively. The memory device 200 may further include a chip select terminal receiving a chip select signal (CS), a clock terminal receiving clock signals CK and CKF, a data clock terminal receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI and DMI, power supply terminals VDD, VSS and VDDQ.

[0023] The command terminal and the address terminal can be supplied with an address signal from the outside and a memory bank address signal ( Figure 2 200). The address signal supplied to the address terminal and the memory bank address signal may be transmitted to the address decoder 210 via the command / address input circuit 205. The address decoder 210 may receive the address signal and supply the decoded row address signal (XADD) to the row decoder 240, and supply the decoded column address signal (YADD) to the column decoder 245. The address decoder 210 may also receive the memory bank address signal and supply the memory bank address signal to both the row decoder 240 and the column decoder 245.

[0024] The command and address terminals may be supplied with a command signal (CMD), an address signal (ADDR), and a chip select signal (CS) from a memory controller and / or a malicious chipset. The command signal may represent various memory commands (e.g., including access commands, which may include read commands and write commands) from the memory controller. The chip select signal may be used to select the memory device 200 in response to the command and address provided to the command terminal and the address terminal. When a valid chip select signal is provided to the memory device 200, the command and address may be decoded and the memory operation may be performed. The command signal may be provided to the command decoder 215 as an internal command signal ICMD via the command / address input circuit 205. The command decoder 215 may include a circuit that decodes the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line). The command decoder 215 may further include one or more registers for tracking various counts or values ​​(e.g., a refresh command received by the memory device 200 or a count of a self-refresh operation performed by the memory device 200).

[0025] The read data may be read from a memory cell specified by a row address (e.g., an address provided with a valid command) and a column address (e.g., an address provided with a read) in the memory array 250. The read command may be received by the command decoder 215, which may provide an internal command to the input / output circuit 260, so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 255 and the input / output circuit 260 according to the RDQS clock signal. The read data may be provided at a time defined by the read delay information RL, which may be programmed in the memory device 100 (e.g., programmed in the mode register ( Figure 2 The read latency information RL may be defined according to clock cycles of the CK clock signal. For example, the read latency information RL may be the number of CK signal clock cycles when the associated read data is provided after a read command is received by the memory device 200.

[0026] The write data may be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 215, which may provide an internal command to the input / output circuit 260, so that the write data may be received by the data receiver in the input / output circuit 260 and supplied to the memory array 250 via the input / output circuit 260 and the read / write amplifier 255. The write data may be written into the memory cell indicated by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write delay WL information. The write delay WL information may be programmed in the memory device 200 (e.g., programmed in a mode register). The write delay WL information may be defined according to the clock cycle of the CK clock signal. For example, the write delay information WL may be the number of clock cycles of the CK signal when the associated access data is received after the write command is received by the memory device 200.

[0027] The power supply terminal may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generating circuit 270. The internal voltage generating circuit 270 may generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 240, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 250, and the internal potential VPERI may be used in many other circuit blocks.

[0028] The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output circuit 260 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 260 so that the power supply noise generated by the input / output circuit 260 does not propagate to other circuit blocks.

[0029] The clock terminal and the data clock terminal may be supplied with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 220. The CK signal and the CKF signal may be complementary, and the WCK signal and the WCKF signal may also be complementary. The complementary clock signals may have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0030] The input buffer included in the clock input circuit 220 may receive an external clock signal. For example, when enabled by the clock / enable signal from the command decoder 215, the input buffer may receive the clock / enable signal. The clock input circuit 220 may receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 230. The internal clock circuit 230 may generate an internal clock signal ICLK based on the received internal clock signal ICLK and the clock enable ( Figure 2 230) provides various phase and frequency controlled internal clock signals. For example, the internal clock circuit 230 may include a clock path ( Figure 2 The internal clock circuit 230 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 260 and may be used as a timing signal for determining the output timing of read data and / or the input timing of write data. The IO clock signal may be provided at a plurality of clock frequencies so that data may be output from and input to the memory device 200 at different data rates. When a higher memory speed is required, a higher clock frequency may be desired. When lower power consumption is required, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 235 and various internal clock signals may be generated accordingly.

[0031] The memory device 200 may be connected to any of a number of electronic devices or components thereof that are capable of utilizing memory for temporary or permanent storage of information. For example, the host device of the memory device 200 may be a computing device (e.g., a desktop or portable computer), a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or a component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.) or a recorder, a vehicle, an appliance, a toy, or any of a number of other products of digital images, audio, and / or video. In one embodiment, the host device may be directly connected to the memory device 200, but in other embodiments, the host device may be indirectly connected to the memory device (e.g., through a networking connection or through an intermediate device).

[0032] The memory device 200 may include a repair circuit 211, which may be coupled to one or more address decoders, such as the address decoder 210, the row decoder 240, and / or the column decoder 245. The repair circuit 211 may be configured to repair defects in memory cells. For example, the repair circuit 211 may replace defective memory cells with redundant memory cells in the memory array 250. As described in further detail below, the repair circuit 211 may include a shared local fuse latch configured to store location information (e.g., address and / or state / enable information) associated with defective memory cells within a group of two or more memory banks. The repair circuit 211 may further include a shared matching circuit that implements repair of the group of two or more memory banks, such as by detecting conditions associated with replacing defective memory cells with redundant memory cells. The shared matching circuit may include a memory bank selection circuit that directs one or more detection outputs according to a memory bank address. In other words, the repair circuit 211 may include one repair, fuse, and / or latch group for each group of two or more memory banks rather than one repair, fuse, and / or latch group for each memory bank. Thus, the number of repairs, fuses, and / or fuse latches may be reduced to account for actual failure rates, thereby reducing resources and / or device footprint associated with repairs, fuses, latches, etc.

[0033] Figure 3A According to an embodiment of the present invention Figure 2 The first repair circuit 300 may correspond to a control circuit Figure 2 Repair of the memory bank 310 within the memory array 250 Figure 2 For example, the first repair circuit 300 may include a bank logic 302, which is operably coupled to a row decoder 304 (eg, Figure 2The memory bank 310 includes a first memory group 306 and a second memory group 308. In some embodiments, the first memory group 306 and the second memory group 308 may each include 64 sectors, 64,000 rows, and / or 64 or 128 redundant / repair rows per bank.

[0034] The bank logic 302 may include a set of fuse latches 312 and a matching circuit 314 configured to control repair according to an external row address (RA) 322 (e.g., a row address associated with a read / write command), an external bank address (BA) 324, and / or a bank group (BG) identifier 326. The bank logic 302 may generate a redundant address 332 and / or a redundant match tag 334 based on the external RA 322, the external BA 324, and / or the BG identifier 326.

[0035] To illustrate the details of the memory bank logic 302, Figure 3B 3 is a detailed block diagram of bank logic according to an embodiment of the present technology. The bank logic 302 may include one row matching circuit and / or one repair fuse set for each row repair in each bank. For example, each row matching circuit (e.g., an XNOR device) may receive and compare the external RA 322 (ExtRA<16:0>) or a portion thereof (ExtRA<15:2>) with a latched row address 342 (Fz <16:0>) from the repair fuse set. n RA<15:2>) for a corresponding repair (n) (n=0, 1, . . . , 7) of eight available repairs. Based on the comparison, each row matching circuit may generate a row match tag 344, which indicates whether the external RA 322 matches the corresponding latched row address 342 (e.g., a representation of a defective row). The row match tags 344 may be combined into a combined match output 346 (Match<7:0>), which is provided to an encoder (e.g., an 8:3 encoder) and / or a detection circuit (e.g., an OR device). Thus, the encoder may generate a redundant address 332 (RedAddr<2:0>) and the detection circuit may generate a redundant match tag 334 (AnyRedMatch) based on the combined match output 346. The redundant address 332 may indicate an instance or location of a redundant row for replacing the latched row address 342, and the redundant match tag 334 may indicate whether any of the latched row addresses 342 matches the external RA 322 (ExtRA<16:0>). When the external RA 322 matches one of the latched row addresses 342 (as indicated by the redundant match flag 334 ), the row decoder 304 may access the redundant row instead of the row indicated by the external RA 322 .

[0036] Figure 4A According to an embodiment of the present invention Figure 2The second repair circuit 400 may correspond to a control circuit 400. Figure 2 A repair of a set of memory banks (including, for example, the first memory bank 406, the second memory bank 408, and / or other memory banks) within the memory array 250 Figure 2 For example, the second repair circuit 400 may include a first memory bank logic 402 and a second memory bank logic 403, each of which is operably coupled to Figure 2 In some embodiments, each of the first memory bank 406 and the second memory bank 408 may include a plurality of memory groups. For example, the first memory bank 406 and the second memory bank 408 may each include a memory group similar to Figure 3A The first memory group 306 and Figure 3A The memory groups of the second memory group 308 may be two memory groups. In some embodiments, each of the memory groups may include 64 sectors, 64,000 rows, and / or eight redundant / repair rows.

[0037] The first bank logic 402 and the second bank logic 403 may interface with the row decoder to implement repairs according to processing results from the shared logic 410. The shared logic 410 may include circuits configured to control repairs (e.g., row repairs) of a bank group (e.g., the first bank 406, the second bank 408, and / or other memory circuit groups). The shared logic 410 may receive an external row address (RA) 422 (e.g., a row address associated with a read / write command). The shared logic 410 may also receive a bank address (BA) identifier 424 and / or a bank group (BG) identifier 426 that identifies a memory bank corresponding to the external RA 422. In other words, the shared logic 410 may receive an external RA 422, an external BA 424, and / or a BG identifier 426 that identifies a group of memory cells designated by a command (e.g., an activate command).

[0038] The shared logic 410 may process the received information to determine whether the designated memory cell is determined to be defective and / or is undergoing repair. In other words, the shared logic 410 may determine whether the received information matches the location information stored in the fuse latch. The shared logic 410 may generate a result representing the result of the processing. For example, the shared logic 410 may generate one or more redundant addresses (e.g., the first redundant address 432 of the first memory bank 406 and / or the second redundant address 436 of the second memory bank 408) that identify redundant memory configured to replace the memory cell designated by the read / write operation (e.g., the defective cell). And, the shared logic 410 may generate one or more flags (e.g., the first valid repair flag 434 of the first memory bank 406 and / or the second valid repair flag 438 of the second memory bank 408) that indicate whether the location information of the activation command matches at least one latched location information. In other words, the valid repair flag may indicate whether the repair row should be accessed instead of the designated row of the corresponding memory bank.

[0039] To illustrate the details of an example of sharing logic 410, Figure 4B 4 is a detailed block diagram of shared logic according to an embodiment of the present technology. The shared logic 410 may include a latched row address 442 (Fz configured to store a latched row address 442 for repair. n RA<15:2>). For example, the shared latches 412 may include eight latch groups (n=0, 1, ..., 7) for eight possible repairs. Each latch group may store the address of the defective row for one repair. The shared latches 412 may also store a latched bank address 443 (Fz) indicating the bank associated with each repair. n BA <0> ). In other words, the latched bank address 443 may identify a bank from within a bank group that includes a defective memory cell designated for replacement / repair. In some embodiments, the shared logic may include 1,000 or more address latches.

[0040] The shared logic 410 may also include a shared matching circuit 414 configured to compare the latched RA 442 with the external RA 422 (ExtRA<16:0>) or a portion thereof (ExtRA<15:2>). The shared matching circuit 414 may include a row matching circuit 452 (e.g., an XNOR device or an XOR device) that compares the latched RA 442 and the latched BA 443 with the external RA 422 and the external BA 424, respectively. Figure 4B, the shared matching circuit 414 may include eight instances of a row matching circuit 452 (e.g., one instance for each repair), each of which determines whether the corresponding latched position information matches the bank / row information designated by the activation operation. Each row matching circuit 452 may generate a row matching flag 444, which indicates whether the activation operation designated the memory cell indicated by the corresponding fuse latch set and designated for the corresponding repair. Therefore, each row matching circuit 452 can be used to serve multiple banks rather than being hardwired to a specific element / bank. In some embodiments, the shared matching circuit 414 may include more than 100 (e.g., 100 to 300) row matching circuits 452. And, in some embodiments, the row matching circuit 452 may be implemented via non-CMOS XNOR logic that precharges the row matching flag 444 to a high level and pulls the flag low if the address does not match.

[0041] The row match tags 444 from each of the row match circuits 452 may be combined into a combined match output 446 (Match<7:0>) and provided to an encoder 454 and / or a repair detection circuit 456. The encoder 454 (e.g., an 8:3 encoder) may be configured to encode the combined match output 446 and generate an internal row address (RedAddr<2:0>) that indicates a set of redundant memory cells corresponding to a repair (e.g., a match to a defective memory cell). The repair detection circuit 456 (e.g., a NOR device) may be configured to generate an internal match tag (AnyRedMatch) that indicates that the external RA 422 and the external BA 424 match a set of memory cells indicating a repair. In other words, the internal match tag may indicate that a redundant row should be accessed instead of the memory cells indicated by the activate operation (e.g., defective memory cells).

[0042] The shared matching circuit 414 may include a bank selection circuit 458 (e.g., a multiplexer, a tri-state buffer set, and / or a high-Z buffer set) configured to generate an internal row address and / or an internal match tag according to the external BA 424. The bank selection circuit 458 may use the internal row address to generate a first redundant address 432 of the first bank 406 or a second redundant address 436 of the second bank 408 according to the external BA 424. The bank selection circuit 458 may also use the internal match tag to generate a first valid repair tag 434 of the first bank 406 or a second valid repair tag 438 of the second bank 408 according to the external BA 424. In other words, the bank selection circuit 458 may repeat one of the addresses and / or one of the match tags for one bank, thereby utilizing the shared latch to control / identify a specific one of the multiple banks rather than duplicating the repair across the entire grouped banks. Thus, a defective redundancy in one bank may be isolated from affecting the corresponding repair in other banks within the group.

[0043] In one or more embodiments, the memory device 200 may include a set of latches configured to temporarily store (e.g., latch) the generated addresses and / or tags before transmitting the signals to the corresponding locations (e.g., memory banks). For example, the memory device 200 may include a first address latch 462 for storing the first redundant address 432, a first tag latch 464 for storing the first valid repair tag 434, a second address latch 464 for storing the second redundant address 436, and / or a second tag latch 468 for storing the second valid repair tag 438. The latch set may be included in the memory bank logic (e.g., the first and / or second memory banks 402 and / or 403) and / or the shared logic 410 (e.g., after the shared matching circuit 414). The shared matching circuit 414 may be configured to generate the Red Addr and / or AnyRedMatch signals in response to each activation command. However, the memory bank may still need to access the previous results (e.g., the Red Addr and / or AnyRedMatch signals, for example, due to the shared configuration). Thus, the latch group can temporarily store the previous result for continuous access by the memory bank. The latch group can be cleared or reset when the corresponding memory bank is precharged.

[0044] In some embodiments, the memory device 200 may be configured to replicate repairs across multiple banks. The memory device 200 (e.g., the shared matching circuit 414, corresponding fuses / latches, etc.) may be configured to not have and / or ignore the latched bank address 443 (BA <0> ). In one or more embodiments, the latched bank address 443 may not be stored in the shared latch 412. The shared matching circuit 414 may process the latched bank address 443 as described above without comparing the latched bank address 443 with the active command. Therefore, the shared matching circuit 414 may process the latched bank address 443 according to the external BA 424 (BA <0> ) handles activation commands, such as for directing data to a calibration location.

[0045] Figure 5 is an illustration of an operating device (e.g., Figure 2 200) is a flowchart of an example method 500. For example, the method 500 may be used to operate Figure 4A The second repair circuit 400, Figure 4A The shared latch 412 and / or Figure 4A The method 500 can effectively or functionally couple (i.e., without or in lieu of direct one-to-one connection) fuses and / or fuse latches for use across a group of memory banks (e.g., Figure 4A The first memory bank 406 and Figure 4AFor example, the method 500 may be used to implement row repair of a grouped memory bank group using a shared latch 412 and a shared matching circuit 414.

[0046] At block 502, the memory device 200 may detect defective memory (eg, Figure 1 In some embodiments, the memory device 200 may implement a built-in self-test (BIST) that may be online and / or offline to test the memory cells (e.g., Figure 2 The memory device 200 may be configured to detect a row within the memory array 250 of the memory device 200. For example, the memory device 200 may perform a test sequence (e.g., via a memory controller, a finite state machine, and / or a processor) using a predetermined sequence of test elements including memory operations, data patterns, and / or addresses. The memory device 200 may also be connected to an external test sequence (e.g., an external tester). The tester may provide commands, conditions, and / or environments to the memory device 200. For testing, the memory device 200 may write a predetermined data pattern to a corresponding address and then read the same address to confirm the same data pattern. When the read pattern does not match the predetermined write data pattern, the memory device 200 may identify the memory cells (e.g., one or more rows) corresponding to the difference as defective.

[0047] At block 504, the memory device 200 may identify a defect location (e.g., a bank and / or row location of a defective memory cell). For example, the memory device 200 may determine a bank identifier and an internal address (e.g., a row address within a bank) that locates / identifies a row within the memory array 250 that includes one or more defective memory cells. The memory device 200 may identify the bank identifier and the internal row address according to a predetermined process based on the test results.

[0048] At block 506, the memory 200 may determine bank information (eg, corresponding to a bank) that identifies / locates a bank (eg, from within a bank group) having one or more defective memory cells. Figure 4A At block 508, the memory device 200 may determine a repair address (eg, an address of a row in a memory bank) for the defective memory cell. The repair address may correspond to Figure 4A of latched RA 442.

[0049] At block 510, the memory device 200 may store defective locations of repaired defective memory cells. The memory device 200 may store defective locations, for example, by setting fuses and / or writing to other non-volatile memory. When storing defective locations, the memory device 200 may store both repair addresses and bank information for each defective memory cell or each group thereof. For example, at block 512, the memory device 200 may store bank information in a first set of fuses associated with the repair. Likewise, at block 514, the memory device 200 may store the repair addresses in a second set of fuses that are paired with the first set of fuses and associated with the same repair.

[0050] The stored location information of the defective memory cell can be used to repair, for example, by accessing / utilizing a redundant memory cell to replace the defective memory cell. As an illustrative example, the memory device 200 can load the stored repair address and the stored bank information into a corresponding latch (e.g., shared latch 412) during initialization or power reset. When a memory operation (e.g., an activation operation) references or targets a row including a defective memory cell, the memory device 200 can use or access the redundant row associated with the defective memory cell.

[0051] At block 552, the memory device 200 may issue / receive an active command (ACT). Based on the active command, the memory device 200 may activate an idle bank, thereby sensing the row in the array of column sense amplifiers of the bank. In other words, the memory device 200 may issue an active command to turn on the row. The active command may be provided by an external source. The active command may include a row address associated with the command operation (e.g., external RA 422, external BA 424, and / or BG identifier 426).

[0052] At block 554, the memory device 200 may obtain the latched information (eg, latched RA 442 and / or latched BA 443). The memory device 200 may provide the latched information to subsequent circuits (eg, Figure 4B The shared matching circuit 414 or the row matching circuit 452) obtains the information.

[0053] At block 562, the memory device 200 may begin to implement an operation (e.g., activate an operation) in response to a command from the host. At block 564, the memory device 200 may compare an operation address (e.g., a target address) with the latched address information. For example, the memory device 200 may use the row matching circuit 452 to compare the external RA 422 and the external BA 424 for the operation with the latched RA and the latched BA loaded into the shared latch 412, respectively. As described above, the row matching circuit 452 may generate a comparison result. Figure 4BFor example, the row matching circuit 452 may activate the row matching flag when the corresponding latch RA 442 and the corresponding latch BA 443 match the external RA 422 and the external BA 424, respectively.

[0054] At block 566, the memory device 200 may generate a match result internally (e.g., within the shared matching circuit 414). For example, the shared matching circuit 414 may generate a match result based on the group of row match tags 444 generated by the grouping. Figure 4B The combined match output 446 may be provided to the encoder 454 and / or the repair detection circuit 456. Thus, the encoder 454 may internally generate a redundant address (e.g., an address or identifier of a repair row associated with a defective row identified by the operation). Likewise, the repair detection circuit 456 may internally generate a valid repair flag as an indication of whether the bank / row address of the operation matches at least one of the latched bank / row addresses.

[0055] At block 568, the memory device 200 may generate a matching result based on the bank information. For example, based on the internally generated redundant address, Figure 4B The bank selection circuit 458 may generate a matching result, which includes the first bank 406 Figure 4B The first redundant address 432 or the second memory bank 408 Figure 4B Similarly, based on the internally generated valid repair flag, the bank selection circuit 458 can generate a matching result, which includes the first bank 406. Figure 4B The first valid repair mark 434 or the second storage body 408 Figure 4B 438 of the second valid repair tag 438. In other words, the bank selection circuit 458 can transfer the matching result (e.g., the internally generated address / tag) to the memory bank designated by the operation (e.g., the memory bank indicated by the external BA 424). Therefore, when the operation address matches the address loaded in the latch shared by the memory bank group, the memory bank selection circuit 458 can implement the repair of the designated memory bank without duplicating the repair across the memory bank group. The process of activating the command can end after generating the matching result, and the memory device 200 can continue with the replacement repair.

[0056] Figure 6 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. Figures 2 to 5 Any of the foregoing apparatus (eg, memory devices) described may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is Figure 6680 is schematically shown in FIG. 680. The system 680 may include a memory device 600, a power supply 682, a driver 684, a processor 686, and / or other subsystems or components 688. The memory device 600 may include a memory device generally similar to the memory device described above with reference to FIG. Figures 2 to 5 The features of the apparatus described herein and thus may include various features for performing direct read requests from a host device. The resulting system 680 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 680 may include, without limitation, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 680 may be housed in a single unit or distributed among multiple, interconnected units (e.g., via a communication network). The components of the system 680 may also include any of a remote device and a variety of computer-readable media.

[0057] It will be appreciated from the above that although the specific embodiments of the present invention technology have been described herein for the purpose of illustration, various modifications may be made without departing from the present invention. In addition, the specific aspects of the new technology described in the context of the content of the specific embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with the embodiments have been described in the context of the content of the specific embodiment of the present technology, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages to fall within the scope of the present technology. Therefore, the present invention and related technologies may encompass other embodiments that are not explicitly shown or described herein.

[0058] In the embodiments described above, the apparatus has been described in the context of DRAM devices. However, apparatus configured in accordance with other embodiments of the present technology may include other types of suitable storage media in addition to or in place of DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0059] The term "processing" used herein includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting and / or manipulating data structures. The term data structure includes information arranged as bits, words or code words, blocks, files, input data, system-generated data (such as calculated or generated data) and program data. In addition, the term "dynamic" used herein describes the process, function, action or implementation scheme that occurs during the operation, use or deployment of the corresponding device, system or embodiment and after or while running the manufacturer or third-party firmware. The process, function, action or implementation scheme that occurs dynamically can occur after or subsequently to design, manufacture and initial testing, setting or configuration.

[0060] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, those skilled in the art will appreciate that the present technology may have additional embodiments and may be used without the above description. Figures 2 to 6 The present technology is practiced in the context of several details of the described embodiments.

Claims

1. A memory device, comprising: A memory array comprising a plurality of memory banks, each of the plurality of memory banks comprising (1) a plurality of memory cells and (2) a plurality of redundant cells configured to replace one or more target memory cells of the plurality of memory cells; a set of shared latches configured to latch a latched row address RA for row repair, wherein the latched RA identifies a target row including the target memory cell; a shared matching circuit coupled to the set of shared latches and the plurality of memory banks, the shared matching circuit being configured to-- receiving an external RA and an external bank address BA associated with the operation; and identifying a repair row based on the external RA, the external BA, and the latched RA, wherein the repair row corresponds to the target row in the memory bank corresponding to the external BA for performing row repair of the plurality of memory banks, and Wherein the repair row includes at least a portion of the plurality of redundant cells.

2. The memory device of claim 1, wherein the shared matching circuit is configured to identify the repair row specific to the bank corresponding to the external BA and not replicate the row repair across the plurality of memory banks.

3. The memory device of claim 1, wherein the shared matching circuit is configured to identify the repair row for replicating the row repair across the plurality of memory banks.

4. The memory device of claim 1 , wherein the shared matching circuit is configured to identify the repair row based on: comparing the external RA with the latched RA; and A matching result of the external RA and the latched RA is directed according to the external BA.

5. The memory device of claim 1, wherein: the set of shared latches being configured to latch, in addition to the latched RA, a latched BA of the row repair, the latched BA representing a target bank within the plurality of memory banks including the target memory cell; and The shared matching circuit is configured to: receiving an external BA associated with the operation; and The repair row is identified based on comparing the external RA and the external BA to the latched RA and the latched BA, respectively.

6. The memory device of claim 5, wherein: The set of shared latches includes a set of latches, wherein each set of latches is each configured to store the latched RA and the latched BA corresponding to one row repair; The shared matching circuit includes row matching circuits each coupled to a unique set of the latches, the row matching circuits each configured to-- comparing the latched BA with the external BA; comparing the latched RA with the external RA; and A row match flag is generated based on the comparison.

7. The memory device of claim 6, wherein each of the row matching circuits is an XNOR device configured to activate the row match flag when the corresponding latched BA and the corresponding latched RA match the external BA and the external RA, respectively.

8. The memory device of claim 6, wherein each of the row matching circuits is a non-CMOS device configured to precharge the row match flag to high before comparing the corresponding latched BA and the corresponding latched RA with the external BA and the external RA, respectively.

9. The memory device of claim 8, wherein the non-CMOS device is configured to pull the row match flag low when the corresponding latched BA and / or the corresponding latched RA are different from the external BA and the external RA, respectively.

10. The memory device of claim 6, wherein the shared matching circuit comprises: an encoder coupled to the row matching circuit, the encoder configured to generate a combined match output based on the row matching signature, wherein the combined match output identifies the repair row; and A bank selection circuit is coupled to the encoder, the bank selection circuit being configured to provide the combination match output to a memory bank associated with the operation according to the external BA.

11. The memory device of claim 10, wherein the encoder is configured to receive a first number of row binary match tags and generate the combined match output comprising a second number of bits, wherein the first number is greater than the second number.

12. The memory device of claim 10, wherein the bank select circuit comprises a set of High-Z buffers configured to transmit the combined match output according to the external BA, wherein each High-Z buffer is coupled to a corresponding bank of the plurality of memory banks.

13. The memory device of claim 10, wherein the bank selection circuit comprises a multiplexer coupled to the plurality of memory banks, the multiplexer configured to provide the combination match output to a bank indicated by the external BA.

14. The memory device of claim 6, wherein the shared matching circuit comprises: a repair detection circuit coupled to the row match circuit, the repair detection circuit configured to generate a valid repair flag based on the row match flag, wherein the valid repair flag indicates whether the operation is associated with a row repair represented in the set of latches; and A bank selection circuit is coupled to the repair detection circuit, the bank selection circuit being configured to provide the valid repair flag for a memory bank associated with the operation according to the external BA.

15. The memory device of claim 14, wherein the repair detection circuit is an OR device configured to activate the valid repair flag when one or more of the row match flags indicates that the corresponding latched BA and the corresponding latched RA match the external BA and the external RA, respectively.

16. The memory device of claim 6 , further comprising a set of latches coupled to the shared matching circuit and the plurality of memory storage bodies, the latch set being configured to store the row matching tags and / or one or more processing results thereof across activation commands for providing access to data stored by the plurality of memory storage bodies, wherein the latch set is configured to be reset based on precharging one or more of the plurality of memory storage bodies.

17. The memory device of claim 1, wherein: The memory array includes a first memory bank and a second memory bank; The external RA and the external BA indicate the first memory bank; The shared matching circuit is configured to identify the repair row in the first memory bank according to the external RA and the external BA.

18. The memory device of claim 17, further comprising: a first row decoder coupled to the first memory bank; a second row decoder coupled to the second memory bank; a first bank logic coupled to the first row decoder and the shared matching circuit, wherein the first bank logic configured to implement memory operations for the first bank through the first row decoder; and A second bank logic is coupled to the second row decoder and the shared matching circuit, wherein the second bank logic is configured to implement memory operations for the second bank through the second row decoder.

19. A method of operating a memory device, the memory device comprising a plurality of memory cells and a plurality of redundant cells, the plurality of redundant cells being configured to replace one or more target memory cells of the plurality of memory cells, the method comprising: obtaining a latched row address RA representing the location of the one or more target memory cells within a memory bank; receiving an operation address for a memory operation, wherein the operation address includes (1) an external bank address BA identifying a memory bank associated with the memory operation and (2) an external RA identifying a target row within the memory bank associated with the memory operation; Based on comparing the external RA with the latched RA to identify a repair row, wherein the repair row corresponds to a row for performing row repair of a plurality of memory banks, and wherein the repair row includes at least a portion of the plurality of redundant cells; and The target row including the target memory cell is replaced according to the external BA using the identified repair row.

20. The method of claim 19, wherein replacing the target row comprises replacing the target row of the memory bank associated with the memory operation and not replicating the row repair across a grouped set of memory banks.

21. The method of claim 19, wherein replacing the target row comprises transferring a redundant address identifying the repair row to a memory bank indicated by the external BA.

22. The method of claim 19, further comprising: obtaining a latched BA representing a memory bank within a memory array including the one or more target memory cells, wherein the latched BA indicates one memory bank from a grouped set of memory banks that share a set of repair latches; in: The latched RA represents the row within the memory bank represented by the latched BA; and Identifying the repair row includes comparing the external BA to the latched BA, wherein the repair row corresponds to a target row within the memory bank represented by the latched BA and the external BA.

23. The method of claim 19, wherein replacing the target row comprises transferring a valid repair flag to the memory bank according to the external BA, wherein the valid repair flag indicates that the external BA matches a latched BA and / or the external RA matches the latched RA stored in a shared set of repair latches.

24. The method of claim 19, further comprising: detecting one or more defective memory cells, wherein the one or more defective memory cells include the target memory cell; identifying the memory bank within the memory array that includes the one or more defective memory cells; storing, via the memory device, a bank identifier corresponding to the identified bank, wherein the bank identifier further corresponds to the latched BA of the instance of the row repair; identifying the target row including the one or more defective memory cells, wherein the target row is in the identified memory bank; and storing, via the memory device, an address corresponding to the target row, wherein the address further corresponds to the instance of the row repair Latch RA.

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