Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: a first active region and a second active region arranged in a stack according to a CFET type configuration relative to a first direction; a first contact structure and a second contact structure, electrically coupled to the first active region respectively; a third contact structure and a fourth contact structure, electrically coupled to the second active region respectively; a first metallization layer above the stack, including: an alpha logic conductor (alpha logic conductor) configured for logic signals; and a power grid (PG) conductor; the alpha logic and PG conductors do not overlap each other; a metallization layer below the stack, including beta logic conductors that do not overlap each other, and relative to a second direction, each of the alpha logic conductor, the PG conductor, and the beta logic conductor at least partially overlaps with one or more of the first contact structure, the second contact structure, the third contact structure, and the fourth contact structure. Embodiments of the present invention also relate to methods for manufacturing semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] An integrated circuit ("IC") includes one or more semiconductor devices. One way to represent a semiconductor device is as a plan view called a layout. The layout is generated in the context of design rules. A set of design rules imposes constraints on the placement of corresponding patterns in the layout, such as geographic / spatial constraints, connectivity constraints, etc. Typically, a set of design rules includes a subset of design rules related to spacing and other interactions between patterns in adjacent or abutting cells, where the patterns represent conductors in a metallization layer.

[0003] Typically, the set of design rules used to generate a layout diagram is specific to the process node by which a semiconductor device will be manufactured based on the layout diagram. The set of design rules compensates for the variability of the corresponding process node. This compensation increases the likelihood that the actual semiconductor device generated by the layout diagram will be an acceptable counterpart to the virtual device on which the layout diagram is based.

[0004] A basic complementary field effect transistor (CFET) includes a stack of first and second active regions, wherein the second active region is stacked over the first active region. Summary of the invention

[0005] According to one aspect of the present invention, a semiconductor device is provided, including a buried logic conductor CFET, the buried logic conductor CFET including: a first active area and a second active area arranged in a stack according to a CFET type configuration relative to a first direction; a first contact structure and a second contact structure, electrically coupled to the first active area respectively; a third contact structure and a fourth contact structure, electrically coupled to the second active area respectively; a first metallization layer (M_1st layer) located above the stack, including: an α logic conductor (α logic conductor) configured for logic signals; and a grid conductor; the α logic conductor and the grid conductor do not overlap with each other; and a metallization layer (M_B layer) located below the stack, including β logic conductors that do not overlap with each other; and wherein, relative to a second direction perpendicular to the first direction, each of the α logic conductor, the grid conductor and the β logic conductor at least partially overlaps with one or more of the first contact structure, the second contact structure, the third contact structure and the fourth contact structure.

[0006] According to another aspect of the present invention, a semiconductor device is provided, including a buried logic conductor CFET, the buried logic conductor CFET including: a first active area and a second active area arranged in a stack according to a CFET type configuration, wherein the second active area is located above the first active area; a gate structure close to the first active area and the second active area; a first contact structure and a second contact structure, electrically coupled to the first active area correspondingly; a third contact structure and a fourth contact structure, electrically coupled to the second active area correspondingly; a first metallization layer (M_1st layer) located above the stack, including: an α logic conductor (α logic conductor) configured for logic signals; and a power grid conductor; and a metallization (M_B) layer (M_B layer) located below the stack, including a β logic conductor; a first through-hole structure, electrically coupled between a first candidate and a first β logic conductor in the M_B layer, the first candidate being one of the gate structures or one of the first contact structure, the second contact structure, the third contact structure or the fourth contact structure.

[0007] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a buried logic conductor (BLC) CFET region, the method comprising: forming a first active region and a second active region arranged in a first stack, wherein the second active region is located above the first active region; forming a gate structure close to the first active region and the second active region; forming a first contact structure and a second contact structure arranged in a second stack, wherein the second contact structure is located above the first contact structure, and the first contact structure and the second contact structure are electrically coupled to the corresponding first active region and the second active region; forming a third contact structure and a fourth contact structure arranged in a third stack, wherein the fourth contact structure is located above the third contact structure, and the third contact structure is electrically coupled to the corresponding first active region and the second active region. The contact structure and the fourth contact structure are electrically coupled to the corresponding first active area and the second active area; an α logic conductor and a power grid conductor are formed in the first metallization layer, and the α logic conductor and the power grid conductor are correspondingly located above the gate structure and the second contact structure and the fourth contact structure, and do not overlap with each other; a β logic conductor is formed in the metallization buried layer, and the β logic conductor is correspondingly located below the gate structure and the first contact structure and the third contact structure, and does not overlap with each other, and represents the corresponding β logic conductor in the metallization buried layer; and a first through-hole structure is formed, and the first through-hole structure is placed between (A) the gate structure, the first contact structure, the second contact structure, the third contact structure or the fourth contact structure and (B) the first β logic conductor and electrically couples them. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] One or more embodiments are illustrated by way of example (and not limitation) in the accompanying drawings, wherein elements having the same reference numerals represent similar elements throughout the description. The accompanying drawings are not drawn to scale unless otherwise disclosed.

[0009] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

[0010] Figure 2A is a circuit diagram according to some embodiments.

[0011] Figure 2B is a three-dimensional view of a semiconductor device according to some embodiments.

[0012] Figure 2C-Figure 2D is a corresponding layout diagram representing a semiconductor device according to some embodiments.

[0013] Figure 2E-2G is a corresponding cross-sectional view of a semiconductor device according to some embodiments.

[0014] Figure 3A is a circuit diagram according to some embodiments.

[0015] 3B(a) and 3C(a) are corresponding layout diagrams representing semiconductor devices according to some embodiments.

[0016] 3B(b) and 3C(b) are layout variations corresponding to FIG. 3B(b) and FIG. 3C(b) according to some embodiments.

[0017] 3B(c) and 3C(c) are layout variations corresponding to FIG. 3B(a) and FIG. 3C(b) according to some embodiments.

[0018] 3B(d) and 3C(d) are layout variations corresponding to FIG. 3B(c) and 3C(c) according to some embodiments.

[0019] 3B(e) and 3C(e) are layout variations corresponding to FIG. 3B(c) and 3C(c) according to some embodiments.

[0020] 3B(f) and 3C(f) are layout variations corresponding to FIG. 3B(c) and 3C(c) according to some embodiments.

[0021] 3B(g) and 3C(g) are layout variations corresponding to FIG. 3B(c) and 3C(f) according to some embodiments.

[0022] 3B(h) and 3C(h) are layout variations corresponding to FIG. 3B(b) and FIG. 3C(g) according to some embodiments.

[0023] Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3His a cross-sectional view of a semiconductor device based on FIG. 3B(a) and FIG. 3C(a) according to some embodiments.

[0024] Figure 4A-4D is an offset cross-sectional view of a corresponding semiconductor device according to some embodiments.

[0025] Figure 5A is a logical block diagram according to some embodiments.

[0026] Figure 5B is a circuit diagram according to some embodiments.

[0027] Figure 5C-5D is a corresponding layout diagram representing a semiconductor device according to some embodiments.

[0028] Figure 5E is a logical block diagram according to some embodiments.

[0029] Figure 5F-5G is a corresponding layout diagram representing a semiconductor device according to some embodiments.

[0030] Fig. 6A is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0031] Figure 6B-6D is a corresponding flow chart of a method of generating a layout diagram according to some embodiments.

[0032] Fig. 6E is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0033] Figure 7 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0034] Figure 8 is a block diagram of a semiconductor device manufacturing system and an IC manufacturing flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0035] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. can be expected. For example, in the following description, forming a first component above or on a second component can include an embodiment in which the first component and the second component are in direct contact, and can also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention can repeat the figure numbers and / or letters in each example. This repetition is for simplicity and clarity, but it does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0036] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0037] In some embodiments, the CFET region has one or more logic conductors (e.g., for data signals or control signals) buried in a metallization layer (MB layer) located below the active area of ​​the CFET region and is referred to herein as a buried logic conductor (BLC) CFET region 102 (1). Compared to another approach for CFETs (which does not include a metallization layer under the active area stack of the CFET, but uses logic conductors in the M0 layer to conduct logic signals), the CFET region of some embodiments has one or more logic conductors buried in the M0 layer 220 (2) ( Figure 2E ) provides the advantage of increased routing resources. More specifically, since logic signals are conducted by corresponding logic conductors in the MB layer, routing resources in the M0 layer that are consumed for conducting logic according to another method are available in the CFET region of some embodiments.

[0038] Figure 1 is a block diagram of a semiconductor device 100 according to at least one embodiment of the present disclosure.

[0039] exist Figure 1In the present invention, semiconductor device 100 includes, inter alia, a circuit macro (hereinafter referred to as macro) 101. In some embodiments, macro 101 is an SRAM macro. In some embodiments, macro 101 is a macro other than an SRAM macro. Macro 101 includes, inter alia, a row region 104 extending in a first direction (e.g., substantially along a first direction). Figure 1 The X-axis in the first direction is extended and is sized to have a height (relative to a second direction substantially perpendicular to the first direction, e.g., substantially along the first direction) to accommodate the CFET region 102 (1). Figure 1 ), for which region, one or more logic conductors (e.g., for data signals or control signals) are buried beneath the active area of ​​the CFET, referred to herein as a buried logic conductor (BLC) CFET region 102(1). Optionally, in some embodiments, the row region 104 also includes a BLC CFET region 102(2), where the optional aspect is illustrated using dashed lines. Optionally, in some embodiments, the row region 104 also includes a BLC CFET region 102(3). Optionally, in some embodiments, in addition to the BLC CFET regions 102(1), 102(2), and 102(3), the row region 104 also includes a BLC CFET region (not shown). Example layout diagrams for obtaining the row region 104 include the layout diagrams disclosed herein.

[0040] Figure 2A is a circuit diagram of inverter 206A according to some embodiments.

[0041] exist Figure 2A In FIG. 2 , the inverter 206A includes a PMOS transistor P1 and an NMOS transistor N1, each of which is configured as a buried logic conductor (BLC) CFET. The inverter 206A has an input I and an output ZN.

[0042] Figure 2B is a three-dimensional view of a semiconductor device 206B including a BLC CFET, according to some embodiments.

[0043] exist Figure 2B , the semiconductor device 206B is connected with Figure 2A The inverter 206A corresponds to the inverter 206B. The inverter 206B includes a buried layer (MB layer) 224 (1) of metallization below the stack of the first active region 208 (1) and the second active region 210 (1), which is arranged according to a typical CFET type configuration.

[0044] exist Figure 2BIn some embodiments, the first active region 208(1) is configured for NMOS transistor technology and the second active region 210(1) is configured for PMOS transistor technology, such that the stack of active regions 208(1) and 210(1) is configured for CMOS technology. In some embodiments, the first active region 208(1) is configured for NMOS transistor technology and the second active region 210(1) is configured for PMOS transistor technology, such that the stack of active regions 208(1) and 210(1) is configured for CMOS technology. In some embodiments, the stack of active regions 208(1) and 210(1) is configured for a technology other than CMOS technology. The first active region (AR) 208(1) is referred to as the ARN region 208(1) to indicate that it is configured for NMOS transistor technology and the second active region (AR) 210(1) is referred to as the ARP region 210(1) to indicate that it is configured for PMOS transistor technology.

[0045] In some embodiments, the ARN region 208(1) and the ARP region 210(1) are configured for nanowire transistor technology. In some embodiments, the ARN region 208(1) and the ARP region 210(1) are configured for nanosheet transistor technology. In some embodiments, the ARN region 208(1) and the ARP region 210(1) are configured for finFET transistor technology. In some embodiments, the ARN region 208(1) and the ARP region 210(1) are configured for planar transistor technology.

[0046] The ARN region 208(1) and the ARP region 210(1) extend in a first direction that is substantially parallel to Figure 2B With respect to a second direction substantially perpendicular to the X-axis, Figure 2B In the second direction, which is substantially parallel to the Z axis, the ARP region 210 (2) is stacked above the ARN region 208 (1). With respect to the third direction, which is substantially perpendicular to the X axis and the Z axis, in Figure 2B , the third direction is substantially parallel to the Y-axis, and the ARP region 210(1) is aligned substantially above the ARN region 208(1) according to a typical CFET-type configuration. In some embodiments, the first direction, the second direction, and the third direction are corresponding directions except that they are substantially parallel to the corresponding X-axis, Z-axis, and Y-axis.

[0047] exist Figure 2BInverter 206B further includes: NMOS source-drain (MDN) contact structure 214(1) and MDN contact structure 214(2) electrically coupled to metal of ARN region 208(1), the latter being an NMOS configuration; gate structure 212(1) electrically coupled to ARN region 208(1) and ARP region 210(1); PMOS source-drain (MDP) contact structure 216(1) and MDP contact structure 216(2) electrically coupled to metal of ARP region 210(1), the latter being a PMOS configuration.

[0048] Inverter 206B also includes a first metallization layer 220(1) (M_1st layer) located above the MDP contact structure 216(1), the gate structure 212(1) and the MDP contact structure 216(2). Here, it is assumed that the numbering convention of the corresponding design rule of the corresponding semiconductor process technology node starts with the first metallization layer (M_1st layer) and the first interconnect layer (VIA_1st) layer above, respectively referred to as the M0 layer and the VIA0 layer. In some embodiments, the numbering convention starts with the M_1st layer and the V_1st layer, respectively referred to as the M1 layer and the VIA1 layer. The M0 layer 220(1) includes logic conductors 222(2) and 222(3) configured for logic signals (e.g., data signals and / or control signals); and power grid (PG) conductors 222(1) and 222(4).

[0049] exist Figure 2B In the embodiment of the present invention, in MB layer 224(1), the width W206B (along the X-axis) of the cell area representing inverter 206B is sufficient to accommodate two logic conductors, namely logic conductors 226(2) and 226(3), and a portion of two PG conductors, namely logic conductors 226(1) and 226(4). In some embodiments, the width W206B is W206B≈pch_M0pg (see below). In some embodiments, a positive number of logic conductors other than two is provided in M0 layer 220(1) within the width of inverter 206B.

[0050] In the M0 layer 220(1), the grid (PG) conductors 322(1) and 322(4) and the logic conductors 322(2) and 322(3) extend substantially parallel to the Y axis and do not overlap each other. In some embodiments, the PG conductors 322(1) and 322(4) provide voltages VDD and VSS, respectively. In some embodiments, the PG conductors 322(1) and 322(4) provide voltages other than the voltages VDD and VSS, respectively. The MB layer 224(1) includes logic conductors 226(1), 226(2), 226(3), and 226(4), which extend substantially parallel to the Y axis and do not overlap each other.

[0051] exist Figure 2B 2, the width of inverter 206B (along the X-axis) is sufficient to accommodate substantially four logic conductors, namely, logic conductors 226(1), 226(2), 226(3), and 226(4) in MB layer 224(1). In some embodiments, a minimum number of two logic conductors, such as logic conductors 226(1) and 226(4), are provided in MB layer 224(1) substantially within the width of inverter 206B, as indicated by logic conductors 226(2) and 226(3) being drawn with dashed lines. In some embodiments, a positive number of logic conductors other than two or four is provided in MB layer 224(1) within the width of inverter 206B.

[0052] Inverter 206B further includes: a via structure 218(1) electrically coupling MDN contact structure 214(2) and MDP contact structure 216(2), and referred to herein as VMDC structure 218(1); a via structure 236(1) electrically coupling MDN contact structure 214(1) and PG conductor 322(4) in M0 layer 220(1), and referred to herein as VMDNT structure 236(1); and a via structure 234(1) electrically coupling MDN contact structure 214(1) and PG conductor 322(4) in M0 layer 220(1). The gate structure 212(1) and the logic conductor 322(3) are coupled and are referred to herein as the VGT structure 234(1); the via structure 238(1) electrically couples the MDP contact structure 216(1) and the PG conductor 322(1) in the M0 layer 220(1) and are referred to herein as the VMDPT structure 238(1); and the VMDPT structure 238(2) electrically couples the MDP contact structure 216(2) and the logic conductor 322(2) in the M0 layer 220(1). The logic conductor 322(3) conducts the input signal I of the inverter 206B. The logic conductor 322(2) conducts the output signal ZN of the inverter 206B.

[0053] The M0 layer includes logic conductors and power grid (PG) conductors for data or control signals. The number of routing tracks trk_M0 of the logic conductor M0 layer 220 (1) is a positive integer equal to or greater than 2, 2≤trk_M0. The M0 layer 220 (1) has multiple pitches (is multi-pitch), including: the pitch of PG conductors 221 (1) and 222 (4), referred to as pitch pch_M0pg in this article; and the pitch of logic conductors 322 (1) and 222 (2), referred to as pitch pch_M0L in this article. In some embodiments, for the same type of elements with substantially parallel long symmetry axes, such as PG conductors 221 (1) and 222 (4) or logic conductors 322 (1) and 222 (2), the pitch refers to the distance between the long symmetry axes of adjacent elements. In some embodiments, pch_M0L<pch_M0pg. The MB layer 224 (1) has a single (unique) pitch, referred to as pitch pch_MB in this article. In some embodiments, pch_MB≤pch_M0pg. In some embodiments, pch_M0L≤pch_MB.

[0054] Figure 2C and Figure 2D are corresponding layout diagrams 206C and 206D representing a semiconductor device including a BLC CFET, according to some embodiments.

[0055] Figure 2E , Figure 2F and Figure 2G are corresponding cross-sectional views 206E, 206F, and 206G of a semiconductor device (including a semiconductor device of a BLC CFET) based on layout views 206C and 206D according to some embodiments.

[0056] Figure 2C-Figure 2D Layout diagrams 206C-206D and Figure 2E-2G The corresponding cross-sectional views 206E-206G follow the Figure 2B A similar numbering convention is used in . For example, Figure 2E-2F As in Figure 2B To help identify corresponding but still different components, Figure 2B-2G The numbering convention is to put parentheses after the component. For example, Figure 2C The active area pattern 208(2) in the layout diagram 206C corresponds to Figure 2E-2F The ARN region 208(2)′ in the inverter cross-sectional view 206E-206G of FIG. 1 , wherein the active area pattern 208(2) and the ARN region 208(2)′ correspond to Figure 2A ARN region 208(1) in the Figure 2C and Figure 2E-2G The elements 208(2) and 208(2)′ in Figure 2B The difference between element 208(1) in FIG. 208(2) and element 208(1) in FIG. 208(2) is reflected by the use of brackets (2), which use brackets (1). Note that the use of apostrophes in alphanumeric string 208(2)' indicates a difference relative to alphanumeric string 208(2), i.e., element 208(2)' represents a structure in a semiconductor device, whereas element 208(2) is a pattern in a layout diagram. For the sake of brevity, the discussion will focus more on the similarities than on the differences. Figure 2C-2G and Figure 2B on the difference between.

[0057] More specifically, corresponding Figure 2E-2G The cross-sectional view 206E-206G of the semiconductor and Figure 2C and Figure 2D The layout of Figures 206C-206D is shown as Figure 2A The inverter 206A corresponds to a semiconductor device of the inverter.

[0058] Included in Figure 2C-2G and Figure 2A The difference between Figure 2C-2G The inverter uses first and second buried logic conductors that conduct input signal I and output signal ZN respectively, and Figure 2B Inverter 206B uses logic conductors 322(3) and 322(2) in M0 layer 220(1) to conduct signals I and ZN, respectively.

[0059] Typically, a layout diagram is a two-dimensional top view that assumes substantially orthogonal first and second directions, for example, corresponding to the X-axis and the Y-axis. Thus, the pattern in the layout diagram represents the upper surface of the structure based on the layout diagram. Typically, the layout diagram includes one or more overlapping patterns. For example, consider the first and second patterns in a given layout diagram, which represent corresponding first and second structures in a semiconductor device based on the given layout diagram. If the second pattern overlaps the first pattern, this indicates that the second structure covers the first structure in the semiconductor device relative to the Z-axis.

[0060] As mentioned above, corresponding Figure 2C and Figure 2DThe inverter represented by layout diagrams 206C and 206D includes a BLC CFET. Layout diagrams 206C-206D assume that the X-axis and the Y-axis are corresponding substantially orthogonal first and second directions. Again, among other things, the BLC CFET includes a stack of first and second active regions arranged according to a typical CFET-type configuration, wherein the second active region is stacked above the first active region. Relative to the Z-axis, the pattern in layout diagram 206C represents a structure in the inverter that is adjacent to the position of the first active region in the inverter along the Z-axis. Relative to the Z-axis, the pattern in layout diagram 206D represents a structure in the inverter that is adjacent to the position of the second active region in the inverter along the Z-axis.

[0061] The inverter layout diagrams 206C-206D and the inverter cross-sectional diagrams 206E-206G will be discussed together according to the relationship between them. Figure 2C-Figure 2D The section designator II(E)-II(E)' in FIG. Figure 2E The corresponding relationship. Figure 2C-Figure 2D The section designator II(F)-II(F)' in FIG. Figure 2F The corresponding relationship. Figure 2C-Figure 2D The section designator II(G)-II(G)' in FIG. Figure 2G The corresponding relationship.

[0062] exist Figure 2C Inverter layout diagram 206C has cell boundary 207C. Inverter layout diagram 206C includes: LC patterns 226(5) and 226(6) which do not overlap each other with respect to the Y axis and correspond to Figure 2E-2G Logic conductors (LC) 226(5)' and 226(6)' in MB layer 224(4); VMDNB pattern 230(1) which is located above LC pattern 226(5) and corresponds to Figure 2G A through-hole structure 230(1) electrically coupling the logic conductor 226(5)' and the MDN contact structure portion 214(4)(1)', wherein the through-hole structure 230(1)' is referred to herein as a VMDNT structure 236(1); a VGB pattern 228(1) located above the LC pattern 226(6), the pattern corresponding to Figure 2F The via structure 228(1)' electrically couples the logic conductor 226(6)' and the gate structure 212(3)(1)'; the active area (AA) pattern 208(2) which is designated for an NMOS configuration and corresponds to Figure 2E-2G ARN region 208(2)′ of the ARN region 208(2)′, and hereinafter referred to as AAN pattern 208(2); MDN patterns 214(3)(1) and 214(3)(1), which cover AAN pattern 208(2), do not overlap each other with respect to the X-axis, and correspond to Figure 2E and Figure 2G The MDN contact structure portions 214(3)(1)' and 214(4)(1)' in FIG. 1 ; gate patterns 212(2)(1), 212(3)(1) and 212(4)(1) which are located above the AAN pattern 208(2) and do not overlap with each other with respect to the X-axis, wherein the gate pattern 212(3)(1) corresponds to Figure 2F The gate structure portion 212 (3) (1) '; VDMC pattern 218 (2), which is located above the MDN pattern 214 (4) (1) and corresponds to Figure 2G VDMC structure 218(2)' in; and VMDNT pattern 236(2) which is located above MDN pattern 214(3)(1) and corresponds to Figure 2E VMDNT structure 236(2)' in.

[0063] Figure 2C LC patterns 226(6) and 226(5) in are designated for corresponding signals I and ZN. Figure 2E-2G The logic conductors 226(6)' and 226(5)' in conduct corresponding signals I and ZN.

[0064] The long axes of the LC patterns 226(5)-226(6) and the AAN pattern 208(2) extend substantially parallel to the X-axis. The long axes of the gate patterns 212(2)(1), 212(3)(1), and 212(4)(1) and the MDN patterns 214(3)(1) and 214(4)(1) extend substantially parallel to the Y-axis.

[0065] exist Figure 2E-2F In the figure: MDN contact structure portion 214(3)(1)' is part of a larger MDN contact structure, which also includes contact structure portions 214(3)(2)', 214(3)(3)' and 214(3)(4)'; MDN contact structure portion 214(4)(1)' is part of a larger MDN contact structure, which also includes contact structure portions 214(4)(2)', 214(4)(3)' and 214(4)(4)'; and gate structure portion 212(3)(1)' is part of a larger gate structure, which also includes 212(3)(1)', 212(3)(2)', 212(3)(3)', '212(3)(4)', '212(3)(5)', '212(3)(6)' and 212(3)(7)'.

[0066] exist Figure 2D , the inverter layout 206D has a cell boundary 207D. The layout 206D includes an active area (AA) pattern 210(2) designated for a PMOS configuration and corresponding to Figure 2E-2GARP region 210(2)', and hereinafter referred to as AAP pattern 210(2); gate patterns 212(2)(2), 212(3)(2) and 212(4)(2), which are located above AAP pattern 210(2) and do not overlap with each other with respect to the X-axis, and wherein gate pattern 212(3)(2) corresponds to Figure 2F The gate structure portion 212(3)(1)′ in FIG. 21; the MDP patterns 216(3)(1) and 216(4)(1), which cover the AAP pattern 210(2), do not overlap each other with respect to the X-axis, and correspond to Figure 2E and Figure 2G MDP contact structure portions 216(3)(1)' and 216(4)(1)' in FIG. 2; VMDNT pattern 236(2); VMDPT pattern 238(3), which corresponds to Figure 2E VMDPT structure 238(3)' in PG patterns 222(6) and 222(9), which correspond to Figure 2E-2G PG conductors 222(6)' and 222(9)' in the M0 layer 220(2); and LC patterns 222(7) and 222(8), which correspond to Figure 2E-2G LC conductors 222(7)' and 222(8)' in the M0 layer 220(2).

[0067] The long axes of the AAP pattern 210(2), the PG patterns 222(6) and 222(9), and the LC patterns 222(7) and 222(7) extend substantially parallel to the X-axis. The long axes of the gate patterns 212(2)(2), 212(3)(2), and 212(4)(2), and the MDP patterns 216(3)(1) and 216(4)(1) extend substantially parallel to the Y-axis.

[0068] Compared to another approach of a CFET-based inverter that does not include a metallization layer under the active area stack of each CFET, but instead uses logic conductors in the M0 layer to conduct signals I and ZN, the inverter of layout diagrams 206C-206D and corresponding cross-sectional diagrams 206E-206G has the advantage of providing increased routing resources in the M0 layer 220(2). More specifically, since the corresponding LC conductors 226(6)' and 226(5)' in the MB layer 224(2) conduct signals I and ZN, routing resources in the M0 layer that are consumed to conduct signals I and ZN according to another approach are available in the inverter of layout diagrams 206C-206D and corresponding cross-sectional diagrams 206E-206G.

[0069] Figure 3A is a circuit diagram of a transmission system 339A including a transmission gate 340A according to some embodiments.

[0070] The transmission system 339A includes PMOS transistors P2-P4 and N2-N4. The transmission gate (TG) 340A includes PMOS transistors P2-P3 and N2-N3. Transistors P2 and N2 are coupled in parallel between nodes nde1 and nde2, where node nde1 represents the input of the transmission system 339A. Transistors P3 and N3 are coupled in parallel between nodes nde2 and nde3, where node nd3 represents the output of the transmission system 339A. The gate terminals of transistors P2 and N3 are coupled together, where the gate terminal of transistor P2 is marked as signal B1, and the gate terminal of transistor N2 is marked as signal B2, where B1=B2. The gate terminals of transistors P3 and N2 are coupled together, where the gate terminal of transistor P3 is marked as signal A1, and the gate terminal of transistor N2 is marked as signal A2, where A1=A2. Transistor P4 is coupled between node nde3 and VDD. Transistor N4 is coupled between node nde3 and VSS. The gate terminals of transistors P4 and N4 receive a control signal C.

[0071] 3B(a) and 3C(a) are corresponding layout diagrams 340B(a) and 340C(a) representing a semiconductor device including a BLC CFET, according to some embodiments.

[0072] Figures 3B(b), 3B(c), 3B(d), 3B(e), 3B(f), 3B(g) and 3B(h) are corresponding layout diagram variations 340(b), 340(c), 340(d), 340(e), 340(f), 340(g) and 340(h) of the layout diagram 340B(a) of Figure 3B(a) according to some embodiments.

[0073] Figures 3C(b), 3C(c), 3C(d), 3C(e), 3C(f), 3C(g) and 3C(h) are corresponding layout diagram variations 340C(b), 340C(c), 340C(d), 340C(e), 340C(f), 340C(g) and 340C(h) of the layout diagram 340C(a) of Figure 3C(a) according to some embodiments.

[0074] Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H are corresponding cross-sectional views 340D, 340E, 340F, 340G, and 340H of a semiconductor device (including a BLC CFET) based on the layouts of FIG. 3B(a) and FIG. 3C(a) according to some embodiments.

[0075] Layout diagrams of FIGS. 3B(a), 3B(b), 3B(c), 3B(d), 3B(e), 3B(f), 3B(g), and 3B(h), 3C(a), 3C(b), 3C(c), 3C(d), 3C(e), 3C(f), 3C(g), and 3C(h), and Figure 3D-Figure 3H The corresponding cross-sectional diagram follows the same Figure 2C-Figure 2D Layout diagrams 206C-206D and Figure 2E-2G 206E-206G. To help identify corresponding but still different components, the layout diagrams of Figures 3B(a), 3B(b), 3B(c), 3B(d), 3B(e), 3B(f), 3B(g), and 3B(h), 3C(a), 3C(b), 3C(c), 3C(d), 3C(e), 3C(f), 3C(g), and 3C(h) and 3B(a) and 3B(b) are similar to the numbering conventions used in the corresponding cross-sectional views 206E-206G of FIG. Figure 3D-Figure 3H The corresponding cross-sectional diagrams use 3-sequence numbers, and Figure 2C-Figure 2D Layout diagrams 206C-206D and Figure 2E-2G The corresponding cross-sectional views 206E-206G of FIG. 206A are numbered using 2-series numbers. For the sake of brevity, the discussion will focus more on the similarities than on the Figure 2C-2G and Figure 2B on the difference between.

[0076] More specifically, the corresponding Figure 3D-Figure 3H A semiconductor of a cross-sectional view and its corresponding layout diagrams 340B(a) and 340C(a) of Figure 3B(a) and Figure 3C(a) and its corresponding layout diagrams 340B(a) and 340C(a) of Figure 3B(b), Figure 3B(c), Figure 3B(d), Figure 3B(e), Figure 3B(f), Figure 3B(g) and Figure 3B(h), Figure 3C(b), Figure 3C(c), Figure 3C(d), Figure 3C(e), Figure 3C(f), Figure 3C(g) and Figure 3C(h) are represented as variations of the layout diagrams with Figure 3A The transmission gate 340A corresponds to a transmission gate semiconductor device.

[0077] According to the relationship between them, the transmission gate layout diagrams 340B(a) and 340C(a) corresponding to FIG. 3B(a) and FIG. 3C(a) and the corresponding Figure 3D-Figure 3H The transmission gate cross-sectional views 206E-206G, 340D-340H will be discussed together. As a result, the detailed discussion will be before the detailed discussion of FIGS. 3B(c), 3B(d), 3B(e), 3B(f), 3B(g), and 3B(h) and FIGS. 3C(b), 3C(c), 3C(d), 3C(e), 3C(f), 3C(g), and 3C(h) Figure 3D-Figure 3H .

[0078] The cross-sectional designator III(D)-III(D)' in FIG. 3B(a) and FIG. 3C(a) shows the cross-sectional designation III(D)-III(D)' in FIG. Figure 3E The cross-sectional indicators III(E)-III(E)' in FIG. 3B(a) and FIG. 3C(a) show the corresponding relationship with Figure 3E The cross-sectional indicators III(F)-III(F)' in FIG. 3B(a) and FIG. 3C(a) show the corresponding relationship with Figure 3F The cross-sectional indicators III(G)-III(G)' in FIG. 3B(a) and FIG. 3C(a) show the corresponding relationship with Figure 3G The cross-sectional indicators III(H)-III(H)' in FIG. 3B(a) and FIG. 3C(a) show the corresponding relationship with Figure 3H The corresponding relationship.

[0079] In FIG. 3B(a), a transmission gate layout diagram 340B(a) has a cell boundary 307B(a). The transmission gate layout diagram 340B(a) includes: LC patterns 326(7) and 326(8) which do not overlap each other with respect to the Y axis and correspond to Figure 3D-Figure 3H Logic conductors (LC) 326(7)' and 326(8)' in MB layer 334(4); VMDNB pattern 330(2) which is located above LC pattern 326(7) and corresponds to Figure 3D A through-hole structure 330(2) electrically coupling the logic conductor 326(7)' and the MDN contact structure portion 314(5)(1)'; a VMDNB pattern 330(3) located above the LC pattern 326(8) and corresponding to Figure 3H A through-hole structure 330(3) electrically coupling the logic conductor 326(8)' and the MDN contact structure portion 314(7)(1)'; a VMDPB pattern 332(1) located above the LC pattern 326(8) and corresponding to Figure 3G A through-hole structure 330(1) electrically coupling a logic conductor 326(8)' and an MDP contact structure 316(5)(1)', wherein the through-hole structure 332(1)' is referred to herein as a VMDPB structure 332(1)'; a VMDPB pattern 332(2) located above the LC pattern 326(7) and corresponding to Figure 3D The through-hole structure 330(2) electrically couples the logic conductor 326(7)' and the MDP contact structure 316(7)(1)'; the AAN pattern 308(3) corresponding to Figure 3D-Figure 3H ARN region 308(3)'; MDN patterns 314(5)(1), 314(6)(1) and 314(7)(1), which cover AAN pattern 308(3), do not overlap with each other with respect to the X-axis, and correspond to Figure 3D , Figure 3F and Figure 3H The MDN contact structure portions 314(5)(1)', 314(6)(1)' and 314(7)(1)' in the embodiment; the gate patterns 313(5)(1), 313(6)(1), 313(7)(1) and 313(8)(1) and 313(8)(1) are located above the AAN pattern 308(3) and do not overlap with each other with respect to the X-axis, wherein the gate patterns 313(6)(1) and 313(7)(1) correspond to Figure 3E and Figure 3G and VDMC pattern 318(3), which is located above MDN pattern 314(6)(1) and corresponds to Figure 3F VDMC structure 318(3)' in.

[0080] LC patterns 326 ( 8 ) and 326 ( 7 ) in FIG. 3B ( a ) are designated for input signal I and output signal ZN, respectively. Figure 3D-Figure 3H The logic conductors 326(8)' and 326(7)' in conduct corresponding signals I and ZN.

[0081] The long axes of the LC patterns 326(7)-326(8) and the AAN pattern 308(3) extend substantially parallel to the X-axis. The long axes of the gate patterns 312(5)(1), 312(6)(1), 312(7)(1), and 313(8)(1) and the MDN patterns 314(5)(1) and 314(6)(1) extend substantially parallel to the Y-axis.

[0082] exist Figure 3D-Figure 3H In the figure: MDN contact structure portion 314(5)(1)' is part of a larger MDN contact structure, which also includes contact structure portions 314(5)(2)', 314(5)(3)' and 314(5)(4)'; MDN contact structure portion 314(6)(1)' is part of a larger MDN contact structure, which also includes contact structure portions 314(6)(2)', 314(6)(3)' and 314(6)(4)'.

[0083] The MDN contact structure portion 314(7)(1)' is part of a larger MDN contact structure, which also includes contact structure portions 314(7)(2)', 314(7)(3)', and 314(7)(4)'; the gate structure portion 312(5)(1)' is part of a larger gate structure, which also includes 312(5)(1)', 312(5)(2)', 312(5)(3)', 312(5)(4)', 312(5)(5)', 312(5)(6)', and 312(5)(7)'; the gate structure portion 312(6)(1)' is part of a larger gate structure, which also includes 312(6)(1)', 312(6)(2)', 312(6)(3)', 312(6)(4 )', '312(6)(5)', '312(6)(6)' and 312(6)(7)'; gate structure portion 312(7)(1)' is part of a larger gate structure, which also includes 312(7)(1)', 312(7)(2)', 312(7)(3)', '312(7)(4)', '312(7)(5)', '312(7)(6)' and 312(7)(7)'; and gate structure portion 312(8)(1)' is part of a larger gate structure, which also includes 312(8)(1)', 312(8)(2)', 312(8)(3)', '312(8)(4)', '312(8)(5)', '312(8)(6)' and 312(8)(7)'.

[0084] In FIG. 3C(a), a pass gate layout diagram 340C(a) has a cell boundary 307C(a). The pass gate layout diagram 340C(a) includes: VMDPB patterns 332(1) and 332(2); AAP pattern 310(3), which corresponds to Figure 3D-Figure 3H ARP region 310(3)'; gate patterns 312(5)(2), 312(6)(2), 312(7)(2) and 312(8)(2), which are located above AAP pattern 310(3) and do not overlap with each other with respect to the X-axis, and wherein gate patterns 312(6)(2) and 312(7)(2) correspond to Figure 3E and Figure 3G Gate structure portions 312(6)(2)' and 312(7)(2)';

[0085] MDP patterns 316(5)(1), 316(6)(1), and 316(7)(1), which cover AAP pattern 310(3), do not overlap with each other with respect to the X-axis, and correspond to Figure 3D , Figure 3F and Figure 3HMDP contact structure portions 316(6)(1)', 316(7)(1)' and 316(8)(1)' in FIG. 3; VMDPT pattern 328(3), which corresponds to Figure 3E The VMDPT structure 328(3)' in FIG. 3 ; the VGT pattern 334(2) is located above the gate pattern 312(6)(2), corresponding to Figure 3E The via structure 312(6)(2)' electrically couples the gate structure 312(6)(2)' and the logic conductor 322(11)'; the VGT pattern 334(3) is located above the gate pattern 312(7)(2), corresponding to Figure 3G The via structure 312(7)(2)' electrically couples the gate structure 312(7)(2)' and the logic conductor 322(12)'; the PG patterns 322(10) and 322(13), which correspond to Figure 3D-Figure 3H PG conductors 322(10)' and 322(13)' in the M0 layer 320(3); and LC patterns 322(11) and 322(12), which correspond to Figure 3D-Figure 3H LC conductors 322(11)' and 322(12)' in the M0 layer 320(3).

[0086] The long axes of the AAP pattern 310(3), the PG patterns 322(10) and 322(13), and the LC patterns 322(11) and 322(12) extend substantially parallel to the X-axis. The long axes of the gate patterns 312(5)(2), 312(6)(2), 312(7)(2), and 312(8)(2), and the MDN patterns 316(5)(1), 316(6)(1), and 316(7)(1) extend substantially parallel to the Y-axis.

[0087] Compared to another approach of CFET-based transmission gates that do not include a metallization layer under the active area stack of each CFET, but instead use logic conductors in the M0 layer to conduct signals I and ZN, the transmission gates of layout diagrams 340B(a) and 340C(a) and corresponding cross-sectional diagrams 340D-340H have the advantage of providing increased routing resources in the M0 layer 320(3). More specifically, since the corresponding LC conductors 326(8)' and 326(7)' in the MB layer 334(3) conduct signals I and ZN, routing resources in the M0 layer that are consumed to conduct signals I and ZN according to another approach are available in the transmission gates of layout diagrams 340B(a) and 340C(a) and corresponding cross-sectional diagrams 340D-340H.

[0088] Likewise, FIG. 3B(b) and FIG. 3C(b) are layout variations of the corresponding FIG. 3B(a) and FIG. 3C(b) according to some embodiments.

[0089] In FIG3B(b), layout diagram 340(B)(b) rearranges portions 342B(a)(i) and 342B(a)(ii) of FIG3B(a) relative to the X-axis. In FIG3C(b), layout diagram 340(C)(b) rearranges portions 342C(a)(i) and 342C(a)(ii) of FIG3C(a) relative to the X-axis.

[0090] Likewise, FIGS. 3B(c) and 3C(c) are layout variations of the corresponding FIGS. 3B(b) and 3C(b) according to some embodiments.

[0091] In FIG3B(c), portions 342B(a)(i) and 342B(a)(ii) are spaced apart from each other along the X-axis, thereby enlarging layout 340B(c) compared to layout 340B(b) of FIG3B(b). In FIG3C(c), portions 342C(a)(i) and 342C(a)(ii) are spaced apart from each other along the X-axis, thereby enlarging layout 340C(c) compared to layout 340C(b) of FIG3C(b).

[0092] Likewise, FIG. 3B(d) and FIG. 3C(d) are layout variations of the corresponding FIG. 3B(c) and FIG. 3C(c) according to some embodiments.

[0093] Compared with the corresponding Figures 3B(c) and 3C(c), in Figures 3B(d) and 3C(d), the VMDPB pattern of Figures 3B(c) and 3C(c) is eliminated, and the MDN pattern is shortened accordingly relative to the Y-axis; and the VGT pattern is placed in a mirror-symmetrical manner about the long axis of the APN pattern.

[0094] Likewise, FIG. 3B(e) and FIG. 3C(e) are layout variations of the corresponding FIG. 3B(c) and FIG. 3C(c) according to some embodiments.

[0095] Compared with the corresponding Figures 3B(c) and 3C(c), in Figures 3B(e) and 3C(e), the VMDNB pattern in portion 342B(a)(ii) of Figure 3B(c) is placed mirror-symmetrically about the long axis of the AAN pattern, and the corresponding MDN pattern is adjusted accordingly, thereby obtaining portion 342B(a)(ii)' which is a variation of portion 342B(a)(ii); and the VMDPB pattern in portion 342C(a)(ii) of Figure 3C(c) is placed mirror-symmetrically about the long axis of the ANP pattern, and the corresponding MDP pattern is adjusted accordingly, thereby obtaining portion 342C(a)(ii)' which is a variation of portion 342C(a)(ii).

[0096] Likewise, FIG. 3B(f) and FIG. 3C(f) are layout variations of the corresponding FIG. 3B(c) and FIG. 3C(c) according to some embodiments.

[0097] Compared with the corresponding Figures 3B(a) and 3C(a), in Figures 3B(f) and 3C(g), parts 342B(a)(ii) and 342(C)(a)(ii) are extended along the X-axis to obtain corresponding modified parts 342B(a)(ii)" and 342(C)(a)(ii)"; and the VMDPT pattern is added to part 342C(a)(ii)".

[0098] Likewise, FIGS. 3B(g) and 3C(g) are layout variations of the corresponding FIGS. 3B(c) and 3C(f) according to some embodiments.

[0099] Compared to the corresponding FIG. 3B(a), in FIG. 3B(g), the portion 342B(b)(i) is extended along the X-axis, thereby obtaining a modified portion 342B(b)(i)'. In addition, FIG. 3B(g) has a portion 342B(e)(i) borrowed from FIG. 3B(e). Compared to FIG. 3C(f), in FIG. 3C(g), the portion 342C(f)(i) is extended along the X-axis, thereby obtaining a modified portion 342C(f)(i)'.

[0100] Likewise, FIG. 3B(h) and FIG. 3C(h) are corresponding cross-sectional views of a semiconductor device, in accordance with some embodiments.

[0101] Compared to FIG. 3B(c), in FIG. 3B(h), portion 342(B)(c)(i) is extended along the X-axis, one of the VMDNB patterns is removed, and the corresponding MDN pattern is correspondingly shortened along the Y-axis, thereby obtaining portion 342B(c)(i)'. In addition, compared to FIG. 3B(c), in FIG. 3B(h), portion 342(B)(c)(ii) of FIG. 3B(c) is extended along the X-axis, one of the VMDNB patterns is removed, and the corresponding MDN pattern is correspondingly shortened along the Y-axis, thereby obtaining portion 342B(c)(ii)'. Compared to FIG. 3C(g), in FIG. 3C(h), portion 342C(f)(i)' is extended along the X-axis, thereby obtaining modified portion 342C(f)(i)'.

[0102] According to some embodiments, Figure 4A , Figure 4B , Figure 4C and Figure 4D is an offset cross-sectional view of a corresponding semiconductor device as a BLC CFET.

[0103] In an offset cross-section view, the "cutting plane" that creates the cross section is bent (or folded) at a right angle to appear stepped or offset, which helps to illustrate features that would otherwise intersect the unfolded cutting plane. More specifically, the corresponding Figure 4A , Figure 4B , Figure 4C and Figure 4DThe offset portions of the BLC CFETs 402C, 402D, 402E, and 402F in FIG. 4 are indicative of the electrical coupling of the MDP and MDN rather than representing a structural arrangement.

[0104] exist Figure 4A , BLC CFET layout diagram 402A includes: logic conductors 426(9) and 426(10) and optional (as shown by dashed lines) logic conductors 426(11) and 426(12), which are located in MB layer 422(4) and do not overlap each other with respect to the Y axis; VMDPB structures 432(3) and 43(4), which are located above corresponding logic conductors 426(9) and 426(10); ARN region 410(4); ARN region 408(4); MDN contact Structure 414(8); MDP contact structure 416(8); gate structure 412(9); VMDPT structures 438(4) and 438(5); PG conductors 422(14) and 422(17) and logic conductors 422(15) and 422(16), which are located in the M0 layer 420(4) and do not overlap with each other, wherein the logic conductors 422(15) and 422(16) are located above the corresponding VMDPT structures 438(4) and 438(5).

[0105] and Figure 4A compared to, Figure 4B The differences include: VMDPB structures 432(3) and 432(4) are removed, and the MDP contact structure 416(9) is correspondingly narrowed along the Y axis; and VMDNB structures 430(4) and 430(5) are added, and the MDN contact structure 414(9) is correspondingly lengthened along the Y axis.

[0106] and Figure 4A compared to, Figure 4C The differences include: the VMDPB structure 432 (4) is removed, and the MDP contact structure 416 (10) is correspondingly narrowed along the Y axis; and the VMDNB structure 436 (3) is added, and the MDN contact structure 414 (10) is correspondingly lengthened along the Y axis.

[0107] and Figure 4B compared to, Figure 4D The differences include: the addition of VMDPT structure 438 (6), and the corresponding lengthening of MDP contact area 416 (11) along the Y axis.

[0108] Figure 5A is a logic block diagram 546A according to some embodiments.

[0109] Specifically, circuit 546A is an AND-OR-Inverting (AOI) gate, and more specifically an AOI22 gate (hereinafter referred to as AOI22 gate 546A). AOI22 546A includes: a first AND gate AND1, which receives inputs A1 and A2; a second AND gate AND2, which receives inputs B1 and B2; and a NOR gate NOR1, which receives the outputs of AND1 and AND2 and provides an output ZN, where ZN represents the output of AOI22. In the alphanumeric text string "AOI22", the numeric string "22" indicates that there are two sets of inputs in the first level or first stage, where the first level of AOI22 gate 546A includes two AND gates, namely, AND1 gate and AND2 gate, and each set includes two inputs. In some embodiments, AOI22 gate 546A has a drive strength of 1 times and is referred to as AOI22X1 or AOI22D1. In some embodiments, for a standard cell library according to a corresponding semiconductor process technology node, a current driving capability (driving strength) of 1 times represents a driving strength of a minimum-sized inverter in the standard cell library.

[0110] Figure 5B is a circuit diagram of the AOI22 circuit 546B according to some embodiments.

[0111] exist Figure 5B , AOI22 546B includes PMOS transistors P5, P6, P7 and P8 and NMOS transistors N7, N8, N9 and N10. Transistors P5 and P6 are coupled between VDD and node nde4. Transistors P7 and P8 are coupled between nodes nde4 and nde5. Node nde5 provides output ZN. Transistor N7 is coupled between node nde5 and node nde6. Transistor N8 is coupled between node nde5 and node nde7. Transistor N9 is coupled between node nde6 and VSS. Transistor N10 is coupled between node nde7 and VSS. Input signal A1 is provided at the gate terminals of transistors P5 and N7. Input signal A2 is provided at the gate terminals of transistors P6 and N9. Input signal B1 is provided at the gate terminals of transistors P7 and N8. Input signal B2 is provided at the gate terminals of transistors P8 and N10.

[0112] Figure 5C-5D are corresponding layout diagrams 546C and 546D representing AOI22 circuit 546B, according to some embodiments.

[0113] correspond Figure 5C and Figure 5DLayout diagrams 546C and 546D of AOI22 circuit 546B include BLC CFETs. Layout diagrams 546C-546D assume that the X-axis and the Y-axis are corresponding substantially orthogonal first and second directions. Again, among other things, the BLCCFET includes a stack of first and second active areas arranged according to a typical CFET-type configuration, wherein the second active area is stacked above the first active area. Relative to the Z-axis, the pattern in layout diagram 546C represents a structure in AOI22 circuit 546B that is adjacent to the position of the first active area in AOI22 circuit 546B along the Z-axis. Relative to the Z-axis, the pattern in layout diagram 546D represents a structure in AOI22 circuit 546B that is adjacent to the position of the second active area in AOI22 circuit 546B along the Z-axis.

[0114] Figure 5E is a block diagram of a scan D flip-flop (SDFQ) 548E according to some embodiments.

[0115] The basic D flip-flop receives a single data signal D. The SDFQ 548E is a D flip-flop (DFF) that can be controlled to select either the data signal DI or the scan / test signal SI.

[0116] exist Figure 5B , SDFQ 548E includes a multiplexer MUX coupled to a D flip-flop DFF. The multiplexer MUX has data inputs I1 and I2 receiving signals DI and SI, respectively, and a control input receiving a scan / test enable signal SE. The output of the multiplexer MUX is coupled to the input of the D flip-flop DFF. The D flip-flop DFF also receives a clock signal CK. The D flip-flop DFF outputs a signal Q when the data signal DI is selected, and outputs a signal SO when the test / scan signal SI is selected.

[0117] Figure 5C-5D 548F and 548G are corresponding layout diagrams representing SDFQ circuit 548E according to some embodiments.

[0118] correspond Figure 5C and Figure 5DLayout diagrams 548F and 548G of SDFQ circuit 548E include BLC CFETs. Layout diagrams 548F-548G assume that the X-axis and the Y-axis are corresponding substantially orthogonal first and second directions. Again, among other things, the BLCCFET includes a stack of first and second active regions arranged according to a typical CFET-type configuration, wherein the second active region is stacked above the first active region. Relative to the Z-axis, the pattern in layout diagram 548F represents a structure in SDFQ circuit 548E that is adjacent to the position of the first active region in SDFQ circuit 548E along the Z-axis. Relative to the Z-axis, the pattern in layout diagram 548G represents a structure in SDFQ circuit 548E that is adjacent to the position of the second active region in SDFQ circuit 548E along the Z-axis.

[0119] Fig. 6A is a flow chart of a method 600 of generating a layout map according to some embodiments.

[0120] According to some embodiments, method 600 may be performed using, for example, an EDA system 700 (discussed below). Figure 7 ) and integrated circuit (IC) manufacturing system 800 (discussed below) Figure 8 ) is implemented. Regarding method 600, examples of layout diagrams include layout diagrams disclosed herein, etc. Examples of semiconductor devices that can be manufactured according to method 600 include Figure 1 A semiconductor device 100 is provided.

[0121] exist Fig. 6A In the method 600, blocks 602-604 are included. At block 602, a layout diagram is generated, which includes, among other things, a pattern representing one or more BCL CFETs as disclosed herein. Examples of semiconductor devices corresponding to the layout diagram generated by block 602 include Figure 1 The semiconductor device 100 is shown below. FIG. 6B to FIG. 6D Block 602 is discussed in more detail. Flow proceeds from block 602 to block 604.

[0122] At block 604, based on the layout, at least one of: (A) one or more photolithography exposures; or (B) fabricating one or more semiconductor masks; or (C) fabricating one or more components in a layer of a semiconductor device is performed. Figure 8 Discussion.

[0123] Figure 6B is a flow chart of a method of generating a layout map according to some embodiments.

[0124] More specifically, according to one or more embodiments, Figure 6B The flowchart shows the Fig. 6A The additional box in box 602 of .

[0125] exist Figure 6B In the embodiment, block 602 includes blocks 620-632. At block 620, first and second active area (AA) patterns are generated in accordance with a CFET-type configuration relative to a first direction, and the second AA pattern is arranged above the first AA pattern in the first stack. An example of the first direction is a Z axis. Examples of the first and second AA patterns include Figure 2C and Figure 2D Flow proceeds from block 620 to block 622 .

[0126] At block 622, first and second gate patterns are generated and the first gate pattern is arranged above the first AA pattern and the second gate pattern is arranged above the second AA pattern in the second stack. Examples of the first and second gate patterns are corresponding to Figure 2C and Figure 2D The process proceeds from block 622 to block 624.

[0127] At block 624, first and second contact patterns are generated and the second contact pattern is arranged above the first contact pattern in the third stack. Examples of the first and second contact patterns are corresponding Figure 2C MDN Pattern 214(3)(1) and Figure 2D From block 624 , flow proceeds to block 626 .

[0128] At block 626, third and fourth contact patterns are generated and the fourth contact pattern is arranged above the third contact pattern in the fourth stack. Examples of the third and fourth contact patterns are corresponding Figure 2C MDN Pattern 214(4)(1) and Figure 2D From block 626 , flow proceeds to block 628 .

[0129] At block 628, an α pattern and a power grid (PG) pattern are generated that are respectively located above the second gate pattern and the second and fourth contact patterns and do not overlap each other. An example of the α pattern is Figure 2D LC patterns 222(7) and 222(8) in FIG. Figure 2E-2G The corresponding logic conductors 222(7)' and 222(8)' in the M0 layer 220(2) of FIG. An example of a PG pattern is Figure 2D The PG patterns 222(6) and 222(9) in FIG. 2 represent Figure 2E-2G Flow proceeds from block 628 to block 630.

[0130] At block 630, a β pattern is generated that is located below the first gate pattern and the first and third contact patterns, respectively, and does not overlap each other. An example of the β pattern is Figure 2C LC patterns 226(5) and 226(6) in FIG. Figure 2E-2G Flow proceeds from block 630 to block 632.

[0131] At block 632, a first via pattern is generated that is disposed between (A) the first gate pattern, the second contact pattern, or the fourth contact pattern and (B) the first β pattern. An example of the first via pattern is Figure 2C VGB 228(1) of , and correspondingly, an example of the first β pattern is Figure 2C Another example of the first through hole pattern is the VMDNB pattern 330(2) of FIG. 3B(a), and correspondingly, another example of the first β pattern is the LC pattern 326(7) of FIG. 3B(a).

[0132] Figure 6C is a flow chart of a method of generating a layout map according to some embodiments.

[0133] More specifically, according to one or more embodiments, Figure 6C The flowchart shows the Fig. 6A The additional box in box 602 of .

[0134] exist Figure 6C In FIG. 6 , block 602 includes blocks 632 and 640-646. Block 632 is discussed above, but in Figure 6C 634(C). At block 634(C), a first through hole pattern is placed between the first gate pattern and the first β pattern. An example of the first through hole pattern is Figure 2C VGB 228(1) of , and correspondingly, an example of the first β pattern is Figure 2C LC pattern 226 (6). Flow exits block 632 from block 634 (C). Flow proceeds from block 632 to block 640.

[0135] At block 640, a second via pattern is generated and placed between the third contact pattern and the second beta pattern. An example of a second via pattern is Figure 2C VMDNB 230(1) of , and correspondingly, an example of the second β pattern is Figure 2C LC pattern 226 (5) of FIG. 6A . Flow proceeds from block 640 to block 642 .

[0136] At block 642, a third via pattern is generated and placed between the third and fourth contact patterns. An example of the third via pattern is Figure 2C VMDC pattern 218(2), and correspondingly, examples of the first and fourth contact patterns are corresponding Figure 2D MDN Pattern 214(4)(1) and Figure 2D From block 642 , flow proceeds to block 644 .

[0137] At block 644, a fourth via pattern is generated and placed between the second contact pattern and the first PG pattern. An example of the fourth via pattern is Figure 2D VMDPT pattern 238(3), and correspondingly, the second contact pattern and the first PG pattern are examples of corresponding Figure 2D From block 644 , flow proceeds to block 646 .

[0138] At block 646, a fifth via pattern is generated and placed between the first contact pattern and the second PG pattern. An example of the fifth via pattern is VMDNT pattern 236(2), and correspondingly, examples of the first contact pattern and the second PG pattern are corresponding Figure 2D MDN pattern 214(3)(1) and PG pattern 222(9).

[0139] Fig.6D is a flow chart of a method of generating a layout map according to some embodiments.

[0140] More specifically, according to one or more embodiments, Fig.6D The flowchart shows the Fig. 6A The additional box in box 602 of .

[0141] exist Fig.6D In FIG. 6 , block 602 includes blocks 632 and 650-658. Block 632 is discussed above, but in Fig.6D 3B(a) as including block 634(D). At block 634(D), a first via pattern is placed between the first contact pattern and the first beta pattern. An example of the first via pattern is the VMDNB pattern 330(2) of FIG. 3B(a), and correspondingly, another example of the first beta pattern is the LC pattern 326(7) of FIG. 3B(a). The process exits block 632 from block 634(D). The process proceeds from block 632 to block 650.

[0142] At block 650, a second via pattern is generated and placed between the second contact pattern and the second β pattern. An example of the second contact pattern is the VMDPB pattern 332(1) of FIG. 3B(a), and correspondingly, an example of the second contact pattern and the second β pattern is the corresponding MDP pattern 316(5)(1) of FIG. 3B(a), and the second β pattern is the LC pattern 326(8) of FIG. 3B(a), which indicates Figure 3D-Figure 3H Logic conductor 326(8)' in MB layer 324(3). Flow proceeds from block 658 to block 652.

[0143] At block 652, a third via pattern is generated and placed between the third contact pattern and the fourth contact pattern. An example of the third via pattern is VMDC 318(3) of FIG. 3B(a). Flow proceeds from block 652 to block 654.

[0144] At block 654, fifth and sixth contact patterns are generated and the sixth contact pattern is arranged above the fifth contact pattern in the fifth stack. Examples of the fifth and sixth contact patterns are the corresponding MDN pattern 314(7)(1) in FIG. 3B(a) and the MDP pattern 316(7)(1) in FIG. 3C(a). Flow proceeds from block 654 to block 656.

[0145] At block 656, a fourth via pattern is generated and placed between the sixth contact pattern and the first β pattern. An example of the fourth via pattern is VMDPB 332(2) in FIG. 3B(a), and correspondingly, an example of the first β pattern is LC 326(7) in FIG. 3B(a), which indicates Figure 3D-Figure 3H Logic conductor 326(7)' in MB layer 324(3). Flow proceeds from block 656 to block 658.

[0146] At block 658, a fifth via pattern is generated and placed between the fifth contact pattern and the second β pattern. An example of the fifth contact pattern is VMDNB 330(3) of FIG. 3B(a), and correspondingly, an example of the second β pattern is LC pattern 326(8) of FIG. 3B(a), which indicates Figure 3D-Figure 3H Logic conductor 326(8)' in MB layer 324(3).

[0147] Fig. 6E is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0148] More specifically, according to one or more embodiments, Fig. 6E The flowchart shows the Fig. 6A The additional box in box 604 of .

[0149] exist Fig. 6EIn the embodiment, block 604 includes blocks 660-662. At block 660, first and second active regions are formed relative to a first direction, and the second active region is arranged above the first active region in the first stack according to a CFET type configuration. An example of the first direction is a Z axis. Examples of the first and second active regions include Figure 2B Flow proceeds from block 660 to block 662.

[0150] At block 662, a gate structure is formed proximate to the first active region and the second active region. An example of a gate structure is Figure 2B The process proceeds from block 662 to block 664.

[0151] At block 664, first and second contact structures are formed and the second contact structure is arranged in the second stack over the first contact structure. Examples of the first and second contact structures are Figure 2B Flow proceeds from block 664 to block 666 .

[0152] At block 666, third and fourth contact structures are formed and the fourth contact structure is disposed above the third contact structure in the third stack. Examples of the third and fourth contact structures are Figure 2B Flow proceeds from block 666 to block 668 .

[0153] At block 668, an alpha logic conductor and a power grid (PG) conductor are formed in the first metallization layer, which are respectively located above the gate structure and the second and fourth contact structures and do not overlap each other. An example of an alpha logic conductor is Figure 2B Logic conductors 222(2) and 222(3) in the M0 layer 220(1). Examples of PG conductors are Figure 2B Flow proceeds from block 668 to block 670.

[0154] At block 670, a beta logic conductor is formed that is located below the gate structure and the first and third contact structures, respectively, and does not overlap each other. An example of a beta logic conductor is Figure 2B Flow proceeds from block 670 to block 672.

[0155] At block 672, a first via structure is formed that is disposed between and electrically couples (A) the first gate structure, the first contact structure, the second contact structure, the third contact structure, or the fourth contact structure and (B) the first beta logic conductor. An example of the first via structure is Figure 2F VGB 228(1)', and correspondingly, the first example of a beta logic conductor is Figure 2F Another example of the first through-hole structure is Figure 3D VMDNB 330(2)', and correspondingly, an example of the first β logic conductor is Figure 3D Logic conductor 326(7)'.

[0156] In some embodiments, the first via structure is disposed between the gate structure and the first beta logic conductor and electrically couples the gate structure to the first beta logic conductor. An example of the first via structure is Figure 2F VGB 228(1)', and correspondingly, the first example of a beta logic conductor is Figure 2F Logic conductor 226(6)'.

[0157] In some embodiments, a second via structure is formed and disposed between and electrically couples the third contact structure and the second beta logic conductor. An example of the second via structure is Figure 2G VMDNB 230(1)', and correspondingly, an example of a second β logic conductor is Figure 2G Logic conductor 226(5)'.

[0158] In some embodiments, a third via structure is formed and disposed between and electrically coupled to the third and fourth contact structures. An example of the third via structure is Figure 2B VMDC 218(1), and correspondingly, examples of the first and fourth contact structures are corresponding Figure 2B The MDN contact structure 214(2) and Figure 2B MDP contact structure 216(2).

[0159] In some embodiments, a fourth via structure is generated and placed between the second contact structure and the first PG conductor to electrically couple them. An example of the fourth via pattern is Figure 2B The VMDPT structure 238(1) and correspondingly, the second contact structure and the first PG conductor are examples of Figure 2B The corresponding MDP patterns 216(1) and 222(1).

[0160] In some embodiments, a fifth via structure is generated and placed between the first contact structure and the second PG conductor and electrically couples them. An example of the fifth via structure is Figure 2BThe VMDNT structure 236(1) and correspondingly, the first contact structure and the second PG conductor are examples of Figure 2B The corresponding MDN pattern 214 (1) and PG conductor 222 (4).

[0161] In some embodiments, the first via structure is disposed between the first contact structure and the first beta logic conductor. An example of the first via structure is Figure 3D VMDNB structure 330(2)', and correspondingly, an example of the first β logic conductor is Figure 3D Logic conductor 326(7)'.

[0162] In some embodiments, a second via structure is formed and disposed between and electrically couples the second contact structure and the second beta logic conductor. An example of a second contact structure is Figure 3D The VMDPB structure 332(1)' and correspondingly, the second contact structure and the second β conductor are examples of Figure 3D The corresponding MDP structure 316(5)(1)'-(4)', and the second β logic conductor is Figure 3D-Figure 3H Logic conductor 326(8)' in MB layer 324(3).

[0163] In some embodiments, a third via structure is formed and disposed between the third contact structure and the fourth contact structure and electrically couples them. An example of the third via pattern is Figure 3D VMDC 318(3)'.

[0164] In some embodiments, fifth and sixth contact structures are formed, and the sixth contact structure is arranged above the fifth contact structure in the fourth stack. Examples of the fifth and sixth contact structures are corresponding Figure 3H The MDN structure in 314(7)(1)'-(4)' and Figure 3H The MDP structure in 316(7)(1)'-(4)'.

[0165] In some embodiments, a fourth via structure is generated and placed between the sixth contact pattern and the first β logic conductor and electrically couples them. An example of the fourth via structure is Figure 3H VMDPB 332(2)' in , and correspondingly, an example of the first β logic conductor is Figure 3D-Figure 3H Logic conductor 326(7)' in MB layer 324(3).

[0166] In some embodiments, a fifth via structure is created and placed between the fifth contact structure and the second beta logic conductor and electrically couples them. An example of the fifth contact structure is Figure 3H VMDNB structure 330(3)', and correspondingly, an example of the second β conductor is Figure 3D-Figure 3H Logic conductor 326(8)' in MB layer 324(3).

[0167] Figure 7 is a block diagram of an electronic design automation (EDA) EDA system 700 according to some embodiments.

[0168] In some embodiments, the EDA system 700 includes an APR system. According to some embodiments, the method of designing a layout diagram described herein represents a wire routing arrangement according to one or more embodiments, and may be implemented using the EDA system 700, for example.

[0169] In some embodiments, the EDA system 700 is a general-purpose computing device that includes a hardware processor 702 and a non-transitory computer-readable storage medium 704. Among other things, the storage medium 704 is encoded, i.e., stores, a computer program code 706, i.e., a set of computer-executable instructions. The instructions 706 executed by the hardware processor 702 represent (at least partially represent) an EDA tool that implements part or all of the methods described herein (hereinafter, the process and / or method) according to one or more embodiments.

[0170] The processor 702 is electrically coupled to the computer readable storage medium 704 via the bus 708. The processor 702 is also electrically coupled to the I / O interface 710 via the bus 708. The network interface 712 is also electrically coupled to the processor 702 via the bus 708. The network interface 712 is connected to the network 714 so that the processor 702 and the computer readable storage medium 704 can be connected to external elements via the network 714. The processor 702 is configured to execute the computer program code 706 encoded in the computer readable storage medium 704 so that the system 700 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0171] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, mobile computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0172] In one or more embodiments, the storage medium 704 stores computer program code 706 configured to enable the EDA system 700 (where such execution (at least in part) represents an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, the storage medium 704 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, the storage medium 704 stores a standard cell library 707, including such standard cells disclosed herein.

[0173] The EDA system 700 includes an I / O interface 710. The I / O interface 710 is coupled to external circuits. In one or more embodiments, the I / O interface 710 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor direction keys that convey information and commands to the processor 702.

[0174] The EDA system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 allows the EDA system 700 to communicate with a network 714 connecting one or more other computer systems. The network interface 712 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 700.

[0175] The EDA system 700 is configured to receive information through the I / O interface 710. The information received through the I / O interface 710 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 702. The information is transmitted to the processor 702 via the bus 708. The EDA system 700 is configured to receive information related to the UI through the I / O interface 710. The information is stored in the computer readable medium 704 as a user interface (UI) 742.

[0176] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 700. In some embodiments, a computer program product such as that available from CADENCE DESIGN SYSTEMS is used. or other suitable layout generation tools to generate a layout diagram including standard cells.

[0177] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / on-machine storage or storage units, for example, one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM, RAM, a memory card, etc.).

[0178] Figure 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and an IC manufacturing flow associated therewith, according to some embodiments.

[0179] In some embodiments, based on the layout diagram, for example, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 800 .

[0180] exist Figure 8 In the present invention, the IC manufacturing system 800 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 860, such as a design room 820, a mask room 830, and an IC manufacturer / fab ("fab") 850. The entities in the system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 820, the mask room 830, and the IC fab 850 are owned by a single larger company. In some embodiments, two or more of the design room 820, the mask room 830, and the IC fab 850 coexist in a common facility and use common resources.

[0181] The design office (or design team) 820 generates an IC design layout diagram 822. The IC design layout diagram 822 includes various geometric patterns designed for the IC device 860. The geometric patterns correspond to the patterns of metal, oxide or semiconductor layers, which constitute various components of the IC device 860 to be manufactured. Various layers are combined to form various IC functions. For example, a part of the IC design layout diagram 822 includes various IC components, such as active areas, gate electrodes, source and drain, metal lines or vias for interconnecting between layers, and openings for pads formed in semiconductor substrates (such as silicon wafers) and various material layers arranged on semiconductor substrates. The design office 820 implements appropriate design processes to form the IC design layout diagram 822. The design process includes one or more of logic design, physical design or placement and routing. The IC design layout diagram 822 is presented in one or more data files with geometric pattern information. For example, the IC design layout diagram 822 can be expressed in a GDSII file format or a DFII file format.

[0182] The mask chamber 830 includes data preparation 832 and mask manufacturing 844. The mask chamber 830 uses the IC design layout drawing 822 to manufacture one or more masks 845 to manufacture various layers of the IC device 860 according to the IC design layout drawing 822. The mask chamber 830 performs mask data preparation 832, wherein the IC design layout drawing 822 is translated into a representative data file ("RDF"). The mask data preparation 832 provides the RDF to the mask manufacturing 844. The mask manufacturing 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 845 or a semiconductor wafer 853. The mask layout data preparation 832 processes the design layout drawing 822 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 850. In Figure 8 , mask data preparation 832 and mask manufacturing 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 may be collectively referred to as mask data preparation.

[0183] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0184] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks an IC design layout 822 that has been processed in OPC using a set of mask creation rules that contain certain geometry and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for the constraints during mask fabrication 844, which may undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0185] In some embodiments, mask data preparation 832 includes a lithography process check (LPC), which simulates the process to be implemented by IC fab850 to manufacture IC device 860. LPC simulates the process based on IC design layout diagram 822 to create a simulated manufactured device, such as IC device 860. The processing parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the simulated manufactured device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 822.

[0186] It should be understood that the above description of mask data preparation 832 has been simplified for clarity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOPs) to modify IC design layout 822 according to manufacturing rules. Additionally, the processes applied to IC design layout 822 during data preparation 832 can be performed in a variety of different orders.

[0187] After mask data preparation 832 and during mask manufacturing 844, a mask 845 or a set of masks 845 is manufactured based on the modified IC design layout 822. In some embodiments, mask manufacturing 844 includes performing one or more photolithography exposures based on the IC design layout 822. In some embodiments, based on the modified IC design layout 822, an electron beam (e-beam) or a multi-electron beam mechanism is used to form a pattern on a mask (photomask or reticle) 845. Mask 845 can be formed with various techniques. In some embodiments, mask 845 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by an opaque area and passes through a transparent area. In one example, a binary mask version of mask 845 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in an opaque area of ​​the binary mask. In another example, a mask 845 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 845, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 844 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 853, such a mask is used in an etching process to form various etching regions in the semiconductor wafer 853, and / or in other suitable processes.

[0188] IC fab 850 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 850 is a semiconductor manufacturing plant. For example, there may be a manufacturing plant for front-end manufacturing (front-end (FEOL) manufacturing) of multiple IC products, while a second manufacturing plant may provide back-end manufacturing (back-end (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing plant may provide other services for the manufacturing business.

[0189] IC fab 850 includes a fabrication tool 852 configured to perform various fabrication operations on a semiconductor wafer 853 to fabricate an IC device 860 according to a mask (e.g., mask 845). In various embodiments, fabrication tool 852 includes one or more of a wafer stepper, an ion implanter, a photoresist coating machine, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0190] IC fab 850 uses mask 845 manufactured by mask chamber 830 to manufacture IC device 860. Therefore, IC fab 850 at least indirectly uses IC design layout 822 to manufacture IC device 860. In some embodiments, semiconductor wafer 853 is made into IC device 860 by IC fab 850 using mask 845. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 822 at least indirectly. Semiconductor wafer 853 includes a silicon substrate or other appropriate substrate having a material layer formed thereon. Semiconductor wafer 853 also includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0191] With respect to integrated circuit (IC) manufacturing systems (e.g., Figure 8 Details of the system 800 and the IC manufacturing process associated therewith are recorded, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, Pre-grant Publication No. 20150278429 published on October 1, 2015, U.S. Pre-grant Publication No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0192] In some embodiments, a method (for manufacturing a semiconductor device including a buried logic conductor (BLC) CFET region) includes: forming a first active region and a second active region arranged in a first stack, wherein the second active region is above the first active region; forming a gate structure adjacent to the first active region and the second active region; forming a first contact structure and a second contact structure arranged in a second stack, wherein the second contact structure is above the first contact structure, and the first contact structure and the second contact structure are electrically coupled to the corresponding first active region and the second active region; forming a third contact structure and a fourth contact structure arranged in a third stack, wherein the fourth contact structure is above the third contact structure, and the third contact structure and the fourth contact structure are electrically coupled to the corresponding first active region and the second active region. The structure is electrically coupled to the corresponding first active area and the second active area; forming an α logic conductor and a power grid (PG) conductor located in the first metallization layer, the α logic conductor and the power grid conductor are correspondingly located above the gate structure and the second contact structure and the fourth contact structure, and do not overlap with each other; forming a β logic conductor located in the metallization buried layer, the β logic conductor is correspondingly located below the gate structure and the first contact structure and the third contact structure, and does not overlap with each other, and represents the corresponding β logic conductor located in the metallization buried layer; and forming a first via structure, the first via structure is disposed between (A) the gate structure, the first contact structure, the second contact structure, the third contact structure or the fourth contact structure and (B) the first β logic conductor and electrically couples it. In some embodiments, the first via structure is disposed between the gate structure and the first β logic conductor; and the method further includes: forming a second via structure, the second via structure is disposed between the third contact structure and the second β logic conductor and electrically couples it. In some embodiments, the method also includes: forming a third through-hole structure, which is placed between the third contact structure and the fourth contact structure and electrically coupled; forming a fourth through-hole structure, which is placed between the second contact structure and the first PG structure and electrically coupled; and forming a fifth through-hole structure, which is placed between the first contact structure and the second PG structure and electrically coupled.In some embodiments, a first via structure is disposed between a first contact structure and a first β logic conductor, and the method further includes: forming a second via structure that is disposed between a second contact structure and a second β logic conductor and electrically couples them; forming a third via structure that is disposed between a third contact structure and a fourth contact structure and electrically couples them; forming a fifth contact structure and a sixth contact structure disposed in a fourth stack, wherein the sixth contact structure is above the fifth contact structure, and the fifth contact structure and the sixth contact structure are electrically coupled to corresponding first and second active regions; forming a fourth via structure that is disposed between the sixth contact structure and the first β logic conductor and electrically couples them, and represents a corresponding via structure of the electrically coupled adjacent structures; and forming a fifth via structure that is disposed between the fifth contact structure and the second β logic conductor and electrically couples them.

[0193] According to an embodiment of the present invention, a semiconductor device is provided, including a buried logic conductor CFET, the buried logic conductor CFET including: a first active region and a second active region disposed in a stack according to a CFET type configuration with respect to a first direction; a first contact structure and a second contact structure electrically coupled to the first active region correspondingly; a third contact structure and a fourth contact structure electrically coupled to the second active region correspondingly; a first metallization layer (M_1st layer) located above the stack, including: an α logic conductor (α logic conductor) configured for logic signals; and a power grid conductor; the α logic conductor and the power grid conductor do not overlap with each other; and a metallization layer (M_B layer) located below the stack, including non-overlapping β logic conductors; and wherein, with respect to a second direction perpendicular to the first direction, each of the α logic conductor, the power grid conductor, and the β logic conductor at least partially overlaps with one or more of the first contact structure, the second contact structure, the third contact structure, and the fourth contact structure.

[0194] In the above semiconductor device, the M_1st layer has a plurality of pitches, including: a pitch pch_M_1st_lgk of the α logic conductor; and a pitch pch_M_1st_pg of the power grid conductor; and pch_M_1st_lgk < pch_M_1st_pg.

[0195] In the above semiconductor device, the M_B layer has a unique pitch represented by a pitch (pch_M_B_lgk) of the β logic conductor.

[0196] In the above semiconductor device, pch_M_1st_lgk < pch_M_B_lgk; or pch_M_B_lgk ≤ pch_M_1st_pg.

[0197] In the semiconductor device described above, the M_B layer has a unique pitch represented by the pitch of the β logic conductor pch_M_B_lgk; and the first pitch pch_M_1st_lgk of the α logic conductor in the M_1st layer is less than pch_M_B_lgk, such that: pch_M_1st_lgk <pch_M_B_lgk。

[0198] In the above semiconductor device, pch_M_B_lgk is less than or equal to the second pitch pch_M_1st_pg of the power grid conductor in the M_1st layer, such that: pch_M_B_lgk≤pch_M_1st_pg.

[0199] In the above semiconductor device, it also includes: a circuit; and wherein the buried logic conductor CFET is included in the circuit.

[0200] In the above-mentioned semiconductor device, the circuit is an inverter, a transmission gate or a flip-flop.

[0201] According to an embodiment of the present invention, a semiconductor device is provided, including a buried logic conductor CFET, the buried logic conductor CFET including: a first active area and a second active area arranged in a stack according to a CFET type configuration, wherein the second active area is located above the first active area; a gate structure close to the first active area and the second active area; a first contact structure and a second contact structure, electrically coupled to the first active area correspondingly; a third contact structure and a fourth contact structure, electrically coupled to the second active area correspondingly; a first metallization layer (M_1st layer) located above the stack, including: an α logic conductor (α logic conductor) configured for logic signals; and a power grid conductor; and a metallization (M_B) layer (M_B layer) located below the stack, including a β logic conductor; a first through-hole structure, electrically coupled between a first candidate and a first β logic conductor in the M_B layer, the first candidate being one of the gate structures or one of the first contact structure, the second contact structure, the third contact structure or the fourth contact structure.

[0202] In the above semiconductor device, the first candidate is a second contact structure; and the semiconductor device further includes: a second via structure electrically coupled between the gate structure and a second β logic conductor in the M_B layer.

[0203] In the above semiconductor device, it further includes: a third through-hole structure electrically coupled between the third contact structure and the first grid conductor in the M_1st layer.

[0204] In the above semiconductor device, the first candidate is the second contact structure; and the semiconductor device further includes: a fourth via structure electrically coupled between the first contact structure and the second conductor in the M_1st layer.

[0205] In the above semiconductor device, the first candidate is the first contact structure; and the semiconductor device also includes: a fifth contact structure electrically coupled to the first active region; a sixth contact structure electrically coupled to the second active region; and a second via structure electrically coupled between the second contact structure and the second β conductor in the M_B layer.

[0206] In the above semiconductor device, it also includes: a third through-hole structure electrically coupled between the third contact structure and the first β conductor in the M_B layer; or a fourth through-hole structure electrically coupled between the fourth contact structure and the second β conductor in the M_B layer.

[0207] In the above semiconductor device, it also includes: a third via structure electrically coupled between the gate structure and the first α conductor in the M_1st layer; or a fourth via structure electrically coupled between the gate structure and the second α conductor in the M_1st layer.

[0208] The semiconductor device further includes: a third through-hole structure electrically coupled between the fifth contact structure and the sixth contact structure.

[0209] According to an embodiment of the present invention, a method for manufacturing a semiconductor device including a buried logic conductor (BLC) CFET region is provided, the method comprising: forming a first active region and a second active region arranged in a first stack, wherein the second active region is located above the first active region; forming a gate structure close to the first active region and the second active region; forming a first contact structure and a second contact structure arranged in a second stack, wherein the second contact structure is located above the first contact structure, and the first contact structure and the second contact structure are electrically coupled to the corresponding first active region and the second active region; forming a third contact structure and a fourth contact structure arranged in a third stack, wherein the fourth contact structure is located above the third contact structure, and the third contact structure is electrically coupled to the corresponding first active region and the second active region. The contact structure and the fourth contact structure are electrically coupled to the corresponding first active area and the second active area; an α logic conductor and a power grid conductor are formed in the first metallization layer, and the α logic conductor and the power grid conductor are correspondingly located above the gate structure and the second contact structure and the fourth contact structure, and do not overlap with each other; a β logic conductor is formed in the metallization buried layer, and the β logic conductor is correspondingly located below the gate structure and the first contact structure and the third contact structure, and does not overlap with each other, and represents the corresponding β logic conductor in the metallization buried layer; and a first through-hole structure is formed, and the first through-hole structure is placed between (A) the gate structure, the first contact structure, the second contact structure, the third contact structure or the fourth contact structure and (B) the first β logic conductor and electrically couples them.

[0210] In the above method, the first via structure is placed between the gate structure and the first β logic conductor; and the method also includes: forming a second via structure, the second via structure is placed between the third contact structure and the second β logic conductor and electrically couples them.

[0211] In the above method, it also includes: forming a third through-hole structure, the third through-hole structure is placed between the third contact structure and the fourth contact structure and electrically coupled; forming a fourth through-hole structure, the fourth through-hole structure is placed between the second contact structure and the first power grid conductor and electrically coupled; and forming a fifth through-hole structure, the fifth through-hole structure is placed between the first contact structure and the second power grid conductor and electrically coupled.

[0212] In the above method, the first through-hole structure is placed between the first contact structure and the first β logic conductor; and the method also includes: forming a second through-hole structure, the second through-hole structure is placed between the second contact structure and the second β logic conductor and electrically coupled; forming a third through-hole structure, the third through-hole structure is placed between the third contact structure and the fourth contact structure and electrically coupled; forming a fifth contact structure and a sixth contact structure arranged in a fourth stack, wherein the sixth contact structure is located above the fifth contact structure, and the fifth contact structure and the sixth contact structure are electrically coupled to the corresponding first active area and the second active area; forming a fourth through-hole structure, the fourth through-hole structure is placed between the sixth contact structure and the first β logic conductor and electrically coupled, and the fourth through-hole structure represents the corresponding through-hole structure of the electrically coupled adjacent structure; and forming a fifth through-hole structure, the fifth through-hole structure is placed between the fifth contact structure and the second β logic conductor and electrically coupled.

[0213] It can be seen that, for those of ordinary skill in the art, one or more of the disclosed embodiments achieve one or more of the advantages set forth above. After reading the foregoing description, those of ordinary skill in the art will be able to conceive of multiple variations, equivalent substitutions, and multiple other embodiments as broadly disclosed herein. Therefore, it is intended that the protection claimed herein be limited only by the limitations contained in the attached claims and their equivalents.

[0214] In an embodiment, a semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: a first active region and a second active region configured and arranged in a stack relative to a first direction according to the CFET type; a first contact structure and a second contact structure electrically coupled to the first active region correspondingly; a third contact structure and a fourth contact structure electrically coupled to the second active region correspondingly; a first metallization layer (M_1st layer) above the stack, including: an α logic conductor (α logic conductor) configured for logic signals; and a power grid (PG) conductor; the α logic and PG conductors do not overlap with each other; a metallization layer (M_B layer) below the stack, including β logic conductors that do not overlap with each other, wherein, relative to a second direction perpendicular to the first direction, each of the α logic conductor, the PG conductor, and the β logic conductor at least partially overlaps with one or more of the first contact structure, the second contact structure, the third contact structure, and the fourth contact structure. In an embodiment, the M_1st layer has multiple pitches, including: a pitch of the α logic conductor (pch_M_1st_lgk); and a pitch of the PG conductor (pch_M_1st_pg); and pch_M_1st_lgk < pch_M_1st_pg. In an embodiment, the M_B layer has a unique pitch represented by a pitch of the β logic conductor (pch_M_B_lgk). In an embodiment, pch_M_1st_lgk < pch_M_B_lgk; or pch_M_B_lgk ≤ pch_M_1st_pg. In an embodiment, the M_B layer has a unique pitch represented by a pitch of the β logic conductor (pch_M_B_lgk); and a first pitch (pch_M_1st_lgk) of the α logic conductor in the M_1st layer is less than pch_M_B_lgk, such that: pch_M_1st_lgk < pch_M_B_lgk. In an embodiment, pch_M_B_lgk is less than or equal to a second pitch (pch_M_1st_pg) of the PG conductor in the M_1st layer, such that: pch_M_B_lgk ≤ pch_M_1st_pg. In an embodiment, the semiconductor device further includes a circuit; and the BPG CFET is included in the circuit. In an embodiment, the circuit is an inverter, a transmission gate, or a flip-flop.

[0215] In an embodiment, a semiconductor device includes a buried logic conductor (BLC) CFET, which BLC CFET includes: a first and a second active region, arranged in a stack according to a CFET type configuration, wherein the second active region is above the first active region; a gate structure proximate to the first active region and the second active region; a first contact structure and a second contact structure, electrically coupled to the first active region respectively; a third contact structure and a fourth contact structure, electrically coupled to the second active region respectively; a first metallization layer (M_1st layer) above the stack, including: an α logic conductor (α logic conductor) configured for logic signals; and a power grid (PG) conductor; and a metallization (M_B) layer (M_B layer) below the stack, and which includes a β logic conductor; a first through-hole structure, electrically coupled between a first candidate and a first β logic conductor in the M_B layer, the first candidate being one of the gate structures or one of the first contact structure, the second contact structure, the third contact structure, or the fourth contact structure. In an embodiment, the first candidate is a second contact structure; and the semiconductor device further includes: a second via structure electrically coupled between the gate structure and the second β logic conductor in the M_B layer. In an embodiment, the semiconductor device further includes: a third via structure electrically coupled between the third contact structure and the first PG conductor in the M_1st layer. In an embodiment, the first candidate is a second contact structure; and the semiconductor device further includes: a fourth via structure electrically coupled between the first contact structure and the second conductor in the M_1st layer. In an embodiment, the first candidate is a first contact structure; and the semiconductor device further includes: a fifth contact structure electrically coupled to the first active region; a sixth contact structure electrically coupled to the second active region; and a second via structure electrically coupled between the second contact structure and the second β conductor in the M_B layer. In an embodiment, the semiconductor device further includes: a third via structure electrically coupled between the third contact structure and the first β conductor in the M_B layer; or a fourth via structure electrically coupled between the fourth contact structure and the second β conductor in the M_B layer. In an embodiment, the semiconductor device further comprises: a third via structure electrically coupled between the gate structure and the first α conductor in the M_1st layer; or a fourth via structure electrically coupled between the gate structure and the second α conductor in the M_1st layer. In an embodiment, the semiconductor device further comprises: a third via structure electrically coupled between the fifth contact structure and the sixth contact structure.

[0216] In an embodiment, a method (for a layout diagram stored on a non-transitory computer-readable medium, for manufacturing a semiconductor device including a buried logic conductor (BLC) CFET region) includes the following steps: generating a first active area (AA) pattern and a second active area pattern arranged in a first stack, wherein the second AA pattern is arranged above the first AA pattern, and the first AA pattern and the second AA pattern represent CFET-type configurations of corresponding first and second active areas in the semiconductor device; generating a first gate pattern and a second gate pattern arranged in a second stack, wherein the first gate pattern is above the first AA pattern, and the second gate pattern is above the second AA pattern, and the first gate pattern and the second gate pattern represent corresponding first portions of a first gate structure; generating a first contact pattern and a second contact pattern arranged in a third stack, wherein the second contact pattern is above the first contact pattern, and the first contact pattern and the second contact pattern represent CFET-type configurations of corresponding first and second active areas domains and a first portion of a corresponding first contact structure and a second contact structure electrically coupled to the corresponding first active region and the second active region; generating a third contact pattern and a fourth contact pattern arranged in a fourth stack, wherein the fourth contact pattern is above the third contact pattern, and the third contact pattern and the fourth contact pattern represent the first portion of the corresponding third contact structure and the fourth contact structure electrically coupled to the corresponding first active region and the second active region; generating an α pattern and a power grid (PG) pattern, which are correspondingly located above the second gate pattern and the second contact pattern and the fourth contact pattern, do not overlap with each other, and represent the corresponding α logic conductor and PG conductor in the first metallization layer; generating a β pattern, which is correspondingly located below the first gate pattern and the first contact pattern and the third contact pattern, do not overlap with each other, and represent the corresponding β logic conductor in the metallization buried layer; and generating a first through-hole pattern, which is placed between (A) the first gate pattern, the second contact pattern or the fourth contact pattern and (B) the first β pattern, and represents the corresponding through-hole structure of the electrically coupled adjacent structure. In an embodiment, the method further includes, based on the layout diagram, at least one of: (A) performing one or more photolithography exposures; (B) manufacturing one or more semiconductor masks; or (C) manufacturing at least one component in a layer of a semiconductor integrated circuit.In an embodiment, a first through-hole pattern is placed between a first gate pattern and a first β pattern; and generating a layout diagram also includes: generating a second through-hole pattern, which is placed between a third contact pattern and a second β pattern, and represents a corresponding through-hole structure of an electrically coupled adjacent structure; generating a third through-hole pattern, which is placed between a third contact pattern and a fourth contact pattern, and represents a corresponding through-hole structure of an electrically coupled adjacent structure; generating a fourth through-hole pattern, which is placed between the second contact pattern and a first PG pattern, and represents a corresponding through-hole structure of an electrically coupled adjacent structure; and generating a fifth through-hole pattern, which is placed between the first contact pattern and the second PG pattern, and represents a corresponding through-hole structure of an electrically coupled adjacent structure. In an embodiment, a first via pattern is placed between a first contact pattern and a first β pattern; and generating a layout diagram further includes: generating a second via pattern, which is placed between a second contact pattern and a second β pattern and represents a corresponding via structure of an electrically coupled adjacent structure; generating a third via pattern, which is placed between a third contact pattern and a fourth contact pattern and represents a corresponding via structure of an electrically coupled adjacent structure; generating a fifth contact pattern and a sixth contact pattern arranged in a fifth stack, wherein the sixth contact pattern is above the fifth contact pattern, and the fifth contact pattern and the sixth contact pattern represent first portions of corresponding fifth structures and sixth structures electrically coupled to corresponding first and second active regions; generating a fourth via pattern, which is placed between the sixth contact pattern and the first β pattern and represents a corresponding via structure of an electrically coupled adjacent structure; and generating a fifth via pattern, which is placed between the fifth contact pattern and the second β pattern and represents a corresponding via structure of an electrically coupled adjacent structure.

[0217] The parts of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art should understand that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and can be subjected to various changes, replacements and modifications without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device includes a buried logic conductor complementary field effect transistor, and the buried logic conductor complementary field effect transistor includes: A first active region and a second active region arranged in a stack according to a complementary field effect transistor type configuration with respect to a first direction; A first contact structure and a second contact structure, electrically coupled to the first active region correspondingly; A third contact structure and a fourth contact structure, electrically coupled to the second active region correspondingly; A first metallization layer M_1st layer located above the stack, including: An α logic conductor configured for logic signals; and A power grid conductor; The α logic conductor and the power grid conductor do not overlap with each other; and A metallization layer M_B layer located below the stack, including non-overlapping β logic conductors; and Wherein, with respect to a second direction perpendicular to the first direction, each of the α logic conductor, the power grid conductor, and the β logic conductor at least partially overlaps with one or more of the first contact structure, the second contact structure, the third contact structure, and the fourth contact structure.

2. The semiconductor device according to claim 1, wherein: The M_1st layer has a plurality of pitches, including: The pitch pch_M_1st_lgk of the α logic conductor; and The pitch pch_M_1st_pg of the power grid conductor; and pch_M_1st_lgk < pch_M_1st_pg.

3. The semiconductor device according to claim 2, wherein: The M_B layer has a unique pitch represented by the pitch pch_M_B_lgk of the β logic conductor.

4. The semiconductor device according to claim 3, wherein: pch_M_1st_lgk < pch_M_B_lgk; or pch_M_B_lgk ≤ pch_M_1st_pg.

5. The semiconductor device according to claim 1, wherein: The M_B layer has a unique pitch represented by the pitch pch_M_B_lgk of the β logic conductor; and The first pitch pch_M_1st_lgk of the α logic conductor in the M_1st layer is less than pch_M_B_lgk, such that: pch_M_1st_lgk < pch_M_B_lgk.

6. The semiconductor device according to claim 5, wherein: pch_M_B_lgk is less than or equal to the second pitch pch_M_1st_pg of the power grid conductor in the M_1st layer, such that: pch_M_B_lgk ≤ pch_M_1st_pg.

7. The semiconductor device according to claim 1, further including: A circuit; And Wherein, the buried logic conductor complementary field effect transistor is included in the circuit.

8. The semiconductor device according to claim 7, wherein: The circuit is an inverter, a transmission gate, or a flip-flop.

9. A semiconductor device includes a buried logic conductor complementary field effect transistor, and the buried logic conductor complementary field effect transistor includes: a first active region and a second active region arranged in a stack according to a complementary field effect transistor type configuration, wherein the second active region is located above the first active region; a gate structure proximate to the first active region and the second active region; A first contact structure and a second contact structure, electrically coupled to the first active region respectively; a third contact structure and a fourth contact structure, electrically coupled to the second active region respectively; A first metallization layer M_1st layer located above the stack, comprising: alpha logic conductors configured for transmitting a first plurality of logic signals; and a grid conductor for providing a plurality of voltages for driving the buried logic conductor complementary field effect transistors; and a metallization layer M_B layer located below the stack, comprising a β logic conductor, the β logic conductor being used to transmit a second plurality of logic signals different from the plurality of voltages; A first via structure electrically coupled between a first candidate and a first β logic conductor in the M_B layer, wherein the first candidate is one of the gate structure, the first contact structure, the second contact structure, the third contact structure, and the fourth contact structure.

10. The semiconductor device according to claim 9, wherein: the first candidate is the second contact structure; and The semiconductor device further comprises: A second via structure is electrically coupled between the gate structure and a second beta logic conductor in the M_B layer.

11. The semiconductor device according to claim 10, further comprising: A third through-hole structure is electrically coupled between the third contact structure and the first grid conductor in the M_1st layer.

12. The semiconductor device according to claim 11, wherein: the first candidate is the second contact structure; and The semiconductor device further comprises: A fourth via structure is electrically coupled between the first contact structure and a second conductor in the M_1st layer.

13. The semiconductor device according to claim 9, wherein: The first candidate is the first contact structure; and The semiconductor device further comprises: a fifth contact structure electrically coupled to the first active region; a sixth contact structure electrically coupled to the second active region; and A second via structure is electrically coupled between the second contact structure and a second beta logic conductor in the M_B layer.

14. The semiconductor device according to claim 13, further comprising: a third via structure electrically coupled between the third contact structure and a first beta logic conductor in the M_B layer; or A fourth via structure is electrically coupled between the fourth contact structure and a second β logic conductor in the M_B layer.

15. The semiconductor device according to claim 13, further comprising: a third via structure electrically coupled between the gate structure and a first α conductor in the M_1st layer; or A fourth via structure is electrically coupled between the gate structure and a second α conductor in the M_1st layer.

16. The semiconductor device according to claim 13, further comprising: A third through-hole structure is electrically coupled between the fifth contact structure and the sixth contact structure.

17. A method of manufacturing a semiconductor device including a buried logic conductor complementary field effect transistor region, the method comprising: forming a first active region and a second active region disposed in a first stack, wherein the second active region is located above the first active region; forming a gate structure proximate to the first active region and the second active region; forming a first contact structure and a second contact structure disposed in a second stack, wherein the second contact structure is located above the first contact structure, and the first contact structure and the second contact structure are electrically coupled to corresponding first and second active regions; forming a third contact structure and a fourth contact structure disposed in a third stack, wherein the fourth contact structure is located above the third contact structure, and the third contact structure and the fourth contact structure are electrically coupled to the corresponding first active region and the second active region; forming an alpha logic conductor and a grid conductor in the first metallization layer, wherein the alpha logic conductor and the grid conductor are correspondingly located above the gate structure and the second contact structure and the fourth contact structure and do not overlap each other; forming a beta logic conductor in a buried metallization layer, the beta logic conductor being correspondingly located below the gate structure and the first and third contact structures and not overlapping each other, and representing a corresponding beta logic conductor in the buried metallization layer; as well as A first via structure is formed, the first via structure being disposed between and electrically coupling (A) the gate structure, the first contact structure, the second contact structure, the third contact structure, or the fourth contact structure and (B) a first β logic conductor.

18. The method of claim 17, wherein: The first via structure is disposed between the gate structure and the first beta logic conductor; and The method further comprises: A second via structure is formed, the second via structure being disposed between and electrically coupling the third contact structure and a second beta logic conductor.

19. The method according to claim 18, further comprising: forming a third via structure disposed between and electrically coupling the third contact structure and the fourth contact structure; forming a fourth via structure disposed between the second contact structure and the first grid conductor and electrically coupling them; as well as A fifth via structure is formed, the fifth via structure being disposed between the first contact structure and the second power grid conductor and electrically coupling them.

20. The method of claim 17, wherein: The first via structure is disposed between the first contact structure and the first beta logic conductor; and The method further comprises: forming a second via structure disposed between and electrically coupling the second contact structure and a second beta logic conductor; forming a third via structure disposed between and electrically coupling the third contact structure and the fourth contact structure; forming a fifth contact structure and a sixth contact structure disposed in a fourth stack, wherein the sixth contact structure is located above the fifth contact structure, and the fifth contact structure and the sixth contact structure are electrically coupled to the corresponding first active region and the second active region; forming a fourth via structure disposed between and electrically coupling the sixth contact structure and the first beta logic conductor, the fourth via structure representing a corresponding via structure electrically coupled to an adjacent structure; and A fifth via structure is formed, the fifth via structure being disposed between and electrically coupling the fifth contact structure and the second beta logic conductor.

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