A back-illuminated single-photon avalanche diode and a manufacturing method thereof

Abstract

The present invention discloses a back-illuminated single-photon avalanche diode and a manufacturing method thereof, belonging to the technical field of single-photon detection. The back-illuminated single-photon avalanche diode includes a P-type epitaxial layer, a P+-heavily doped region is arranged inside the P-type epitaxial layer, a P--lightly doped region is coaxially arranged around the P+-heavily doped region, a P-type avalanche doping region is coaxially arranged below the P--lightly doped region, N+-heavily doped regions are arranged on both sides of the P+-heavily doped region, an N-well region is coaxially arranged below the N+-heavily doped regions, N-type avalanche doping regions are arranged at intervals below the P-type avalanche doping region, and an N--lightly doped region is arranged below the N-type avalanche doping region. The present invention adopts the method of back-illuminating light, optimizes the device structure, and integrates the peripheral circuit of the device below the device. The detection efficiency of the device is improved. An avalanche junction is formed by the P-type avalanche doping region, the central region of the P-type epitaxial layer and the N-type avalanche doping region, and the use of this sub-structure significantly reduces the dark count rate of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of single-photon detection, and particularly relates to a back-illuminated single-photon avalanche diode with a low dark count rate and a manufacturing method thereof. Background Art

[0002] Single-photon detection technology has broad application prospects in the fields of national defense construction, industry, and civilian life, such as quantum key distribution, lidar, fluorescence lifetime imaging, and three-dimensional vision systems. The single-photon avalanche diode (single photon avalanche photodiode, denoted as SPAD) based on the CMOS process, as a core device for single-photon detection, has received increasing attention and emphasis from researchers. The single-photon avalanche diode in Geiger mode is a detector that can detect extremely weak optical signals. It has advantages such as large internal gain, high sensitivity, fast response speed, high detection efficiency, low noise, small volume, strong structure, and easy integration. With the continuous expansion of the application fields of single-photon detection, the performance requirements for SPADs are also getting higher and higher. The dark count rate characteristic is one of the core parameters for judging the performance of SPAD devices. Devices with a smaller dark count can better exclude the interference of noise signals and accurately detect the signal light.

[0003] Traditional single-photon avalanche diodes have a relatively high dark count rate, and currently, more research has been conducted on single-photon avalanche diodes with front-side illumination. When this structure of single-photon avalanche diode is integrated with a quenching circuit and a readout circuit, the circuit is fabricated around the single-photon avalanche diode, and the photosensitive area of the single-photon avalanche diode only accounts for a small part of the entire pixel, resulting in very low detection efficiency. Summary of the Invention

[0004] Object of the Invention: The object of the present invention is to propose a back-illuminated single-photon avalanche diode and a manufacturing method thereof in view of the deficiencies existing in the structure of the existing single-photon avalanche diode, so that the device has a lower dark count rate and a higher detection efficiency at room temperature. The present invention adopts a P-type avalanche doping region, a P-type epitaxial layer central region, and an N-type avalanche doping region, which can obtain a lower electric field in the avalanche region and avoid the generation of tunneling effects, thereby reducing the dark count rate of the device. By adopting the method of illuminating the device from the back side with light and integrating the circuit below the device, the detection efficiency of the device can be effectively improved.

[0005] Technical Solution: To achieve the above object, the present invention provides the following technical solution:

[0006] Back-illuminated single-photon avalanche diode, comprising a P-type epitaxial layer, with a P+ heavily doped region disposed inside the P-type epitaxial layer, a P- lightly doped region coaxially disposed around the P+ heavily doped region, a P-type avalanche doped region coaxially disposed below the P- lightly doped region, N+ heavily doped regions disposed on both sides of the P+ heavily doped region, an N-well region coaxially disposed below the N+ heavily doped regions, N-type avalanche doped regions disposed at intervals below the P-type avalanche doped region, and an N- lightly doped region disposed below the N-type avalanche doped region.

[0007] Further, the P+ heavily doped region is contained inside the P- lightly doped region.

[0008] Further, the P-type avalanche doped region partially overlaps with the P- lightly doped region, and the N-type avalanche doped region partially overlaps with the N- lightly doped region.

[0009] Further, the central region of the P-type epitaxial layer is a part of the P-type epitaxial layer.

[0010] Further, the P-type avalanche doped region and the N-type avalanche doped region are separated by the central epitaxial layer region.

[0011] Further, a cathode is led out from the upper end of the N+ heavily doped region; an anode is led out from the upper end of the P+ heavily doped region.

[0012] Further, the manufacturing method of the back-illuminated single-photon avalanche diode includes the following steps:

[0013] 1) Growing a P-type epitaxial layer by an epitaxial process;

[0014] 2) Thermally growing a silicon dioxide layer on the upper end face of the P-type epitaxial layer (1);

[0015] 3) Spin-coating a photoresist on the silicon dioxide layer, selectively exposing and developing through a mask template to expose the silicon dioxide layer in the region where the P+ heavily doped region (2) is located;

[0016] 4) Removing the silicon dioxide in the region where the P+ heavily doped region (2) is located through an etching process to expose the P-type epitaxial silicon;

[0017] 5) After ion-implanting P-type impurities, removing the photoresist; forming the P+ heavily doped region (2);

[0018] 6) Spin-coating a photoresist on the upper end face of the structure formed in step 5), exposing through an exposure and development process to expose the region where the P- lightly doped region (3) is located, ion-implanting P-type impurities to form the P- lightly doped region (3); removing the photoresist;

[0019] 7) Spin coat photoresist on the upper end face of the structure formed in step 6). Through the exposure and development process, expose the area where the P-type avalanche doping region (4) is located. Form the P-type avalanche doping region (4) by ion implanting P-type impurities. Remove the photoresist.

[0020] 8) Spin coat photoresist on the upper end face of the structure formed in step 7). Through the exposure and development process, expose the area where the N+ heavily doped region (5) is located. Form the N+ heavily doped region (5) by ion implanting N-type impurities. Remove the photoresist.

[0021] 9) Spin coat photoresist on the upper end face of the structure formed in step 8). Through the exposure and development process, expose the area where the N-well region (6) is located. Form the N-well region (6) by ion implanting N-type impurities. Remove the photoresist.

[0022] 10) Spin coat photoresist on the upper end face of the structure formed in step 9). Through the exposure and development process, expose the area where the N-type avalanche doping region (7) is located. Form the N-type avalanche doping region (7) by ion implanting N-type impurities. Remove the photoresist.

[0023] 11) Spin coat photoresist on the upper end face of the structure formed in step 10). Through the exposure and development process, expose the area where the N- lightly doped region (8) is located. Form the N- lightly doped region (8) by ion implanting N-type impurities. Remove the photoresist.

[0024] 12) Perform an annealing process.

[0025] 13) Deposit a certain thickness of silicon dioxide protective layer on the upper end face of the structure formed in step 12).

[0026] 14) Spin coat photoresist on the upper end face of the structure formed in step 13). Through the exposure and development process, expose the areas where the cathode (9) and anode (10) are located. Through the etching process, remove the silicon dioxide deposited in the areas where the cathode (9) and anode (10) are located. Remove the photoresist.

[0027] 15) On the upper end face of the structure formed in step 14), deposit metallic aluminum using the magnetron sputtering process.

[0028] 16) Spin coat photoresist on the upper end face of the structure formed in step 15). Through the exposure and development process, expose the areas other than where the cathode (9) and anode (10) are located. Through the etching process, remove the metallic aluminum in the areas other than where the cathode (9) and anode (10) are located. Remove the photoresist.

[0029] 17) Through a heat treatment process, alloying of the cathode (9) and the anode (10) in the structure formed in step 16) is completed.

[0030] The beneficial effects of the present invention are as follows: Compared with the existing technologies, for the back-illuminated single-photon avalanche diode of the present invention, by optimizing the structure, light is irradiated from the back of the device, and the peripheral circuit is integrated below the device, increasing the area of the photosensitive region of the device in the entire pixel and improving the detection efficiency of the device. The avalanche region formed by the P-well central region, the P-type epitaxial layer central region, and the central N-type region has a relatively low doping level, and the avalanche junction is a graded junction, significantly reducing the electric field in the avalanche region. Therefore, the generation of the tunneling effect is suppressed, and its dark count rate is significantly lower than that of the devices with the existing structures. Description of the Drawings

[0031] Figure 1 It is a schematic cross-sectional structure diagram of a single-photon avalanche diode;

[0032] Figure 2 It is a simulated electric field distribution diagram of the cross-section of a single-photon avalanche diode;

[0033] Figure 3 It is a curve diagram of the simulated detection efficiency of a single-photon avalanche diode;

[0034] Reference numerals: 1 - P-type epitaxial layer, 2 - P+ heavily doped region, 3 - P- lightly doped region, 4 - P-type avalanche doping region, 5 - N+ heavily doped region, 6 - N-well region, 7 - N-type avalanche doping region, 8 - N- lightly doped region, 9 - cathode, 10 - anode, 101 - P-type epitaxial layer central region. Detailed Embodiments

[0035] To better understand the content of the present invention for patent, the technical solution of the present invention will be further described below with reference to the drawings.

[0036] As Figure 1 shown, the back-illuminated single-photon avalanche diode includes a P-type epitaxial layer 1. Inside the P-type epitaxial layer 1, a P+ heavily doped region 2 is provided. Coaxially outside the P+ heavily doped region 2, a P- lightly doped region 3 is provided. Coaxially below the P- lightly doped region 3, a P-type avalanche doping region 4 is provided. On both sides of the P+ heavily doped region 2, N+ heavily doped regions 5 are provided. Coaxially below the N+ heavily doped regions 5, an N-well region 6 is provided. The P-type avalanche doping region 4 is provided at an interval below the N-type avalanche doping region 7, and an N- lightly doped region 8 is provided below the N-type avalanche doping region 7.

[0037] The P+ heavily doped region 2 is included inside the P- lightly doped region 3.

[0038] The P-type avalanche doping region 4 and the P- lightly doped region 3, and the N-type avalanche doping region 7 and the N- lightly doped region 8 all have partial overlaps.

[0039] The central region 101 of the P-type epitaxial layer is a part of the P-type epitaxial layer 1.

[0040] The P-type avalanche doping region 4 and the N-type avalanche doping region 7 are separated by the epitaxial layer central region 101.

[0041] The cathode 9 is led out from the upper end of the N+-heavily doped region 5; the anode 10 is led out from the upper end of the P+-heavily doped region 2.

[0042] The present invention is not limited to the following embodiments. Figure 2 It is the simulated electric field distribution diagram of the embodiment, Figure 3 It is the detection efficiency curve diagram of the embodiment. After measurement, the reverse bias breakdown voltage of the PN junction in the present invention is 46.5V. At room temperature, under an applied overbias voltage of 5V, the dark count rate is 0.81Hz / μm 2 。The maximum electric field is 3.54×10 5 V / cm. When the overbias voltage is 5V, the detection efficiency at a light wavelength of 850nm is 20%.

[0043] The manufacturing method of the back-illuminated single-photon avalanche diode includes the following steps:

[0044] 1) Growing a P-type epitaxial layer 1 by an epitaxial process;

[0045] 2) Thermally growing a silicon dioxide layer on the upper end face of the P-type epitaxial layer 1;

[0046] 3) Spin-coating a photoresist on the silicon dioxide layer, selectively exposing and developing through a mask template to expose the silicon dioxide layer in the region where the P+-heavily doped region 2 is located;

[0047] 4) Removing the silicon dioxide in the region where the P+-heavily doped region 2 is located through an etching process to expose the P-type epitaxial silicon;

[0048] 5) After ion-implanting P-type impurities, removing the photoresist; forming the P+-heavily doped region 2;

[0049] 6) Spin-coating a photoresist on the upper end face of the structure formed in step 5), exposing through an exposure and development process to expose the region where the P-lowly doped region 3 is located, forming the P-lowly doped region 3 by ion-implanting P-type impurities; removing the photoresist;

[0050] 7) Spin-coating a photoresist on the upper end face of the structure formed in step 6), exposing through an exposure and development process to expose the region where the P-type avalanche doping region 4 is located; forming the P-type avalanche doping region 4 by ion-implanting P-type impurities; removing the photoresist;

[0051] 8) Spin-coat photoresist on the upper end face of the structure formed in step 7). Through the exposure and development process, expose the area where the N+-heavily doped region 5 is located. Form the N+-heavily doped region 5 by ion implanting N-type impurities. Remove the photoresist.

[0052] 9) Spin-coat photoresist on the upper end face of the structure formed in step 8). Through the exposure and development process, expose the area where the N-well region 6 is located. Form the N-well region 6 by ion implanting N-type impurities. Remove the photoresist.

[0053] 10) Spin-coat photoresist on the upper end face of the structure formed in step 9). Through the exposure and development process, expose the area where the N-type avalanche-doped region 7 is located. Form the N-type avalanche-doped region 7 by ion implanting N-type impurities. Remove the photoresist.

[0054] 11) Spin-coat photoresist on the upper end face of the structure formed in step 10). Through the exposure and development process, expose the area where the N--lightly doped region 8 is located. Form the N--lightly doped region 8 by ion implanting N-type impurities. Remove the photoresist.

[0055] 12) Perform an annealing process.

[0056] 13) Deposit a certain thickness of silicon dioxide protective layer on the upper end face of the structure formed in step 12).

[0057] 14) Spin-coat photoresist on the upper end face of the structure formed in step 13). Through the exposure and development process, expose the areas where the cathode 9 and anode 10 are located. Through the etching process, remove the silicon dioxide deposited in the areas where the cathode 9 and anode 10 are located. Remove the photoresist.

[0058] Remove the photoresist.

[0059] 15) On the upper end face of the structure formed in step 14), deposit metallic aluminum using the magnetron sputtering process.

[0060] 16) Spin-coat photoresist on the upper end face of the structure formed in step 15). Through the exposure and development process, expose the areas other than where the cathode 9 and anode 10 are located. Through the etching process, remove the metallic aluminum in the areas other than where the cathode 9 and anode 10 are located. Remove the photoresist.

[0061] 17) Through the heat treatment process, complete the alloying of the cathode 9 and anode 10 in the structure formed in step 16).

[0062] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, the doping concentrations of each region in the device structure and the device manufacturing process can also be adjusted, and these adjustments should also be regarded as the protection scope of the present invention.

Claims

1. A back-illuminated single-photon avalanche diode, characterized in that: It includes a P-type epitaxial layer (1), a P+-heavily doped region (2) is arranged inside the P-type epitaxial layer (1), a P--lightly doped region (3) is coaxially arranged around the P+-heavily doped region (2), a P-type avalanche doping region (4) is coaxially arranged below the P--lightly doped region (3), N+-heavily doped regions (5) are arranged on both sides of the P+-heavily doped region (2), an N-well region (6) is coaxially arranged below the N+-heavily doped regions (5), an N-type avalanche doping region (7) is arranged at intervals below the P-type avalanche doping region (4), and an N--lightly doped region (8) is arranged below the N-type avalanche doping region (7); The P+-heavily doped region (2) is contained inside the P--lightly doped region (3); the P-type avalanche doping region (4) and the P--lightly doped region (3), the N-type avalanche doping region (7) and the N--lightly doped region (8) all have partial overlaps; the P-type epitaxial layer central region (101) is a part of the P-type epitaxial layer (1); the P-type avalanche doping region (4) and the N-type avalanche doping region (7) are separated by the epitaxial layer central region (101); a cathode (9) is led out from the upper end of the N+-heavily doped region (5); an anode (10) is led out from the upper end of the P+-heavily doped region (2); A method for manufacturing a back-illuminated single-photon avalanche diode, comprising the following steps: 1) Growing a P-type epitaxial layer (1) by an epitaxial process; 2) Thermally growing a silicon dioxide layer on the upper end face of the P-type epitaxial layer (1); 3) Spin-coating a photoresist on the silicon dioxide layer, selectively exposing and developing through a mask template to expose the silicon dioxide layer in the region where the P+-heavily doped region (2) is located; 4) Through an etching process, removing the silicon dioxide in the region where the P+-heavily doped region (2) is located to expose the P-type epitaxial silicon; 5) After ion-implanting P-type impurities, removing the photoresist; forming the P+-heavily doped region (2); 6) Spin-coating a photoresist on the upper end face of the structure formed in step 5), through an exposure and development process, exposing the region where the P--lightly doped region (3) is located, and forming the P--lightly doped region (3) by ion-implanting P-type impurities; removing the photoresist; 7) Spin-coating a photoresist on the upper end face of the structure formed in step 6), through an exposure and development process, exposing the region where the P-type avalanche doping region (4) is located; forming the P-type avalanche doping region (4) by ion-implanting P-type impurities; removing the photoresist; 8) Spin-coating a photoresist on the upper end face of the structure formed in step 7), through an exposure and development process, exposing the region where the N+-heavily doped region (5) is located; forming the N+-heavily doped region (5) by ion-implanting N-type impurities; removing the photoresist; 9) Spin-coating a photoresist on the upper end face of the structure formed in step 8), through an exposure and development process, exposing the region where the N-well region (6) is located; forming the N-well region (6) by ion-implanting N-type impurities, and removing the photoresist; 10) Spin-coat photoresist on the upper end face of the structure formed in step 9). Through the exposure and development process, expose the area where the N-type avalanche doping region (7) is located. Form the N-type avalanche doping region (7) by ion implanting N-type impurities. Remove the photoresist. 11) Spin-coat photoresist on the upper end face of the structure formed in step 10). Through the exposure and development process, expose the area where the N-low doping region (8) is located. Form the N-low doping region (8) by ion implanting N-type impurities. Remove the photoresist. 12) Perform an annealing process. 13) Deposit a certain thickness of silicon dioxide protective layer on the upper end face of the structure formed in step 12). 14) Spin-coat photoresist on the upper end face of the structure formed in step 13). Through the exposure and development process, expose the areas where the cathode (9) and anode (10) are located. Remove the silicon dioxide deposited in the areas where the cathode (9) and anode (10) are located through an etching process. Remove the photoresist. 15) On the upper end face of the structure formed in step 14), deposit metallic aluminum using a magnetron sputtering process. 16) Spin-coat photoresist on the upper end face of the structure formed in step 15). Through the exposure and development process, expose the area outside the areas where the cathode (9) and anode (10) are located. Remove the metallic aluminum in the area outside the areas where the cathode (9) and anode (10) are located through an etching process. Remove the photoresist. 17) Complete the alloying of the cathode (9) and anode (10) in the structure formed in step 16) through a heat treatment process.

Images