Short-wave infrared focal plane array chip and manufacturing method, sensor and manufacturing method

Abstract

The application discloses a short-wave infrared focal plane array chip and a manufacturing method thereof, a sensor and a manufacturing method thereof. The chip comprises a substrate structure, a first intrinsic layer on one side of a buried oxygen layer, and a first heavily doped region in the first intrinsic layer; an absorption layer on the side of the first intrinsic layer away from the buried oxygen layer, the absorption layer comprising at least one germanium layer; a second heavily doped region penetrating through the absorption layer and the first intrinsic layer, the second heavily doped region being in direct contact with the first heavily doped region in the first intrinsic layer; an avalanche layer on the side of the absorption layer away from the substrate structure, the avalanche layer comprising an intrinsic germanium layer and a germanium-silicon layer, and satisfying a lattice matching condition with the absorption layer; a second intrinsic layer on the side of the avalanche layer away from the absorption layer, the second intrinsic layer comprising a third heavily doped region; a first electrode electrically connected with the second heavily doped region and a second electrode electrically connected with the third heavily doped region. The chip has a low dark count rate and avalanche breakdown voltage, and high sensitivity and response speed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sensors, in particular to a short-wave infrared focal plane array chip and a manufacturing method thereof, and a sensor comprising the short-wave infrared focal plane array chip and a manufacturing method thereof. BACKGROUND

[0002] Single Photon Avalanche Photodetectors (SPADs) are a kind of high-sensitivity devices that can detect the energy of a single photon. According to the working wavelength, SPADs are divided into near-infrared (NIR, 0.78 μm ~ 1.1 μm) SPADs, short-wave infrared (SWIR, 1.1 μm ~ 3 μm) SPADs, mid-wave infrared (MWIR, 3 μm ~ 5 μm) SPADs and long-wave infrared (LWIR, 8 μm ~ 14 μm) SPADs. Among them, short-wave infrared SPADs sensors (i.e. sensors comprising short-wave infrared SPADs) play an important role in many emerging applications such as optical communication, quantum information, ranging, coherent sensing, medical diagnosis, analytical instruments, laser radar (LIDAR), life science and over-the-horizon imaging.

[0003] Although commercial indium gallium arsenide (InGaAs) short-wave infrared SPADs sensors have been widely used in laser radar, optical communication, quantum communication and other application scenarios, they usually use small-size and expensive indium phosphide (InP) wafers as substrates. The manufacturing process of SPADs sensors is expensive, not compatible with standard CMOS process production lines, the number of SPADs detectors formed on a single wafer is limited, the yield of the formed SPADs sensors is low, the price of a single chip is expensive, and mass production is not possible.

[0004] Compared with III-V semiconductor materials, germanium-based semiconductor materials have the advantages of silicon-based epitaxy (large size, 8 inches, even 12 inches), high compatibility with CMOS process production lines, excellent photoelectric response in the short-wave infrared band, etc. and are considered as one of the important technical solutions for mass production of short-wave infrared SPADs sensors. However, the dark current, dark count rate (DCR), avalanche breakdown voltage, single photon detection efficiency, sensitivity and response speed of known germanium SPADs sensors cannot meet the standard of commercial products. SUMMARY

[0005] To solve the above technical problems, the present application provides a short-wave infrared focal plane array chip and a manufacturing method thereof, and a sensor comprising the short-wave infrared focal plane array chip and a manufacturing method thereof.

[0006] Specifically, the embodiment of the present application provides the following technical scheme:

[0007] A short-wave infrared focal plane array chip, comprising at least one single-photon avalanche photodetector, the short-wave infrared focal plane array chip comprising:

[0008] A substrate structure comprising a buried oxygen layer and a first intrinsic layer located on one side of the buried oxygen layer, the first intrinsic layer having a first heavily doped region therein;

[0009] An absorption layer located on the side of the first intrinsic layer away from the buried oxygen layer, the absorption layer comprising at least one germanium layer;

[0010] A second heavily doped region penetrating through the absorption layer and the first intrinsic layer, the second heavily doped region being in direct contact with the first heavily doped region in the first intrinsic layer;

[0011] An avalanche layer located on the side of the absorption layer away from the substrate structure, the avalanche layer comprising an intrinsic germanium layer and a germanium-silicon layer, and the avalanche layer and the absorption layer satisfying a lattice matching condition;

[0012] A second intrinsic layer located on the side of the avalanche layer away from the absorption layer, the second intrinsic layer having a third heavily doped region therein;

[0013] A reflective layer located on the side of the second intrinsic layer away from the avalanche layer;

[0014] A first via penetrating through the reflective layer, the second intrinsic layer and the avalanche layer, the first via exposing a part of the surface of a quantum well sensing layer in the absorption layer and a part of the surface of the second heavily doped region away from the buried oxygen layer, and the first via not being in contact with the third heavily doped region;

[0015] A passivation layer located on the surface of the first via and the surface of the reflective layer, the passivation layer having a second via and a third via therein, the second via exposing at least a part of the surface of the second heavily doped region, and the third via exposing at least a part of the surface of the reflective layer;

[0016] A first electrode electrically connected to the second heavily doped region through the second via and a second electrode electrically connected to the third heavily doped region through the third via.

[0017] Optionally, the substrate structure further comprises a silicon substrate on an insulator located on the side of the buried oxygen layer away from the first intrinsic layer.

[0018] Optionally, in the quantum well sensing layer, the content of germanium in the germanium-silicon layer ranges from 0 to 30%, and in the avalanche layer, the content of germanium in the germanium-silicon layer ranges from 0 to 30%.

[0019] Optionally, the second heavily doped region comprises a first sub-heavily doped region and a second sub-heavily doped region, and the first sub-heavily doped region and the second sub-heavily doped region are located on opposite sides of the first heavily doped region.

[0020] Optionally, the first intrinsic layer is an intrinsic germanium layer, an intrinsic GaAs layer, an intrinsic AlAs layer, an intrinsic InGaAs layer, an intrinsic AlGaAs layer, or an intrinsic GeSi layer.

[0021] If the first intrinsic layer is an intrinsic GeSi layer, the content of Si in the GeSi layer is less than 30%.

[0022] Optionally, the avalanche layer comprises at least one of an intrinsic germanium / germanium-silicon multiple quantum well layer and an intrinsic germanium / germanium-silicon superlattice layer.

[0023] Optionally, the absorption layer comprises a stacked sensing layer and a quantum well sensing layer, wherein the sensing layer is a germanium sensing layer, and the quantum well sensing layer is a germanium / germanium-silicon quantum well sensing layer.

[0024] Optionally, further comprising: a charge layer located in the surface of the quantum well sensing layer, and in a plane parallel to the plane where the absorption layer is located, a projection of the charge layer is located within the projection range of the first heavily doped region, and a preset distance between the projection boundary of the charge layer and the projection boundary of the first heavily doped region is greater than zero.

[0025] A sensor comprising the short-wave infrared focal plane array chip of any one of the above.

[0026] A method for manufacturing a short-wave infrared focal plane array chip, the short-wave infrared focal plane array chip comprising at least one single-photon avalanche photodetector, the method comprising:

[0027] Manufacturing a substrate structure, the substrate structure comprising a silicon substrate, a buried oxygen layer located on the surface of the silicon substrate, and a first intrinsic layer located on the side of the buried oxygen layer away from the silicon substrate, the first intrinsic layer having a first heavily doped region therein;

[0028] Forming an absorption layer on the side of the first intrinsic layer away from the buried oxygen layer, the absorption layer comprising at least one germanium layer;

[0029] Forming a second heavily doped region penetrating through the absorption layer and the first intrinsic layer, and in the first intrinsic layer, the second heavily doped region is in direct contact with the first heavily doped region;

[0030] Forming an avalanche layer on the side of the absorption layer away from the substrate structure, the avalanche layer comprising an intrinsic germanium layer and a germanium-silicon layer, and the avalanche layer and the absorption layer satisfy a lattice matching condition;

[0031] forming a second intrinsic layer on a side of the avalanche layer away from the absorption layer, the second intrinsic layer having a third heavily doped region therein;

[0032] forming a reflection layer on a side of the second intrinsic layer away from the avalanche layer;

[0033] forming a first via through the reflection layer, the second intrinsic layer and the avalanche layer, the first via exposing a surface of a quantum well sensing layer portion in the absorption layer and a surface of the third heavily doped region away from the buried oxide layer, and the first via not contacting the third heavily doped region;

[0034] forming a passivation layer on the surface of the first via and a surface of the reflection layer, the passivation layer having a second via and a third via therein, the second via exposing at least a surface of the third heavily doped region, and the third via exposing at least a surface of the reflection layer;

[0035] forming a first electrode electrically connected to the third heavily doped region through the second via and a second electrode electrically connected to the third heavily doped region through the third via.

[0036] Optionally, forming the absorption layer on a side of the first intrinsic layer away from the buried oxide layer comprises: forming the absorption layer on a side of the first intrinsic layer away from the buried oxide layer by using a homoepitaxy process.

[0037] forming the avalanche layer on a side of the absorption layer away from the substrate structure comprises: forming the avalanche layer on a side of the absorption layer away from the substrate structure by using a homoepitaxy process.

[0038] forming the second intrinsic layer on a side of the avalanche layer away from the absorption layer comprises: forming the second intrinsic layer on a side of the avalanche layer away from the absorption layer by using a homoepitaxy process.

[0039] Optionally, the manufacturing method further comprises, after forming the absorption layer and before forming the avalanche layer: forming a charge layer on a surface of the quantum well sensing layer, a projection of the charge layer in a plane parallel to a plane in which the absorption layer is located being located within a projection range of the first heavily doped region, and a preset distance between a projection boundary of the charge layer and a projection boundary of the first heavily doped region being greater than zero.

[0040] A manufacturing method of a sensor, the manufacturing method comprising the manufacturing method of the short-wave infrared focal plane array chip according to any one of the preceding embodiments.

[0041] Optionally, the method further comprises: thinning the substrate structure and removing at least part of the silicon substrate.

[0042] Compared with the prior art, the technical solution has the following advantages:

[0043] In the technical scheme provided by the embodiment of the present application, the avalanche layer includes an intrinsic germanium layer and a germanium-silicon layer, and the avalanche layer and the absorption layer satisfy the lattice matching condition, so that the lattices of the absorption layer and the avalanche layer are highly matched, the lattice mismatch between the absorption layer and the avalanche layer is reduced, the dark current, the dark count rate (DCR) and the avalanche breakdown voltage of the short-wave infrared focal plane array chip applied to a sensor are reduced, the single-photon detection efficiency, the sensitivity and the response speed of the sensor including the short-wave infrared focal plane array chip are improved, and the sensor can meet the commercial standards. BRIEF DESCRIPTION OF DRAWINGS

[0044] The above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals can refer to the same or similar elements. It should be understood that the drawings are schematic, and the original and elements are not necessarily drawn according to the scale.

[0045] Figure 1 A structure schematic diagram of a short-wave infrared focal plane array chip provided by the present application is provided.

[0046] Figure 2 A structure schematic diagram of a sensor provided by the present application is provided.

[0047] Figures 3-14 A structure schematic diagram of a short-wave infrared focal plane array chip provided by the present application is provided.

[0048] Figures 15-16 A structure schematic diagram of a sensor provided by the present application is provided. DETAILED DESCRIPTION

[0049] The embodiments in the present application will be described in detail below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0050] Various modifications and changes can be made to the present application without departing from the spirit or scope of the present application. It is obvious that the present application is intended to cover modifications and changes as long as they fall within the scope of the corresponding claims (the technical scheme to be protected) and their equivalents. It should be noted that the embodiments provided by the embodiments of the present application can be combined with each other without contradiction.

[0051] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0052] As described in the background section, the known Ge SPADs sensor cannot meet the commercial standards in terms of dark current, dark count rate (DCR), avalanche breakdown voltage, single-photon detection efficiency, sensitivity and response speed.

[0053] This is because the known Ge SPADs sensor is directly formed on a silicon substrate, and respectively uses germanium and silicon as a short-wave infrared sensing layer (i.e., an absorption layer) and an avalanche layer, and there is a large lattice mismatch defect at the germanium / silicon interface, so that there is a large lattice mismatch between the germanium absorption layer and the silicon avalanche layer in the entire device layer structure, resulting in that the known Ge SPADs sensor cannot meet the commercial standards in terms of dark current, dark count rate (DCR), avalanche breakdown voltage, single-photon detection efficiency, sensitivity and response speed. Therefore, under the current material and device structure limitations, it is urgent to solve the defect regulation problem of the germanium / silicon interface to improve the dark current, dark count rate (DCR), avalanche breakdown voltage, single-photon detection efficiency, sensitivity and response speed of the Ge SPADs device by suppressing the defect density in the device structure, and to lay a foundation for the development of the Ge-on-insulator SPADs sensor in the fields of automotive electronics, food safety detection and medical diagnosis.

[0054] In addition, in terms of light irradiation mode, the traditional Ge SPADs sensor usually adopts a front-irradiation mode, and the light utilization rate and photoelectric conversion rate are low, the image quality formed is poor, and there are many noise points. In a high-contrast scene, the front-irradiation type Ge SPADs sensor is prone to overexposure and underexposure, and has a narrow dynamic range.

[0055] Therefore, the present application provides a short-wave infrared focal plane array chip and a manufacturing method thereof, wherein the short-wave infrared focal plane array chip comprises at least one single-photon avalanche photodetector.

[0056] The short-wave infrared focal plane array chip provided by the present application comprises at least one single-photon avalanche photodetector. Optionally, the short-wave infrared focal plane array chip comprises a plurality of single-photon avalanche photodetectors, one single-photon avalanche photodetector corresponding to one pixel. Specifically, the plurality of single-photon avalanche photodetectors can be arranged in an array, but the present application does not limit this, and the specific arrangement is determined as appropriate.

[0057] Specifically, as shown in FIG. 1, the short-wave infrared focal plane array chip comprises a plurality of single-photon avalanche photodetectors 1, and each single-photon avalanche photodetector 1 corresponds to one pixel. Figure 1As shown, the short-wave infrared focal plane array chip provided by the embodiment of the present application comprises:

[0058] A substrate structure 10, the substrate structure 10 comprises a buried oxygen layer 11 and a first intrinsic layer 12 located on one side of the buried oxygen layer 11, and the first intrinsic layer 12 has a first heavily doped region 14 therein;

[0059] An absorption layer 20 located on the side of the first intrinsic layer 12 away from the buried oxygen layer 11, the absorption layer 20 comprises at least one germanium layer;

[0060] A second heavily doped region 23 penetrating through the absorption layer 20 and the first intrinsic layer 12, in the first intrinsic layer 12, the second heavily doped region 23 is in direct contact with the first heavily doped region 14, and the doping type of the second heavily doped region is the same as that of the first heavily doped region;

[0061] An avalanche layer 30 located on the side of the absorption layer 20 away from the substrate structure 10, the avalanche layer 30 comprises an intrinsic germanium layer and a germanium-silicon layer, and the avalanche layer 30 satisfies the lattice matching condition with the absorption layer 20;

[0062] A second intrinsic layer 40 located on the side of the avalanche layer 30 away from the absorption layer 20, and the second intrinsic layer 40 has a third heavily doped region 41 therein;

[0063] A reflection layer 50 located on the side of the second intrinsic layer 40 away from the avalanche layer 30;

[0064] A first via penetrating through the reflection layer 50, the second intrinsic layer 40 and the avalanche layer 30, the first via exposes part of the surface of a quantum well sensing layer 22 in the absorption layer 20 and the surface of the second heavily doped region 23 away from the buried oxygen layer 11, and the first via does not contact the third heavily doped region 41;

[0065] A passivation layer 60 is formed on the surface of the first via and the surface of the reflection layer 50, and the passivation layer 60 has a second via and a third via therein, the second via exposes at least part of the surface of the second heavily doped region 23, and the third via exposes at least part of the surface of the reflection layer 50;

[0066] A first electrode 71 electrically connected to the second heavily doped region 23 through the second via and a second electrode 72 electrically connected to the third heavily doped region 41 through the third via.

[0067] In the technical scheme provided in the embodiments of the present application, the avalanche layer includes an intrinsic germanium layer and a germanium-silicon layer, and the avalanche layer and the absorption layer satisfy the lattice matching condition, so that the lattices of the absorption layer and the avalanche layer are highly matched, the lattice mismatch between the absorption layer and the avalanche layer is reduced, the dark current, the dark count rate (DCR) and the avalanche breakdown voltage of the short-wave infrared focal plane array chip when applied to a sensor are reduced, the single-photon detection efficiency, the sensitivity and the response speed of the sensor including the short-wave infrared focal plane array chip are improved, and the sensor can meet the commercial standards.

[0068] Optionally, in an embodiment of the present application, the substrate structure further includes a silicon substrate 13 on the insulator away from the first intrinsic layer 12 side of the buried oxygen layer 11, but the present application is not limited thereto, and the specific substrate structure is determined according to the actual situation.

[0069] Optionally, in an embodiment of the present application, the silicon substrate is a silicon-on-insulator substrate, and the substrate structure is a GOI wafer, but the present application is not limited thereto, and in other embodiments of the present application, the substrate structure can also be a GOS (Germanium on Sapphire) wafer, a GOG (Germanium on Glass) wafer, a III-V-OI (III-V on Insulator) wafer, a III-V-OS (III-V on Sapphire) wafer, a III-V-OG (III-V on Glass) wafer, etc., and the present application is not limited thereto, and the specific substrate structure is determined according to the actual situation.

[0070] It should be noted that the GOI wafer is a germanium-on-insulator wafer, which is a relatively new technology, similar to the SOI, but a germanium layer is used on the insulating layer instead of a silicon layer; the GOS wafer refers to a sapphire-on-germanium wafer; the GOG wafer, i.e., the germanium-on-glass wafer, is an advanced semiconductor material, which is composed of an upper germanium (Ge) layer and a lower glass (Glass) layer; the III-V-OI wafer refers to a III-V compound semiconductor-on-insulator wafer, such as a gallium arsenide (GaAs) on insulator; the III-V-OS wafer refers to a III-V compound on sapphire wafer; and the III-V-OG wafer refers to a III-V compound on glass wafer.

[0071] Hereinafter, the short-wave infrared focal plane array chip provided in the embodiments of the present application will be described by taking the substrate structure as a GOI wafer as an example.

[0072] Optionally, in an embodiment of the present application, the thickness of the first intrinsic layer in the substrate structure is in the range of 100 nm to 500 nm; correspondingly, in this embodiment, the thickness of the first heavily doped region is in the range of 100 nm to 500 nm, but the present application does not limit this, which is determined according to the actual situation.

[0073] Specifically, in an embodiment of the present application, the first intrinsic layer can be an intrinsic germanium layer, or an intrinsic GaAs layer, an intrinsic AlAs layer, an intrinsic InGaAs layer, an intrinsic AlGaAs layer, or an intrinsic GeSi layer, and the present application does not limit this, as long as it is lattice-matched with germanium. It should be noted that when the first intrinsic layer is an intrinsic GeSi layer, the content of Si in the GeSi layer is less than 30%, so that the intrinsic GeSi layer is lattice-matched with germanium.

[0074] Optionally, in an embodiment of the present application, the absorption layer 20 includes a stacked sensing layer 21 and a quantum well sensing layer 22, wherein the sensing layer 21 is a germanium sensing layer, and the quantum well sensing layer 22 is a germanium / germanium-silicon quantum well sensing layer. It should be noted that in this embodiment, the quantum well sensing layer has a quantum effect, and better absorption and faster response speed can be achieved in a very small thickness. Therefore, in this embodiment, the absorption layer includes a stacked germanium sensing layer and a germanium / germanium-silicon quantum well sensing layer, which can achieve better absorption and faster response speed in a smaller thickness of the absorption layer, thereby enabling the short-wave infrared focal plane array chip to have a faster working speed and a smaller thickness.

[0075] In addition, in the embodiment of the present application, the absorption layer includes a germanium sensing layer and a germanium / germanium-silicon multi-quantum well sensing layer as a light sensing layer, which can improve the light absorption efficiency of the sensor including the short-wave infrared focal plane array chip at 1310 nm and 1550 nm wave bands by introducing a germanium / germanium-silicon multi-quantum well sensing layer.

[0076] In addition, when the first intrinsic layer is an intrinsic germanium layer, there is no germanium and silicon interface between the first intrinsic layer and the absorption layer, thereby removing the lattice mismatch defects existing between the substrate structure and the absorption layer, reducing the dark current, dark count rate (DCR) and avalanche breakdown voltage of the short-wave infrared focal plane array chip when applied to a sensor, and improving the single-photon detection efficiency, sensitivity and response speed of the sensor including the short-wave infrared focal plane array chip.

[0077] Optionally, in an embodiment of the present application, the content of germanium in the silicon germanium layer in the quantum well sensing layer ranges from 0 to 30%, so that the lattices of the silicon germanium layer and the germanium layer in the quantum well sensing layer are matched, thereby forming a high-quality quantum well sensing layer.

[0078] In another embodiment of the present application, the absorption layer 20 can also only include the sensing layer 21 or the quantum well sensing layer 22, which is not limited in the present application and is determined according to specific conditions.

[0079] Specifically, in an embodiment of the present application, the thickness of the absorption layer ranges from 500 nm to 3000 nm, but the present application is not limited thereto and is determined according to specific conditions.

[0080] On the basis of any of the above embodiments, in an embodiment of the present application, as shown in Figure 1 The second heavily doped region 23 includes a first sub-heavily doped region 231 and a second sub-heavily doped region 232, and the first sub-heavily doped region 231 and the second sub-heavily doped region 232 are located on the opposite sides of the first heavily doped region 14, so that the first heavily doped region 14 and the second heavily doped region 23 form a U-shaped structure.

[0081] Taking the first heavily doped region as a P-type heavily doped region as an example, the first heavily doped region and the second heavily doped region form a U-shaped structure, which can increase the contact area of the absorption layer and the P-type heavily doped region, reduce the contact resistance of the first electrode to a certain extent, form a good ohmic contact between the germanium sensing layer and the P-type heavily doped region, and improve the single-photon detection efficiency of SPADs in the short-wave infrared focal plane array chip; the second heavily doped region can be used as an optical and electrical crosstalk blocking layer between adjacent pixels, which can isolate adjacent pixels, thereby reducing the dark current and dark count rate of the short-wave infrared focal plane array chip, easily forming a low-crosstalk short-wave infrared focal plane array chip without sacrificing resolution.

[0082] Specifically, in an embodiment of the present application, the thickness of the second heavily doped region ranges from 500 nm to 3000 nm, but the present application is not limited thereto and is determined according to specific conditions.

[0083] In an embodiment of the present application, the avalanche layer comprises at least one of intrinsic germanium / germanium-silicon multi-quantum well layer and intrinsic germanium / germanium-silicon superlattice layer. Specifically, the avalanche layer can be intrinsic germanium / germanium-silicon multi-quantum well layer, intrinsic germanium / germanium-silicon superlattice layer, intrinsic germanium / germanium-silicon multi-quantum well layer and intrinsic germanium layer, intrinsic germanium / germanium-silicon superlattice layer and intrinsic germanium layer, or intrinsic germanium / germanium-silicon multi-quantum well layer, intrinsic germanium / germanium-silicon superlattice layer and intrinsic germanium layer. The present application does not limit the arrangement order of the layers.

[0084] It should be noted that in the above embodiment, if the avalanche layer is intrinsic germanium / germanium-silicon multi-quantum well layer or intrinsic germanium / germanium-silicon superlattice layer, the avalanche layer is a periodic structure of intrinsic germanium layer and germanium-silicon layer; if the avalanche layer comprises at least two of intrinsic germanium / germanium-silicon multi-quantum well layer, intrinsic germanium / germanium-silicon superlattice layer and intrinsic germanium layer, the avalanche layer is a non-periodic structure of intrinsic germanium layer and germanium-silicon layer.

[0085] In the periodic structure of intrinsic germanium layer and germanium-silicon layer, the intrinsic germanium layer and the germanium-silicon layer are staggered, and each intrinsic germanium layer has the same thickness and other parameters, and each germanium-silicon layer has the same thickness and other parameters. In the non-periodic structure of intrinsic germanium layer and germanium-silicon layer, the intrinsic germanium layer and the germanium-silicon layer are staggered, but at least one parameter of different intrinsic germanium layers is different, such as thickness, at least one parameter of different germanium-silicon layers is different, such as thickness, or doping concentration is different, etc.

[0086] In the present embodiment, the avalanche layer adopts the combined structure of germanium layer and germanium-silicon layer, which can make the avalanche layer have a higher ionization coefficient compared to the avalanche layer made of germanium material only. In addition, in the present embodiment, the avalanche layer adopts the germanium / germanium-silicon multi-layer structure, which can significantly improve the avalanche gain of the avalanche layer, greatly reduce the operating voltage of the short-wave infrared focal plane array chip, avoid introducing a large amount of excess noise (reducing avalanche noise) when the short-wave infrared focal plane array chip is working, thereby reducing the dark current (including but not limited to surface leakage current and tunneling current, etc.) of the short-wave infrared focal plane array chip, and reducing the dark count rate of the short-wave infrared focal plane array chip.

[0087] Specifically, in one embodiment of the present application, the content of germanium in the germanium-silicon layer is 0-30% in the avalanche layer, so that the lattice of the germanium-silicon layer and the germanium layer in the avalanche layer is well matched, thereby forming a high-quality intrinsic germanium / germanium-silicon multi-avalanche layer structure.

[0088] Optionally, in one embodiment of the present application, the thickness of the avalanche layer is 200-1000 nm, but the present application is not limited thereto, and the thickness can be determined according to the actual situation.

[0089] It should be noted that, compared with the use of a germanium layer in the absorption layer, the use of a silicon layer in the avalanche layer, the use of a stacked germanium sensing layer and a germanium / germanium-silicon quantum well sensing layer structure in the absorption layer, and the use of an intrinsic germanium layer and a germanium-silicon layer in the avalanche layer in the present embodiment can make the lattices of the absorption layer and the avalanche layer highly matched, reduce the lattice mismatch between the absorption layer and the avalanche layer, reduce the dark current, dark count rate (DCR) and avalanche breakdown voltage of the short-wave infrared focal plane array chip when applied to a sensor, and improve the single-photon detection efficiency, sensitivity and response speed of the sensor including the short-wave infrared focal plane array chip.

[0090] Optionally, in one embodiment of the present application, the thickness of the absorption layer is at least 1.5 times the thickness of the avalanche layer, or the thickness of the avalanche layer is at most two-thirds of the thickness of the absorption layer, so that the short-wave infrared focal plane array chip provided in the present embodiment has both the small geometric size advantage of the avalanche layer and the large geometric size advantage of the absorption layer.

[0091] It should be noted that the geometric size of the avalanche layer is a core parameter affecting the performance of the short-wave infrared focal plane array chip. The larger the thickness and size of the avalanche layer, the larger the electric field (reverse breakdown voltage) required to reach avalanche breakdown. However, when the electric field (reverse breakdown voltage) is too large, a large amount of tunneling current will be generated, followed by a large amount of avalanche noise. Therefore, a thinner and smaller avalanche layer helps to suppress the generation of tunneling current and avalanche noise. In the present application, the size of the avalanche layer also determines the size of the pixel (i.e. the pixel size) of the short-wave infrared focal plane array chip. The smaller the pixel, the higher the resolution of the image sensor. At the same time, the small geometric size of the avalanche layer reduces the capacitance of the avalanche layer in the short-wave infrared focal plane array chip, and improves the sensitivity and response speed of the short-wave infrared focal plane array chip.

[0092] In addition, increasing the size of the absorption layer can effectively increase the interaction area between light and the absorption layer, increase the probability of generating electron-hole pairs by photons, and effectively improve the single-photon detection efficiency of the short-wave infrared focal plane array chip.

[0093] Therefore, the short-wave infrared focal plane array chip provided by the embodiments of the present application can improve the single-photon detection efficiency of the short-wave infrared focal plane array chip by simply increasing the size of the light absorption layer without introducing avalanche noise, changing the pixel size (resolution), sensitivity and response speed. On the contrary, without affecting the single-photon detection efficiency of the short-wave infrared focal plane array chip, the generation of tunneling current and avalanche noise is suppressed by reducing the size of the avalanche layer, the resolution of the short-wave infrared focal plane array chip is improved, the capacitance of the avalanche layer in the short-wave infrared focal plane array chip is reduced, and the sensitivity and response speed of the short-wave infrared focal plane array chip are improved.

[0094] On the basis of any of the above embodiments, in an embodiment of the present application, the short-wave infrared focal plane array chip further comprises: a charge layer 24 located in the surface of the quantum well sensing layer, in a plane parallel to the plane where the absorption layer 20 is located, the projection of the charge layer 24 is located within the projection range of the first heavily doped region 14, and there is a preset distance between the projection boundary of the charge layer 24 and the projection boundary of the first heavily doped region 14, the preset distance is greater than zero. Specifically, the charge layer 24 can be a germanium-silicon charge layer, a germanium charge layer, or a germanium / germanium-silicon quantum well charge layer.

[0095] It should be noted that in the present embodiment, the charge layer can reduce the electric field of the absorption layer, increase the electric field of the avalanche layer, ensure that a certain potential difference is formed between the absorption layer and the avalanche layer, so that the light absorption layer and the avalanche layer can independently complete their respective tasks. In other words, it is hoped that the avalanche layer is in a high electric field region and the absorption layer is in a low electric field region, so that the performance of the single-photon avalanche photodetector in the short-wave infrared focal plane array chip can be improved at the same time.

[0096] It should be noted that since the charge layer 24 is a germanium-silicon charge layer, a germanium charge layer or a germanium / germanium-silicon quantum well charge layer, the lattice of the charge layer and the germanium sensing layer in the absorption layer is also highly matched, thereby further reducing the dark current, dark count rate (DCR) and avalanche breakdown voltage of the short-wave infrared focal plane array chip when applied to a sensor, and improving the single-photon detection efficiency, sensitivity and response speed of the sensor including the short-wave infrared focal plane array chip.

[0097] Optionally, in an embodiment of the present application, the thickness of the charge layer is 100 nm, but the present application does not limit this, and the specific thickness is determined according to the situation.

[0098] It can be seen from the above that, in the short-wave infrared focal plane array chip provided by the embodiment of the present application, the lattice mismatch defects existing between the germanium and the silicon interface are removed between the substrate structure and the absorption layer, the lattice of the avalanche layer and the absorption layer, the charge layer and the germanium-based sensing layer is highly matched, the entire device layer structure has small lattice mismatch and thermal mismatch, the hetero-material interface quality is good, and excellent electrical performance is achieved, thereby reducing the dark current, dark current, dark count rate and avalanche breakdown voltage of the sensor including the short-wave infrared focal plane array chip.

[0099] On the basis of any of the above embodiments, in an embodiment of the present application, the second intrinsic layer 40 is the same material as the first intrinsic layer 12, such as both being intrinsic germanium layers, but the present application does not make a limitation in this regard, and the specific conditions are determined as appropriate.

[0100] Optionally, in an embodiment of the present application, the thickness of the second intrinsic layer is in the range of 100 nm to 500 nm, and the thickness of the third heavily doped region is in the range of 100 nm to 500 nm, but the present application does not make a limitation in this regard, and the specific conditions are determined as appropriate.

[0101] Specifically, in an embodiment of the present application, the first heavily doped region is a P-type heavily doped region, the second heavily doped region is a P-type heavily doped region, the first electrode is a P electrode, the third heavily doped region is an N-type heavily doped region, and the second electrode is an N electrode; in another embodiment of the present application, the first heavily doped region is an N-type heavily doped region, the second heavily doped region is an N-type heavily doped region, the first electrode is an N electrode, the third heavily doped region is a P-type heavily doped region, and the second electrode is a P electrode.

[0102] It should be noted that, in any of the above embodiments, the reflective layer 50 can form a vertical resonant cavity with the buried oxygen layer 11 to enhance the interaction between light and the absorption layer. Optionally, the reflective film layer can be a periodic or non-periodic stacking structure of two of SiO2 layers, SiNx layers and other high-K dielectric layers. Taking the reflective layer as an example of a periodic or non-periodic stacking structure of SiO2 layers and SiNx layers, the periodic structure of SiO2 layers and SiNx layers means that the SiO2 layers and SiNx layers are arranged alternately, and each parameter of each SiO2 layer is the same, and each parameter of each SiNx layer is the same, and the non-periodic structure of SiO2 layers and SiNx layers means that the SiO2 layers and SiNx layers are arranged alternately, but at least one parameter of different SiO2 layers is different, and at least one parameter of different SiNx layers is different.

[0103] Optionally, in an embodiment of the present application, the thickness of the reflective layer is in the range of 10 nm to 200 nm, but the present application does not make a limitation in this regard, and the specific conditions are determined as appropriate.

[0104] Correspondingly, the application also provides a sensor comprising the short-wave infrared focal plane array chip provided by any of the above embodiments. Since the structure of the short-wave infrared focal plane array chip has been described in the above embodiments, it will not be repeated here.

[0105] Optionally, in an embodiment of the application, as shown in Figure 2 the sensor further comprises a readout circuit 80 electrically connected to the first electrode 71 and the second electrode 72 in the short-wave infrared focal plane array chip, and the readout circuit 80 is configured to convert the analog signals output by the first electrode 71 and the second electrode 72 into digital signals for subsequent signal processing and analysis. Specifically, in an embodiment of the application, the readout circuit is bonded to the first electrode and the second electrode through In bumps or Cu bumps, but the application is not limited thereto, and the specific bonding method can be determined as appropriate.

[0106] The short-wave infrared focal plane array chip provided by the application adopts a backside incidence structure, and light can directly pass through the silicon substrate and the buried oxygen layer (or called the oxide layer) into the absorption layer without passing through the N-type electrode layer and the P-type electrode layer, thereby avoiding the phenomenon of light absorption or reflection by the metal electrode, promoting the light to enter each pixel more effectively, improving the utilization rate of light, and thus greatly improving the image quality. Higher light utilization rate means that under the same conditions, the backside incidence sensor (including the sensor comprising the short-wave infrared focal plane array chip) can provide higher sensitivity, larger dynamic range, higher signal-to-noise ratio, and clearer image (i.e. fewer noise points) under low light conditions.

[0107] In addition, the short-wave infrared focal plane array chip provided by the application is of a backside incidence structure, which avoids the attenuation, scattering and interference that may be introduced when light passes through the metal electrode layer and other functional layers of devices, and reduces the optical cross-influence between different pixels. Therefore, it allows a tighter and smaller pixel layout (i.e. more circuits can be arranged, and smaller pixel size can be used, so that the distance between pixels is smaller) in the same area.

[0108] Therefore, when the sensor provided in the embodiments of the present application works, backside incident light is adopted, the light is irradiated onto the photosensitive element (absorption layer and avalanche layer) from the back side, so that the light can enter each pixel more effectively, the light utilization rate is improved, and thus the image quality is greatly improved. Moreover, the sensor provided in the embodiments of the present application can accommodate more circuits, and can adopt smaller pixel size, so that the distance between pixels is smaller, the photoelectric conversion rate is higher, and the noise is less. In addition, the sensor provided in the embodiments of the present application adopts a shallow island process (i.e., the first via only penetrates the reflection layer, the second intrinsic layer and the avalanche layer, and does not penetrate the absorption layer), divides the image into multiple regions with different exposure degrees, and can obtain a good dynamic range by synthesizing the images of different regions.

[0109] In addition, the embodiments of the present application further provide a manufacturing method of a short-wave infrared focal plane array chip, which is used for manufacturing the short-wave infrared focal plane array chip provided in any of the above embodiments. Specifically, the manufacturing method of the short-wave infrared focal plane array chip provided in the embodiments of the present application comprises:

[0110] S1: manufacturing a substrate structure 10, as shown in Figure 3 and Figure 4 The substrate structure 10 comprises a silicon substrate 13, a buried oxygen layer 11 located on the surface of the silicon substrate 13, and a first intrinsic layer 12 located on the side of the buried oxygen layer 11 away from the silicon substrate 13, as shown in Figure 4 The first intrinsic layer 12 has a first heavily doped region 14 therein.

[0111] Specifically, in one embodiment of the present application, manufacturing the substrate structure comprises:

[0112] As shown in Figure 3 manufacturing the substrate structure 10, the substrate structure 10 comprises a silicon substrate 13, a buried oxygen layer 11 located on the surface of the silicon substrate 13, and a first intrinsic layer 12 located on the side of the buried oxygen layer 11 away from the silicon substrate 13;

[0113] As shown in Figure 4 forming a first heavily doped region 14 in the first intrinsic layer 12. It should be noted that the first heavily doped region is used for electrical connection with the first electrode to be formed subsequently. Optionally, in one embodiment of the present application, the first heavily doped region is formed in the first intrinsic layer by ion implantation. Specifically, in one embodiment of the present application, the first heavily doped region is a first P-type heavily doped region, and the first electrode is a P electrode; in another embodiment of the present application, the first heavily doped region is a first N-type heavily doped region, and the first electrode is an N electrode, and the present application does not limit this, which is determined according to the specific situation.

[0114] Optionally, in an embodiment of the present application, the silicon substrate is a silicon-on-insulator substrate, and the substrate structure is a GOI wafer, but the present application is not limited thereto, and in other embodiments of the present application, the substrate structure can also be a GOS (Germanium on Sapphire) wafer, a GOG (Germanium on Glass) wafer, a III-V-OI (III-V on Insulator) wafer, a III-V-OS (III-V on Sapphire) wafer, a III-V-OG (III-V on Glass) wafer, etc., and the present application is not limited thereto, and the specific substrate structure can be determined as appropriate.

[0115] The manufacturing method provided by the embodiments of the present application will be described below by taking the substrate structure as a GOI wafer as an example.

[0116] Specifically, in an embodiment of the present application, the substrate structure can be a commercially available GOI wafer, and the manufacturing method thereof can be various, including but not limited to a GOI wafer formed by smart-cut, wafer-bonding and condensation.

[0117] Optionally, in an embodiment of the present application, the thickness of the first intrinsic layer in the substrate structure is in a range of 100 nm to 500 nm; and correspondingly, in the embodiment, the thickness of the first heavily doped region is in a range of 100 nm to 500 nm, but the present application is not limited thereto, and the specific thickness can be determined as appropriate.

[0118] On the basis of any of the above embodiments, in an embodiment of the present application, the first intrinsic layer can be an intrinsic germanium layer, or an intrinsic GaAs layer, an intrinsic AlAs layer, an intrinsic InGaAs layer, an intrinsic AlGaAs layer or an intrinsic GeSi layer, and the present application is not limited thereto, as long as it is lattice-matched with germanium. It should be noted that when the first intrinsic layer is an intrinsic GeSi layer, the content of Si in the GeSi layer is less than 30%, so that the intrinsic GeSi layer is lattice-matched with germanium.

[0119] S2: as shown in FIG. 2, an absorption layer 20 is formed on the side of the first intrinsic layer 12 away from the buried oxygen layer 11, and the absorption layer 20 comprises at least one germanium layer. Figure 5

[0120] ​Optionally, in an embodiment of the present application, the absorption layer 20 comprises a stacked sensing layer 21 and quantum well sensing layer 22, wherein the sensing layer 21 is a germanium sensing layer, and the quantum well sensing layer 22 is a germanium / germanium-silicon quantum well sensing layer. It should be noted that, in the embodiment, the quantum well sensing layer has quantum effect, and better absorption and faster response speed can be achieved in a small thickness. Therefore, in the embodiment, the absorption layer comprises a stacked germanium sensing layer and germanium / germanium-silicon quantum well sensing layer, and better absorption and faster response speed can be achieved in a small thickness of the absorption layer, so that the short-wave infrared focal plane array chip has faster working speed and smaller thickness.

[0121] In addition, in the embodiment of the present application, the absorption layer comprises a germanium sensing layer and a germanium / germanium-silicon multi-quantum well sensing layer as a light sensing layer, and the light absorption efficiency of the sensor comprising the short-wave infrared focal plane array chip in the 1310 nm band and the 1550 nm band can be improved by introducing the germanium / germanium-silicon multi-quantum well sensing layer.

[0122] Optionally, in an embodiment of the present application, the content of germanium in the germanium-silicon layer in the quantum well sensing layer ranges from 0 to 30%, so that the lattices of the germanium-silicon layer and the germanium layer in the quantum well sensing layer are well matched, thereby forming a high-quality quantum well sensing layer.

[0123] In another embodiment of the present application, the absorption layer 20 can also only comprise the sensing layer 21 or the quantum well sensing layer 22, which is not limited in the present application and can be determined as appropriate.

[0124] Specifically, in an embodiment of the present application, the forming process of the absorption layer can be a homoepitaxy process, which can be MBE (Molecular Beam Epitaxy), UHV-CVD (Ultra-High Vacuum Chemical Vapor Deposition), RPCVD (Reduced Pressure Chemical Vapor Deposition), or the like. The absorption layer is formed on the side of the first intrinsic layer away from the buried oxygen layer by using the homoepitaxy process, so that the crystal quality of the germanium sensing layer and the germanium / germanium-silicon quantum well sensing layer is very high. However, the present application is not limited thereto and can be determined as appropriate.

[0125] Optionally, in one embodiment of the present application, the thickness of the absorption layer ranges from 500 nm to 3000 nm, but the present application does not limit this and it depends on the specific circumstances.

[0126] S3: If Figure 6 As shown, a second heavily doped region 23 is formed that penetrates the absorption layer 20 and the first intrinsic layer 12. Within the first intrinsic layer 12, the second heavily doped region 23 is in direct contact with the first heavily doped region 14, so that the electrode contact end of the first heavily doped region 14 can be led out through the second heavily doped region 23, thereby facilitating the subsequent electrical connection between the first electrode and the first heavily doped region. Specifically, the first electrode is electrically connected to the first heavily doped region through the second heavily doped region. Optionally, in one embodiment of the present application, ion implantation is used to form the second heavily doped region that penetrates the absorption layer and the first intrinsic layer, but this application is not limited to this and the specific circumstances may vary.

[0127] Optionally, in one embodiment of the present application, continue as Figure 6 As shown, the second heavily doped region 23 includes a first sub-heavily doped region 231 and a second sub-heavily doped region 232. The first sub-heavily doped region 231 and the second sub-heavily doped region 232 are located on opposite sides of the first heavily doped region 14, so that the first heavily doped region 14 and the second heavily doped region 23 are U-shaped structures.

[0128] Specifically, in one embodiment of the present application, the thickness of the second heavily doped region ranges from 500 nm to 3000 nm, but the present application does not impose any limitation thereto, and the thickness depends on the specific circumstances.

[0129] S4: As Figure 7 As shown, an avalanche layer 30 is formed on the side of the absorption layer 20 away from the substrate structure 10. The avalanche layer 30 is an intrinsic germanium / germanium silicon multi-avalanche layer structure, and the avalanche layer 30 and the absorption layer 20 meet the lattice matching condition. Specifically, the avalanche layer can be an intrinsic germanium / germanium silicon multi-quantum well layer, an intrinsic germanium / germanium silicon superlattice layer, a stacked structure of an intrinsic germanium / germanium silicon multi-quantum well layer and an intrinsic germanium layer, a stacked structure of an intrinsic germanium / germanium silicon superlattice layer and an intrinsic germanium layer, or a stacked structure of an intrinsic germanium / germanium silicon multi-quantum well layer, an intrinsic germanium / germanium silicon superlattice layer and an intrinsic germanium layer. This application does not limit this, and the specific configuration depends on the specific situation. It should be noted that when the avalanche layer is a stacked structure of an intrinsic germanium / germanium silicon multi-quantum well layer and an intrinsic germanium layer, or a stacked structure of an intrinsic germanium / germanium silicon superlattice layer and an intrinsic germanium layer, or a stacked structure of an intrinsic germanium / germanium silicon multi-quantum well layer, an intrinsic germanium / germanium silicon superlattice layer and an intrinsic germanium layer, the present application does not limit the arrangement order in the stacked structure.

[0130] It should be noted that in the above embodiment, if the avalanche layer is the intrinsic germanium / germanium-silicon multi-quantum well layer or the intrinsic germanium / germanium-silicon superlattice layer, the avalanche layer is a periodic structure of the intrinsic germanium layer and the germanium-silicon layer; if the avalanche layer includes at least two of the intrinsic germanium / germanium-silicon multi-quantum well layer, the intrinsic germanium / germanium-silicon superlattice layer, and the intrinsic germanium layer, the avalanche layer is a non-periodic structure of the intrinsic germanium layer and the germanium-silicon layer.

[0131] In the embodiment, the avalanche layer adopts the combined structure of the germanium layer and the germanium-silicon layer, which can make the avalanche layer have a higher ionization coefficient compared with the avalanche layer made of germanium material only. In addition, in the embodiment, the avalanche layer adopts the germanium / germanium-silicon multi-layer structure, which can significantly improve the avalanche gain of the avalanche layer, greatly reduce the operating voltage of the short-wave infrared focal plane array chip, avoid introducing a large amount of excess noise (reducing avalanche noise) when the short-wave infrared focal plane array chip is working, thereby reducing the dark current (including but not limited to surface leakage current and tunneling current, etc.) of the short-wave infrared focal plane array chip, and reducing the dark count rate of the short-wave infrared focal plane array chip.

[0132] Optionally, in an embodiment of the present application, the forming process of the avalanche layer can be a homoepitaxy process, specifically MBE, UHV-CVD or RPCVD, etc., so that the crystal quality of the avalanche layer is very high by forming the avalanche layer on the side of the absorption layer away from the substrate structure through the homoepitaxy process. However, the present application is not limited thereto, and the specific method is determined according to the situation.

[0133] Specifically, in an embodiment of the present application, in the avalanche layer, the content of germanium in the germanium-silicon layer is 0-30%, so that the lattice of the germanium-silicon layer and the germanium layer in the avalanche layer is matched, thereby forming a high-quality intrinsic germanium / germanium-silicon multi-avalanche layer structure.

[0134] Optionally, in an embodiment of the present application, the thickness of the avalanche layer is 200 nm-1000 nm, but the present application is not limited thereto, and the specific method is determined according to the situation.

[0135] On the basis of the above embodiment, in an embodiment of the present application, as Figure 8As shown, the manufacturing method further includes forming a charge layer 24 on the surface of the quantum well sensing layer 22 after forming the absorption layer and before forming the avalanche layer. In a plane parallel to the absorption layer 20, the projection of the charge layer 24 is located within the projection range of the first heavily doped region 14, and there is a preset distance between the projection boundary of the charge layer 24 and the projection boundary of the first heavily doped region 14, and the preset distance is greater than zero. Specifically, the charge layer 24 can be a germanium silicon charge layer or a germanium charge layer, so as to prevent the carriers generated by the avalanche layer 30 from entering the absorption layer 20 in large quantities during the avalanche process of the avalanche layer 30.

[0136] Optionally, in one embodiment of the present application, the charge layer is formed by ion implantation, and the thickness of the charge layer is 100 nm, but the present application does not limit this, and the specific thickness depends on the circumstances.

[0137] S5: If Figure 9 As shown, a second intrinsic layer 40 is formed on the side of the avalanche layer 30 away from the absorption layer 20, as shown in FIG. Figure 10 As shown, a third heavily doped region 41 is defined in the second intrinsic layer 40 .

[0138] Specifically, in one embodiment of the present application, a second intrinsic layer 40 is formed on a side of the avalanche layer 30 away from the absorption layer 20 , and the second intrinsic layer 40 has a third heavily doped region 41 including:

[0139] like Figure 9 As shown, a second intrinsic layer 40 is formed on the side of the avalanche layer 30 away from the absorption layer 20. Optionally, the second intrinsic layer 40 is made of the same material as the first intrinsic layer 12, such as an intrinsic germanium layer. Specifically, the second intrinsic layer 40 is formed by a homoepitaxial process, such as MBE, UHV-CVD, or RPCVD. By using a homoepitaxial process to form the second intrinsic layer 40 on the side of the avalanche layer 30 away from the absorption layer 20, the crystal quality of the second intrinsic layer 40 is very high. However, this application is not limited to this, and the specific process depends on the specific situation.

[0140] like Figure 10 As shown, a third heavily doped region 41 is formed in the second intrinsic layer 40, and the third heavily doped region 41 is used to be electrically connected to the second electrode formed subsequently. Optionally, in one embodiment of the present application, a third heavily doped region is formed in the second intrinsic layer by ion implantation. Specifically, if the first heavily doped region is a P-type heavily doped region, the third heavily doped region is an N-type heavily doped region, and the second electrode is an N-electrode; if the first heavily doped region is an N-type heavily doped region, the third heavily doped region is a P-type heavily doped region, and the second electrode is a P-electrode.

[0141] Optionally, in one embodiment of the present application, the thickness of the second intrinsic layer ranges from 100nm to 500nm, and the thickness of the third heavily doped region ranges from 100nm to 500nm, but the present application does not limit this and it depends on the specific situation.

[0142] It should be noted that in the short-wave infrared focal plane array chip manufacturing method provided in the embodiment of the present application, the absorption layer, the avalanche layer, and the second intrinsic layer are all formed by homogeneous epitaxy, so that the absorption layer, the avalanche layer, and the second intrinsic layer are all in a lattice matching state. The crystal quality of the epitaxial layer is extremely high, so that the sensor including the short-wave infrared focal plane array chip has the characteristics of low dark current and dark count rate.

[0143] S6: As Figure 11 As shown, a reflective film layer 50 is formed on the side of the second intrinsic layer 40 away from the avalanche layer 30, so that the reflective layer 50 can form a vertical resonant cavity with the buried oxide layer 11 to enhance the interaction between light and the absorption layer. Optionally, the reflective film layer can be a SiO2 layer, SiN x Alternatively, in one embodiment of the present application, the thickness of the reflective layer ranges from 10 nm to 200 nm, but the present application does not limit this, and the specific thickness depends on the circumstances.

[0144] S7: As Figure 12 As shown, a first through hole is formed through the reflective layer 50, the second intrinsic layer 40 and the avalanche layer 30, and the first through hole exposes a portion of the surface of the quantum well sensing layer 22 in the absorption layer and the surface of the second heavily doped region 23 away from the buried oxide layer 11, and the first through hole does not contact the third heavily doped region 41.

[0145] S8: Continue as Figure 12 As shown, a passivation layer 60 is formed on the surface of the first through hole and the surface of the reflective layer 50, as shown in FIG. Figure 13 As shown, a second through hole and a third through hole are formed in the portion of the passivation layer 60 covering the surface of the second heavily doped region 23, wherein the second through hole exposes at least a portion of the surface of the second heavily doped region 23, and the third through hole exposes at least a portion of the surface of the reflective layer 50;

[0146] S9: As Figure 14As shown, the first electrode 71 is formed in the region where the second through hole is located, and the second electrode 72 is formed in the region where the third through hole is located, wherein the first electrode 71 fills the second through hole and is electrically connected with the second heavily doped region 23, thereby realizing electrical connection with the first heavily doped region 14, and the second electrode 72 fills the third through hole and is electrically connected with the reflective layer 50, thereby realizing electrical connection with the third heavily doped region 41.

[0147] Correspondingly, the application also provides a manufacturing method of a sensor, which comprises the manufacturing method of the short-wave infrared focal plane array chip provided in any of the above embodiments. Since the manufacturing method of the short-wave infrared focal plane array chip has been described in the above embodiments, no further description is given here.

[0148] Optionally, in an embodiment of the application, as shown in the figure, the method further comprises: bonding a readout integrated circuit (ROIC) 80 on the short-wave infrared focal plane array chip, wherein the readout integrated circuit 80 is electrically connected with the first electrode 71 and the second electrode 72 in the short-wave infrared focal plane array chip, and is used to convert the analog signals output by the first electrode 71 and the second electrode 72 into digital signals for subsequent signal processing and analysis. Figure 15 Specifically, in an embodiment of the application, the readout integrated circuit is bonded with the first electrode and the second electrode through In bumps or Cu bumps, but the application does not make any limitation in this regard, which is subject to change as the case may be.

[0149] Specifically, in an embodiment of the application, the readout integrated circuit is bonded with the first electrode and the second electrode in the short-wave infrared focal plane array chip through In bump bonding or Cu bump bonding by using flip-chip technology, but the application does not make any limitation in this regard, which is subject to change as the case may be.

[0150] In addition, since the buried oxygen layer and the first intrinsic layer in the substrate structure do not block infrared signals, and the silicon substrate has a certain blocking effect on infrared signals, in an embodiment of the application, as shown in the figure, the method further comprises: Figure 16 back thinning the substrate structure to remove at least part of the silicon substrate in the substrate structure, so that when the infrared light signal of the sensor enters from the back of the sensor, the blocking effect of the silicon substrate on the infrared light signal is reduced.

[0151] Optionally, in an embodiment of the application, back thinning the substrate structure to remove at least part of the silicon substrate in the substrate structure can remove part of the silicon substrate or remove all of the silicon substrate, and the application does not make any limitation in this regard, which is subject to change as the case may be.

[0152] It should be noted that in the embodiment, the back thinning step of the substrate structure is performed after the readout circuit is bonded on the short-wave infrared focal plane array chip, so that the bonding process is not affected by the too thin thickness of the short-wave infrared focal plane array chip.

[0153] As can be seen from the above, the manufacturing method of the short-wave infrared focal plane array chip and the manufacturing method of the sensor provided in the embodiments of the present application have simple construction, are easy to implement in the process flow, are highly compatible with the standard CMOS manufacturing process, and are easy to mass produce.

[0154] Moreover, the sensor manufactured by the sensor manufacturing method provided in the embodiments of the present application has a backside incidence structure, and light can directly pass through the silicon substrate and the buried oxygen layer (or the oxide layer) to enter the absorption layer without passing through the N-type electrode layer and the P-type electrode layer, thereby avoiding the phenomenon of light absorption or reflection by the metal electrode, promoting the light to enter each pixel more effectively, improving the light utilization rate, and greatly improving the image quality. Higher light utilization rate means that the backside incidence sensor (including the short-wave infrared focal plane array chip sensor) can provide higher sensitivity, a larger dynamic range, a higher signal-to-noise ratio, and a clearer image (i.e., fewer noise points) under low light conditions under the same conditions.

[0155] In addition, the sensor manufactured by the sensor manufacturing method provided in the embodiments of the present application has a backside incidence structure, thereby avoiding the attenuation, scattering, and interference that may be introduced when light passes through the metal electrode layer and other functional layers of the device, and reducing the optical cross-influence between different pixels. Therefore, a more compact and smaller pixel layout (i.e., more circuits can be arranged, and a smaller pixel size can be used, so that the distance between pixels is smaller) is allowed in the same area.

[0156] Therefore, the sensor manufactured by the sensor manufacturing method provided in the embodiments of the present application irradiates light onto the photosensitive element (absorption layer and avalanche layer) from the back side, so that the light can enter each pixel more effectively, improves the light utilization rate, and greatly improves the image quality. Moreover, the sensor manufactured by the sensor manufacturing method provided in the embodiments of the present application can arrange more circuits, can use a smaller pixel size, so that the distance between pixels is smaller, the photoelectric conversion rate is higher, and the noise points are fewer. In addition, the sensor manufactured by the sensor manufacturing method provided in the embodiments of the present application uses the shallow island process to divide the image into multiple regions with different exposure degrees, and a good dynamic range can be obtained by synthesizing the images of different regions.

[0157] In summary, the short-wave infrared focal plane array chip and the manufacturing method thereof provided by the embodiments of the present application, including the sensor of the short-wave infrared focal plane array chip and the manufacturing method thereof, help to promote the rapid development of low-cost LiDAR chips (LiDAR chips are core components of a laser radar system, and are used to realize high-precision ranging and three-dimensional modeling functions) and high-speed optical communication chips, and have great research significance and economic benefits.

[0158] The various embodiments in the specification are described in a progressive, or parallel, or progressive and parallel combination manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0159] It should be noted that in the description of the present application, it should be understood that the drawings and the description of the embodiments are illustrative but not limiting. The same reference numerals in the embodiments throughout the specification indicate the same structure. In addition, for the purpose of understanding and ease of description, the thickness of some layers, films, panels, regions and the like in the drawings may be exaggerated. It can be understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element can be directly on the other element or there can be an intermediate element. In addition, "on" means positioning an element on another element or below another element, but essentially does not mean positioning on the upper side of another element according to the direction of gravity.

[0160] The terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0161] It is also noted that the relational terms herein, such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a vesicle or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such vesicle or apparatus. An element proceeded by "comprises a... " does not, without more constraints, preclude the existence of additional identical elements in the vesicle or apparatus that comprises the recited element.

[0162] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A shortwave infrared focal plane array chip, characterized in that: The short-wave infrared focal plane array chip comprises at least one single-photon avalanche photodetector, wherein the short-wave infrared focal plane array chip comprises: A substrate structure comprising a buried oxide layer and a first intrinsic layer located on one side of the buried oxide layer, wherein the first intrinsic layer has a first heavily doped region; an absorption layer located on a side of the first intrinsic layer away from the buried oxide layer, the absorption layer comprising at least one germanium layer; a second heavily doped region penetrating the absorption layer and the first intrinsic layer, wherein the second heavily doped region is in direct contact with the first heavily doped region in the first intrinsic layer; an avalanche layer located on a side of the absorption layer away from the substrate structure, the avalanche layer comprising an intrinsic germanium layer and a germanium silicon layer, and the avalanche layer and the absorption layer satisfy a lattice matching condition; a second intrinsic layer located on a side of the avalanche layer away from the absorption layer, wherein the second intrinsic layer has a third heavily doped region; a reflective layer located on a side of the second intrinsic layer away from the avalanche layer; a first through hole penetrating the reflective layer, the second intrinsic layer, and the avalanche layer, wherein the first through hole exposes a portion of the surface of the quantum well sensing layer in the absorption layer and a surface of the second heavily doped region away from the buried oxide layer, and the first through hole does not contact the third heavily doped region; a passivation layer located on a surface of the first through hole and a surface of the reflective layer, wherein the passivation layer has a second through hole and a third through hole, wherein the second through hole exposes at least a portion of the surface of the second heavily doped region, and the third through hole exposes at least a portion of the surface of the reflective layer; a first electrode electrically connected to the second heavily doped region through the second through-hole, and a second electrode electrically connected to the third heavily doped region through the third through-hole.

2. The shortwave infrared focal plane array chip according to claim 1, characterized in that: The substrate structure further includes a silicon substrate located on an insulator on a side of the buried oxide layer away from the first intrinsic layer.

3. The shortwave infrared focal plane array chip according to claim 1, characterized in that: In the quantum well sensing layer, the content of germanium in the germanium silicon layer is in the range of 0-30%; in the avalanche layer, the content of germanium in the germanium silicon layer is in the range of 0-30%.

4. The shortwave infrared focal plane array chip according to claim 1, characterized in that: The second heavily doped region includes a first heavily doped sub-region and a second heavily doped sub-region, and the first heavily doped sub-region and the second heavily doped sub-region are located on two opposite sides of the first heavily doped region.

5. The shortwave infrared focal plane array chip according to claim 1, characterized in that: The first intrinsic layer is an intrinsic germanium layer, an intrinsic GaAs layer, an intrinsic AlAs layer, an intrinsic InGaAs layer, an intrinsic AlGaAs layer or an intrinsic GeSi layer; If the first intrinsic layer is an intrinsic GeSi layer, the Si content in the GeSi layer is less than 30%.

6. The shortwave infrared focal plane array chip according to claim 1, characterized in that: The avalanche layer includes at least one of an intrinsic germanium / germanium silicon multi-quantum well layer and an intrinsic germanium / germanium silicon superlattice layer.

7. The shortwave infrared focal plane array chip according to claim 1, characterized in that: The absorption layer includes a stacked sensing layer and a quantum well sensing layer, wherein the sensing layer is a germanium sensing layer, and the quantum well sensing layer is a germanium / germanium silicon quantum well sensing layer.

8. The shortwave infrared focal plane array chip according to claim 1, characterized in that: Also includes: A charge layer located on the surface of the quantum well sensing layer has a projection located within a projection range of the first heavily doped region in a plane parallel to the absorption layer, and a preset distance is present between a projection boundary of the charge layer and a projection boundary of the first heavily doped region, wherein the preset distance is greater than zero.

9. A sensor, characterized in that: The short-wave infrared focal plane array chip comprises the short-wave infrared focal plane array chip according to any one of claims 1 to 8.

10. A method for manufacturing a short-wave infrared focal plane array chip, characterized in that: The short-wave infrared focal plane array chip includes at least one single-photon avalanche photodetector, and the method includes: Fabricating a substrate structure, the substrate structure comprising a silicon substrate, a buried oxide layer located on a surface of the silicon substrate, and a first intrinsic layer located on a side of the buried oxide layer away from the silicon substrate, wherein the first intrinsic layer has a first heavily doped region; forming an absorption layer on a side of the first intrinsic layer away from the buried oxide layer, wherein the absorption layer comprises at least one germanium layer; forming a second heavily doped region penetrating the absorption layer and the first intrinsic layer, wherein the second heavily doped region is in direct contact with the first heavily doped region in the first intrinsic layer; forming an avalanche layer on a side of the absorption layer away from the substrate structure, wherein the avalanche layer comprises an intrinsic germanium layer and a germanium silicon layer, and the avalanche layer and the absorption layer meet a lattice matching condition; forming a second intrinsic layer on a side of the avalanche layer away from the absorption layer, wherein the second intrinsic layer has a third heavily doped region; forming a reflective layer on a side of the second intrinsic layer away from the avalanche layer; forming a first through hole penetrating the reflective layer, the second intrinsic layer, and the avalanche layer, wherein the first through hole exposes a portion of the surface of the quantum well sensing layer in the absorption layer and a surface of the second heavily doped region away from the buried oxide layer, and the first through hole does not contact the third heavily doped region; forming a passivation layer on the surface of the first through hole and the surface of the reflective layer, wherein the passivation layer has a second through hole and a third through hole, wherein the second through hole exposes at least a portion of the surface of the second heavily doped region, and the third through hole exposes at least a portion of the surface of the reflective layer; A first electrode electrically connected to the second heavily doped region through the second through-hole and a second electrode electrically connected to the third heavily doped region through the third through-hole are formed.

11. The manufacturing method according to claim 10, characterized in that: Forming an absorption layer on a side of the first intrinsic layer away from the buried oxide layer includes: forming an absorption layer on a side of the first intrinsic layer away from the buried oxide layer using a homoepitaxial process; Forming the avalanche layer on the side of the absorption layer away from the substrate structure includes: forming the avalanche layer on the side of the absorption layer away from the substrate structure using a homoepitaxial process; The forming of the second intrinsic layer on the side of the avalanche layer away from the absorption layer comprises: forming the second intrinsic layer on the side of the avalanche layer away from the absorption layer by adopting a homoepitaxial process.

12. The manufacturing method according to claim 10, characterized in that: After forming the absorption layer and before forming the avalanche layer, the manufacturing method further includes: forming a charge layer on the surface of the quantum well sensing layer, wherein in a plane parallel to the absorption layer, the projection of the charge layer is located within the projection range of the first heavily doped region, and there is a preset distance between the projection boundary of the charge layer and the projection boundary of the first heavily doped region, and the preset distance is greater than zero.

13. A method for manufacturing a sensor, characterized in that: The manufacturing method includes the manufacturing method of the short-wave infrared focal plane array chip according to any one of claims 10 to 12.

14. The manufacturing method according to claim 13, characterized in that: The method further includes: thinning the substrate structure to remove at least a portion of the silicon substrate.

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