resident map descriptor

Abstract

A processor receives a request to access one or more levels of a portion of a persistent texture (PRT) resource. The levels represent textures at different levels of detail (LODs) and the request includes normalized coordinates indicative of a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more persistent maps indicative of texels that are resident in the PRT resource. The processor converts the normalized coordinates to texel coordinates in the one or more persistent maps based on the offsets and accesses the one or more persistent maps based on the texel coordinates in response to the request to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

Description

Background Technology

[0001] A graphics processing unit (GPU) uses a graphics pipeline consisting of a series of programmable shaders and fixed-function hardware blocks to process three-dimensional (3-D) graphics. For example, a 3-D model of an object visible in a frame can be represented by a set of triangles, other polygons, or patches, which are processed in the graphics pipeline to produce pixel values ​​for display to the user. Triangles, other polygons, or patches are collectively referred to as primitives. The process involves mapping textures to primitives to incorporate visual details with a resolution higher than that of the primitives. The GPU includes dedicated memory for storing texture values, making these texture values ​​available for mapping to primitives processed in the graphics pipeline. Textures can be stored on disk or generated programmatically when needed by the graphics pipeline. Texture data stored in dedicated GPU memory is populated by loading textures from disk or by programmatically generating data. Dedicated GPU memory is typically relatively small, which limits the amount of texture data that can be stored in it. Furthermore, the overhead required to populate texture data can be significant, especially if only a small subset of the texture data is used to render the final screen image. Attached Figure Description

[0002] This disclosure will be better understood by referring to the accompanying drawings, and many features and advantages of this disclosure will become apparent to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0003] Figure 1 It is a block diagram of a processing system, according to some implementation schemes, including a graphics processing unit (GPU) for creating visual images intended to be output to a display.

[0004] Figure 2 A graphics pipeline, according to some implementation schemes, is described that can process high-order geometric primitives to generate rasterized images of three-dimensional (3D) scenes at a predetermined resolution.

[0005] Figure 3 It is a flowchart illustrating the transformation between different levels and standardized coordinate spaces of partially resident texture (PRT) resources according to some implementation schemes.

[0006] Figure 4 It is a flowchart of the transformation between resident graphs in texel space and normalized coordinate space according to some implementation schemes.

[0007] Figure 5 It is a block diagram of texture descriptors based on some implementation schemes.

[0008] Figure 6It is a diagram showing the relationship between PRT resources and resident graphs at the level of some implementation schemes.

[0009] Figure 7 It is a flowchart of a method for generating and storing texture descriptors according to some implementation schemes.

[0010] Figure 8 It is a flowchart of a method for generating and storing texture descriptors according to some implementation schemes. Detailed Implementation

[0011] In some cases, texture information is represented using layered texture maps stored on the GPU in a partially resident texture (PRT) resource. Each level in the map represents the texture at a level of detail (LOD). The standard convention is to reduce the LOD at higher levels of the map; however, inverse level numbering can also be used. The dimensions of the PRT resource (in texel space) are reduced by a factor of two with each successively higher level. Shaders or applications use normalized texture coordinates to access the levels of the PRT resource's map. Normalized (u,v) texture coordinates are normalized from their actual dimensions (e.g., the range from 0..dim to 1) to a normalized range of 0.0 to 1.0.

[0012] By saving space in dedicated GPU memory by filling a subset of texels in the texture hierarchy, texture information is not necessarily resident in all texels across all texture levels of the PRT resource. A drawback of storing texture information in the PRT resource is that the texture hardware returns black in response to application sampling of texels not resident in dedicated GPU memory. This drawback is overcome by generating a resident map that indicates the best LOD (or lowest texture level) filled in the PRT resource. For example, texels in the resident map can indicate that the corresponding texel in the PRT resource is resident at level 3 of the texture (and all higher levels / lower LODs). The resident map uniformly divides the normalized texture coordinate space according to the dimensions of the resident map. For example, a 2x2 resident graph uniformly divides the normalized (u,v) texture coordinate space into four texels, covering the (u,v) ranges (0.0..0.5, 0.0..0.5), (0.5..1.0, 0.0..0.5), (0.0..0.5, 0.5..1.0), and (0.5..1.0, 0.5..1.0). Therefore, depending on the dimension of the PRT resource at the map sampling level, a single texel of the resident graph slices out a tile containing a different number of texels at different map levels of the PRT resource.

[0013] The shader (or corresponding application) samples a PRT resource using a sampling operation. The PRT resource includes normalized (u,v) coordinates indicating the sampling location in normalized (u,v) texture coordinate space. The normalized coordinates are converted to texel coordinates using the dimensions of the PRT resource at one or more map levels. For example, if the requested map level has 8x8 texel dimensions, the normalized u-coordinates are converted to texel coordinates by multiplying by (8-1) = 7, and the normalized v-coordinates are converted to texel coordinates by multiplying by (8-1) = 7. The texel coordinates are then converted to addresses within the texel data, and these addresses are used to extract the texel data. However, as discussed above, not all texels are necessarily resident at all levels of the PRT resource. To prevent the texture hardware from returning black texels in response to requests to access non-resident texels, resident maps are sampled to identify the best fill map level for the PRT resource. Subsequent sampling of the PRT resource is clamped to this LOD, causing the application to return texel values ​​instead of black when attempting to access non-resident texels at a lower / higher LOD of the texture. In some cases, coordinate transformation includes the step of generating additional positions in normalized texture coordinate space, which are then converted to texel positions in texel space. In some cases, such as anisotropic texture filtering, generating additional positions and corresponding texel positions requires knowledge of the dimensions of the PRT resource in texel space.

[0014] For both PRT resources and resident maps, a consistent transformation from normalized (u,v) coordinates to texel coordinates must be performed. Incorrect coordinate transformations leading to inaccurate texel identification in the resident map can result in missing PRT coordinates due to incorrectly calculated lowest map level / highest LOD at the sample location. The shader might then attempt to access non-resident texels at lower map levels / higher LODs, potentially causing unwanted visual artifacts as the sampling operation returns black. Coordinate transformations between normalized (u,v) coordinates and texel coordinates in the resident map are performed based on the dimensions of the resident map. Coordinate transformations between normalized coordinates and texel coordinates for the PRT resource are performed based on the dimensions of the accessed map level of the PRT resource. Therefore, the texture hardware must know the dimensions of both the resident map and the PRT resource to ensure that sampled texels in the resident map are correctly mapped to the texels that will be accessed during PRT resource sampling operations. Thus, the dimensions of the PRT resource and the resident map need to be passed to the texture hardware to ensure that the sampling process of the resident map can reproduce the sampling process of the original PRT resource.

[0015] Texture descriptors are used to transmit dimensions and other attributes to texture hardware by encoding information into a finite set of bits. Examples of attributes transmitted in a texture descriptor include a pointer to the texture, the dimensions of the PRT resource, the data encoding format, the number of bytes per texel, the compression ratio, the compression type, etc. The size of a texture descriptor is typically aligned to the machine's word size; for example, a texture descriptor may include 256 bits, aligned to either a 32-bit word or a 64-bit word, depending on the machine type. Modifying the texture descriptor to transmit explicit dimensions of the PRT resource in addition to the dimensions of the resident graph would require a significant increase in the size of the texture descriptor, which would necessitate substantial changes to the texture pipeline, including modifications to the request path from the shader to the texture hardware and to any other hardware receiving the texture descriptor. For example, a regular texture descriptor represents one dimension using a 16-bit resident graph, and textures typically consist of three dimensions, totaling 48 bits. Therefore, increasing the size of the texture descriptor is not a practical method for transmitting dimensions of the resident graph to the texture hardware.

[0016] Figures 1 to 8 An embodiment of a technique is disclosed that reduces the amount of information incorporating information indicating resident map dimensions into a texture descriptor by constraining the dimensions of the resident map to correspond to the dimensions of the levels in a hierarchical representation of a partially resident texture (PRT) resource. In some cases, the hierarchical representation is a texture. The resident map dimension is determined based on the distance (or offset) in texture space between the resident map level and a reference level (such as the highest level of the PRT resource). The texture descriptor includes information representing the dimensions of the PRT resource, the offset between the reference level and the resident map level, and information pointing to the address of the resident map. The offset indicates multiple levels between the reference level and the resident map level. The number of levels between the reference level and the resident map level indicates the ratio of the dimensions of the reference level and the resident map level. In some embodiments, the (u,v) dimensions of each level in the hierarchical representation differ by a factor of two from the corresponding dimensions in the adjacent levels of the hierarchical representation. The offset of the two levels between the reference level and the resident map level will therefore indicate a difference of a factor of four between the (u,v) dimensions of the reference level and the resident map level. Therefore, the dimensions of the resident graph are determined using the dimensions of the reference level and the ratio of the reference level indicated by the offset to the dimensions of the resident graph level.

[0017] In response to a request to sample a PRT resource, the sampling location in the resident map is determined by converting the normalized coordinates in the request to texel coordinates in the resident map using the dimensions of the resident map determined according to the offset. Therefore, when both sets of dimensions are needed, both the PRT resource dimensions and the resident map dimensions can be conveniently derived from understanding the PRT resource dimensions and the offset of the resident map. The texel coordinates of the sampling location are used to access the texel, and the texel value indicates the lowest map level / highest level of detail (LOD) in one or more corresponding texels resident in the PRT resource. The sampling location in the PRT resource is determined by mapping the normalized coordinates to texel coordinates in the PRT resource based on the dimensions of the PRT resource's map level indicated in the texture descriptor. The texel coordinates in the PRT resource are used to access the texels in the PRT resource's map level. Access to the texels of the PRT resource is clamped to the LOD indicated by the value in the corresponding texel in the resident map. In some implementations, offset information is incorporated into previously unused bits of the texture descriptor, keeping the texture descriptor size constant.

[0018] Figure 1 This is a block diagram of a processing system 100, according to some embodiments, including a graphics processing unit (GPU) 105 for creating visual images intended to be output to a display 110. The processing system 100 includes a memory 115. Some embodiments of the memory 115 are implemented as dynamic random access memory (DRAM). However, the memory 115 may also be implemented using other types of memory, including static random access memory (SRAM), non-volatile RAM, etc. In the illustrated embodiment, the GPU 105 communicates with the memory 115 via a bus 120. However, some embodiments of the GPU 105 communicate with the memory 115 via a direct connection or via other buses, bridges, switches, routers, etc. The GPU 105 can execute instructions stored in the memory 115, and the GPU 105 can store information such as the results of the executed instructions in the memory 115. For example, the memory 115 may store a copy 125 of instructions from program code that will be executed by the GPU 105. Some embodiments of the GPU 105 include multiple processor cores (not shown for clarity) that can independently execute instructions simultaneously or in parallel.

[0019] Processing system 100 includes a central processing unit (CPU) 130 for executing instructions. Some embodiments of CPU 130 include multiple processor cores (not shown for clarity) capable of executing instructions independently, simultaneously, or in parallel. CPU 130 is also connected to bus 120 and can therefore communicate with GPU 105 and memory 115 via bus 120. CPU 130 can execute instructions such as program code 135 stored in memory 115, and CPU 130 can store information such as the results of the executed instructions in memory 115. CPU 130 is also capable of initiating graphics processing by issuing a draw call to GPU 105. A draw call is a command generated by CPU 130 and transmitted to GPU 105 to instruct GPU 105 to render an object (or a portion of an object) in a frame. Some embodiments of a draw call include information such as defined textures, states, shaders, render objects, buffers, etc., used by GPU 105 to render the object or a portion thereof. GPU 105 renders objects to generate pixel values, which are provided to display 110, which uses the pixel values ​​to display an image representing the rendered objects.

[0020] Input / output (I / O) engine 140 handles input or output operations associated with display 110 and other components of processing system 100, such as keyboard, mouse, printer, external disk, etc. I / O engine 140 is coupled to bus 120, enabling it to communicate with GPU 105, memory 115, or CPU 130. In the illustrated embodiment, I / O engine 140 is configured to read information stored on external storage medium 145, such as optical disc (CD), digital video disc (DVD), etc.

[0021] External storage medium 145 stores information representing program code used to implement applications such as video games. The program code on external storage medium 145 can be written to memory 115 to form a copy 125 of instructions to be executed by GPU 105 or CPU 130. External storage medium 145 also stores information representing textures used to render images for presentation on display 110. A portion of the texture stored on external storage medium 145 is written to memory 115, which stores that information as texture information 150. While external storage medium 145... Figure 1 While the external storage medium 145 is depicted as a disk, some implementations of the external storage medium 145 are implemented as a server (or server cloud) that downloads or streams information to the processing system 100, for example, via a wired or wireless communication link to the processing system 100.

[0022] GPU 105 implements a graphics pipeline (not shown for clarity). Figure 1(As shown in the diagram), it includes multiple stages configured to process different primitives or binaries simultaneously in response to a draw call. The stages of the graphics pipeline in GPU 105 can simultaneously process different primitives generated by applications such as video games. Primitive processing includes mapping textures to primitives, for example, to provide additional detail. GPU 105 accesses texture data from texture information 150 stored in memory 115 or from local memory 155 associated with GPU 105. Texture data is stored in partially resident texture (PRT) resources located in memory 115 or local memory 155. PRT resources include texture data represented at different levels of detail (LOD) in different levels of a layered representation of textures, such as texture map representations. Texture data is not necessarily filled in all texels at a level of the PRT resource before GPU 105 requests access to it. For example, texture data may not have been written from external storage medium 145 to memory 115 or local memory 155. As another example, CPU 130 may not have programmatically generated texture data according to instructions in program code 135.

[0023] The GPU 105 (or a shader or application executing on the GPU 105) accesses the resident graph before, simultaneously with, or as part of a request to access texture data from a PRT resource. Information in the resident graph is used to determine whether the requested texture data is resident in the PRT resource. As discussed herein, a PRT resource represents texture data as a hierarchical set of levels representing textures at different LODs, for example, as a texture map. Therefore, different levels of a PRT resource have different dimensions in texel space. Some implementations of the resident graph are constrained to have a dimension corresponding to one of the levels of the PRT resource. For example, a resident graph can be represented as a 2x2 texel array corresponding to a level of a PRT resource that also includes a 2x2 texel array representing textures at lower LODs. The texels in the resident graph include information indicating the lowest (and highest) level (LOD) of the PRT resource, which includes resident texels contained by the corresponding texels in the resident graph.

[0024] The request from GPU 105 to access PRT resources includes normalized coordinates (or associated coordinates) indicating a location within the texture. These normalized coordinates are called (u,v) coordinates. GPU 105 converts the normalized coordinates in the request to texel coordinates within the resident graph using the resident graph's dimensions. Based on the PRT resource's level dimensions, the normalized coordinates are then converted to texel coordinates within the PRT resource's level. This transformation is performed such that the texture location indicated by the texel coordinates in the resident graph is the same as the location indicated by the texel coordinates in one or more levels of the PRT resource. Therefore, GPU 105 can access information indicating (or that can be used to derive) the dimensions of both the resident graph and the PRT resource's level.

[0025] A texture descriptor includes a dimension of one of the levels of the PRT resource and an offset between a reference level in the PRT resource and a level associated with the resident graph. Some implementations of the texture descriptor include a dimension of one of the levels of the PRT resource (e.g., the level with the highest LOD representation of the texture). The dimensions of the other levels of the PRT resource are then determined based on the relationships between the dimensions of the levels. For example, if the PRT resource is represented as a texture, the dimensions of successive levels of the PRT resource are increased or decreased by a factor of two. The texture descriptor also includes an offset between a reference level and the levels of the PRT resource that match the dimensions of the resident graph. In some implementations, the reference level is the same as the level that determines the dimensions of the PRT resource and the level of the texture descriptor, e.g., the level with the highest LOD representation of the texture. Some implementations of the texture descriptor include multiple offsets between the reference level and different dimensions in the resident graph. For example, the texture descriptor may include three different offsets corresponding to three separate dimensions of the resident graph.

[0026] GPU 105 uses information from the texture descriptor to convert the requested normalized coordinates to texel coordinates at the PRT resource level using dimensions at the PRT resource level, and to convert the normalized coordinates to texel coordinates in the resident graph using offsets included in the texture descriptor. The offsets are used to determine the dimensions of the resident graph using known dimensions at the reference level. In some implementations, the offsets indicate multiple levels between the reference level and the resident graph levels. The dimensions of the resident graph are then determined based on the ratio of the known dimensions at the reference level to the dimensions determined by the number of levels between the reference level and the resident graph levels. The processor converts the normalized coordinates to texel coordinates in the resident graph based on the offsets and, in response to a request, accesses the resident graph based on the texel coordinates to determine whether the amount of texture indicated by the normalized coordinates is resident in the PRT resource.

[0027] GPU 105 uses texel coordinates in the resident graph to identify the texel in the resident graph corresponding to the requested access location in the PRT resource. The value of the texel in the resident graph indicates the lowest / highest LOD in the texture representation of the PRT resource filled with resident texels. Access requests to the PRT resource are clamped to the level indicated by the texel values ​​in the resident graph. For example, the lowest / highest LOD indicated in the request is constrained to be at the same or higher (same or lower LOD) level as the lowest / highest LOD indicated in the texel in the resident graph. Clamping access requests in this way ensures that the information returned in response to an access request is a representation of the texture, rather than the default black texel returned in response to an attempt to access a non-resident texel in the PRT resource.

[0028] Figure 2A graphics pipeline 200, according to several implementations, is depicted capable of processing high-order geometric primitives to generate rasterized images of three-dimensional (3D) scenes at a predetermined resolution. The illustrated implementation of the graphics pipeline 200 is implemented according to the DX11 specification. Other implementations of the graphics pipeline 200 are implemented according to other application programming interfaces (APIs), such as Vulkan, Metal, DX12, etc. The graphics pipeline 200 in... Figure 1 Some implementations of the GPU 105 shown are implemented. The graphics pipeline 200 has a hierarchy of storage resources 201, such as one or more memories or caches for implementing buffers and storing vertex data, texture data, etc. It can be used... Figure 1 Some implementations of the memory 115 shown implement the storage resource 201.

[0029] Input assembler 202 is configured to access information from storage resource 201 for objects that define portions of the scene model. Vertex shader 203, which can be implemented in software, logically receives a single vertex of a primitive as input and outputs a single vertex. Some implementations of shaders (such as vertex shader 203) implement large-scale single-instruction multiple-data (SIMD) processing, enabling the simultaneous processing of multiple vertices. Figure 2 The illustrated graphics pipeline 200 implements a unified shader model, ensuring that all shaders included in the pipeline 200 have the same execution platform on a shared, large-scale SIMD computational unit. Therefore, shaders, including vertex shader 203, are implemented using a common set of resources referred to herein as the unified shader pool 204. Some implementations of the unified shader pool 204 use... Figure 1 The processor in the GPU105 shown is used for implementation.

[0030] Shell shader 205 operates on input higher-order patches or control points used to define the input patches. Shell shader 205 outputs a tessellation factor and other patch data. Optionally, the primitives generated by shell shader 205 can be provided to tessellation 206. Tessellation 206 receives objects (such as patches) from shell shader 205 and generates information identifying primitives corresponding to the input objects, for example, by tessellizing the input objects based on the tessellation factor provided by shell shader 205 to tessellation 106. Tessellation further divides higher-order input primitives (such as patches) into a set of lower-order output primitives representing finer levels of detail, for example, as indicated by a tessellation factor specifying the granularity of the primitives produced by the tessellation process. Thus, the scene model can be represented by a smaller number of higher-order primitives (to save memory or bandwidth), and additional detail can be added by tessellizing the higher-order primitives.

[0031] Domain shader 207 takes as input domain location and (optionally) other patch data. Domain shader 207 operates on the provided information and generates a single vertex for output based on the input domain location and other information. Geometry shader 208 receives input primitives and outputs up to four primitives generated by geometry shader 208 based on the input primitives. A primitive stream is provided to rasterizer 209, and up to four primitive streams can be merged into a buffer in storage resource 201. Rasterizer 209 performs shading operations and other operations such as clipping, viewpoint splitting, snipping, and viewport selection. Pixel shader 210 takes as input pixel streams and outputs zero or another pixel stream in response to the input pixel streams. Output merger box 211 performs blending, depth, stencil, or other operations on the pixels received from pixel shader 210.

[0032] Some or all shaders in the graphics pipeline 200 can perform texture mapping using texture data stored in storage resource 201. For example, pixel shader 210 can read texture data from storage resource 201 and use the texture data to shade one or more pixels. The shaded pixels are then provided to a display (such as...) Figure 1 The illustrated display 110 is used to present the data to the user. In the illustrated embodiment, texture data is stored in a PRT resource 215, which stores the texture data in a hierarchical structure representing the levels of texture data at different LODs. For example, the PRT resource 215 may store the texture data as a texture map, which includes dimensions that increase from one level to another in a manner that doubles in each dimension. However, other hierarchical structures are used in other embodiments, which have other ratios of dimensions between levels. Not all texels at all levels of the PRT resource 215 are resident, i.e., including the valid data representing the texture. Therefore, resident texels in the PRT resource 215 are indicated in the resident graph (RM) 220. As discussed herein, normalized coordinates provided by shaders, such as vertex shader 203, shell shader 205, domain shader 207, geometry shader 208, and pixel shader 210, are converted to texel coordinates in the PRT resource 215 or the resident graph 220. The conversion is performed using information in the texture descriptor (TD) 225. The information in texture descriptor 225 includes the dimension of the level of PRT resource 215, the offset between the reference level and the level of resident graph 220, the address of resident graph 220 in storage resource 201, etc.

[0033] Figure 3 This is a block diagram (300, 301) illustrating the transformation between different levels of PRT resources and standardized coordinate spaces according to some implementation schemes. Figure 1 The processing system 100 shown and Figure 2Some embodiments of the illustrated graphics pipeline 200 perform transformations. The PRT resource includes a hierarchical structure representing texture levels at different levels of depth (LOD). A first level 305 of the PRT resource has a first dimension 310 and a second dimension 315 determined by the number of texels in the first level 305. For example, dimensions 310 and 315 in texel space can be 64 pixels and 64 pixels, respectively. A second level 318 of the PRT resource has a first dimension 320 and a second dimension 325 determined by the number of texels in the second level 318. For example, dimensions 320 and 325 can be 32 pixels and 32 pixels, respectively.

[0034] Shaders, or applications running on shaders, typically provide requests to access PRT resources using normalized coordinates known as (u,v) coordinates. Normalized coordinates are in the range u = 0.0..1.0 and v = 0.0..1.0. Based on dimensions 310, 315, for example, the following transformation is used to perform a transformation 330 between the first level 305 in texel coordinates and the first level 335 in normalized coordinates:

[0035] U_texel = U_normalized * (width - 1)

[0036] V_texel = V_normalized * (height - 1)

[0037] The width is dimension 310 measured in texels, and the height is dimension 315 measured in texels. A transformation 340 is performed between the second level 318 in texel coordinates and the second level 345 in normalized coordinates based on dimensions 320 and 325, for example, replacing the width with dimension 320 and the height with dimension 325 in the above formula.

[0038] Figure 4 This is a block diagram illustrating the transformation 400 between a resident graph 405 in texel space and a normalized coordinate space, based on some implementation schemes. Figure 1 The processing system 100 shown and Figure 2 Some embodiments of the illustrated graphics pipeline 200 perform transformations. A resident graph 405 has a first dimension 410 and a second dimension 415 determined by the number of texels in the resident graph 405. For example, dimensions 410 and 415 in texel space can be 2 pixels and 2 pixels, respectively. As discussed herein, a request to access a PRT resource associated with a resident graph 405 includes normalized coordinates in the range u = 0.0..1.0 and v = 0.0..1.0. Based on dimensions 410 and 415, for example, the following transformation is used to perform a transformation 420 between the resident graph 405 in texel coordinates and the resident graph 425 in normalized coordinates:

[0039] U_texel = U_normalized * (width - 1)

[0040] V_texel = V_normalized * (height - 1)

[0041] The width is a dimension of 410 measured in texels, and the height is a dimension of 415 measured in texels. Texture hardware (such as in...) Figure 2 The processor implemented in the graphics pipeline 200 shown uses resident graph 405 and at different levels (e.g., Figure 3 The dimensions of PRT resources at levels 305 and 318 (as shown) are used to ensure that standardized coordinates provided in access requests for PRT resources refer to different levels (e.g., Figure 3 The PRT resources shown at levels 305 and 318 are located in the same position as those in resident graph 405. As discussed here, this information is provided in the texture descriptor.

[0042] Figure 5 This is a block diagram of texture descriptor 500 according to some implementation schemes. Texture descriptor 500 represents... Figure 2 Some embodiments of the texture descriptor 225 are shown. Texture descriptor 500 is associated with machines that use texture descriptors (such as...). Figure 1 The GPU 105 shown and Figure 2 The word size alignment of the illustrated graphics pipeline 200. For example, the texture descriptor 500 may include 256 bits, which may be aligned with 32-bit or 64-bit words depending on the type of machine.

[0043] Texture descriptor 500 includes information 505 representing the dimensions of the PRT resource's level. Some implementations of information 505 use 16 bits to represent one dimension of the PRT resource's level. If the texture includes three dimensions, information 505 uses a total of 48 bits to represent the dimensions of the PRT resource's level. In some implementations, information 505 represents the dimension of the texture's lowest / highest LOD representation.

[0044] Texture descriptor 500 includes information 510 indicating the address of a resident graph associated with the PRT resource. For example, information 510 may indicate... Figure 2 The address of the resident graph 220 is stored in the storage resource 201 shown.

[0045] Texture descriptor 500 includes information 515 representing an offset used to derive resident maps, such as... Figure 2The dimensions of the resident map 220 are shown. Offsets are used to derive the dimensions of the resident map based on the dimensions of a reference level, such as the lowest level (with the highest LOD) of the PRT resource. In some implementations, the offset indicates multiple levels between the reference level and the resident map's levels. The number of levels between the reference level and the resident map's levels indicates the ratio of the dimensions of the reference level to the resident map's levels. Therefore, the dimensions of the resident map are determined by scaling or multiplying the dimensions of the reference level by the ratio indicated by the offset. Using offsets to represent the levels of the resident map reduces the size of the texture descriptor 500. For example, if the PRT resource is stored as a texture with eight levels, only three bits are used to represent the offset.

[0046] Figure 6 This is a block diagram 600 showing the relationship 600 between the PRT resource and the level of the resident graph 605 according to some implementation schemes. The resident graph 605 has a dimension of 2 texels by 2 texels. The values ​​in the texels of the resident graph 605 indicate the lowest level of the PRT resource (which corresponds to the highest LOD), and it includes tiles of resident texels mapped to the corresponding texels in the resident graph 605. Figure 6 The PRT resource shown includes a first level 610 assigned level reference number 0, a second level 615 assigned level reference number 1, a third level 620 assigned level reference number 2, and a fourth level 625 assigned level reference number 3. Levels 610, 615, 620, and 625 are levels in the texture representation of the PRT resource, and the dimensions of levels 610, 615, 620, and 625 increase or decrease by a factor of two in subsequent levels. For example, level 610 has a dimension of 8 texels by 8 texels, and the next subsequent level 615 has a dimension of 4 texels by 4 texels.

[0047] As discussed herein, transforming the dimensions of resident graph 605 based on information stored in the texture descriptor ensures that the boundaries of texels in resident graph 605 are correctly mapped to corresponding regions in levels 610, 615, 620, and 625. In the illustrated embodiment, resident graph 605 has the same dimensions as level 620 of the PRT resource, for example, 2 texels by 2 texels. Therefore, the normalized coordinates in a request for accessing the PRT resource at level 620 refer to the same locations in level 620 and resident graph 605. The transformation dimensions, as discussed herein, ensure that the normalized coordinates also refer to the same locations in the other levels 610, 615, and 625. For example, texels in transformed version 630 of resident graph 605 correspond to the correct texel tiles in level 610, texels in transformed version 635 of resident graph 605 correspond to the correct texel tiles in level 615, and texels in transformed version 640 of resident graph 605 correspond to the correct texel tiles in level 625.

[0048] Cross-shading texels in levels 610, 615, 620, and 625 are resident in the PRT resource. In the illustrated embodiment, the texel in the PRT resource corresponding to the top-left corner of resident graph 605 (e.g., texel coordinate 0,0) is only resident at level 625 of the PRT resource. Therefore, the value of texel (0,0) is equal to level reference number 3. The texel in the PRT resource corresponding to the top-right corner of resident graph 605 (e.g., texel coordinate 0,1) is resident at levels 610 and higher / lower LODs of the PRT resource. Therefore, the value of texel (0,1) is equal to level reference number 0. The texel in the PRT resource corresponding to the bottom-left corner of resident graph 605 (e.g., texel coordinate 1,0) is resident at levels 615 and higher / lower LODs of the PRT resource. Therefore, the value of texel (1,0) is equal to level reference number 1. The texels in the PRT resource corresponding to the lower right corner of the resident graph 605 (e.g., texel coordinate 1,1) are resident at level 615 and higher / lower LOD of the PRT resource. Therefore, the value of texel (1,1) is equal to level reference number 1.

[0049] Figure 7 This is a flowchart of method 700 for generating and storing texture descriptors according to some implementation schemes. Method 700 in Figure 1 The GPU 105 shown and Figure 2 Some implementations of the graphics pipeline 200 shown are implemented. For example, a driver implemented in GPU 105 can be used to generate texture descriptors. Method 700 is used to generate... Figure 5 Some embodiments of the texture descriptor 500 are shown. The texture descriptor includes information defining the level dimension in a hierarchy that defines the level of the PRT resource representing the texture at different LODs. The texture descriptor is also associated with a resident graph used for the PRT resource.

[0050] In block 705, the driver determines an offset for determining the level of the resident graph, which is constrained to have a texel dimension corresponding to one of the levels of the PRT resource. In some implementations, the reference level is the lowest / highest LOD in the hierarchy of levels of the PRT resource. The reference level can be used by the driver, for example, by storing a value indicating the reference level in one or more registers, memory locations, buffers, etc.

[0051] In box 710, the driver determines the level of the resident graph. Information indicating the level of the resident graph can be used by the driver, for example, as a value stored in one or more registers, memory locations, buffers, etc.

[0052] In box 715, the driver determines the offset between the reference level and the resident map level. Some implementations of the offset indicate multiple levels between the reference level and the resident map level. For example, if the reference level is level 0 of the texture map representation and the resident map level corresponds to level 3 of the texture map representation, the offset value is 3.

[0053] In block 720, the driver generates a texture descriptor that includes the dimensions of the PRT resource's levels and an offset representing the dimensions of the resident map's levels relative to the reference level. The number of bits required to represent the offset is much smaller than the number of bits required to directly represent the dimensions of the resident map's levels. For example, if one dimension of the resident map's levels is represented by 16 bits and the texture comprises three dimensions, a total of 48 bits are needed to represent the dimensions of the resident map's levels. Conversely, if the number of levels in the hierarchical representation of the PRT resource is eight, only three bits are needed to represent the possible offsets of the resident map's levels. In some implementations, the driver includes information representing the address of the resident map to the texture descriptor, as well as additional information including a pointer to the texture, the dimensions of the PRT resource, the data encoding format, the number of bytes per texel, the compression ratio, the compression type, etc.

[0054] In box 725, the driver stores the texture descriptor in a memory location accessible to shaders or applications that access PRT resources and resident graphs. For example, the texture descriptor may be stored in... Figure 1 The memory 115 shown or Figure 2 The storage resource 201 shown.

[0055] Figure 8 This is a flowchart of a method 800 for generating and storing texture descriptors according to some implementation schemes. Method 800 is generated by texture hardware, such as... Figure 1 The circuitry shown in some implementations of the GPU 105 and Figure 2 The graphical pipeline 200 shown is implemented.

[0056] In box 805, the texture hardware receives a request to access one or more levels of a PRT resource. The request includes normalized coordinates (or associated coordinates) that indicate the location within the texture as represented by one or more levels of the PRT resource.

[0057] In box 810, texture hardware access includes the texture descriptor and the corresponding resident graph associated with the PRT resource. The texture descriptor includes information defining the dimensions of the PRT resource's level and offsets used to determine the level of the resident graph.

[0058] In block 815, the texture hardware determines the dimensions of the resident map based on offsets. In some embodiments, the offsets indicate multiple levels between the resident map level and a reference level. The number of levels indicates the ratio of the resident map dimension to the dimension of the reference level. Therefore, the texture hardware determines the resident map dimension by scaling (or multiplying) the dimension of the reference level by the ratio indicated by the offset. In some embodiments, separate offsets exist for multiple different resident map dimensions (e.g., three offsets), and the texture hardware determines the resident map dimension by applying the separate offsets to the reference level.

[0059] In box 820, the texture hardware uses the dimensions of the resident graph to convert the normalized coordinates derived from the request into texel coordinates in the resident graph. In some implementations, such as Figure 4 Perform the conversion as shown.

[0060] In box 825, the texture hardware accesses the resident map using texel coordinates. For example, the texture hardware identifies texels in the resident map based on texel coordinates transformed from normalized coordinates in the request. A texel includes information indicating the lowest / highest LOD in a PRT resource, which includes resident texels representing the texture. In some embodiments, the information in the texels indicates the lowest level of the map, which includes resident texels for the portion of the texture in the PRT resource surrounded by the boundaries of texels in the resident map.

[0061] In box 830, the access request is clamped to the PRT resource level indicated in the texels of the resident graph. In some implementations, the access request is clamped to a level by restricting the access request to access only PRT resources at the same or higher level (at a lower LOD) as the level indicated in the texels of the resident graph. The request is then submitted to the PRT resource. Clamping the request ensures that the request is accessing a portion of the resident PRT resource, such that the PRT resource returns information representing the texture at the requested location, rather than returning the default black value for non-resident texels.

[0062] As described herein, in some embodiments, a method includes: receiving at a processor a request to access at least one of a plurality of levels of a partially resident texture (PRT) resource, wherein the plurality of levels represent textures at different levels of detail (LOD), wherein the request includes normalized coordinates indicating a location in the texture; accessing at the processor a texture descriptor, the texture descriptor including information indicating a dimension of a first level of the plurality of levels and at least one offset between a reference level and at least one second level of the plurality of levels, the at least one second level being associated with at least one resident graph indicating texels resident in the PRT resource; converting the normalized coordinates to texel coordinates in the at least one resident graph based on the at least one offset; and, in response to the request, accessing at the processor the at least one resident graph based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource. In one aspect, the first level corresponds to one of the plurality of levels having the highest LOD, and wherein the reference level corresponds to the first level. In another aspect, the texture descriptor includes information indicating a plurality of offsets between the reference level and a plurality of second levels associated with the plurality of resident graphs.

[0063] In one aspect, the at least one offset indicates multiple levels between the at least one second level and the reference level. In another aspect, converting the normalized coordinates to texel coordinates includes determining the dimension of the at least one resident graph based on the ratio of the dimension of the at least one resident graph (based on the number of levels between the at least one second level and the reference level) to the dimension of the reference level. In yet another aspect, converting the normalized coordinates to texel coordinates includes converting the normalized coordinates to texel coordinates based on the dimension of the at least one resident graph. In yet another aspect, the method includes: converting the normalized coordinates to texel coordinates in at least one of the multiple levels of the PRT resource based on the dimension of the first level among the multiple levels, wherein the texel coordinates in the at least one resident graph indicate the same position as the texel coordinates in at least one of the multiple levels of the PRT resource.

[0064] In one aspect, the method includes: identifying texels in the at least one resident graph based on the texel coordinates in the at least one resident graph; and accessing information indicating the highest LOD (Level of Detail) of a resident tile in the PRT corresponding to the texel in the at least one resident graph. In another aspect, the method includes: receiving texture data having a LOD less than or equal to the highest LOD resident in the tile, in response to the request.

[0065] In some embodiments, an apparatus includes: a memory configured to store at least one resident graph and a texture descriptor, wherein the at least one resident graph indicates whether texels in a partially resident texture (PRT) resource representing a texture are resident in the PRT resource, and wherein the texture descriptor includes information representing a dimension of a first level among a plurality of levels and at least one offset between a reference level and at least one second level among the plurality of levels associated with the at least one resident graph; and a processor configured to receive a request to access at least one of the plurality of levels of the PRT resource, wherein the request includes normalized coordinates indicating a position in the texture, and wherein the processor is configured to convert the normalized coordinates to texel coordinates in the at least one resident graph based on the at least one offset, and to access the at least one resident graph based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource. In one aspect, the first level corresponds to one of the plurality of levels having the highest LOD among the plurality of levels, and wherein the reference level corresponds to the first level. In another aspect, the texture descriptor includes information representing a plurality of offsets between the reference level and a plurality of second levels associated with the plurality of resident graphs.

[0066] In one aspect, the at least one offset indicates multiple levels between the at least one second level and the reference level. In another aspect, the processor is configured to determine the dimension of the at least one resident graph based on a ratio of the dimension of the at least one resident graph to the dimension of the reference level, based on the number of levels between the at least one second level and the reference level. In yet another aspect, the processor is configured to convert the normalized coordinates to texel coordinates based on the dimension of the at least one resident graph. In yet another aspect, the processor is configured to convert the normalized coordinates to texel coordinates in at least one of the multiple levels of the PRT resource based on the dimension of the first level among the multiple levels, wherein the texel coordinates in the at least one resident graph indicate the same location as the texel coordinates in at least one of the multiple levels of the PRT resource.

[0067] In another aspect, the processor is configured to identify texels in the at least one resident graph based on the texel coordinates in the at least one resident graph and access information indicating the highest LOD (Level of Detail) of the resident texel in the PRT corresponding to the at least one resident graph. In another aspect, the processor is configured to receive texture data having a LOD less than or equal to the highest LOD of the resident texel in the PRT in response to the request.

[0068] In some implementations, a method includes: generating at a processor at at least one resident map comprising a plurality of first texels, the plurality of first texels including values ​​indicating a first level among a plurality of levels of a partially resident texture (PRT) resource, wherein the plurality of levels represent textures at different levels of detail (LOD), wherein the first level indicates which of the plurality of levels of the PRT resource is resident in memory associated with the processor, and wherein the dimension of the at least one resident map corresponds to the dimension of at least one second level among the plurality of levels; determining at the processor an offset between the at least one second level and a reference level among the plurality of levels; and storing from the processor to the memory a texture descriptor, the texture descriptor including information indicating the dimension of a third level among the plurality of levels and the at least one offset. In one aspect, the texture descriptor includes information indicating the reference level and a plurality of offsets between the reference level and a plurality of second levels associated with the plurality of resident maps, wherein the at least one offset indicates a plurality of levels between the at least one second level and the reference level, wherein the third level corresponds to the one among the plurality of levels having the highest LOD, and wherein the reference level corresponds to the third level.

[0069] Computer-readable storage media can include any non-transitory storage medium or a combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compressed optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable media may be embedded in a computing system (e.g., system RAM or ROM), permanently attached to a computing system (e.g., a magnetic hard disk drive), removably attached to a computing system (e.g., an optical disc or a flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0070] In some implementations, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software includes one or more executable instruction sets stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disk storage devices, solid-state storage devices such as flash memory, caches, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be in the form of source code, assembly language code, object code, or other instruction formats that are interpreted or otherwise executed by one or more processors.

[0071] It should be noted that not all activities or elements described in the general description above are required. A particular activity or apparatus may be unnecessary and may perform one or more other activities, or may include elements other than those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes may be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, this specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0072] The benefits, other advantages, and solutions to the problems have been described above with reference to specific embodiments. However, the benefits, advantages, and solutions to the problems described, as well as any features that may bring about or make more prominent any benefit, advantage, or solution to the problem, should not be construed as being key, essential, or necessary features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be readily apparent to those skilled in the art who benefit from the teachings herein. No limitation is intended to be made on the details of the constructions or designs shown herein other than those described in the appended claims. Therefore, it is apparent that the specific embodiments disclosed above may be altered or modified, and all such variations are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A method for generating and storing texture descriptors, comprising: The normalized coordinates of a request to access a Partially Persistent Texture (PRT) resource are converted to texel coordinates in the PRT based on a texture descriptor. The PRT resource includes multiple levels representing textures at different levels of detail (LOD). The texture descriptor includes information representing the dimensions of a first level of the multiple levels and information indicating a resident graph of texels residing in the PRT resource. The texture descriptor also includes information representing the offset between the first and second levels of the multiple levels. Access the PRT resource based on the texel coordinates and the resident graph.

2. The method of claim 1, wherein the first level corresponds to the one among the plurality of levels that has the highest LOD among the plurality of levels.

3. The method of claim 1, wherein the texture descriptor includes information representing a plurality of offsets between the first level and a plurality of second levels associated with a plurality of resident graphs, wherein the plurality of offsets includes the offset.

4. The method of claim 1, wherein the offset indicates a plurality of levels between the second level and the first level.

5. The method of claim 4, further comprising: The normalized coordinates are converted to texel coordinates in the resident graph based on the offset, wherein converting the normalized coordinates to the texel coordinates includes determining the dimension of the resident graph based on the ratio of the dimension of the resident graph to the dimension of the first level based on the number of levels between the second level and the first level.

6. The method of claim 5, wherein converting the normalized coordinates to the texel coordinates comprises converting the normalized coordinates to the texel coordinates based on the dimensions of the resident graph.

7. The method according to claim 5, further comprising: The normalized coordinates are converted into texel coordinates in at least one of the multiple levels of the PRT resource based on the dimension of the first level of the multiple levels, wherein the texel coordinates in the resident graph indicate the same position as the texel coordinates in at least one of the multiple levels of the PRT resource.

8. The method according to claim 1, further comprising: Identify texels in the resident graph based on the texel coordinates in the resident graph; as well as The access indication corresponds to the information of the highest LOD of the texel in the PRT tile, which is resident in the resident graph.

9. The method of claim 8, further comprising: In response to the request, texture data having a LOD less than or equal to the highest LOD residing in the tile is received.

10. An apparatus for generating and storing texture descriptors, comprising: A processor coupled to a memory, which stores: A resident graph, which indicates whether a texture pixel is resident in a partially resident texture (PRT) resource comprising multiple levels, wherein the multiple levels represent textures at different levels of detail (LOD); and A texture descriptor, comprising information representing the dimension of a first level among the plurality of levels and the resident graph, and further comprising information representing the offset between the first level and a second level among the plurality of levels, wherein... The processor is configured to: Receive a request to access at least one of the plurality of levels of the PRT resource, wherein the request includes normalized coordinates indicating a position in the texture; and Based on the texture descriptor, the request is converted into texel coordinates of the resident texels of the PRT resource.

11. The device of claim 10, further comprising the memory coupled to the processor.

12. The device of claim 10, wherein The first level corresponds to the one among the plurality of levels that has the highest LOD among the plurality of levels.

13. The device of claim 10, wherein the texture descriptor includes information representing a plurality of offsets between the first level and a plurality of second levels associated with a plurality of resident graphs, wherein the plurality of offsets includes the offset.

14. The device of claim 10, wherein the offset indicates a plurality of levels between the second level and the first level.

15. The device of claim 14, wherein the processor is configured to determine the dimension of the resident graph based on a ratio of the dimension of the resident graph based on the number of levels between the second level and the first level to the dimension of the first level.

16. The device of claim 15, wherein the processor is configured to convert the normalized coordinates to the texel coordinates based on the offset and the dimension of the resident graph.

17. The device of claim 15, wherein the processor is configured to: The normalized coordinates are converted into texel coordinates in at least one of the multiple levels of the PRT resource based on the dimension of the first level of the multiple levels, wherein the texel coordinates in the resident graph indicate the same position as the texel coordinates in at least one of the multiple levels of the PRT resource.

18. The device of claim 10, wherein the processor is configured to: Identify texels in the resident graph based on the texel coordinates in the resident graph; and access information indicating the highest LOD of the resident texel in the PRT tile corresponding to the resident texel in the resident graph.

19. The device of claim 18, wherein the processor is configured to: In response to the request, texture data having a LOD less than or equal to the highest LOD residing in the tile is received.

20. A method for generating and storing texture descriptors, comprising: At the processor, an offset between a first level and a second level of a plurality of levels of a partially resident texture (PRT) resource indicated by a resident graph is identified, wherein the plurality of levels represent textures at different levels of detail (LOD), and wherein the first level indicates which of the plurality of levels of the PRT resource is resident in memory associated with the processor. as well as A texture descriptor is stored, the texture descriptor including information representing the dimension of the first level among the plurality of levels and the offset.

21. The method of claim 20, wherein the texture descriptor includes information representing a plurality of offsets between the first level and a plurality of second levels associated with a plurality of resident graphs, wherein the offsets indicate the number of levels between the second level and the first level, wherein the first level corresponds to one of the plurality of levels having the highest LOD among the plurality of levels.

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