Display device

Abstract

A display device according to an embodiment of the present invention includes a pixel arranged in a display. The pixel includes: a first electrode extending in a first direction; a second electrode including a first electrode unit, a second electrode unit, and a third electrode unit, the first electrode unit is separated from the first electrode in a direction intersecting the first direction and extending in the first direction, the second electrode unit extends from the first electrode unit in a second direction, and the third electrode unit extends from the second electrode unit in the first direction; a third electrode, at least one region of the third electrode is separated from the third electrode unit in a direction intersecting the first direction, and the third electrode extends in the first direction; a first light-emitting element connected between the first electrode and the second electrode; and a second light-emitting element connected between the second electrode and the third electrode.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a display device. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting element using a material having a reliable inorganic crystal structure and a technology for manufacturing a light-emitting device using the light-emitting element have been developed. For example, a technology for manufacturing a plurality of ultra-small light-emitting elements having a small size corresponding to a range from the nanometer level to the micrometer level and a technology for forming a light source of various light-emitting devices (e.g., pixels of a display device) using the ultra-small light-emitting element have been developed. Summary of the invention

[0003] Technical issues

[0004] An object of the present disclosure is to provide a display device including a light emitting element.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure may include a pixel arranged in a display area. The pixel may include: a first electrode extending in a first direction; a second electrode including a first electrode portion, a second electrode portion, and a third electrode portion, the first electrode portion being spaced apart from the first electrode in a direction intersecting the first direction and extending in the first direction, the second electrode portion extending from the first electrode portion in a second direction, and the third electrode portion extending from the second electrode portion in the first direction; a third electrode including at least one region spaced apart from the third electrode portion in a direction intersecting the first direction and extending in the first direction; a first light-emitting element connected between the first electrode and the second electrode; and a second light-emitting element connected between the second electrode and the third electrode.

[0007] In an embodiment, the second electrode portion may be disposed between the first electrode and the third electrode.

[0008] In an embodiment, the first electrode may be spaced apart from the first electrode portion with respect to the second direction.The third electrode may be spaced apart from the third electrode portion with respect to the second direction.

[0009] In an embodiment, at least one region of the third electrode and the first electrode may be disposed in a line at positions spaced apart from each other with respect to the first direction.The first electrode portion and the third electrode portion may be disposed in a line with respect to the first direction.

[0010] In an embodiment, the first electrode and the third electrode portion may be disposed at positions spaced apart from each other on a line with respect to the first direction.At least one region of the third electrode and the first electrode portion may be disposed at positions spaced apart from each other on a line with respect to the first direction.

[0011] In an embodiment, the first light emitting element may include a P-type terminal electrically connected to the first electrode and an N-type terminal electrically connected to the second electrode. The second light emitting element may include a P-type terminal electrically connected to the second electrode and an N-type terminal electrically connected to the third electrode.

[0012] In an embodiment, the display device may further include: a first electrode line electrically connected to the first electrode and configured to be supplied with a first power voltage or a first driving signal; and a second electrode line electrically connected to the third electrode and configured to be supplied with a second power voltage or a second driving signal.

[0013] In an embodiment, the display device may further include: a third light emitting element including a P-type end electrically connected to the third electrode and an N-type end opposite to the P-type end; and a fourth electrode electrically connected between the N-type end of the third light emitting element and the second electrode line.

[0014] A display device according to an embodiment of the present disclosure may include a first pixel, the first pixel including a light-emitting element arranged in a plurality of series stages. The first pixel may include: a first sub-region to a K-th sub-region, respectively corresponding to the first series stage to the K-th series stage, K being a natural number of 2 or greater; a first electrode and a second electrode of each series stage in the plurality of series stages, arranged at positions spaced apart from each other in each sub-region from the first sub-region to the K-th sub-region; a first light-emitting element to a K-th light-emitting element, respectively connected between the first electrode and the second electrode in the first sub-region to the K-th sub-region; a first electrode line, connected to the first electrode of the first sub-region; a second electrode line, connected to the second electrode of the K-th sub-region; and at least one intermediate electrode, arranged between two consecutive sub-regions in the first sub-region to the K-th sub-region, and connected to the second electrode of the previous sub-region and the first electrode of the next sub-region. The intermediate electrode may extend in a direction intersecting the direction along which the first electrode and the second electrode extend.

[0015] In an embodiment, the first electrode line and the second electrode line may be arranged to face each other, and the first sub-region to the Kth sub-region are placed between the first electrode line and the second electrode line. Each of the first electrode line and the second electrode line may extend in a direction intersecting the direction along which the first electrode and the second electrode extend.

[0016] In an embodiment, the first and second electrode lines and the intermediate electrode may be arranged in parallel with each other, and at least one sub-region is disposed between the first and second electrode lines and the intermediate electrode.

[0017] In an embodiment, the first to K-th sub-regions may be continuously disposed in a first direction. The intermediate electrode may extend between two continuous sub-regions along a second direction crossing the first direction.

[0018] In an embodiment, the first electrode and the second electrode may extend in the first direction and may be disposed parallel to each other in each of the first to K-th sub-regions.

[0019] In an embodiment, the first electrode and the second electrode may be disposed at regular intervals in each of the first to K-th sub-regions.

[0020] In an embodiment, the intermediate electrode may be integrally connected to the second electrode of the preceding sub-region and the first electrode of the succeeding sub-region.

[0021] In an embodiment, the intermediate electrode may have a width smaller than a width of each of the first electrode line and the second electrode line.

[0022] In an embodiment, the first electrode line may be supplied with a first power voltage or a first driving signal. The second electrode line may be supplied with a second power voltage or a second driving signal.

[0023] In an embodiment, the first pixel may further include a pixel circuit connected between the first electrode line and a first power source supplying the first power voltage.

[0024] In an embodiment, the first electrode and the second electrode may be disposed in the same repeating pattern in each of the first to Kth sub-regions.

[0025] In an embodiment, in two consecutive sub-regions, the first electrode and the second electrode may be disposed in a symmetrical shape based on the intermediate electrode.

[0026] In an embodiment, the display device may further include a second pixel having the same structure as the first pixel and disposed adjacent to the first pixel. The first electrode lines and the intermediate electrode of the first and second pixels may be separated from each other between the first and second pixels.

[0027] In an embodiment, the second electrode lines of the first pixel and the second pixel may be integrally connected to each other.

[0028] In an embodiment, the first pixel may further include at least one reverse light-emitting element, which is connected between the first electrode and the second electrode in at least one series connection stage of the plurality of series connection stages in a direction opposite to the light-emitting element. The number of reverse light-emitting elements may be less than the number of light-emitting elements.

[0029] In an embodiment, the first pixel may also include at least one of the following elements: a first partition wall, disposed under the corresponding first electrode; a second partition wall, disposed under the corresponding second electrode; a first contact electrode, disposed above the corresponding first electrode and each configured to electrically connect a corresponding one of the first electrodes to the first end of the at least one light-emitting element; and a second contact electrode, disposed above the corresponding second electrode and each configured to electrically connect a corresponding one of the second electrodes to the second end of the at least one light-emitting element.

[0030] In an embodiment, the display device may further include a bank configured to integrally surround an emission region of the first pixel including the first to K-th sub-regions.

[0031] Beneficial Effects

[0032] In a display device including pixels according to an embodiment of the present disclosure, each light source unit can be formed using light emitting elements supplied to the emission region of each pixel efficiently, and the efficiency of power to be used to align the light emitting elements can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1a and Figure 1b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0034] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0035] Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0036] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0037] Figure 5a to Figure 5e 2 are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0038] Figure 6 and Figure 7 are plan views each showing a pixel according to an embodiment of the present disclosure.

[0039] Figure 8 and Fig. 9 are pixels according to an embodiment of the present disclosure (for example, pixels and Figure 6 and Figure 7 A plan view of a modified embodiment related to an embodiment of the present invention.

[0040] Figures 10 to 13 are cross-sectional views each showing a pixel according to an embodiment of the present disclosure.

[0041] Figures 14a to 14c are plan views sequentially illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0042] Fig.15 and Fig.16 are all methods for manufacturing a display device according to an embodiment of the present disclosure (for example, Fig.14a A plan view of different modified embodiments related to the embodiment of the present invention. DETAILED DESCRIPTION

[0043] Now, various embodiments of the present disclosure will be referred to in detail. Since the embodiments of the present disclosure can be variously modified in many different forms, specific examples of various embodiments of the present disclosure are shown in the drawings and described below. However, the present disclosure is not limited to the following embodiments and can be modified into various forms.

[0044] Some elements that are not directly related to the features of the present disclosure may be omitted in the accompanying drawings to clearly explain the present disclosure. In addition, the sizes, proportions, etc. of some elements in the accompanying drawings may be slightly exaggerated. It should be noted that throughout the accompanying drawings, the same reference numerals are used to represent the same or similar elements, and repeated descriptions will be omitted.

[0045] It will be understood that, although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, it is explained that there are stated features, wholes, steps, operations, elements, components and / or combinations thereof, but it is not excluded that there are or add one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when the first component or part is arranged on the second component or part, the first component or part can not only be directly located on the second component or part, but also the third component or part can be located between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions according to the viewing angle or direction. In addition, as long as there is no special mention in the sentence, the singular form can also include the plural form.

[0046] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting element LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting element LD is illustrated, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0047] Reference Figure 1a and Figure 1b , the light emitting element LD according to the embodiment of the present disclosure may include a first conductive type semiconductor layer 11 (also referred to as a "first semiconductor layer"), a second conductive type semiconductor layer 13 (also referred to as a "second semiconductor layer"), and an active layer 12 disposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting element LD may include the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13 which are continuously stacked in a longitudinal direction.

[0048] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end with respect to the longitudinal direction.

[0049] In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a first end of the light emitting element LD. The other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a second end of the light emitting element LD.

[0050] In the embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type" includes rod-like shapes and strip-like shapes such as cylindrical and prism-like shapes extending in a longitudinal manner (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0051] In an embodiment, the light emitting element LD may have a small size ranging from nanometer level to micrometer level. For example, each light emitting element LD may have a diameter D and / or a length L ranging from nanometer level to micrometer level. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (for example, a display device using a light emitting device using the light emitting element LD as a light source).

[0052] The first conductive type semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first conductive type semiconductor layer 11 may include an N-type semiconductor layer including any one of semiconductor materials of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material for forming the first conductive type semiconductor layer 11 is not limited thereto, and the first conductive type semiconductor layer 11 may be formed of various other materials.

[0053] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and may have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0054] If a voltage equal to or greater than the threshold voltage is applied to each of the opposite ends of the light emitting element LD, the light emitting element LD can emit light by recombination of electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for pixels of various light emitting devices and display devices.

[0055] The second conductive type semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer having a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a P-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials and doped with a second conductive dopant such as Mg. However, the material for forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0056] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer circumferential surface of the active layer 12, and may further surround predetermined areas of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting element LD relative to the longitudinal direction, for example, the two base sides of the cylinder (at Figure 1a and Figure 1b In the embodiment, the top and bottom surfaces of the light emitting element LD are exposed without covering the two substrate sides.

[0057] In an embodiment, the insulating film INF may include silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium dioxide (TiO 2 ) is at least one insulating material, but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0058] In an embodiment, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF, the light emitting element LD may further include additional other components. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0059] For example, Figure 2a and Figure 2b As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. Figure 3a and Figure 3b As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0060] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. Each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, each of the electrode layers 14 and 15 may be formed by a transparent electrode material (such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO)) alone or in combination. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0061] In an embodiment, the insulating film INF may at least partially surround the outer circumferential surface of the electrode layers 14 and 15, or may not surround the outer circumferential surface. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, for example, at least one region of each of the electrode layers 14 and 15 may be exposed. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0062] If the insulating film INF is provided on the surface of the light-emitting element LD, specifically, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, at least one of the contact electrodes connected to the opposite ends of the light-emitting element LD). Therefore, the electrical stability of the light-emitting element LD can be ensured. In the description of each embodiment of the present disclosure, the term "connection (or combination)" may generally refer to physical and / or electrical connection (or combination). In addition, the term "connection (or combination)" may generally refer to direct and / or indirect connection (or combination) and integral or non-integrated connection.

[0063] In addition, due to the insulating film INF formed on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on each light emitting element LD, even when a plurality of light emitting elements LD are disposed adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0064] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, each light emitting element LD may be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed rather than unevenly aggregated in the solution.

[0065] In a non-limiting embodiment related hereto, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material (such as Teflon TM or Cytop TM ) or corresponding materials.

[0066] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in a display device, but also in various devices that require a light source. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices that require a light source, such as a lighting device.

[0067] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device is shown, and in particular, a display panel PNL provided in the display device is shown as a reference. Figures 1a to 3b The light emitting element LD is described as an example of a means of a light source. For example, each pixel unit PXU of the display panel PNL and each pixel forming the pixel unit PXU may include a plurality of light emitting elements LD.

[0068] For illustration purposes, Figure 4 The structure of the display panel PNL focusing on the display area DA according to the embodiment is simply shown. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0069] Reference Figure 4, the display panel PNL according to an embodiment of the present disclosure may include a base layer BSL and a plurality of pixels disposed on the base layer BSL. In an embodiment, the pixel may include a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color, and / or a third pixel PXL3 configured to emit light of a third color. In the following embodiments, the term "pixel PXL" or "plurality of pixels PXL" will be used to collectively refer to any one pixel or two or more pixels among the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0070] In detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area except the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0071] In an embodiment, the display area DA may be disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed in the peripheral area of ​​the display panel PNL in such a manner as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0072] The base layer BSL may form a base of the display panel PNL. In an embodiment, the base layer BSL may be a rigid or flexible substrate or film, and its material or properties are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not particularly limited.

[0073] In addition, the base layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the base layer BSL may be a transparent, translucent, opaque, or reflective base.

[0074] One area on the base layer BSL may be defined as a display area DA in which pixels PXL are disposed, and another area thereof may be defined as a non-display area NDA. For example, the base layer BSL may include a display area DA and a non-display area NDA disposed around the display area DA, the display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed. Each pixel area may generally refer to a pixel circuit area in which a pixel circuit of a corresponding pixel PXL is formed and / or an emission area in which a light emitting element of a light source (or light source unit) constituting the pixel PXL and a first electrode and a second electrode connected thereto are disposed. Various lines and / or internal circuits of the pixels PXL connected to the display area DA may be disposed in the non-display area NDA.

[0075] A plurality of pixels PXL are dispersed and arranged in the display area DA. For example, the plurality of pixels PXL may be regularly arranged in the display area DA in a stripe or five-tile (or PenTile) arrangement manner. The arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and / or schemes.

[0076] In an embodiment, two or more pixels PXL emitting light of different colors may be disposed in the display area DA. For example, a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color, and a third pixel PXL3 configured to emit light of a third color may be disposed in the display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 disposed adjacent to each other may form one pixel unit PXU that may emit light of different colors.

[0077] In an embodiment, each first pixel PXL1 may be a red pixel that emits red light, each second pixel PXL2 may be a green pixel that emits green light, and each third pixel PXL3 may be a blue pixel that emits blue light. In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light-emitting element associated with a first color, a light-emitting element associated with a second color, and a light-emitting element associated with a third color as light sources, so that the pixels may emit light of the first color, light of the second color, and light of the third color, respectively. In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may respectively have light-emitting elements configured to emit light of the same color, and may respectively include color filters and light conversion layers having different colors and disposed on corresponding light-emitting elements to respectively emit light of the first color, light of the second color, and light of the third color.

[0078] However, the color, type, and / or number of the pixels PXL forming each pixel unit PXU are not particularly limited. For example, the color of light to be emitted from each pixel PXL may be changed in various ways.

[0079] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first power source and a second power source). Figures 1a to 3b The light-emitting element LD of any one of the embodiments, for example, has at least one ultra-small rod-type light-emitting element LD corresponding to a small size of nanometer to micrometer scale. However, in the embodiment of the present disclosure, the type of light-emitting element LD that can be used as the light source of the pixel PXL is not limited thereto. For example, in an embodiment, each pixel PXL may include a light-emitting element having a core-shell structure and manufactured by a growth method. In an embodiment, the light-emitting element having a core-shell structure may be an ultra-small core-shell light-emitting element having a small size corresponding to nanometer to micrometer scale, but the size of the light-emitting element having a core-shell structure is not limited.

[0080] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL that can be applied to the display device according to the present disclosure is not particularly limited. For example, each pixel PXL may have a structure that is the same as that of a pixel for a passive or active light-emitting display device having various known structures and / or that can operate with various known driving schemes.

[0081] Figure 5a to Figure 5e 1 and 2 are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figure 5a to Figure 5e Different embodiments of the pixel PXL that can be applied to an active display device are shown. However, the types of the pixel PXL and the display device to which the embodiments of the present disclosure can be applied are not limited thereto. In the embodiments, Figure 5a to Figure 5e Each pixel PXL shown in FIG. 1 may be set to Figure 4 Any one of the pixels PXL on the display panel PNL. The pixels PXL may have substantially the same or similar structures. For example, Figure 5a to Figure 5e Each pixel PXL shown in FIG. 1 may be Figure 4 The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same structure.

[0082] Reference Figure 5aThe pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further include a pixel circuit PXC configured to drive the light source unit LSU.

[0083] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected to each other between a first power source VDD supplying a first power voltage and a second power source VSS supplying a second power voltage. For example, the light source unit LSU may include a first electrode ET1 connected to the first power source VDD, a second electrode ET2 connected to the second power source VSS, and a plurality of light emitting elements LD connected in parallel to each other between the first electrode ET1 and the second electrode ET2 in the same direction. In an embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

[0084] In an embodiment, each light emitting element LD may include a P-type terminal connected to a first power source VDD through a first electrode ET1 and an N-type terminal connected to a second power source VSS through a second electrode ET2. In an embodiment, the light emitting element LD may be connected in parallel between the first electrode ET1 and the second electrode ET2 in a forward direction. In this way, each light emitting element LD connected between the first power source VDD and the second power source VSS in a forward direction may form an effective light source. A group of effective light sources may form a light source unit LSU of a pixel PXL.

[0085] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, at least during the emission period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or more.

[0086] In an embodiment, a first end (e.g., a P-type end) of the light emitting element LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through one electrode of the light source unit LSU (e.g., a first electrode ET1 (also referred to as a "first pixel electrode") of each pixel PXL), and may be connected to the first power source VDD through the pixel circuit PXC and the first power line PL1. A second end (e.g., an N-type end) of the light emitting element LD may be commonly connected to the second power source VSS through another electrode of the light source unit LSU (e.g., a second electrode ET2 (also referred to as a "second pixel electrode") of each pixel PXL) and the second power line PL2.

[0087] The light emitting element LD of the light source unit LSU can emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can supply a driving current corresponding to the grayscale value of the data of the corresponding frame to the light source unit LSU. The driving current supplied to the light source unit LSU can be divided into a portion flowing to the light emitting element LD connected in the forward direction. Therefore, each light emitting element LD can emit light having a brightness corresponding to the current applied thereto, so that the light source unit LSU can emit light having a brightness corresponding to the driving current.

[0088] In an embodiment, the light source unit LSU may further include at least one ineffective light source in addition to the light emitting elements LD forming each effective light source. For example, at least one reverse light emitting element LDrv may be further connected between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0089] Each reverse light-emitting element LDrv together with the light-emitting element LD forming an effective light source can be connected in parallel with each other between the first electrode ET1 and the second electrode ET2, and each reverse light-emitting element LDrv can be connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to the direction of the light-emitting element LD. For example, the N-type end of the reverse light-emitting element LDrv can be connected to the first power supply VDD via the first electrode ET1. The P-type end of the reverse light-emitting element LDrv can be connected to the second power supply VSS via the second electrode ET2. Even when a predetermined driving voltage (e.g., a normal direction driving voltage) is applied between the first electrode ET1 and the second electrode ET2, the reverse light-emitting element LDrv remains ineffective. Therefore, current does not substantially flow through the reverse light-emitting element LDrv.

[0090] In an embodiment, in the step of aligning the light emitting element LD between the first electrode ET1 and the second electrode ET2 to form each light source unit LSU, the light emitting element LD supplied to each pixel area (e.g., the emission area of ​​each pixel PXL) may be controlled to be aligned and biased in any one direction (e.g., the forward direction) by adjusting the alignment signal (or alignment voltage) to be applied to the first electrode ET1 and the second electrode ET2 or forming a magnetic field. In this case, at least one reverse light emitting element LDrv connected in the reverse direction may be further connected between the first electrode ET1 and the second electrode ET2 of each pixel PXL together with the plurality of light emitting elements LD connected in the forward direction. In an embodiment, in the case where the light emitting element LD is biased and aligned to increase the number of light emitting elements LD connected between the first electrode ET1 and the second electrode ET2 of each pixel PXL in the forward direction, the number of reverse light emitting elements LDrv connected between the first electrode ET1 and the second electrode ET2 in the reverse direction may be less than the number of light emitting elements LD connected in the forward direction. For example, the number of reverse light emitting elements LDrv connected between the first electrode ET1 and the second electrode ET2 in the reverse direction may be 30% or less of the number of light emitting elements LD connected in the forward direction.

[0091] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0092] The first transistor (also referred to as a "driving transistor") T1 is connected between the first power source VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0093] The second transistor (also referred to as a "switching transistor") T2 may be connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0094] During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0095] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode thereof is connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal to be supplied to the first node N1 during each frame period.

[0096] Despite Figure 5a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0097] For example, Figure 5b As shown in , both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj to the pixel PXL in each frame period may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of the gate-on voltage. Figure 5a The voltage level of the embodiment is opposite to the voltage level. For example, in Figure 5b In the embodiment, as the grayscale value to be expressed increases, a data signal with a higher voltage may be supplied.

[0098] In addition to the connection positions of some circuit elements and the voltage levels of control signals (eg, scan signals and data signals) being changed according to the type of transistor, Figure 5b The pixel PXL shown in FIG. 1 is similar in construction and operation to the Figure 5a The pixel PXL shown in FIG. 1 is substantially similar. Therefore, the pixel PXL shown in FIG. 1 is omitted. Figure 5b A detailed description of the pixel PXL.

[0099] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a well-known pixel circuit that may have various structures and / or may be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a well-known pixel circuit that may have various structures and / or may be operated by various driving schemes. Figure 5c is constructed in the same manner as the embodiment shown in FIG.

[0100] Reference Figure 5c, the pixel circuit PXC can be connected not only to the scan line Si in the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged on the i-th row of the display area DA can also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to the third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0101] The first transistor T1 may be connected between the first power source VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power source VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 may be connected to the first electrode of the light source unit LSU (e.g., the first contact electrode and / or the first pixel electrode of the corresponding pixel PXL) via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control the driving current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0102] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj can be transmitted to the first transistor T1.

[0103] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 can be turned on to electrically connect the first transistor T1 in a diode form.

[0104] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 may be the lowest voltage of the data signal or less.

[0105] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having a gate cut-off voltage (for example, a high level voltage) is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and may be turned on in other cases.

[0106] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having the gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and may be turned on in other cases.

[0107] The seventh transistor T7 is connected between the second node N2 and the initialization power supply Vint, and the first electrode of the light source unit LSU (for example, the first pixel electrode ET1 of the corresponding pixel PXL) is connected to the second node N2. The gate electrode of the seventh transistor T7 is connected to any one scan line of the next level (the next horizontal pixel column), for example, connected to the i+1th scan line Si+1. When the scan signal of the gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 can be turned on so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU can be initialized. The control signal for controlling the operation of the seventh transistor T7 can be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 can be connected to the scan line of the corresponding horizontal row, that is, the i-th scan line Si. In this case, when a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power source Vint may be supplied to the first electrode of the light source unit LSU.

[0108] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0109] Despite Figure 5c , the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0110] although Figure 5a to Figure 5c 1 and 2 show an embodiment in which all effective light sources (ie, light emitting elements LD) constituting each light source unit LSU are connected in parallel to each other, but the present disclosure is not limited thereto. Figure 5d and Figure 5e As shown in FIG. 1 , the light source unit LSU of each pixel PXL may be configured to include a series structure. Figure 5d and Figure 5e In the description of the embodiment of Figure 5a to Figure 5c Detailed description of components similar or identical to components of the embodiments (e.g., pixel circuit PXC).

[0111] Reference Figure 5d , the light source unit LSU may include a plurality of light emitting elements connected in series with each other. For example, the light source unit LSU may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3 connected in series between a first power source VDD and a second power source VSS in a forward direction and constituting each effective light source. Hereinafter, when a specific light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 is specified, the corresponding light emitting element will be referred to as the first light emitting element LD1, the second light emitting element LD2, or the third light emitting element LD3. The term "light emitting element LD" or "a plurality of light emitting elements LD" will be used to arbitrarily specify at least one of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, or collectively specify as the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3.

[0112] The P-type end of the first light emitting element LD1 may be connected to the first power source VDD through the first electrode ET1 of the light source unit LSU. The N-type end of the first light emitting element LD1 may be connected to the P-type end of the second light emitting element LD2. The P-type end of the second light emitting element LD2 may be connected to the N-type end of the first light emitting element LD1. The N-type end of the second light emitting element LD2 may be connected to the P-type end of the third light emitting element LD3. The P-type end of the third light emitting element LD3 may be connected to the N-type end of the second light emitting element LD2. The N-type end of the third light emitting element LD3 may be connected to the second power source VSS through the second electrode ET2 of the light source unit LSU and the second power line PL2. In this way, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be connected in series between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0113] Despite Figure 5d , the light emitting elements LD are connected to have a three-stage series structure, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, two light emitting elements LD may be connected to have a two-stage series structure, or four or more light emitting elements LD may be connected to have a four-stage or more series structure.

[0114] When it is assumed that the same brightness is expressed using light emitting elements LD having the same conditions (e.g., the same size and / or number), in the light source unit LSU having a structure in which the light emitting elements LD are connected in series, the voltage to be applied between the first electrode ET1 and the second electrode ET2 can be increased, and the amount of driving current flowing to the light source unit LSU can be reduced compared to the light source unit LSU having a structure in which the light emitting elements LD are connected in parallel. Therefore, in the case where the light source unit LSU of each pixel PXL is formed of a series structure, as the display device is driven, the panel current flowing through the display panel PNL can be reduced. Therefore, power consumption can be reduced.

[0115] In an embodiment, at least one series stage may include a plurality of light emitting elements LD connected in parallel to each other. In this case, the light source unit LSU may be formed by a series / parallel combination structure. For example, the light source unit LSU may be formed by a series / parallel combination structure. Figure 5e The embodiment shown is constructed.

[0116] Reference Figure 5e, each series connection stage of the light source unit LSU may include a plurality of light emitting elements LD connected in parallel to each other. For example, the light source unit LSU may include a plurality of first light emitting elements LD1 disposed in a first series connection stage (also referred to as the "first stage" or the "first row") and a plurality of second light emitting elements LD2 disposed in a second series connection stage (also referred to as the "second stage" or the "second row") after the first series connection stage. In addition, the light source unit LSU may selectively further include at least one series connection stage after the second series connection stage. For example, the light source unit LSU may also include a plurality of third light emitting elements LD3 disposed in a third series connection stage (referred to as the "third stage" or the "third row") after the second series connection stage. In an embodiment, at least one series connection stage may further include at least one reverse light emitting element LDrv, but the present disclosure is not limited thereto. For example, each pixel PXL may also include at least one reverse light emitting element LDrv connected in a direction opposite to that of the light emitting element LD in at least one of the plurality of series connection stages. In an embodiment, when the light emitting element LD is aligned by controlling an alignment signal (or alignment voltage) or forming a magnetic field so that the light emitting element LD supplied to each pixel area (e.g., the emission area of ​​each pixel PXL) is biased in any one direction (e.g., the forward direction), the number of reverse light emitting elements LDrv arranged in each pixel PXL can be less than the number of effective light sources (i.e., the light emitting element LD) arranged along the forward direction in the pixel PXL.

[0117] The first light emitting element LD1 may be connected in parallel to each other between the first electrode ET1[1] and the second electrode ET2[1] of the first series stage. The second light emitting element LD2 may be connected in parallel to each other between the first electrode ET1[2] and the second electrode ET2[2] of the second series stage. The third light emitting element LD3 may be connected in parallel to each other between the first electrode ET1[3] and the second electrode ET2[3] of the third series stage.

[0118] In an embodiment, the first electrodes ET1[1] to ET1[3] and the second electrodes ET2[1] to ET2[3] provided in each series stage may form sub-electrodes (or also referred to as "separate electrodes") dispersed and provided in the light source unit LSU. Hereinafter, the term "first electrode ET1" (also referred to as "first sub-electrode") will be used to arbitrarily specify at least one first electrode among the first electrodes ET1[1] to ET1[3] (also referred to as "first sub-electrodes") provided in each series stage, or to collectively specify the first electrodes ET1[1] to ET1[3] provided in each series stage. Similarly, the term "second electrode ET2" (also referred to as "second sub-electrode") will be used to arbitrarily specify at least one second electrode among the second electrodes ET2[1] to ET2[3] (also referred to as "second sub-electrodes") provided in each series stage, or to collectively specify the second electrodes ET2[1] to ET2[3] provided in each series stage.

[0119] In this way, in the case where the light source unit LSU of each pixel PXL is constructed by connecting a plurality of light emitting elements LD in a series / parallel combination structure, the driving current / voltage conditions can be easily controlled to correspond to the specifications of the desired product. For example, when it is assumed that light emitting elements LD having the same conditions (e.g., the same size and / or number) are used and the same brightness is expressed, the same conditions as those having the same size and / or number are used. Figure 5a to Figure 5c Compared with the driving current of the light source unit LSU of the structure in which all the light emitting elements LD are connected in parallel with each other as shown in the embodiment of FIG. 1 , the light source unit LSU in which the light emitting elements LD are connected in a series / parallel combination structure can reduce the driving current and is Figure 5d Compared with the driving voltage of the light source unit LSU of the structure in which all the light emitting elements LD are connected in series as shown in the embodiment of the present invention, the driving voltage to be applied to the opposite end of the light source unit LSU can be reduced. In the case where all the light emitting elements LD are connected in series, if at least one of the light emitting elements LD connected in series with each other is not completely connected in the forward direction, the path along which the driving current can flow in the pixel PXL is blocked, thereby possibly causing a black spot defect. On the other hand, in the case where the light emitting elements LD are connected to each other in a series / parallel combination structure, even if some of the light emitting elements LD in each series stage are not completely connected in the forward direction or defects occur in some of the light emitting elements LD, the driving current is allowed to flow through other light emitting elements LD of the corresponding series stage. Therefore, defects of the pixel PXL can be prevented or reduced.

[0120] As shown in the foregoing embodiments, the pixel PXL according to the embodiments of the present disclosure may include a pixel circuit PXC and / or a light source unit LSU that may have various structures. The structure of the pixel PXL that may be applied to the present disclosure is not limited to Figure 5a to Figure 5e, and each pixel PXL may have various well-known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a well-known pixel circuit that may have various structures and / or may be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be constructed in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode ET1 and the second electrode ET2 of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0121] Figure 6 and Figure 7 are plan views each showing a pixel PXL according to an embodiment of the present disclosure, for example, Figure 6 and Figure 7 Shown include Figure 4 Different embodiments of the pixel unit PXU of the first pixel PXL1, the second pixel PXL2 and the third pixel PXL3. For example, Figure 6 and Figure 7 Various embodiments regarding the shapes and arrangement structures of the first and second electrodes ET1 and ET2 are shown.

[0122] In an embodiment, Figure 6 and Figure 7 Each pixel PXL shown in FIG. 1 may be Figure 5a to Figure 5e Any one of the pixels PXL shown in . For example, Figure 6 and Figure 7 Each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 shown in FIG. Figure 5e The pixel PXL includes a plurality of light emitting elements LD connected in a series / parallel combination structure as shown in the embodiment.

[0123] In the embodiment, the display area ( Figure 4 The pixels PXL in the DA) may have substantially the same or similar structures. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same structure. Therefore, hereinafter, the structure of each pixel PXL will be described based on the first pixel PXL1.

[0124] In an embodiment, Figure 6 and Figure 7 The structure of each pixel PXL with the light source unit LSU of the pixel PXL as the center is shown. Here, each pixel PXL may further include a circuit element (eg, forming a circuit element) for controlling each light source unit LSU. Figure 5a to Figure 5eIn an embodiment, the circuit element may be disposed on a layer different from the layer of the light source unit LSU. For example, the circuit element may be disposed on a substrate layer ( Figure 4 The light source unit LSU may be disposed in a pixel circuit layer on one surface of a BSL, and the display element layer is disposed on the pixel circuit layer.

[0125] also, Figure 6 and Figure 7 An embodiment is shown in which each light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (e.g., at least one circuit element forming a pixel circuit PXC), and / or a signal line (e.g., a scan line Si and / or a data line Dj) through a first contact hole CH1 and a second contact hole CH2, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ET1 and the second electrode ET2 of each pixel PXL may be directly connected to a predetermined power line and / or a signal line without using, for example, a contact hole and / or an intermediate line.

[0126] Reference Figures 4 to 7 , each pixel PXL (for example, the first pixel PXL1) according to an embodiment of the present disclosure may include a plurality of light emitting elements LD disposed in a plurality of series stages. For example, each pixel PXL may include a first light emitting element to a K-th light emitting element LD respectively disposed in a first series stage to a K-th (K is a natural number of 2 or greater) series stage. In an embodiment, the first light emitting element to the K-th light emitting element LD may be respectively disposed in a first sub-region to a K-th sub-region. For example, each pixel PXL may include a first sub-region to a K-th sub-region corresponding to the first series stage to the K-th (K is a natural number of 2 or greater) series stage, respectively, and a first light emitting element to a K-th light emitting element LD respectively disposed in the first sub-region to the K-th sub-region.

[0127] For example, when the pixel PXL includes a plurality of light emitting elements LD (e.g., first to third light emitting elements LD1 to LD3) arranged in three series stages (e.g., first, second, and third series stages) and constituting each light source unit LSU, the pixel PXL may include a first sub-region SAR1 corresponding to the first series stage and in which at least one first light emitting element LD1 is arranged, a second sub-region SAR2 corresponding to the second series stage and in which at least one second light emitting element LD2 is arranged, and a third sub-region SAR3 corresponding to the third series stage and in which at least one third light emitting element LD3 is arranged. Hereinafter, the term "sub-region SAR" or "plurality of sub-regions SAR" will be used to arbitrarily designate at least one of the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3, or to designate a plurality of sub-regions collectively.

[0128] In addition, each pixel PXL may include a first electrode ET1 and a second electrode ET2 of each series connection stage disposed at positions spaced apart from each other in each of the first to K-th sub-regions SAR. For example, each pixel PXL may include a first electrode ET1[1] and a second electrode ET2[1] of a first series connection stage disposed at positions spaced apart from each other in the first sub-region SAR1, a first electrode ET1[2] and a second electrode ET2[2] of a second series connection stage disposed at positions spaced apart from each other in the second sub-region SAR2, and a first electrode ET1[3] and a second electrode ET2[3] of a third series connection stage disposed at positions spaced apart from each other in the third sub-region SAR3.

[0129] At least one effective light source may be connected between the first electrode ET1 and the second electrode ET2 of each series connection stage. For example, a plurality of light emitting elements LD may be connected between the first electrode ET1 and the second electrode ET2 of each series connection stage in a forward direction. In other words, in the present embodiment, each sub-region SAR may be a region including the first electrode ET1 and the second electrode ET2 constituting each series connection stage and at least one light emitting element LD electrically connected between the first electrode ET1 and the second electrode ET2.

[0130] In addition, each pixel PXL may further include a plurality of electrode lines. For example, each pixel PXL may further include a first electrode line MLI1 connected to a first electrode of a first series connection stage (e.g., a first electrode ET1[1] of a first sub-region SAR1), a second electrode line MLI2 connected to a second electrode of a last series connection stage (e.g., a second electrode ET2[3] of a third sub-region SAR3), and at least one intermediate electrode SLI disposed between two consecutive sub-regions SAR.

[0131] In an embodiment, the first sub-region to the K-th sub-region SAR (e.g., the first sub-region SAR1 to the third sub-region SAR3) corresponding to the first series connection stage to the K-th series connection stage (e.g., the first series connection stage to the third series connection stage) respectively may be continuously arranged in the emission area EMA of the corresponding pixel PXL. For example, the emission area EMA of each pixel PXL may include the first sub-region to the K-th sub-region SAR continuously arranged in the first direction DR1. In an embodiment, the first direction DR1 may be a vertical direction (or a column direction), but the present disclosure is not limited thereto. For example, in an embodiment, the first direction DR1 may be a horizontal direction (or a row direction). Alternatively, in an embodiment, the first direction DR1 may be a diagonal direction.

[0132] For example, if each light source unit LSU includes a plurality of light emitting elements LD dispersed in three series stages, the emission area EMA in which the light source unit LSU is disposed may be divided into three sub-areas SAR with respect to the first direction DR1. In other words, the emission area EMA of each pixel PXL may include a plurality of sub-areas SAR in which the light emitting elements LD of the series stages constituting the light source unit LSU of the pixel PXL and the first and second electrodes ET1 and ET2 are disposed. In an embodiment, each emission area EMA may further include an area formed between the sub-areas SAR.

[0133] For example, the emission area EMA may include first, second, and third subregions SAR1, SAR2, and SAR3 continuously arranged in the first direction DR1 and an area formed between the first, second, and third subregions SAR1, SAR2, and SAR3 (e.g., an area in which each intermediate electrode SLI is arranged).

[0134] In an embodiment, the emission area EMA of each pixel PXL may refer to an area where a light emitting element LD forming a light source unit LSU of at least the corresponding pixel PXL is disposed. The emission area EMA may be defined by a dam structure (also referred to as a "pixel defining layer"), etc. For example, a light shielding dam including an opening for exposing the emission area EMA of each pixel PXL may be disposed between the pixels PXL.

[0135] In the first sub-region SAR1, at least one first series first electrode ET1[1], at least one first series second electrode ET2[1] spaced apart from the first series first electrode ET1[1], and at least one first light emitting element (e.g., a plurality of first light emitting elements connected in parallel to each other) LD1 electrically connected between the first series first electrode ET1[1] and the first series second electrode ET2[1] may be provided. Similarly, in the second sub-region SAR2, at least one second series first electrode ET1[2], at least one second series second electrode ET2[2] spaced apart from the second series first electrode ET1[2], and at least one second light emitting element (e.g., a plurality of second light emitting elements connected in parallel to each other) LD2 electrically connected between the second series first electrode ET1[2] and the second series second electrode ET2[2] may be provided. In addition, in the case where the pixel PXL also includes a third sub-region SAR3 corresponding to the third series stage, in the third sub-region SAR3, at least one third series stage first electrode ET1[3], at least one third series stage second electrode ET2[3] spaced apart from the third series stage first electrode ET1[3], and at least one third light emitting element (for example, a plurality of third light emitting elements connected in parallel to each other) LD3 electrically connected between the third series stage first electrode ET1[3] and the third series stage second electrode ET2[3] can be provided.

[0136] The first and second electrodes ET1 and ET2 of each series stage may be disposed at positions spaced apart from each other in each corresponding sub-region SAR. In an embodiment, the first and second electrodes ET1 and ET2 of each series stage may be regularly arranged in each corresponding sub-region SAR, but the present disclosure is not limited thereto.

[0137] In an embodiment, the first electrode ET1 and the second electrode ET2 may have a strip shape extending in any one direction in each sub-region SAR. For example, the first electrode ET1 and the second electrode ET2 may each have a strip shape extending in the first direction DR1 in the corresponding sub-region SAR, and may be arranged in parallel with each other. For example, the first electrode ET1 and the second electrode ET2 of each series stage may extend in the first direction DR1 in each corresponding sub-region SAR, and may be continuously or alternately arranged at positions spaced apart from each other in the second direction DR2 intersecting the first direction DR1. In an embodiment, the first electrode ET1 and the second electrode ET2 may be arranged in each sub-region SAR at regular intervals. Therefore, the light emitting element LD may be aligned more regularly in each sub-region SAR.

[0138] However, the shapes, orientations and / or relative arrangement structures of the first and second electrodes ET1 and ET2 are not limited thereto and may be changed in various ways. For example, in an embodiment, the first and second electrodes ET1 and ET2 of each series stage may be arranged at positions spaced apart from each other in a double helix structure or the like.

[0139] Each first electrode ET1 may be electrically connected to a first electrode line (also referred to as a "first main electrode line" or a "first main alignment line") MLI1 or a second electrode ET2 of a previous series stage. For example, a first electrode ET1[1] of a first series stage as a first series stage may be connected to the first electrode line MLI1 integrally or non-integrally. In an embodiment, in the case where the first electrode ET1[1] of the first series stage and the first electrode line MLI1 are integrally connected to each other, the first electrode ET1[1] of the first series stage and the first electrode line MLI1 may be considered as different regions of one electrode, one line, or one pattern.

[0140] The first electrode ET1 of each of the other series stages can be electrically connected to the second electrode ET2 of the previous series stage. For example, the first electrode ET1[2] of the second series stage can be connected to the second electrode ET2[1] of the first series stage integrally or non-integrally. The first electrode ET1[3] of the third series stage can be connected to the second electrode ET2[2] of the second series stage integrally or non-integrally.

[0141] Each second electrode ET2 can be electrically connected to the first electrode ET1 or the second electrode line (also referred to as a "second main electrode line" or a "second main alignment line") MLI2 of the subsequent series stage. For example, the second electrode ET2[1] of the first series stage can be connected to the first electrode ET1[2] of the second series stage. The second electrode ET2[2] of the second series stage can be connected to the first electrode ET1[3] of the third series stage. In the case where each light source unit LSU includes only two series stages, the second electrode ET2[2] of the second series stage can be connected to the second electrode line MLI2 integrally or non-integrally.

[0142] The second electrode ET2[3] of the last K-th series stage (e.g., the third series stage) may be connected to the second electrode line MLI2 integrally or non-integrally. In an embodiment, when the second electrode ET2[3] of the third series stage and the second electrode line MLI2 are integrally connected to each other, the second electrode ET2[3] of the third series stage and the second electrode line MLI2 may be considered as one electrode, one line, or different regions of one pattern.

[0143] In an embodiment, the first electrode ET1 and the second electrode ET2 may be arranged in each emission area EMA in a regular pattern. In addition, the corresponding number of the first electrode ET1 and the second electrode ET2 arranged in each sub-area SAR is not particularly limited. For example, each sub-area SAR may include one or more first electrodes ET1 and second electrodes ET2, and the corresponding numbers of the first electrodes ET1 and second electrodes ET2 may be the same or different from each other.

[0144] In an embodiment, Figure 6 As shown in , the first electrode ET1 and the second electrode ET2 may be arranged in two consecutive sub-regions SAR in a shape in which the first electrode ET1 and the second electrode ET2 are symmetrical to each other based on the intermediate electrode SLI arranged between the two sub-regions SAR. For example, in the first sub-region SAR1, two first series-stage first electrodes ET1[1] may be arranged, and one first series-stage second electrode ET2[1] parallel to the first series-stage first electrode ET1[1] may be arranged between the first series-stage first electrodes ET1[1]. In the second sub-region SAR2, one second series-stage first electrode ET1[2] integrally connected to one first series-stage second electrode ET2[1] may be arranged to be symmetrical to the first series-stage second electrode ET2[1] based on the first intermediate electrode SLI1 arranged between the first sub-region SAR1 and the second sub-region SAR2, and two second series-stage second electrodes ET2[2] may be arranged on opposite sides of one second series-stage first electrode ET1[2] so that the two second series-stage second electrodes ET2[2] are symmetrical to the two first series-stage first electrodes ET1[1] based on the first intermediate electrode SLI1. Similarly, in the third sub-region SAR3, two third series stage first electrodes ET1[3] integrally connected to the two second series stage second electrodes ET2[2] can be arranged to be symmetrical with the two second series stage second electrodes ET2[2] based on the second intermediate electrode SLI2 arranged between the second sub-region SAR2 and the third sub-region SAR3, and one third series stage second electrode ET2[3] can be arranged between the two third series stage first electrodes ET1[3], so that one third series stage second electrode ET2[3] is symmetrical with the one second series stage first electrode ET1[2] based on the second intermediate electrode SLI2.

[0145] In an embodiment, Figure 7As shown in , the first electrode ET1 and the second electrode ET2 may be arranged in each sub-region SAR in the same repeating pattern. For example, in each of the first sub-region SAR1 to the third sub-region SAR3, two first electrodes ET1 may be arranged, and one second electrode ET2 may be arranged between the two first electrodes ET1 so that the second electrode ET2 is parallel to the first electrode ET1. In other words, the shapes and arrangement structures of the first electrode ET1 and the second electrode ET2 may be changed in various ways according to the embodiment.

[0146] At least one light emitting element LD (e.g., a plurality of light emitting elements LD) may be connected between the first electrode ET1 and the second electrode ET2 of each series connection. For example, a plurality of first light emitting elements LD1 may be connected in parallel between the first electrode ET1[1] and the second electrode ET2[1] of the first series connection. Similarly, a plurality of second light emitting elements LD2 may be connected in parallel between the first electrode ET1[2] and the second electrode ET2[2] of the second series connection, and a plurality of third light emitting elements LD3 may be connected in parallel between the first electrode ET1[3] and the second electrode ET2[3] of the third series connection.

[0147] In an embodiment, each light emitting element LD may be a light emitting element made of a material having an inorganic crystal structure and having an ultra-small size (eg, ranging from nanometer to micrometer). Figures 1a to 3b As shown in , each light emitting element LD may be an ultra-small rod-type light emitting element having a size ranging from nanometer level to micrometer level. The size, type, shape, etc. of the light emitting element LD may be changed in various ways.

[0148] although Figure 6 and Figure 7 In the region where a pair of first electrodes ET1 and second electrodes ET2 are disposed to face each other, each light emitting element LD is uniformly arranged horizontally between the first electrode ET1 and the second electrode ET2 along the second direction DR2, but the present disclosure is not limited thereto. For example, at least one of the light emitting elements LD may be arranged and / or connected along a diagonal direction between the first electrode ET1 and the second electrode ET2. Alternatively, although Figure 6 and Figure 7 Not shown, but at least one light emitting element (eg, an ineffective light source other than the reverse light emitting element LDrv) that is not completely connected between the first electrode ET1 and the second electrode ET2 may be further disposed in each sub-region SAR and / or a region disposed around the sub-region SAR.

[0149] In an embodiment, the light emitting element LD may be prepared in a diffused form in a predetermined solution, and then may be supplied to the emission area EMA of each pixel PXL by an inkjet scheme or the like. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to each emission area EMA. Here, if a predetermined alignment signal (or alignment voltage) is applied to the first electrode ET1 and the second electrode ET2, an electric field is formed between the first electrode ET1 and the second electrode ET2, whereby the light emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2. After aligning the light emitting element LD, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting element LD may be reliably disposed between the first electrode ET1 and the second electrode ET2.

[0150] Each light emitting element LD may include a first terminal EP1 connected to a first electrode ET1 of a corresponding series stage and a second terminal EP2 connected to a second electrode ET2 of a corresponding series stage. In an embodiment, the first terminal EP1 may be a P-type terminal, and the second terminal EP2 may be an N-type terminal.

[0151] In an embodiment, each light emitting element LD may be connected between the first electrode ET1 and the second electrode ET2 of each series stage in the forward direction. For example, the first end EP1 of each light emitting element LD may be directly connected to the first electrode ET1 of any series stage, or may be connected to the first electrode ET1 of any series stage through at least one contact electrode. Similarly, the second end EP2 of each light emitting element LD may be directly connected to the second electrode ET2 of any series stage, or may be connected to the second electrode ET2 of any series stage through at least one contact electrode. The light emitting element LD connected between the first electrode ET1 and the second electrode ET2 of each series stage in the forward direction may form an effective light source of the corresponding series stage.

[0152] Despite Figure 6 and Figure 7 , but at least one series stage may further include at least one reverse light emitting element (e.g., in a reverse direction) connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to the direction of the light emitting element LD constituting the corresponding effective light source. Figure 5a to Figure 5e For example, at least one sub-region SAR may include at least one reverse light emitting element LDrv connected between the first electrode ET1 and the second electrode ET2 in the reverse direction. The at least one reverse light emitting element LDrv may remain disabled in the pixel PXL.

[0153] During the period in which the display device is operated, the first electrode line MLI1 may be supplied with a voltage of a first power source VDD (e.g., a first power voltage) or a first drive signal (e.g., a scan signal, a data signal, or a predetermined other control signal). In an embodiment, the first electrode line MLI1 may be electrically connected to a first contact hole CH1, a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the first electrode line MLI1 may be electrically connected to a predetermined circuit element disposed thereunder through the first contact hole CH1, and may be connected to the first power line PL1 through the circuit element. For example, each pixel PXL may further include a pixel circuit PXC connected between the first electrode line MLI1 and the first power source VDD. In an embodiment, the pixel circuit PXC may be disposed under each light source unit LSU, and may be connected to the first electrode line MLI1 of the light source unit LSU through the first contact hole CH1. In an embodiment, the first electrode line MLI1 may be connected to a signal line supplied with a predetermined first drive signal via the first contact hole CH1, etc. In an embodiment, the first electrode line MLI1 may be directly connected to the first power line PL1 or the predetermined signal line without using the first contact hole CH1 and / or the circuit element. In this case, the first electrode line MLI1 may be integrally or non-integrally connected to the first power line PL1 or the predetermined signal line.

[0154] In an embodiment, a first electrode line MLI1 connected to a first series stage first electrode ET1[1] of each pixel PXL may be first manufactured to be commonly connected to a plurality of pixels PXL, and a first alignment signal (or a first alignment voltage) may be supplied in the step of aligning the light emitting element LD. Thereafter, the first electrode line MLI1 between the pixels PXL may be disconnected so that the pixels PXL may be manufactured to be individually operable. For example, the first electrode line MLI1 may be disconnected between a first pixel PXL1 and a second pixel PXL2 adjacent to each other, between a second pixel PXL2 and a third pixel PXL3 adjacent to each other, and between pixel units PXU adjacent to each other, so that the corresponding pixels PXL may be separated from each other to be individually operable. In other words, in an embodiment, the first electrode line MLI1 of the pixel PXL may be separated from each other between adjacent pixels PXL.

[0155] During the period in which the display device is operated, the second electrode line MLI2 may be supplied with a voltage of a second power source VSS (e.g., a second power voltage) or a second drive signal (e.g., a scan signal, a data signal, or a predetermined other control signal). In an embodiment, the second electrode line MLI2 may be electrically connected to a second contact hole CH2, a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the second electrode line MLI2 may be connected to a second power line PL2 disposed thereunder through a second contact hole CH2. In an embodiment, the second electrode line MLI2 may be directly connected to the second power line PL2 or a predetermined signal line without using, for example, a second contact hole CH2 and / or a circuit element. In this case, the second electrode line MLI2 may be connected integrally or non-integrally to the second power line PL2 or the predetermined signal line.

[0156] In an embodiment, the second electrode line MLI2 connected to the second electrode ET2[3] of the last series connection stage (e.g., the third series connection stage) of each pixel PXL may be commonly connected to a plurality of pixels PXL. For example, the second electrode lines MLI2 of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be integrally connected to each other. In an embodiment, the second electrode lines MLI2 of a plurality of pixel units PXU may be integrally connected to each other.

[0157] In the step of aligning the light emitting element LD, a predetermined second alignment signal (or second alignment voltage) may be supplied to the second electrode line MLI2. During a period in which the display device is actually driven, a voltage of a second power source VSS or a predetermined second driving signal may be supplied to the second electrode line MLI2.

[0158] In an embodiment, the first electrode line MLI1 and the second electrode line MLI2 may be disposed to face each other, and the first to K-th sub-regions SAR (e.g., the first to third sub-regions SAR1 to SAR3) of each pixel PXL are disposed between the first electrode line MLI1 and the second electrode line MLI2. For example, the first electrode line MLI1 of each pixel PXL may be disposed adjacent to the first sub-region SAR1 and connected to the first electrode ET1[1] of the first series connection stage disposed in the first sub-region SAR1. The second electrode line MLI2 of each pixel PXL may be disposed adjacent to the last sub-region SAR (e.g., the third sub-region SAR3) and connected to the second electrode ET2[3] of the third series connection stage disposed in the third sub-region SAR3. For example, the first electrode line MLI1 and the second electrode line MLI2 of each pixel PXL may be disposed above the first sub-region SAR1 and below the third sub-region SAR3, respectively, and electrically connected to the first electrode ET1[1] of the first sub-region SAR1 and the second electrode ET2[3] of the third sub-region SAR3, respectively.

[0159] For example, the first electrode line MLI1 and the second electrode line MLI2 may be arranged in parallel with each other, and the first sub-region to the K-th sub-region SAR of each pixel PXL are placed between the first electrode line MLI1 and the second electrode line MLI2. For example, each of the first electrode line MLI1 and the second electrode line MLI2 may extend in a second direction DR2 that intersects with the first direction DR1 along which the first electrode ET1 and the second electrode ET2 extend respectively. For example, each of the first electrode line MLI1 and the second electrode line MLI2 may extend in a direction perpendicular to the direction along which the first electrode ET1 and the second electrode ET2 extend respectively. In an embodiment, the second direction DR2 may be a horizontal direction (or a row direction), but the present disclosure is not limited thereto. For example, in an embodiment, the second direction DR2 may be a vertical direction (or a column direction). Alternatively, in an embodiment, the second direction DR2 may be a diagonal direction.

[0160] The electrode line MLI including the first electrode line MLI1 and the second electrode line MLI2 of each pixel PXL may be a main alignment line supplied with a predetermined alignment signal to be applied to each light source unit LSU in the step of aligning the light emitting element LD in each pixel PXL to manufacture the display device, and is disposed on a path along which an alignment current corresponding to the alignment signal flows. In addition, the electrode line MLI may be a main drive / power line supplied with a predetermined drive voltage to be applied to each light source unit LSU in response to a data signal of each frame in the step of driving the display device (for example, when the display device is used), and is disposed on a path along which a drive current of each pixel PXL flows.

[0161] Each intermediate electrode SLI may be electrically connected to both the second electrode ET2 disposed in the previous sub-region SAR of the two consecutive sub-regions SAR and the first electrode ET1 disposed in the subsequent sub-region SAR. For example, in the case where each pixel PXL includes a light source unit LSU formed of three series stages, the pixel PXL may include a first intermediate electrode SLI1 and a second intermediate electrode SLI2, the first intermediate electrode SLI1 being disposed between the first sub-region SAR1 and the second sub-region SAR2 and electrically connected to the second electrode ET2[1] of the first sub-region SAR1 and the first electrode ET1[2] of the second sub-region SAR2, and the second intermediate electrode SLI2 being disposed between the second sub-region SAR2 and the third sub-region SAR3 and electrically connected to the second electrode ET2[2] of the second sub-region SAR2 and the first electrode ET1[3] of the third sub-region SAR3.

[0162] In an embodiment, each intermediate electrode SLI may be integrally connected to the second electrode ET2 of the previous sub-region SAR and the first electrode ET1 of the next sub-region SAR. In this case, in the step of forming the first electrode ET1 and the second electrode ET2 of each series connection stage, the intermediate electrode SLI may be simultaneously formed between the series connection stages. Therefore, each intermediate electrode SLI may be formed between consecutive series connection stages without a separate additional process of forming the intermediate electrode SLI. According to the aforementioned embodiment, the process of manufacturing the pixel PXL and the display device including the pixel PXL may be simplified, and the manufacturing efficiency thereof may be improved.

[0163] In an embodiment, each intermediate electrode SLI may be disposed between the first electrode line MLI1 and the second electrode line MLI2, and may be spaced apart from each of the first electrode line MLI1 and the second electrode line MLI2, with at least one sub-region SAR interposed therebetween. For example, the first electrode line MLI1 and the second electrode line MLI2 and at least one intermediate electrode SLI of each pixel PXL may be disposed parallel to each other, with at least one sub-region SAR interposed therebetween.

[0164] For example, in the same manner as the first electrode lines MLI1 and the second electrode lines MLI2, each intermediate electrode SLI may extend in a direction crossing the direction along which the first electrode ET1 and the second electrode ET2 extend. For example, each intermediate electrode SLI may extend along the second direction DR2 between two consecutive sub-regions SAR.

[0165] In an embodiment, the intermediate electrode SLI of each series stage may be formed in a form commonly connected to a plurality of pixels PXL, and may be supplied with a predetermined intermediate level alignment signal (or intermediate alignment voltage) in the step of aligning the light emitting element LD. For example, the first intermediate electrode SLI1 of the first pixel PXL1 may be formed in a form commonly connected to the first intermediate electrodes SLI1 of the second pixel PXL2 and the third pixel PXL3, and may be supplied with a predetermined first intermediate level alignment signal (or first intermediate alignment voltage) in the step of aligning the light emitting element LD. The second intermediate electrode SLI2 of the first pixel PXL1 may be formed in a form commonly connected to the second intermediate electrodes SLI2 of the second pixel PXL2 and the third pixel PXL3, and may be supplied with a predetermined second intermediate level alignment signal (or second intermediate alignment voltage) in the step of aligning the light emitting element LD.

[0166] In other words, the intermediate electrode SLI may be formed to directly apply a predetermined alignment voltage between consecutive series stages in the step of aligning the light emitting element LD. Due to the intermediate electrode SLI, an alignment signal may be applied to the light source unit LSU using a series structure of each pixel PXL even in the step of aligning the light emitting element LD. Therefore, the alignment current flowing through the display panel PNL may be reduced, so that the efficiency of the energy (electricity, or power) required when aligning the light emitting element LD may be improved.

[0167] Since the alignment current flowing through the first electrode line MLI1 and the second electrode line MLI2 is reduced, the voltage drop (IR drop) occurring in the first electrode line MLI1 and the second electrode line MLI2 is reduced, so that the line width of the first electrode line MLI1 and / or the second electrode line MLI2 can be reduced. In addition, the capacity of an amplifier (not shown) of a power supply for applying an alignment signal can be reduced.

[0168] In addition, when the intermediate electrode SLI is formed so that the light emitting element LD can be biased and aligned between the first electrode ET1 and the second electrode ET2 while applying a predetermined alignment voltage between the series stages, in the step of aligning the light emitting element LD during the process of manufacturing the display device, the direction of the alignment voltage / current to be applied to the first electrode ET1 and the second electrode ET2 can match the direction of the driving voltage / current to be applied to the first electrode ET1 and the second electrode ET2 in the step of actually driving the display device. Therefore, when the display device is actually driven, the light emitting element LD can be biased and aligned in the direction corresponding to the forward direction. According to an embodiment of the present disclosure, the number of light emitting elements LD connected between the first electrode ET1 and the second electrode ET2 in the forward direction of each pixel PXL can be increased. Therefore, each light source unit LSU can be formed using the light emitting element LD supplied to the emission area EMA of each pixel PXL effectively.

[0169] Except for the node where the first electrode ET1 and the second electrode ET2 are connected in series between the corresponding series stages, each intermediate electrode SLI may not form a substantial current path, unlike the first electrode line MLI1 and the second electrode line MLI2. Therefore, each intermediate electrode SLI may be formed to have a width smaller than the width of the first electrode line MLI1 and the second electrode line MLI2. For example, when the first electrode line MLI1 and the second electrode line MLI2 have a first width W1 and a second width W2, respectively, each intermediate electrode SLI may have a third width W3 smaller than each of the first width W1 and the second width W2. In an embodiment, the first width W1 and the second width W2 may be the same as or different from each other. In the case where the width of each intermediate electrode SLI is reduced, the capacity of the amplifier of the power supply for applying the predetermined alignment signal may be further reduced in the step of aligning the light emitting element LD.

[0170] After the alignment of the light emitting element LD is completed, the intermediate electrode SLI between the pixels PXL can be disconnected and separated. For example, the intermediate electrodes SLI of the corresponding series stages can be disconnected from each other between the first pixel PXL1 and the second pixel PXL2 adjacent to each other, between the second pixel PXL2 and the third pixel PXL3 adjacent to each other, and between the pixel units PXU adjacent to each other. Therefore, the pixels PXL can be separated in a form that can be controlled individually.

[0171] exist Figure 6 and Figure 7 In the description of the embodiment, although in the foregoing description, the first electrode ET1 and the second electrode ET2 have been described as being separate components due to the corresponding series stages, in relation to the electrodes of each pixel PXL as a whole, at least two electrodes arranged in a plurality of series stages may be considered as different regions of a single electrode. For example, the second electrode ET2[1] of the first series stage, the first intermediate electrode SLI1, and the first electrode ET1[2] of the second series stage connected integrally with each other may be considered as the first electrode portion, the second electrode portion, and the third electrode portion of a single electrode (e.g., referred to as the “second electrode”). Similarly, the second electrode ET2[2] of the second series stage, the second intermediate electrode SLI2, and the first electrode ET1[3] of the third series stage connected integrally with each other may be considered as the first electrode portion, the second electrode portion, and the third electrode portion of another single electrode (e.g., referred to as the “third electrode”).

[0172] In this regard, the structure of the electrodes disposed in the emission area EMA of each pixel PXL will be described. Each pixel PXL may include: at least one first electrode (e.g., the first electrode ET1[1] of the first series stage), electrically connected to the first electrode line MLI1 and extending in the first direction DR1; at least one second electrode, including a first electrode portion and a third electrode portion (e.g., the second electrode ET2[1] of the first series stage and the first electrode ET1[2] of the second series stage) spaced apart from the first electrode and both extending in the first direction DR1, and a second electrode portion (e.g., the first intermediate electrode SLI1) extending along the second direction DR2 between the first electrode and the third electrode; and at least one third electrode (e.g., the second electrode ET2[2] of at least the second series stage), spaced apart from the first electrode and the second electrode and at least one region thereof extending in the first direction DR1. In addition, each pixel PXL may include at least one first light emitting element LD1 electrically connected between the first electrode and the second electrode, and at least one second light emitting element LD2 electrically connected between the second electrode and the third electrode.

[0173] In an embodiment, the first electrode portion of the second electrode (the second electrode ET2[1] of the first series connection stage) may extend in the first direction DR1 and may be spaced apart from the first electrode (the first electrode ET1[1] of the first series connection stage) relative to a direction (e.g., the second direction DR2) intersecting the first direction DR1. For example, the first electrode portion of the second electrode may be disposed in parallel with the first electrode.

[0174] In an embodiment, the second electrode portion of the second electrode (the first intermediate electrode SLI1) may extend from the first electrode portion (e.g., a lower end region of the first electrode portion) in the second direction DR2. In an embodiment, the second electrode portion of the second electrode may be disposed between the first electrode and the third electrode at a position spaced apart from the first electrode and the third electrode, but the present disclosure is not limited thereto.

[0175] In an embodiment, the third electrode portion of the second electrode (the first electrode ET1[2] of the second series stage) may extend from the second electrode portion in the first direction DR1. In an embodiment, the first electrode portion and the third electrode portion of the second electrode may be arranged in a line along the first direction DR1, but the present disclosure is not limited thereto. For example, Figure 6 As shown in , the first electrode portion and the third electrode portion of the second electrode may each have a structure extending in a line along the first direction DR1. In an embodiment, the first electrode portion and the third electrode portion of the second electrode may each extend in the first direction DR1, but may not be arranged in a line. For example, Figure 7As shown in , the first electrode portion and the third electrode portion of the second electrode may each be bent (or folded) at a junction with the second electrode portion.

[0176] Likewise, the third electrode may include a first electrode portion and a third electrode portion (e.g., the second electrode ET2[2] of the second series stage and the first electrode ET1[3] of the third series stage) which are spaced apart from the first electrode and the second electrode and both extend in the first direction DR1, and a second electrode portion (e.g., the second intermediate electrode SLI2) extending along the second direction between the first electrode portion and the third electrode portion. However, in the case where each pixel PXL includes only two series stages, the third electrode may include only the first electrode portion and / or the second electrode portion.

[0177] In an embodiment, the first electrode portion of the third electrode (the second electrode ET2[2] of the second series stage) may extend in the first direction DR1, and may be spaced apart from the third electrode portion of the second electrode (the first electrode ET1[2] of the second series stage) relative to a direction intersecting the first direction DR1 (e.g., the second direction DR2). For example, the first electrode portion of the third electrode may be disposed in parallel with the third electrode portion of the second electrode.

[0178] In an embodiment, the second electrode portion of the third electrode (the second intermediate electrode SLI2) may extend from the first electrode portion (e.g., the lower end region of the first electrode portion) in the second direction DR2. In an embodiment, the second electrode portion of the third electrode may be disposed between the second electrode and the fourth electrode at a position spaced apart from the second electrode and the fourth electrode, but the present disclosure is not limited thereto.

[0179] In an embodiment, the third electrode portion of the third electrode (the first electrode ET1[3] of the third series stage) may extend from the second electrode portion in the first direction DR1. In an embodiment, the first electrode portion and the third electrode portion of the third electrode may be arranged in a line along the first direction DR1, but the present disclosure is not limited thereto. For example, Figure 6 As shown in , the first electrode portion and the third electrode portion of the third electrode may both have a structure extending in a line along the first direction DR1. In an embodiment, the first electrode portion and the third electrode portion of the third electrode may both extend in the first direction DR1, but may not be arranged in a line. For example, Figure 7 As shown in , the first electrode portion and the third electrode portion of the third electrode may each be bent at a junction with the second electrode portion.

[0180] The third electrode may be electrically connected to the second electrode line MLI2. In an embodiment, when each pixel PXL includes only two series stages, the third electrode may be directly connected to the second electrode line MLI2. In an embodiment, when each pixel PXL includes three or more series stages, at least one electrode and / or light emitting element may be connected between the third electrode and the second electrode line MLI2. For example, each pixel PXL may also include at least one third light emitting element LD3 electrically connected between the third electrode and the second electrode line MLI2 and a fourth electrode (e.g., the second electrode ET2[3] of the third series stage) electrically connected between the third light emitting element LD3 and the second electrode line MLI2.

[0181] In an embodiment, at least one region of the first electrode and at least one region of the third electrode may be disposed at positions spaced apart from each other on a line. Figure 6 As shown in , the first electrode portions of the first electrode and the third electrode may be arranged in a line along the first direction DR1, and may be arranged at positions spaced apart from each other, with the second electrode portion of the second electrode placed therebetween. In this case, the first electrode portion and the third electrode portion of the second electrode may be arranged in a line along the first direction DR1. For example, the first electrode portion and the third electrode portion of the second electrode may be spaced apart from the first electrode portions of the first electrode and the third electrode by the same distance in the second direction DR2, respectively. The shape, structure and / or relative arrangement relationship of the electrodes arranged in each pixel PXL may be changed according to the embodiment.

[0182] For example, in an embodiment, Figure 7 As shown in , the first electrode and the third electrode portions of the second electrode may be disposed at positions spaced apart from each other on a line along the first direction DR1. In this case, the first electrode portion of the second electrode and at least one region of the third electrode (e.g., the first electrode portion of the third electrode) may be disposed at positions spaced apart from each other on a line.

[0183] At least one first light emitting element LD1 may be electrically connected between the first electrode and the second electrode. At least one second light emitting element LD2 may be electrically connected between the second electrode and the third electrode. In addition, when each pixel PXL further includes a fourth electrode, at least one third light emitting element LD3 may be electrically connected between the third electrode and the fourth electrode.

[0184] In an embodiment, the first light emitting element LD1 may be connected between the first electrode and the first electrode portion of the second electrode. The second light emitting element LD2 may be connected between the third electrode portion of the second electrode and the first electrode portion of the third electrode. Similarly, the third light emitting element LD3 may be connected between the third electrode portion of the third electrode and the fourth electrode.

[0185] The first light emitting element LD1 may be connected between the first electrode and the second electrode in a forward direction. For example, a first end (e.g., a P-type end) EP1 of the first light emitting element LD1 may be electrically connected to the first electrode. A second end (e.g., an N-type end opposite to the P-type end) EP2 of the first light emitting element LD1 may be electrically connected to the second electrode.

[0186] Similarly, the second light emitting element LD2 may be connected between the second electrode and the third electrode in the forward direction. The third light emitting element LD3 may be connected between the third electrode and the fourth electrode in the forward direction. For example, the first end (e.g., the P-type end) EP1 of the second light emitting element LD2 may be electrically connected to the second electrode. The second end (e.g., the N-type end opposite to the P-type end) EP2 of the second light emitting element LD2 may be electrically connected to the third electrode. In addition, the first end (e.g., the P-type end) EP1 of the third light emitting element LD3 may be electrically connected to the third electrode. The second end (e.g., the N-type end opposite to the P-type end) EP2 of the third light emitting element LD3 may be electrically connected to the fourth electrode.

[0187] In other words, the corresponding electrodes and / or electrode portions may be designated by different names or terms, depending on the viewpoint. In addition, a plurality of electrodes or electrode portions connected to each other integrally or non-integrally, etc. may be considered as a single element or separate elements separated from each other. Therefore, the structure of the pixel PXL according to an embodiment of the present disclosure may be interpreted in a narrow sense with respect to each sub-region SAR or pixel PXL, or in a broad sense with respect to each pixel unit PXU or display area DA.

[0188] Figures 8 to 9 are all pixels PXL according to an embodiment of the present disclosure (for example, respectively showing Figure 6 and Figure 7 A plan view of a modified embodiment of the embodiment related to the embodiment of the present invention). Figure 8 and Fig. 9 In the description of the embodiment of Figure 6 and Figure 7 A detailed description of a construction similar or identical to that of a construction.

[0189] Reference Figure 8 and Fig. 9, each pixel PXL may further selectively include a first contact electrode CE1 and a second contact electrode CE2 respectively disposed above the first electrode ET1 and the second electrode ET2. For example, each first series-stage first contact electrode CE1[1] may be disposed on each corresponding first series-stage first electrode ET1[1]. Each first series-stage second contact electrode CE2[1] may be disposed on each corresponding first series-stage second electrode ET2[1]. Similarly, each second series-stage first contact electrode CE1[2] may be disposed on each corresponding second series-stage first electrode ET1[2]. Each second series-stage second contact electrode CE2[2] may be disposed on each corresponding second series-stage second electrode ET2[2]. Each third series-stage first contact electrode CE1[3] may be disposed on each corresponding third series-stage first electrode ET1[3]. Each third series-stage second contact electrode CE2[3] may be disposed on each corresponding third series-stage second electrode ET2[3].

[0190] In an embodiment, the first contact electrode CE1 may be formed to have separate patterns respectively over the first electrode ET1 of each series stage. The first contact electrode CE1 may electrically connect each first electrode ET1 with a first end EP1 of at least one light emitting element LD adjacent to the first electrode ET1.

[0191] Likewise, the second contact electrode CE2 may be formed to have separate patterns respectively over the second electrode ET2 of each series stage. The second contact electrode CE2 may electrically connect each second electrode ET2 with a second end EP2 of at least one light emitting element LD adjacent to the second electrode ET2.

[0192] Since the first contact electrode CE1 and the second contact electrode CE2 are formed, the light emitting element LD may be more reliably connected between the first electrode ET1 and the second electrode ET2.

[0193] In addition, each pixel PXL may further selectively include a first partition wall PW1 (also referred to as “first wall” or “first bank”) and a second partition wall PW2 (also referred to as “second wall” or “second bank”) respectively disposed under the first electrode ET1 and the second electrode ET2 .

[0194] In an embodiment, the first partition wall PW1 may be provided to have separate patterns respectively under the first electrode ET1 of each series stage. If the first partition wall PW1 is provided under the first electrode ET1, the first electrode ET1 may protrude upward in the region in which the first partition wall PW1 is provided. Therefore, the light emitted from the first end EP1 of the light emitting element LD facing the first electrode ET1 may be controlled to travel more efficiently in the front direction of the display device.

[0195] Likewise, the second partition wall PW2 may be provided with separate patterns respectively under the second electrode ET2 of each series stage. If the second partition wall PW2 is provided under the second electrode ET2, the second electrode ET2 may protrude upward in the region in which the second partition wall PW2 is provided. Thus, the light emitted from the second end EP2 of the light emitting element LD facing the second electrode ET2 may be controlled to travel more efficiently in the front direction of the display device.

[0196] In addition, the display device may further include a bank BNK that defines and / or divides the emission area EMA of each pixel PXL. For example, the bank BNK may be disposed between the emission areas EMA of the pixels PXL to integrally surround each emission area EMA including the sub-areas SAR of each pixel PXL. For example, the bank BNK may include a plurality of openings corresponding to the respective emission areas EMA of the pixels PXL, and may be formed in the display area DA in a grid shape. In an embodiment, the bank BNK may include a light shielding material and / or a reflective opaque material so that light leakage between adjacent pixels PXL may be prevented.

[0197] according to Figures 6 to 9 In each embodiment shown in , the light emitting element LD supplied to the emission area EMA of each pixel PXL can be connected in at least a series structure. For example, the light emitting element LD supplied to the emission area EMA of each pixel PXL can be connected in a series / parallel combination structure to form each light source unit LSU. Therefore, not only can each pixel PXL be driven reliably, but also the driving current flowing through the display panel PNL can be reduced. Therefore, the power consumption efficiency can be improved.

[0198] In addition, since each intermediate electrode SLI is formed between consecutive series stages, a predetermined alignment / driving signal can be supplied to the light emitting element LD in a state where the light emitting element LD is connected in a series / parallel combination structure. Therefore, the power consumption efficiency at the time of operation can be improved, and the power efficiency for aligning the light emitting element LD can be improved. Compared with an embodiment in which all the light emitting elements LD of each light source unit LSU are connected in parallel, the line width of the first electrode line MLI1 and the second electrode line MLI2 can be reduced, and the capacity of the amplifier for supplying the power supply of the predetermined alignment signal can be reduced.

[0199] In addition, since each intermediate electrode SLI is formed between consecutive series stages, the direction of the alignment voltage / current to be applied to the first electrode ET1 and the second electrode ET2 in the step of aligning the light emitting element LD can match the direction of the driving voltage / current to be applied to the first electrode ET1 and the second electrode ET2 in the step of actually driving the display device. Therefore, in the case where the light emitting element LD is bias-aligned between the first electrode ET1 and the second electrode ET2, the number of light emitting elements LD forwardly connected between the first electrode ET1 and the second electrode ET2 of each pixel PXL can be increased.

[0200] In an embodiment, in the step of aligning the light emitting element LD, the light emitting element supplied to the emission area EMA may be aligned and biased in any one direction (e.g., in a direction corresponding to a forward direction during operation) by adjusting an alignment signal (or alignment voltage) to be applied to the first electrode ET1 and the second electrode ET2 or by forming a magnetic field. For example, in the step of aligning the light emitting element LD, when adjusting the waveform of the alignment signal or forming a magnetic field in each emission area EMA, the number of light emitting elements LD oriented in the forward direction so that each of its first ends EP1 is oriented toward the first electrode ET1 and each of its second ends EP2 is oriented toward the second electrode ET2 may be controlled to be greater than the number of reverse light emitting elements LDrv oriented so that each of its first ends EP1 is oriented toward the second electrode ET2 and each of its second ends EP2 is oriented toward the first electrode ET1. For example, the light emitting element LD may be aligned by controlling the process conditions so that the ratio of the number of light emitting elements LD oriented in the forward direction to the number of reverse light emitting elements LDrv oriented in the direction opposite to the direction of the light emitting element LD becomes approximately 80:20. Therefore, the number of light-emitting elements LD that can be used as effective light sources to form each light source unit LSU among the light-emitting elements supplied to the emission area EMA of each pixel PXL can be increased. That is, according to the aforementioned embodiment, the application efficiency of the light-emitting element LD can be improved. In addition, since the number of light-emitting elements LD connected in the forward direction in each series stage is increased, it is possible to prevent the phenomenon in which the alignment / driving current does not flow in any series stage because there is no light-emitting element LD aligned in the forward direction in the series stage, or it is possible to prevent the alignment / driving current from gathering on a small number of light-emitting elements LD aligned in the forward direction. Therefore, each pixel PXL can be reliably driven.

[0201] Figures 10 to 13 are cross-sectional views each showing a pixel PXL according to an embodiment of the present disclosure, for example, Figures 10 to 13 Shows the corresponding Figure 8In the embodiment, the structures of the second pixel PXL2 and the third pixel PXL3 may be substantially the same as or similar to the structure of the first pixel PXL1. Figures 10 to 13 as well as Figures 4 to 9 An embodiment of a cross-sectional structure of each pixel PXL will be described.

[0202] Reference Figures 4 to 13 According to an embodiment of the present disclosure, a pixel PXL and a display device including the pixel PXL may include a display element layer DPL including a plurality of light emitting elements LD disposed in an emission area EMA of each pixel PXL on a surface of a base layer BSL. In addition, the pixel PXL and the display device including the pixel PXL may further selectively include a pixel circuit layer PCL. For example, the pixel PXL and the display device including the pixel PXL may further include a pixel circuit layer PCL disposed between the base layer BSL and the display element layer DPL.

[0203] In an embodiment, the pixel circuit layer PCL may include at least one circuit element electrically connected to the light emitting element LD. For example, the pixel circuit layer PCL may include at least one circuit element forming the pixel circuit PXC of each pixel PXL.

[0204] For example, the pixel circuit layer PCL may include a plurality of transistors T and a storage capacitor Cst disposed in each pixel region and forming a corresponding pixel circuit PXC, and also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU. Here, in the case where the pixel circuit PXC is omitted and each light source unit LSU is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted. For illustration purposes, Figures 10 to 13 Only one transistor T among the circuit elements and lines disposed on the pixel circuit layer PCL is representatively shown. Here, the plane / section structure of the pixel circuit layer PCL may be changed in various ways. The position and section structure of each transistor T may be changed in various ways according to the embodiment.

[0205] In addition, the pixel circuit layer PCL may include a plurality of insulating layers disposed between corresponding electrodes and / or lines. In an embodiment, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV continuously stacked on one surface of the base layer BSL. In some embodiments, the pixel circuit layer PCL may further include at least one light shielding pattern (not shown) disposed under at least some of the transistors T.

[0206] The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, the corresponding layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0207] In an embodiment, each transistor T may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes TE1 and TE2. Figures 10 to 13 An embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in at least one transistor T provided in each pixel region may be formed integrally with the corresponding semiconductor layer SCL.

[0208] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0209] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0210] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and may overlap at least one region of the semiconductor layer SCL.

[0211] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor layer SCL, with at least one interlayer insulating layer ILD disposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on respective different ends of the semiconductor layer SCL, with the gate insulating layer GI and the interlayer insulating layer ILD disposed therebetween. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to the first region and the second region of the semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, any one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0212] At least one transistor T provided in the pixel circuit PXC may be connected to at least one pixel electrode. Figure 5e Any one of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 shown in FIG. 1 (e.g., the drain electrode) can be electrically connected to the first series stage first electrode ET1[1] of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) passing through the passivation layer PSV and through a first electrode line MLI1 disposed above the passivation layer PSV.

[0213] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be arranged on the same layer as the layer of one electrode in each circuit element forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be arranged on the same layer as the layer of the gate electrode GE. The data line Dj of each pixel PXL may be arranged on the same layer as the layer of the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. In addition, the first power line PL1 and / or the second power line PL2 may be arranged on the same layer as the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2.

[0214] In an embodiment, the display element layer DPL may include a light source unit LSU for each pixel PXL. For example, the display element layer DPL may include a plurality of first electrodes ET1 and second electrodes ET2 disposed in an emission area EMA of each pixel PXL and a plurality of light emitting elements LD disposed between the first electrodes ET1 and the second electrodes ET2. In addition, the display element layer DPL may further selectively include a first partition wall PW1 and a second partition wall PW2 configured to cause predetermined areas of the first electrodes ET1 and the second electrodes ET2 to protrude upward and a first contact electrode CE1 and a second contact electrode CE2 configured to more reliably connect the light emitting element LD between the first electrode ET1 and the second electrode ET2. In addition, the display element layer DPL may further include, for example, at least one conductive layer and / or an insulating layer.

[0215] In an embodiment, the display element layer DPL may include first and second partition walls PW1 and PW2, first and second electrodes ET1 and ET2, a first insulating layer INS1, a light emitting element LD, an insulating pattern INP, first and second contact electrodes CE1 and CE2, and a second insulating layer INS2 that are continuously arranged and / or formed above the base layer BSL and / or the pixel circuit layer PCL.

[0216] The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other in the emission region of each pixel PXL. The first partition wall PW1 and the second partition wall PW2 may protrude from the base layer BSL and / or the pixel circuit layer PCL in the height direction of the base layer BSL. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same height, but the present disclosure is not limited thereto.

[0217] In an embodiment, the first partition wall PW1 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and each first electrode ET1. The first partition wall PW1 may be disposed adjacent to the first end EP1 of the light emitting element LD. For example, one side surface of each first partition wall PW1 may be positioned adjacent to the first end EP1 of the light emitting element LD and disposed to face the first end EP1.

[0218] In an embodiment, the second partition wall PW2 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and the second electrode ET2. The second partition wall PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, one side surface of the second partition wall PW2 may be positioned adjacent to the second end EP2 of the light emitting element LD and disposed to face the second end EP2.

[0219] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. Fig.10 and Fig.12 As shown in , the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side. In an embodiment, as shown in Fig.11 and Fig.13 As shown in , the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side surface. At least one electrode and / or insulating layer disposed above the first partition wall PW1 and the second partition wall PW2 may have a curved surface in a region corresponding to the first partition wall PW1 and the second partition wall PW2.

[0220] In other words, the shape of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or changed in position.

[0221] Each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material including at least one inorganic material and / or an organic material. For example, the first partition wall PW1 and the second partition wall PW2 may include an insulating material including various known inorganic insulating materials such as silicon nitride (SiN x ) or silicon oxide (SiO x )) of at least one inorganic layer. Optionally, the first partition wall PW1 and the second partition wall PW2 may include at least one organic layer and / or a photoresist layer containing various known organic insulating materials, or may form a single-layer or multi-layer insulator containing an organic / inorganic material combination. In an embodiment of the present disclosure, the constituent materials of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways.

[0222] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may be used as a reflector. For example, the first partition wall PW1 and the second partition wall PW2 together with the first electrode ET1 and the second electrode ET2 disposed on the first partition wall PW1 and the second partition wall PW2 may be used as a reflector to guide light emitted from each light emitting element LD in a desired direction, thereby improving the light efficiency of the pixel PXL.

[0223] The first electrode ET1 and the second electrode ET2 may be disposed over the first partition wall PW1 and the second partition wall PW2, respectively. The first electrode ET1 and the second electrode ET2 may be disposed at positions spaced apart from each other in each pixel region (particularly, each emission area EMA).

[0224] In an embodiment, the first electrode ET1 and the second electrode ET2 respectively disposed above the first partition wall PW1 and the second partition wall PW2 may have shapes corresponding to the corresponding shapes of the first partition wall PW1 and the second partition wall PW2. For example, the first electrode ET1 and the second electrode ET2 may have inclined surfaces or curved surfaces corresponding to the first partition wall PW1 and the second partition wall PW2, respectively, and protrude in the height direction of the base layer BSL.

[0225] Each of the first electrode ET1 and the second electrode ET2 may include at least one conductive material. For example, each of the first electrode ET1 and the second electrode ET2 may include at least one metal among various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or alloys thereof), conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO), etc.), and the like. 2 )) and at least one material among a conductive polymer (such as PEDOT), but the present disclosure is not limited thereto. For example, each of the first electrode ET1 and the second electrode ET2 may include other conductive materials such as carbon nanotubes and graphene. In other words, each of the first electrode ET1 and the second electrode ET2 may include at least one of various conductive materials to have conductivity, and its constituent materials are not particularly limited. In addition, each of the first electrode ET1 and the second electrode ET2 may have the same conductive material or at least one different conductive material.

[0226] Each of the first electrode ET1 and the second electrode ET2 may have a single-layer structure or a multi-layer structure. For example, each of the first electrode ET1 and the second electrode ET2 may include at least one reflective electrode layer. Each of the first electrode ET1 and the second electrode ET2 may also selectively include at least one of at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive cover layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0227] In an embodiment, the reflective electrode layer of each of the first electrode ET1 and the second electrode ET2 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or their alloys), but the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ET1 and the second electrode ET2 including the reflective electrode layer may enable light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each light emitting element LD to travel in the direction of displaying an image (e.g., in the forward direction). Specifically, if the first electrode ET1 and the second electrode ET2 have inclined or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively, and are disposed to face the first end EP1 and the second end EP2 of the light emitting element LD, respectively, light emitted from the first end EP1 and the second end EP2 of each light emitting element LD can be reflected by the first electrode ET1 and the second electrode ET2, and thus can more reliably travel in the forward direction of the display panel PNL (e.g., in the upward direction of the base layer BSL). Thus, the efficiency of light emitted from the light emitting element LD can be improved.

[0228] In addition, the transparent electrode layer of each of the first electrode ET1 and the second electrode ET2 can be formed by various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ET1 and the second electrode ET2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ET1 and the second electrode ET2 are each formed by a multilayer structure including at least two layers, the voltage drop caused by the signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting element LD.

[0229] In addition, if each of the first electrode ET1 and the second electrode ET2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ET1 and the second electrode ET2 can be prevented from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive cover layer may be selectively included in the first electrode ET1 and the second electrode ET2, and may be omitted according to the embodiment. In addition, the conductive cover layer may be considered as a component of each of the first electrode ET1 and the second electrode ET2, or as a separate component disposed on the first electrode ET1 and the second electrode ET2.

[0230] The first insulating layer INS1 may be disposed on a predetermined region of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may be formed to cover a predetermined region of the first electrode ET1 and the second electrode ET2, and may include an opening to expose other predetermined regions of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may expose the first electrode ET1 and the second electrode ET2 in predetermined first contact portions CNT1 and second contact portions CNT2, respectively. In some embodiments, the first insulating layer INS1 may be omitted. In this case, the light emitting element LD may be directly disposed on one end of each of the passivation layer PSV and / or the first electrode ET1 and the second electrode ET2.

[0231] In an embodiment, the first insulating layer INS1 may be mainly formed to cover the entire surface of the first electrode ET1 and the second electrode ET2. After the light emitting element LD is supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ET1 and the second electrode ET2 in corresponding predetermined regions (e.g., corresponding first contact portions CNT1 and second contact portions CNT2) on the first partition wall PW1 and the second partition wall PW2. In an embodiment, the first insulating layer INS1 may be patterned in the form of a separate pattern that is partially disposed under the light emitting element LD after the supply and alignment of the light emitting element LD have been completed.

[0232] In other words, the first insulating layer INS1 may be disposed between the first and second electrodes ET1 and ET2 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ET1 and ET2. After forming the first and second electrodes ET1 and ET2, the first insulating layer INS1 may be formed to cover the first and second electrodes ET1 and ET2, so that the first and second electrodes ET1 and ET2 may be prevented from being damaged or metal may be prevented from being precipitated in a subsequent process. In addition, the first insulating layer INS1 may stably support each light emitting element LD.

[0233] The first insulating layer INS1 may be formed of a single layer or a plurality of layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the first insulating layer INS1 may include a layer including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ) etc. The constituent material of the first insulating layer INS1 is not particularly limited.

[0234] A plurality of light emitting elements LD may be supplied to each pixel region (specifically, an emission region EMA of each pixel PXL in which the first insulating layer INS1 is formed) and aligned in each pixel region (specifically, an emission region EMA of each pixel PXL in which the first insulating layer INS1 is formed). For example, a plurality of light emitting elements LD may be supplied to each emission region EMA by an inkjet method or the like, and the light emitting elements LD may be aligned with the directionality between the first electrode ET1 and the second electrode ET2 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ET1 and the second electrode ET2.

[0235] In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first electrodes ET1 and second electrodes ET2 in a horizontal direction so that opposite ends (i.e., first ends EP1 and second ends EP2) of each light emitting element LD relative to its longitudinal direction overlap with the pair of first electrodes ET1 and second electrodes ET2. In addition, in an embodiment, other light emitting elements LD may be disposed between a pair of first electrodes ET1 and second electrodes ET2 in a diagonal direction. In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first electrodes ET1 and second electrodes ET2 so that at least some of the light emitting elements LD do not overlap with the first electrodes ET1 and second electrodes ET2 and may be connected to the first electrodes ET1 and second electrodes ET2, respectively, through the first contact electrodes CE1 and second contact electrodes CE2.

[0236] The insulating pattern INP may be disposed on a predetermined region of the light emitting element LD. For example, the insulating pattern INP may expose the first end EP1 and the second end EP2 of the light emitting element LD, and may be disposed only partially above a predetermined region of the light emitting element LD including a corresponding central region of the light emitting element LD. The insulating pattern INP may be formed in an independent pattern in each emission region EMA, but the present disclosure is not limited thereto. According to an embodiment, the insulating pattern INP may be omitted. In this case, the opposite ends of the first contact electrode CE1 and the second contact electrode CE2 may be disposed directly on the light emitting element LD.

[0237] The insulating pattern INP may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the insulating pattern INP may include a layer including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ), various organic / inorganic insulating materials such as photoresist (PR) materials, etc. The constituent material of the insulating pattern INP is not particularly limited.

[0238] After the alignment of the light emitting element LD has been completed, an insulating pattern INP is formed on the light emitting element LD so that the light emitting element LD can be prevented from being removed from the aligned position. In addition, in the case where there is a space between the first insulating layer INS1 and the light emitting element LD, the space can be filled with an insulating material introduced therein during the process of forming the insulating pattern INP. Therefore, the light emitting element LD can be supported more stably.

[0239] The opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting element LD that are not covered by the insulating pattern INP may be covered by the first contact electrode CE1 and the second contact electrode CE2, respectively. For example, the respective ends of the first contact electrode CE1 and the second contact electrode CE2 may be disposed on the first end EP1 and the second end EP2 of the light emitting element LD at positions spaced apart from each other, with the insulating pattern INP interposed therebetween.

[0240] In an embodiment, Fig.10 and Fig.11 As shown in , the first contact electrode CE1 and the second contact electrode CE2 can be simultaneously formed on the same layer on one surface of the base layer BSL. Therefore, the process of manufacturing the pixel PXL and the display device including the pixel PXL can be simplified. For example, compared with the case where the first contact electrode CE1 and the second contact electrode CE2 are formed by corresponding mask processes, the number of mask processes required to form the pixel PXL can be reduced, and the first contact electrode CE1 and the second contact electrode CE2 can be more easily formed.

[0241] In an embodiment, Fig.12 and Fig.13 As shown in , the first contact electrode CE1 and the second contact electrode CE2 may be continuously formed on different layers on one surface of the base layer BSL. An additional third insulating layer INS3 may be provided between the first contact electrode CE1 and the second contact electrode CE2. In other words, the positions and relative arrangement relationship of the first contact electrode CE1 and the second contact electrode CE2 may be changed in various ways.

[0242] In addition, the first contact electrode CE1 and the second contact electrode CE2 may be respectively disposed above the first electrode ET1 and the second electrode ET2 to cover the exposed regions (e.g., the first contact portion CNT1 and the second contact portion CNT2) of the first electrode ET1 and the second electrode ET2. For example, the first contact electrode CE1 and the second contact electrode CE2 may be respectively disposed on at least predetermined regions of the first electrode ET1 and the second electrode ET2 to contact the first electrode ET1 and the second electrode ET2 in the first contact portion CNT1 and the second contact portion CNT2, respectively. Therefore, the first contact electrode CE1 and the second contact electrode CE2 may be respectively electrically connected to the first electrode ET1 and the second electrode ET2. The first electrode ET1 and the second electrode ET2 may be respectively electrically connected to the first end EP1 and the second end EP2 of the light emitting element LD through the first contact electrode CE1 and the second contact electrode CE2.

[0243] In an embodiment, the first contact electrode CE1 and the second contact electrode CE2 may be formed of various transparent conductive materials. For example, the first contact electrode CE1 and the second contact electrode CE2 may include at least one of various transparent conductive materials including ITO, IZO and ITZO, and may be substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from the light emitting element LD through the first end EP1 and the second end EP2 may be emitted out of the display device through the first contact electrode CE1 and the second contact electrode CE2.

[0244] The second insulating layer INS2 may be disposed on the first contact electrode CE1 and the second contact electrode CE2. For example, the second insulating layer INS2 may be formed and / or disposed on the entire surface of the display area DA of the base layer BSL on which the first partition wall PW1 and the second partition wall PW2, the first electrode ET1 and the second electrode ET2, the light emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2 are formed, so that the second insulating layer INS2 may cover the first partition wall PW1 and the second partition wall PW2, the first electrode ET1 and the second electrode ET2, the light emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2. The second insulating layer INS2 may include at least one inorganic layer and / or an organic layer.

[0245] In an embodiment, the second insulating layer INS2 may include a thin film encapsulation layer having a multi-layer structure, but the present disclosure is not limited thereto. In some embodiments, at least one overcoat layer and / or an encapsulation substrate, etc. may be further disposed over the second insulating layer INS2.

[0246] In an embodiment, the second insulating layer INS2 may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the second insulating layer INS2 may include silicon nitride (SiN x ), silicon oxide (SiO x ) etc. The constituent material of the second insulating layer INS2 is not particularly limited.

[0247] Figures 14a to 14c is a method for manufacturing a display device according to an embodiment of the present disclosure (for example, a method for manufacturing a display device including Figure 8 A plan view of an embodiment of a method for displaying a pixel unit PXU of a display device. Figures 14a to 14c In order to more clearly illustrate the connection / disconnection structure of the electrode line MLI between the pixels PXL, the illustration of the bank BNK will be omitted.

[0248] Reference Figures 4 to 14a , the first electrode ET1 and the second electrode ET2, the first electrode line MLI1 and the second electrode line MLI2, and the intermediate electrode SLI of the pixel PXL can be formed on the base layer BLS (or on the base layer BLS on which the pixel circuit layer PCL is formed). A plurality of light emitting elements LD can be supplied to the emission area EMA on which the first electrode ET1 and the second electrode ET2, the first electrode line MLI1 and the second electrode line MLI2, and the intermediate electrode SLI are formed of each pixel PXL. By applying a predetermined alignment signal between the first electrode line MLI1 and the second electrode line MLI2 and the intermediate electrode SLI, the light emitting element LD can be aligned between the first electrode ET1 and the second electrode ET2. In the step of aligning the light emitting element LD, the first electrode line MLI1 and the second electrode line MLI2 can be the main alignment line through which the alignment current corresponding to the alignment signal flows, and the intermediate electrode SLI can be the sub-alignment line for directly applying the predetermined alignment signal between the series stages.

[0249] In an embodiment, the first electrode line MLI1 and the second electrode line MLI2 and the intermediate electrode SLI may be first commonly connected to a plurality of pixels PXL. For example, the first electrode line MLI1 of the first pixel PXL1 may be integrally formed with the first electrode line MLI1 of the second pixel PXL2 and the third pixel PXL3. The second electrode line MLI2 of the first pixel PXL1 may be integrally formed with the second electrode line MLI2 of the second pixel PXL2 and the third pixel PXL3. For example, the first electrode line MLI1 may be first formed to have a closed state rather than being in an open state in the open line area MLIda between the first pixel PXL1 to the third pixel PXL3.

[0250] Likewise, each intermediate electrode SLI of the first pixel PXL1 may be formed integrally with the corresponding intermediate electrode SLI of the second pixel PXL2 and the third pixel PXL3 (e.g., the intermediate electrode SLI disposed between the consecutive series connection stages in the same row or the same order). For example, the first intermediate electrode SLI1 disposed between the first series connection stage and the second series connection stage of the first pixel PXL1 may be formed integrally with the first intermediate electrode SLI1 disposed between the first series connection stage and the second series connection stage of the second pixel PXL2 and the third pixel PXL3. The second intermediate electrode SLI2 disposed between the second series connection stage and the third series connection stage of the first pixel PXL1 may be formed integrally with the second intermediate electrode SLI2 disposed between the second series connection stage and the third series connection stage of the second pixel PXL2 and the third pixel PXL3. For example, each intermediate electrode SLI may be first formed to have a closed state rather than being in an open state in the open line area SLIda between the first pixel PXL1 to the third pixel PXL3.

[0251] In an embodiment, since a predetermined alignment signal is supplied through the first electrode line MLI1 and the second electrode line MLI2 and the intermediate electrode SLI, a predetermined alignment voltage can be directly applied between the first electrode ET1 and the second electrode ET2 of each series stage. For example, since the first alignment signal generator SG1, the second alignment signal generator SG2, and the third alignment signal generator SG3 (or different output channels of a single signal generator) are respectively connected between the first electrode line MLI1 and the first intermediate electrode SLI1, between the first intermediate electrode SLI1 and the second intermediate electrode SLI2, and between the second intermediate electrode SLI2 and the second electrode line MLI2, a predetermined AC voltage can be applied to each series stage.

[0252] Reference Fig.14a and Fig.14b After the alignment of the light emitting element LD has been completed, the first electrode line MLI1 is disconnected in the open line area MLIda between the adjacent pixels PXL, so that the first electrode lines MLI1 of the pixels PXL can be separated from each other. In addition, regarding the intermediate electrode SLI, the intermediate electrode SLI is disconnected in the open line area SLIda between the adjacent pixels PXL, so that the intermediate electrodes SLI of the pixels PXL can be separated from each other.

[0253] Reference Fig.14c Each first contact electrode CE1 may be formed on each corresponding first electrode ET1 and the first end EP1 of the light emitting element LD adjacent thereto. Each second contact electrode CE2 may be formed on each corresponding second electrode ET2 and the second end EP2 of the light emitting element LD adjacent thereto. Therefore, the light emitting element LD may be reliably connected between the first electrode ET1 and the second electrode ET2.

[0254] In an embodiment, the following may be performed in reverse order: Fig.14b The steps of separating the first electrode line MLI1 and the intermediate electrode SLI shown in FIG. Fig.14c For example, in the embodiment of the present disclosure, after the alignment of the light emitting element LD has been completed, the first contact electrode CE1 and the second contact electrode CE2 are respectively formed on the first end EP1 and the second end EP2 of the light emitting element LD, after which the first electrode line MLI1 and the intermediate electrode SLI can be separated between the pixels PXL.

[0255] In addition, in the embodiment, when each pixel PXL does not include the first contact electrode CE1 and the second contact electrode CE2, the process of forming the first contact electrode CE1 and the second contact electrode CE2 can be omitted. In this case, each first electrode ET1 can be directly connected to the first end EP1 of the adjacent light emitting element LD, and each second electrode ET2 can be directly connected to the second end EP2 of the adjacent light emitting element LD.

[0256] Figure 15 to Figure 16 are all methods for manufacturing a display device according to an embodiment of the present disclosure (for example, Fig.14a The plan view of different modified embodiments of the embodiment of the present invention). Fig.15 and Fig.16 In the description of the embodiment of Fig.14a The configurations of the embodiments are similar or identical to the detailed description of the configurations.

[0257] Reference Fig.15 The shapes and / or arrangement structures of the first and second electrodes ET1 and ET2 may be changed in various ways according to the embodiment. In the embodiment, although the shapes and / or arrangement structures of the first and second electrodes ET1 and ET2 are changed, the light emitting element LD may be arranged in a manner similar to that of the embodiment. Fig.14a The embodiment of the present invention is basically the same as the embodiment of the present invention. Fig.15 In an embodiment, a predetermined AC voltage can also be applied to each series stage by connecting alignment signal generators (for example, a first alignment signal generator SG1, a second alignment signal generator SG2, and a third alignment signal generator SG3) between the first electrode line MLI1 and the first intermediate electrode SLI1, between the first intermediate electrode SLI1 and the second intermediate electrode SLI2, and between the second intermediate electrode SLI2 and the second electrode line MLI2, respectively.

[0258] Reference Fig.16, in the step of aligning the light emitting element LD, the AC voltage output from the single alignment signal generator SG can be distributed and supplied to multiple series stages through the power transformer TRF. For example, the power transformer TRF can be connected between the alignment signal generator SG configured to output a predetermined AC voltage and the first electrode line MLI1 and the second electrode line MLI2 and the intermediate electrode SLI. In an embodiment, the power transformer TRF may include an output coil corresponding to the corresponding series stage. For example, the power transformer TRF may include an input coil Li connected to the alignment signal generator SG and a first coil Lo1, a second coil Lo2, and a third coil Lo3 connected to the opposite ends of the first series stage, the second series stage, and the third series stage, respectively. In other words, the method of applying the alignment signal can be changed in various ways according to the embodiment. For example, a predetermined alignment signal can be supplied to the first electrode ET1 and the second electrode ET2 of each series stage by various power systems and / or power supply methods.

[0259] In the various embodiments of the present disclosure described above, in the steps of aligning and driving the light emitting element LD, a series structure may be used in the same manner. For example, in both the alignment and driving steps, the light emitting element LD may be connected in a series / parallel combination structure. Therefore, the power efficiency for aligning the light emitting element LD may be improved, and each light source unit LSU may be formed more efficiently using the light emitting element LD aligned (e.g., bias aligned) between the first electrode ET1 and the second electrode ET2. In addition, the alignment / driving current flowing through the display panel PNL may be reduced by applying at least a series structure to each light source unit LSU, so that the capacity of the amplifier provided on the output terminal of the power supply (e.g., a power system for applying a predetermined alignment signal) used when aligning the light emitting element LD and the width of the first electrode line MLI1 and / or the second electrode line MLI2 may be selectively reduced.

[0260] Although the spirit and scope of the present disclosure are described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and modifications may be made therein without departing from the scope of the disclosure defined by the claims.

[0261] The scope of the present disclosure is not limited by the specific embodiments of the present specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device, comprising pixels arranged in a display area, wherein the pixels include: A first electrode extending in a first direction; a second electrode including a first electrode portion, a second electrode portion, and a third electrode portion, wherein the first electrode portion is spaced apart from the first electrode in a second direction intersecting the first direction and extends in the first direction, the second electrode portion extends from the first electrode portion in the second direction, and the third electrode portion extends from the second electrode portion in the first direction; a third electrode including at least one region spaced apart from the third electrode portion in the second direction intersecting the first direction and extending in the first direction; A first light emitting element connected between the first electrode and the second electrode; as well as a second light emitting element connected between the second electrode and the third electrode, wherein the at least one region of the third electrode and the first electrode are arranged at positions spaced apart from each other on a line relative to the first direction, and the first electrode portion and the third electrode portion are arranged on a line relative to the first direction, or The first electrode and the third electrode portion are disposed at positions spaced apart from each other on a line with respect to the first direction, and the at least one region of the third electrode and the first electrode portion are disposed at positions spaced apart from each other on a line with respect to the first direction.

2. The display device according to claim 1, wherein: The second electrode portion is disposed between the first electrode and the third electrode.

3. The display device according to claim 1, in, The first electrode is spaced apart from the first electrode portion with respect to the second direction, and Wherein, the third electrode is spaced apart from the third electrode portion relative to the second direction.

4. The display device according to claim 1, in, The first light emitting element includes a P-type terminal electrically connected to the first electrode and an N-type terminal electrically connected to the second electrode, and The second light emitting element includes a P-type terminal electrically connected to the second electrode and an N-type terminal electrically connected to the third electrode.

5. The display device according to claim 1, further comprising: a first electrode line electrically connected to the first electrode and configured to be supplied with a first power voltage or a first driving signal; as well as The second electrode line is electrically connected to the third electrode and is configured to be supplied with a second power voltage or a second driving signal.

6. The display device according to claim 5, further comprising: a third light emitting element, comprising a P-type terminal electrically connected to the third electrode and an N-type terminal opposite to the P-type terminal; as well as The fourth electrode is electrically connected between the N-type end of the third light emitting element and the second electrode line.

7. A display device, comprising a first pixel, the first pixel comprising a light emitting element arranged in a plurality of series stages, in, The first pixel comprises: The first sub-region to the Kth sub-region correspond to the first series connection stage to the Kth series connection stage, respectively, and K is a natural number of 2 or more; A first electrode and a second electrode of each of the plurality of series stages extend in a first direction in each of the first to K-th subregions and are disposed at positions spaced apart from each other along a second direction intersecting the first direction; The first to K-th light-emitting elements are connected between the first electrode and the second electrode in the first to K-th sub-regions, respectively; a first electrode line connected to a first electrode of the first sub-region; a second electrode line connected to the second electrode of the Kth sub-region; and at least one intermediate electrode, disposed between two consecutive sub-regions from the first sub-region to the Kth sub-region, and connected to the second electrode of the previous sub-region and the first electrode of the next sub-region, wherein the at least one intermediate electrode extends in the second direction intersecting the first direction along which the first electrode and the second electrode extend, wherein the second electrode in the latter sub-region and the first electrode in the former sub-region are arranged at positions spaced apart from each other on a line relative to the first direction, and the first electrode in the latter sub-region and the second electrode in the former sub-region are arranged on a line relative to the first direction, or The first electrode in the rear sub-region and the first electrode in the front sub-region are arranged at positions spaced apart from each other on a line relative to the first direction, and the second electrode in the rear sub-region and the second electrode in the front sub-region are arranged at positions spaced apart from each other on a line relative to the first direction.

8. The display device according to claim 7, in, The first electrode line and the second electrode line are arranged to face each other, and the first sub-region to the Kth sub-region are placed between the first electrode line and the second electrode line, and Each of the first electrode lines and the second electrode lines extends in the second direction intersecting the first direction along which the first electrode and the second electrode extend.

9. The display device according to claim 8, wherein: The first and second electrode lines and the at least one intermediate electrode are arranged in parallel with each other, and at least one sub-region is disposed between the first and second electrode lines and the at least one intermediate electrode.

10. The display device according to claim 7, in, The first sub-region to the Kth sub-region are continuously arranged in the first direction, and The at least one intermediate electrode extends between the two continuous sub-regions along the second direction crossing the first direction.

11. The display device according to claim 10, wherein: The first electrode and the second electrode extend in the first direction and are disposed parallel to each other in each of the first to K-th sub-regions.

12. The display device according to claim 11, wherein: The first electrode and the second electrode are disposed at regular intervals in each of the first to K-th sub-regions.

13. The display device according to claim 7, wherein: The at least one intermediate electrode is integrally connected to the second electrode of the preceding sub-region and the first electrode of the succeeding sub-region.

14. The display device according to claim 7, wherein: The at least one intermediate electrode has a width smaller than a width of each of the first electrode lines and the second electrode lines.

15. The display device according to claim 7, in, The first electrode line is supplied with a first power voltage or a first driving signal, and The second electrode line is supplied with a second power voltage or a second driving signal.

16. The display device according to claim 15, wherein: The first pixel further includes a pixel circuit connected between the first electrode line and a first power source supplying the first power voltage.

17. The display device according to claim 7, wherein: The first electrode and the second electrode are disposed in the same repeating pattern in each of the first to K-th sub-regions.

18. The display device according to claim 7, wherein: In the two consecutive sub-regions, the first electrode and the second electrode are arranged in a symmetrical shape based on the at least one intermediate electrode.

19. The display device according to claim 7, further comprising a second pixel having the same structure as that of the first pixel and disposed adjacent to the first pixel, in, The first electrode line and at least one intermediate electrode of the first pixel and the first electrode line and at least one intermediate electrode of the second pixel are separated from each other between the first pixel and the second pixel.

20. The display device according to claim 19, wherein: The second electrode line of the first pixel and the second electrode line of the second pixel are integrally connected to each other.

21. The display device according to claim 7, in, The first pixel further includes at least one reverse light emitting element connected between the first electrode and the second electrode in at least one series connection stage of the plurality of series connection stages in a direction opposite to the light emitting element, and The number of the reverse light-emitting elements is less than the number of the light-emitting elements.

22. The display device according to claim 7, wherein: The first pixel further includes at least one of the following elements: A first partition wall is disposed below the corresponding first electrode; A second partition wall is disposed below the corresponding second electrode; first contact electrodes, disposed above the corresponding first electrodes and each configured to electrically connect a corresponding one of the first electrodes to a first end of at least one light emitting element; as well as The second contact electrodes are disposed above the corresponding second electrodes and are each configured to electrically connect a corresponding one of the second electrodes to a second end of at least one light emitting element. 23 . The display device according to claim 7 , further comprising a bank configured to integrally surround an emission region of the first pixel including the first to K th sub-regions.

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