Multi-level DC-DC converters

Abstract

A multi-stage DC-to-DC converter circuit and method permits a full range of output voltages, including near and at zone boundaries. Embodiments alternate between adjacent or neighboring zones, operating in a first zone for a selected time, and then operating in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge the capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution in which disordered state transitions are allowed to increase or decrease the voltage across a particular capacitor to prevent voltage overstress on the converter's main switches. Constraints may be imposed on the entire sequence of state transitions to reduce or avoid transition state switching, thereby allowing each capacitor an opportunity to have its voltage steered for balancing as needed.

Description

[0001] Cross-reference to related applications and claiming priority

[0002] This application claims priority to the following patent applications, all of which are assigned to the assignee of the present invention and are incorporated by reference in their entirety:

[0003] U.S. patent application No. 16 / 249,794, filed on January 16, 2019, entitled “Multi-Level DC-DC Converter with Boundary Transition Control”;

[0004] U.S. patent application No. 16 / 249,796, filed on January 16, 2019, entitled “Multi-Level DC-DC Converter with Lossy Voltage Balancing”; and

[0005] U.S. patent application No. 16 / 249,805, filed on January 16, 2019, entitled “Multi-Level DC-DC Converter with Lossless Voltage Balance.” background (1) Technical field

[0007] The present invention relates to electronic circuits, and more particularly to multi-level DC to DC converter circuits. (2) Background technology

[0009] Many electronic products, particularly mobile computing and / or communication products and components (e.g., laptops, ultrabooks, tablets, LCD and LED displays) require multiple voltage levels. For example, a radio transmitter power amplifier may require a relatively high voltage (e.g., 12V or higher), while logic circuitry may require a fairly low voltage level (e.g., 1V to 2V). Still other circuitry may require an intermediate voltage level (e.g., 5V to 10V). In addition, some electronic components, such as LCDs and LED displays, may require a variable voltage level to allow for different light intensity levels, such as from dim to bright.

[0010] A DC-to-DC converter is often used to generate a lower or higher DC voltage from a DC power source such as a battery. A DC-to-DC converter that generates intermediate and / or low voltage levels from a higher voltage DC power source is often called a buck converter, so called because V OUT Less than V IN, so the converter "steps down" the input voltage. DC-to-DC converters that generate a higher voltage level than the DC supply are often called boost converters because V OUT Greater than V IN Some DC-to-DC converter circuits can output multiple output voltages and can be configured as both a buck converter or a boost converter, with the operating mode selectable by control circuitry.

[0011] For example, FIG1 is a schematic diagram of a prior art two-stage inverting buck-boost converter circuit 100 based on an inductor. and The two switches designated are coupled in series between a DC input having a voltage V1 and a DC output having a voltage V2. The inductor L1 is coupled in parallel with the switches. and The switch may be, for example, an electronic switch, such as a field effect transistor, in particular a MOSFET. The clock signal and are complementary and are provided in a known manner by a clock / control circuit (not shown). Clock Duty Cycle - Clock Signal The ratio of on-time (ON) to off-time (OFF) determines the instantaneous voltage across inductor L1 and, therefore, the average voltage V2 at the output of the circuit (other circuitry not shown may be used to smooth V2). The output voltage V2 can be expressed in terms of V1 and the duty cycle DC as:

[0012] V2=-V1×[DC / (1–DC)] [Formula 1]

[0013] For example, if V l If the duty cycle is 5V and 40% (.4), then V2 equals -3.33V, while if the duty cycle is 60% (.6), then V2 equals -7V. The inductor L1 of the inverting buck-boost converter of Figure 1 is therefore exposed to two voltage levels (V1 and V2) and has two switching states ( ON and OFF, or OFF and ON), and is often considered a "2-level converter".

[0014] The problem with the circuit configuration of Figure 1 is that the minimum inductor size is limited by the maximum value of the difference between V1 and V2 and the lowest switching frequency of inductor L1. The larger the voltage difference and the lower the frequency, the larger the inductor needs to be. In addition, for some technologies (e.g., low-voltage CMOS), each switch The ability to withstand the OFF state voltage is the limiting factor of the input voltage range.

[0015] Therefore, there is a need for a DC-to-DC converter circuit and related methods that allow for a smaller minimum inductor size while permitting a full range of output voltages. There is also a need for related circuits and methods that avoid voltage overstress of the switching transistors. The present invention addresses these needs and more. Summary of the Invention

[0016] The present invention encompasses multi-stage DC-DC converter circuits and related methods that permit a full range of output voltages across all operating regions. Embodiments allow for the generation of output voltages very close to and at the boundaries of each region. Some embodiments include circuits and methods that allow for balancing capacitor voltages and avoiding voltage overstress on converter circuit switching transistors at startup and during operation.

[0017] More specifically, in order to generate an output voltage very close to the boundaries of each zone and at the boundaries of each zone, embodiments of the present invention essentially alternate (switch) between adjacent (or even adjacent) zones. Thus, the multi-stage DC-to-DC converter circuit according to this aspect of the invention will operate in the first zone for a selected time, and then operate in the second zone for a selected time before transitioning back to the first zone. Thus, the two zones are considered a single "super-zone."

[0018] Some embodiments of multi-stage DC-to-DC converter circuits include a parallel "shadow" capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge it, or couples two or more capacitors together to transfer charge from a higher-voltage capacitor to a lower-voltage capacitor, all under the control of real-time capacitor voltage measurement. The capacitor voltage is restored to a target voltage in real time, preventing the FET switches from seeing excessively high voltages. Additionally, the "shadow" capacitor voltage balancing circuit can be used to precharge the DC-to-DC converter capacitors at a relatively slow and uniform rate, causing the capacitor voltage to rise proportionally, thereby preventing voltage overstress on the DC-to-DC converter's main switches.

[0019] Some embodiments utilize a lossless voltage balancing solution that allows for chaotic state transitions within a multi-stage DC-to-DC converter circuit to occur during normal operation. The net effect of these chaotic state transitions is to increase or decrease the voltage across a particular capacitor, thereby preventing voltage overstress on the DC-to-DC converter's main switches. In some embodiments, constraints are placed on the entire sequence of state transitions to reduce or avoid transition state switching, allowing each capacitor the opportunity to have its voltage directed as needed, rather than forcing one capacitor to voltage balance and then another to voltage balance.

[0020] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic diagram of a prior art two-stage inverting buck-boost converter circuit based on an inductor.

[0022] Figure 2A FIG1 is a schematic diagram of an inductor-based multi-level inverting buck-boost converter circuit that overcomes many of the limitations of the two-stage converter of FIG1 .

[0023] Figure 2B is a schematic diagram of a general type of inductor-based multi-level converter circuit that can be configured as a buck-boost converter, or a buck converter, or a boost converter.

[0024] Figure 3A is a state transition diagram showing the state transitions of the switches of the 3-level converter in two operating regions.

[0025] Figure 3B is shown with Figure 3A Corresponding graph of the output voltage V2 range relative to the input voltage V1.

[0026] Figure 4A is a state transition diagram showing the state transitions of the switches of the 4-level converter in three operating regions.

[0027] Figure 4B is shown with Figure 4A A diagram of the corresponding regional voltage range.

[0028] Figure 5A is a state transition diagram showing the state transitions of switches of a 5-level converter in four operating regions.

[0029] Figure 5B is shown with Figure 5A A diagram of the corresponding regional voltage range.

[0030] Figure 6 is a schematic diagram of a 5-level DC to DC inverting buck-boost converter circuit.

[0031] Figure 7A It is aimed at Figure 6 A state transition diagram of a possible boundary region transition pattern for the boundary region between region 1 and region 2 of a 5-level DC-to-DC converter circuit.

[0032] Figure 7B It is aimed at Figure 6 A state transition diagram of a possible boundary region transition pattern for the boundary region between region 2 and region 3 of the 5-level DC-to-DC converter circuit.

[0033] Figure 7C It is aimed at Figure 6 A state transition diagram of a possible boundary region transition pattern for the boundary region between region 3 and region 4 of the 5-level DC-to-DC converter circuit.

[0034] Figure 7D is a set of timing diagrams that shows the Figure 7A The state transitions shown in FIG. 4A and FIG. 4B correspond to the duty ratios of Region 1, the sub-region Region 1-2_Low and the sub-region Region 1-2_High, and Region 2 described in Table 4A and Table 4B.

[0035] Figure 7E This is a diagram showing a mixture of duty ratios near the polarity inversion boundary according to the first embodiment.

[0036] Figure 7F This is a diagram showing a mixture of duty ratios near the polarity inversion boundary according to the second embodiment.

[0037] Figure 8 is a schematic diagram of a first embodiment of a multi-stage DC-to-DC converter circuit including a capacitor voltage balancing circuit according to the present invention.

[0038] Figure 9 is a timing diagram showing capacitor voltage (in relative volts) as a function of time (in milliseconds) for a 5-level multi-level DC to DC converter circuit.

[0039] Figure 10 is used for Figure 6 State transition diagram of a possible lossless capacitor voltage balancing transition mode for a 5-level DC-to-DC converter circuit.

[0040] Figure 11 is used for Figure 6 Schematic diagram of one embodiment of clock and control circuitry for a multi-stage DC-to-DC converter circuit of the type shown in .

[0041] Figure 12 It is shown by Figure 11 The generator circuit generates three triangle waveforms plus the error voltage V EAOut and timing diagrams of regional transitions for various bias voltages.

[0042] FIG. 13 is a block diagram of a typical prior art transceiver that might be used in a wireless device such as a cellular telephone.

[0043] Figure 14 A process flow diagram of a method for generating a full range of output voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage.

[0044] Figure 15 is a process flow diagram of a first method of balancing capacitor voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage.

[0045] Figure 16 is a process flow diagram of a second method of balancing capacitor voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage.

[0046] Like reference numbers in the various drawings indicate like elements. DETAILED DESCRIPTION

[0047] The present invention includes multi-stage DC-DC converter circuits and related methods that allow for a full range of output voltages across all operating regions. Embodiments allow for the generation of output voltages very close to and at the boundaries of each region. Some embodiments include circuits and methods that allow for balancing capacitor voltages and avoiding voltage overstress on converter circuit switching transistors.

[0048] Multi-level DC-to-DC converters

[0049] The inductor-based multi-stage DC-to-DC converter switches between at least three states, each of which defines one of at least three different voltages presented to the inductor (in contrast, the converter circuit of FIG. 1 switches between only two states). During normal operation for a specific input voltage and output voltage, the multi-stage converter circuit switches back and forth between the two states (e.g., between 0V and V1 / 2). However, when the input voltage and / or output voltage changes, it may be necessary to change to a different pair of states (e.g., V1 / 2 and V1). The inductor-based multi-stage DC-to-DC converter can be configured as a buck-only converter, a boost-only converter, or a buck-boost converter, and can be inverting or non-inverting.

[0050] As an example, Figure 2AFIG1 is a schematic diagram of a multi-level inductor-based inverting buck-boost converter circuit 200, a type that overcomes many of the limitations of the two-level converter of FIG1 . Multi-level converter 200 converts an input voltage V1 to an output voltage V2 by actively switching two or more series-connected switches (typically MOSFETs). The state transition pattern of the switches determines the operating region and the corresponding V2 range.

[0051] exist Figure 2A In the example of FIG. 1 , the multi-level converter circuit 200 includes a shunt inductor L1 bracketed by two sets ( V1 set, V2 set) of switches connected in series. The switches connected in series are driven by their respective clock signals (eg, and Where x=1 to N, and N is an integer ≥ 2). The switches connected in series include a switch path having a voltage input configured to be coupled to a voltage source and a voltage output configured to be coupled to an electrical load. Each pair of switches in the first group of switches coupled in series and the second group of switches coupled in series are separated by a corresponding node. Each pair of switches in a group (e.g., and ) is coupled to each pair of switches in another group (eg, and ) between the corresponding nodes. Therefore, the switch and The node A1 between the two terminals is coupled to the switch through capacitor C1. and Node A2 between them. Similarly, the clock signal for each V1 and V2 switch group and are complementary and are provided by a control circuit (not shown).

[0052] Figure 2B is a schematic diagram of a general type of inductor-based multi-level converter circuit 250 that can be configured as a buck-boost converter, a buck converter, or a boost converter. Although similar in most respects to Figure 2A The multi-level converter circuit 200 is shown in FIG. 2 , but the inductor L1 can be considered to have a different circuit node C that can be connected in a variety of different configurations.

[0053] For example, connecting circuit node C to circuit ground 252 and using circuit nodes A and D for DC input and terminals B and E for DC output produces Figure 2A2. A multi-stage inverting buck-boost converter circuit 200 is shown. In another configuration, if circuit node B is connected to circuit ground 252 and an input voltage is applied at circuit nodes A and D, the output voltage at circuit nodes C and E will be a fraction of the input voltage, resulting in a buck converter configuration. In yet another configuration, if circuit node B is connected to circuit ground 252 and an input voltage is applied at circuit nodes C and E, the output voltage at circuit nodes A and D will be a multiple of the input voltage, resulting in a boost configuration. Thus, the circuitry within dashed box 254 can be considered a three-terminal core device having circuit nodes or terminals A, B, and C.

[0054] For any allowed value of N, the inductor L1 of the multi-level converters 200, 250 is exposed to more than two voltage levels and has more than two states. By increasing the number of levels, the voltage across the inductor L1 is reduced, thereby reducing the required inductance.

[0055] For example, if Figure 2A If the converter circuit is configured such that N=2, the circuit will function as a 3-level converter comprising two sets of two switches (four switches in total), a capacitor C1, and an inductor L1. The switches will be driven by a 2-phase clock mode. For example, Figure 3A is a state transition diagram showing the state transitions of the switches of the 3-level converter in two operating regions, and Figure 3B is shown with Figure 3A A plot of the corresponding range of regional output voltages V2 relative to input voltage V1. Different switching modes determine which region is operational and in what state, and output voltage V2 is regulated by controlling the time converter 200 spends in each state transition STx (similar to the variable duty cycle of a conventional 2-level converter). The duty cycle of a region is the amount of time spent in the first state transition (e.g., ST1) relative to the amount of time spent in the second state transition (e.g., ST2). For example, a duty cycle of 33% / 67% for Region 1 of a 3-level converter means that the bit sequence in ST1 is enabled for 33% of the cycle, and the bit sequence in ST2 is enabled for 67% of the cycle.

[0056] exist Figure 3A In the example shown in FIG1 , operation in region 1 allows the output voltage V2 to range from approximately 0 to approximately -1 / 1V1 (i.e., -1V1 at a 50% duty cycle of the equivalent 2-level converter circuit; see Equation 1 above). Operation in region 2 allows the V2 output voltage to range from approximately -1V1 to a value close to negative infinity (at a 100% duty cycle of the equivalent 2-level converter circuit). The binary value of each state transition STx represents Figure 2A The corresponding switch in the V1 switch group (in this example and ) of the conducting (ON) state or disconnecting (OFF) state; the states of the switches in the V2 switch group will be exactly complementary. In the following example, each state transition ST x The least significant bit is mapped to the switch The next more significant bit is mapped to the switch Each additional significant bit maps to the next switch in the line, and thus the most significant bit N maps to switch

[0057] Therefore, in Figure 3A When operating in zone 1, the switch and Both are initially OFF (ST1=00 in the first row) and then transition to ON and OFF (ST2=10 in the first row), respectively. (Correspondingly, the complementary switches in the V2 group and Both are initially ON and then transition OFF and ON respectively. The next transition in region 1 switches and Both are set to OFF (ST1=00 in the second row) and then transition to OFF and ON respectively (ST2=01 in the second row). The next transition is from ST2=01 in the second row to ST1=00 in the third row. This completes one switching cycle of the 3-level converter circuit when operating in region 1, and the cycle repeats. When operating in region 2, the switches and Initially, they are on and off (ST2=10 in the first row), and then both turn on (ST3=11 in the first row). The next transition in region 2 turns the switch and The first two levels are set to off and on (ST2=01 in the second row), and then both are turned on (ST3=11 in the second row). The next transition is from ST3=11 in the second row to ST2=10 in the third row. This completes one switching cycle of the 3-level converter circuit when operating in region 2, and the cycle repeats.

[0058] like Figure 3BAs a rough guide, operation in Region 1 allows for a range of reverse buck voltages (0 to approximately -1V1), while operation in Region 2 allows for a range of reverse boost voltages (approximately -1V1 to something close to negative infinity), in both cases depending on the duty cycle selected for state transition STx. Compared to the inductor of the 2-level converter, the inductor L1 of the 3-level converter sees twice (2×) the fundamental frequency and no more than half the voltage. Therefore, the lower voltage and higher frequency experienced by inductor L1 allow the use of a smaller inductor.

[0059] As another example, if Figure 2A If the converter circuit is configured such that N=3, the circuit will function as a 4-level converter comprising two groups of three switches (six switches in total), two capacitors C1, C2 and an inductor L1. The switches will be driven by a three-phase clock pattern. For example, Figure 4A is a state transition diagram showing the state transitions of the switches of the 4-level converter in the three operating regions, and Figure 4B is shown with Figure 4A The corresponding region voltage range is shown in the figure. Similarly, different switching modes determine which region is operational. Figure 4A In the example shown in FIG1 , operation in Region 1 allows the V2 output voltage to range from approximately 0 to approximately -1 / 2V1 (at an equivalent 2-stage converter circuit duty cycle of approximately 33%). Operation in Region 2 allows the V2 output voltage to range from approximately -1 / 2V1 to approximately -4 / 2V1 (i.e., -2V1 at an equivalent 2-stage converter circuit duty cycle of approximately 67%). Operation in Region 3 allows the V2 output voltage to range from approximately -2V1 to something approaching negative infinity (at an equivalent 2-stage converter circuit duty cycle of 100%). The binary value of each state transition STx represents the V1 switch group (in this example, and ) in the on or off state of the corresponding switch in the V2 switch group; likewise, the states of the switches in the V2 switch group will be exactly complementary. Compared to the inductor of the 2-level converter, the inductor L1 of the 4-level converter sees three times (3×) the fundamental frequency and experiences no more than 1 / 3 the voltage, so a significantly smaller inductor can be used.

[0060] As another example, if Figure 2A If the converter circuit is configured such that N=4, the circuit will function as a 5-level converter comprising three groups of three switches (eight switches in total), three capacitors C1, C2, C3, and an inductor L1. The switches will be driven by a 4-phase clock pattern. For example, Figure 5A is a state transition diagram showing the state transitions of the switches of the 5-level converter in four operating regions, and Figure 5B is shown with Figure 5AThe corresponding region voltage range is shown in the figure. Similarly, different switching modes determine which region is operational. Figure 5A In the example shown in FIG1 , operation in region 1 allows the V2 output voltage to range from approximately 0 to approximately -1 / 3V1 (at a 25% duty cycle of the equivalent 2-stage converter circuit). Operation in region 2 allows the V2 output voltage to range from approximately -1 / 3V1 to approximately -3 / 3V1 (i.e., -1V1, at a 50% duty cycle of the equivalent 2-stage converter circuit). Operation in region 3 allows the V2 output voltage to range from approximately -1V1 to approximately -9 / 3V1 (i.e., -3V1, at a 75% duty cycle of the equivalent 2-stage converter circuit). Operation in region 4 allows the V2 output voltage to range from approximately -3V1 to something approaching negative infinity (at a 100% duty cycle of the equivalent 2-stage converter circuit). The binary value of each state transition STx represents the corresponding switch in the V1 switch group (i.e., and )'s on state or off state; similarly, the states of the switches in the V2 switch group will be exactly complementary.

[0061] Compared to the inductor of the 2-level converter, the inductor L1 of the 5-level converter sees four times (4×) the fundamental frequency and experiences no more than 1 / 4 the voltage, thus allowing the use of a significantly smaller inductor. For example, Table 1 compares the voltage across inductor L1 of a conventional 2-level inverting buck-boost architecture with the voltage across inductor L1 of a 5-level inverting buck-boost architecture for the same V1 and V2 voltage levels.

[0062]

[0063] Table 1

[0064] Multilevel DC-to-DC Converter Design Challenges

[0065] Despite having many advantages over 2-level converters, multi-level converters are more complex and difficult to control. One significant problem is that while generating a V2 output voltage that is within each region is relatively simple, generating V2 very close to and at the boundaries of each region is generally not possible due to the finite pulse width of the clock signal and the fact that the duty cycle cannot actually be 0% or 100%. For example, generating a V2 output of exactly -1 / 3 V1 in a 5-level converter would require a 100% duty cycle state for capacitor C2, which is impossible. More generally, the minimum duty cycle is determined by the minimum pulse width that the circuit can handle. For example, if the minimum pulse width is 12ns and the frequency seen by inductor L1 is 5MHz (200ns period), then the minimum duty cycle will be 6%. In Figure 3B 、 Figure 4B and Figure 5BIn FIG, the wide black band at the boundary of each region is the "boundary region", which represents the output voltage V2 that cannot be obtained using a conventional multi-stage DC to DC converter circuit. For example, referring to Figure 3B , Region 1 and Region 2 should theoretically abut -V1, but actual circuits cannot generate output voltages very close to (eg, ±6-10%) or at the theoretical boundaries of each region.

[0066] Another challenge is to ensure that the capacitor voltages are perfectly balanced so that all FET switches experience similar V DS However, there are non-ideal conditions that can cause the capacitor voltages to become unbalanced, such as mismatched capacitance, capacitor equivalent series resistance (ESR), FET switch on-resistance (R ON ) and asymmetric capacitor charging / discharging (e.g., due to different series combinations of switches and capacitors between states). Unbalanced capacitors can cause breakdown of FET switches due to exposure to excessive voltage.

[0067] A related problem is that an excessively high charging rate of the capacitor may cause voltage overstress on the switching transistor during startup of the converter circuit.

[0068] In order to generate an output voltage very close to the boundaries of each region and at the boundaries of each zone, embodiments of the present invention essentially alternate (switch) between adjacent (or even neighboring) regions. Thus, a multi-level DC-to-DC converter circuit according to this aspect of the invention will operate in a first region for a selected time, and then operate in a second region for a selected time before switching back to the first region. Thus, the two regions are considered a single "super-region."

[0069] Some embodiments of multi-stage DC-to-DC converter circuits include a parallel "shadow" capacitor voltage balancing circuit that connects a capacitor Cx to a source voltage to charge the capacitor, or couples two or more capacitors Cx together to transfer charge from a higher-voltage capacitor to a lower-voltage capacitor, all under the control of real-time capacitor voltage measurements. The capacitor voltage is restored to a target voltage in real time, preventing the FET switches from seeing excessively high voltages. Additionally, the "shadow" capacitor voltage balancing circuit can be used to precharge the DC-to-DC converter capacitors at a relatively slow and uniform rate, causing the capacitor voltage to rise proportionally, thereby preventing voltage overstress on the DC-to-DC converter's main switches.

[0070] Some embodiments utilize a lossless voltage balancing solution that allows for chaotic state transitions within a multi-stage DC-to-DC converter circuit to occur during normal operation. The net effect of these chaotic state transitions is to increase or decrease the voltage across a particular capacitor, thereby preventing voltage overstress on the DC-to-DC converter's main switches. In some embodiments, constraints are placed on the entire sequence of state transitions to reduce or avoid transition state switching, allowing each capacitor the opportunity to have its voltage directed as needed, rather than forcing voltage balancing on one capacitor and then another.

[0071] 5-Level DC-to-DC Converter Circuit Example

[0072] For ease of understanding, the examples described in this specification utilize a 5-level DC to DC converter circuit. For example, Figure 6 is a schematic diagram of a 5-level DC to DC inverting buck-boost converter circuit 600. However, without loss of generality, the inventive aspects of the present invention may be applied to other multi-level DC to DC converter circuits, including non-inverting versions, buck-only versions, and boost-only versions.

[0073] exist Figure 6 In the example, the clock and control circuit 602 provides a variable duty cycle clock pulse to the V1 switch group. And provide variable duty cycle clock pulses to the V2 switch group Wherein, for this example, x=1 to 4. The clock pulses for the V2 switch group are complementary to the corresponding clock pulses for the V1 switch group. The clock pulses are essentially pulse width modulated (PWM) switching voltages.

[0074] For normal operation, the clock pulses are Figure 5A The regional pattern shown in FIG is applied to a 5-level DC to DC converter circuit 600 to generate Figure 5A The output voltage V2 is within the range shown in FIG. Therefore, in order to select a specific output voltage V2, it is determined which region should be selected as the operating region (thereby determining the pattern of the state transition bit sequence) and the corresponding duty cycle (thereby determining the specific value of V2 relative to V1). For example, if V1 = 3V, then for a desired V2 of -0.922V (therefore, V2 will be less than -1 / 3V1), Figure 5AIn the example of FIG. 6 , the clock and control circuit 602 may be in region 1, and the duty cycle in the ST1 state may be 6% of the cycle time, and the duty cycle in the ST2 state may be 94% of the cycle time. A duty cycle exceeding 6% of the cycle time in the ST1 state and a duty cycle less than 94% of the cycle time in the ST2 state will cause V2 to have a value closer to zero. In some embodiments, the clock and control circuit 602 may include a mapping of V2 (relative to V1) based on the region and cycle time value, which can be determined for a specific circuit by modeling, calculation, and / or empirical calibration. The mapping can be implemented in a lookup table (LUT) or in combinational logic.

[0075] Figure 6 Switch in It can be, for example, a field effect transistor (especially a MOSFET) and can be implemented on an integrated circuit "chip". A single switch symbol is shown, but the switch One or more of the transistors may comprise, for example, a series stack of transistors, particularly MOSFETs, to handle higher voltages.

[0076] The three capacitors C1 to C3 preferably have the same value and are typically spaced relative to the switch. Off-chip. Inductor L1 will also typically be off-chip. As an example of values ​​for a 1.25 MHz switching frequency, capacitors C1 to C3 can be approximately 2 microfarads or higher, and inductor L1 can be approximately 110 nanohenries. For the configuration shown, the capacitor voltage V Cx Under ideal proportional balance conditions as described in Table 2.

[0077] Capacitor voltage <h2 style=";text-align:left;direction:ltr"><![CDATA[V <h2 style=";text-align:left;direction:ltr"> C1 <h2 style=";text-align:left;direction:ltr"> =1 / 4(V1–V2)]]><h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr"><![CDATA[V <h2 style=";text-align:left;direction:ltr"> C2 <h2 style=";text-align:left;direction:ltr"> =1 / 2(V1–V2)]]><h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr"><![CDATA[V <h2 style=";text-align:left;direction:ltr"> C3 <h2 style=";text-align:left;direction:ltr"> =3 / 4(V1–V2)]]><h2 style=";text-align:left;direction:ltr">

[0078] Table 2

[0079] Boundary area transformation

[0080] To generate output voltages within the boundary regions, embodiments of the present invention essentially alternate (switch) between adjacent (or even neighboring) regions by setting the states of the converter circuit switches in a boundary region transition pattern. For a 5-level DC-to-DC converter circuit, there are three boundary regions between Region 1 and Region 2, between Region 2 and Region 3, and between Region 3 and Region 4; see, for example, Figure 5B Thus, in one example embodiment, to generate an output voltage V2 near or at the theoretical boundary between Region 2 and Region 3 (i.e., near or at -V1 in this example), the switch will toggle between state transitions ST2, ST3, and ST4 (see Figure 7B, further described below). Thus, for this particular example, the 5-level DC-to-DC converter circuit 600 will operate in Region 2 for a selected time and in the adjacent Region 3 for a selected time. Thus, Region 2 and Region 3 are considered a single "super-region." More generally, in certain situations, it may be useful to create a super-region using non-adjacent regions or using more than two regions (adjacent and / or non-adjacent).

[0081] According to the present invention, many different boundary region transition modes can be used to alternately switch between regions. For example, 7A to 7C is used for Figure 6 A state transition diagram of possible boundary region transition patterns of the boundary regions of the 5-level DC to DC conversion circuit 600. The transition states within each region and between each region preferably follow a reflected binary code (also known as Gray code) bit sequence so that only one bit position is changed per transition, thereby reducing switching losses and the magnitude of voltage transients. 7A to 7C A specific reflected binary code is shown in , but other reflected binary code bit sequences may be used.

[0082] Figure 7A It is aimed at Figure 6 FIG1 is a state transition diagram of one possible boundary region transition pattern for a 5-level DC-DC converter circuit 600 for the boundary region between Region 1 and Region 2. In the example shown, starting at ST1 0000, the 5-level converter circuit 600 first transitions to ST2 1000, the same Region 1 transition as a conventional 5-level converter. However, the second transition is from ST2 1000 to ST3 1100—i.e., to Region 2 (in contrast, in a conventional converter, the second transition would be from ST2 1000 to ST1 0000, both in Region 1). The third transition is from ST3 1100 to ST2 0100 (in region 2), the fourth transition is from ST2 0100 to ST1 0000 (back to region 1, indicated by the "top" left arrow in the second row), the fifth transition is from ST1 0000 to ST2 0100 (in region 1, indicated by the "bottom" right arrow in the second row), and the sixth transition is from ST2 0100 to ST3 0110 (back to region 2). The remaining transitions within and between regions 1 and 2 of super-region 1-2 are similar. Figure 7A The super region 1-2 of FIG. 1 has a total of 16 transitions constituting one repeating cycle, whereas the conventional single region pattern has 8 transitions (see FIG. 1 for an example). Figure 5A ). Figure 7A The bit sequence of the transition state in the Figure 6 The V1 switch group in the Figure 6The bit sequence of the V2 switch group in will be complementary. When powered up for this operating mode, the power-on reset initializes the circuit state to ST10000 in region 1.

[0083] Figure 7B It is aimed at Figure 6 A state transition diagram of a possible boundary region transition pattern for the boundary region between region 2 and region 3 of the 5-level DC-DC converter circuit 600. The pattern of state transition within a region and state transition between regions is similar to Figure 7A is similar, but the bit sequence values ​​are different for each state. Similarly, Figure 7C It is aimed at Figure 6 A state transition diagram of a possible boundary region transition pattern for the boundary region between region 3 and region 4 of the 5-level DC-DC converter circuit 600. The pattern of state transition within a region and state transition between regions is similar to Figure 7A Similar (again, the bit sequence value is different for each state).

[0084] Therefore, when in the boundary region operating mode, the clock and control circuit 602 controls the switching state using a 16-transition cycle. Figure 6 In contrast, when in normal operating mode (ie, not near or at a region boundary), the clock and control circuit 602 controls the V1 and V2 switch groups using an 8-transition cycle of switch states.

[0085] Depend on Figure 5A and 7A to 7C The bit sequences (and their complementary bit sequences) represented by the binary values ​​in Figure 6 The clock and control circuit 602 generates a bit sequence and outputs the appropriate switch voltage to Figure 6 Switch in Set the corresponding on-state or off-state. A simple 3-bit control code can be used to select the mode of regional or boundary region operation for the clock and control circuit 602; an example of such a region selection code is shown in Table 3. Alternatively, the clock and control circuit 602 can be coupled to a direct control line for each region (i.e., non-binary coded); thus, for the current example, 7 control lines would be required to select among the regions (including the boundary regions). In either case, the value of the region selection code can be determined by selecting (statically or dynamically) a particular output voltage V2, which in turn can be caused by applying a digital code or an analog voltage or current to the clock and control circuit 602.

[0086] Control Line# Region selection code Active area / boundary area 1 000 Area 1 2 001 Boundary Area 1-2 3 010 Area 2 4 011 Boundary Area 2-3 5 100 Area 3 6 101 Boundary Area 3-4 7 110 Area 4

[0087] Table 3

[0088] The clock and control circuit 602 may include a mapping of V2 (relative to V1) based on the normal region, the boundary region, and the cycle time value. The mapping value may be determined for a particular circuit by modeling, calculation, and / or empirical calibration. The mapping may be implemented in a lookup table (LUT) or in combinational logic. A more detailed example of the clock and control circuit is described below with respect to Figure 11 Provide a description.

[0089] Transformation of bounding regions using subregions

[0090] Although 7A to 7C Shown Figure 6 Which switches in the circuit 602 are set to be on or off to achieve an output voltage V2 near or at a theoretical inter-region boundary, but enhancements can be made to smooth the transitions from region to region. In particular, the complexity of switching capacitors C1 to C3 and inductor L1 between states may require some dynamic control of the duty cycle (pulse width) for each selected regional operating mode to better match V2 at the region transition boundaries. Therefore, it is often useful to design the clock and control circuit 602 to generate a duty cycle that provides a smooth V2 voltage ramp near and at the region boundaries.

[0091] In some embodiments where the polarity of the error amplifier is periodically reversed to allow for an increase in the effective output voltage range of the error amplifier, it has been found useful to subdivide the boundary region into two portions, one on the lower voltage side of the theoretical region boundary and the other on the higher voltage side of the theoretical region boundary. In such embodiments, the error amplifier polarity is reversed at the junction of the two portions or subregions. For example, the boundary region between Region 1 and Region 2 can be divided to include a Region 1-2_Low subregion and a Region 1-2_High subregion; similar subdivisions can be made for the boundary region between Region 2 and Region 3, and for the boundary region between Region 3 and Region 4. In addition to the error amplifier polarity reversal in these embodiments, the clock synchronization between the low and high boundary subregions varies between a fixed pulse width and a modulated pulse width, as further described below.

[0092] Taking super region 1-2 as an example, when V l=3V, Table 4A shows possible duty cycles for operation in Region 1 near the low side of the boundary between Regions 1 and 2 (transitioning towards Region 2). With a selected value of 6% of the cycle time in the ST1 state and a selected value of 94% of the cycle time in the ST2 state, V2 = -0.922V. If a particular clock and control circuit 602 cannot generate a duty cycle less than 6%, then a boundary region transition can be used to obtain a V2 value closer to and at the theoretical boundary between Regions 1 and 2. For example, using Figure 7A For the 16 state transition cycles shown in FIG, V2 = -0.785 V is generated for a Region 1-2_Low sub-region duty cycle of 17% for ST1 and a Region 1-2_Low sub-region duty cycle of 83% for ST2, and V2 = -1.082 V is generated for a Region 1-2_Low sub-region duty cycle of 6% for ST3 and a Region 1-2_Low sub-region duty cycle of 94% for ST2, for an average V2 of -0.934 V (keeping in mind that other circuitry, such as an output storage capacitor, can be used to further smooth V2). It is noteworthy that the duty cycle of the ST1-ST2 state transition in the Region 1-2_Low sub-region actually increases to generate a lower V2 voltage to offset the higher V2 voltage of the ST2-ST3 state transition.

[0093]

[0094] Table 4A

[0095] Similarly, Table 4B shows possible duty cycles for operation in the Region 1-2_High sub-region (again, transitioning toward Region 2). A duty cycle of 6% for ST1 and 94% for ST2 yields V2 = -0.922, and a duty cycle of 17% for ST3 and 83% for ST2 yields V2 = -1.24V, for an average V2 of -1.081V. Achieving higher V2 values ​​ultimately requires operating in Region 2, near the high side of the theoretical boundary between Regions 1 and 2. With a selected value of 94% of the cycle time in the ST2 state and 6% of the cycle time in the ST3 state, V2 = -1.082V. Note that the transition between Region 1-2_Low and Region 1-2_High can be considered (and implemented) as a polarity reversal of the duty cycle (17 / 83 / 94 / 6% in Region 1-2_Low vs. 6 / 94 / 83 / 17% in Region 1-2_High).

[0096]

[0097] Table 4B

[0098] The example duty cycles in Tables 4A and 4B show that V2 ramps smoothly from low to high. Similar tables can be generated for the sub-regions region 2-3_low and region 2-3_high, and the sub-regions region 3-4_low and region 3-4_high. It should be clear that other duty cycle values ​​(and other values ​​of V1) will produce other values ​​of V2. However, the goal is to select a duty cycle that closely matches (a) the V2 within the region but near the boundary region with (b) the average V2 of the two regions between which the boundary region switches.

[0099] Figure 7D is a set of graphs showing the corresponding regions for Region 1, sub-regions Region 1-2_Low and Region 1-2_High, and Region 2. Figure 7A The state transitions shown in Table 4A and Table 4B correspond to the duty cycles described in Table 4A. The duty cycle diagram for Region 1 corresponds to the Region 1 variable-width "error amplifier" path values ​​in Table 4A. The diagram for Region 1-2_Low is a combination of the following two duty cycles: the Region 1-2_Low variable-width "error amplifier" path values ​​and the Region 1-2_Low fixed-width "fixed bias" path values ​​in Table 4A. The diagram for Region 1-2_High is a combination of the following two duty cycles: the Region 1-2_High fixed-width "fixed bias" path values ​​and the variable-width "error amplifier" path values ​​in Table 4B. The duty cycle diagram for Region 2 corresponds to the Region 2 variable-width "error amplifier" path values ​​in Table 4B.

[0100] In the embodiment shown, for output settings very close to the transition from Region 1-2_Low to Region 1-2_High (the "polarity reversal boundary"), the duty cycle can be considered to be a mix of the Region 1-2_Low combined duty cycle and the Region 1-2_High combined duty cycle. For example, Figure 7E is a graph showing the mix of duty cycles near the polarity reversal boundary of the first embodiment. Note that some pulse widths are fixed and some pulse widths are variable, and the percentage of variable width pulses is the endpoint value. In this example, the variable pulse widths for ST1 and ST3 can range between 6% and 17%. As the variable pulse width moves away from the polarity reversal boundary toward region 1 (left) or region 2 (right), the variable pulse width increases, and it typically takes many cycles for the variable width pulse to change from 17% to 6% or from 6% to 17% near the polarity reversal boundary. When used below in Figure 11 When the control loop of the circuit shown in settles to the correct output voltage for the current conditions (selected settings and load), the variable pulse width will stop changing. Whenever the commanded output voltage changes or there is a load step transient (meaning the output load current changes), the variable pulse width will change again.

[0101] Figure 7FFIG is a diagram showing the mixing of duty ratios near the polarity inversion boundary of the second embodiment. Figure 7E The description applies to Figure 7F , the only difference is the location of the polarity reversal boundary between the fixed width ST3 and ST1 pulses, while in Figure 7E In FIG, the polarity reversal boundary is between the variable width ST1 and ST3 pulses. Figure 7E and Figure 7F A mixed duty cycle mode of is an alternative; in practice, typically only one mixed duty cycle mode will be used.

[0102] A simple 4-bit control code can be used to select the mode of regional operation for the clock and control circuit 602—region transition or boundary sub-region transition (low or high); an example of such a region selection code is shown in Table 5. Alternatively, the clock and control circuit 602 can be coupled to direct control lines for each region (i.e., non-binary coded); thus, for the current example, 10 control lines would be required to select between regions and boundary sub-regions. In either case, the value of the region selection code is determined by the selection (statically or dynamically) of a particular output voltage V2, which in turn can be caused by applying a digital code or an analog voltage or current to the clock and control circuit 602.

[0103] Control Line# Region selection code Active area / boundary sub-area 1 0000 Area 1 2 0001 Region 1-2_Low (Boundary Sub-Region) 3 0010 Region 1-2_High (Boundary Sub-Region) 4 0011 Area 2 5 0100 Region 2-3_Low (Boundary Sub-Region) 6 0101 Region 2-3_High (Boundary Sub-Region) 7 0110 Area 3 8 0111 Region 3-4_Low (Boundary Sub-Region) 9 1000 Region 3-4_High (Boundary Sub-Region) 10 1001 Area 4

[0104] Table 5

[0105] In the following about Figure 11 The specific clock and control circuitry used to select active regions (including border sub-regions) is described in detail.

[0106] Capacitor Voltage Balancing - First Embodiment

[0107] As mentioned above, one challenge of multi-stage DC-to-DC converter circuits is to ensure that the capacitor voltages are substantially perfectly proportionally balanced so that all FET switches experience similar drain-to-source voltages, V DS , because unbalanced capacitors can cause breakdown of FET switches due to exposure to high voltage. Figure 6 For the 5-stage DC-to-DC converter circuit 600, the fully proportionally balanced capacitor target voltage would be as shown in Table 2 above; at such a target voltage, all switches would see 1 / 4 (V1–V2) of V DS Also note that even in the 3-stage with a single capacitor C1, the capacitor voltage needs to be managed (balanced) so that the coupled FET switches experience similar drain-to-source voltages V DSHowever, due to the aforementioned non-ideal conditions that can cause the capacitor voltage to become unbalanced, the capacitor voltage needs to be restored to the target voltage in real time to prevent the FET switch from seeing excessively high voltages.

[0108] One solution for balancing capacitor voltages in a multi-stage DC-to-DC converter circuit is to provide a parallel "shadow" circuit that conditionally couples capacitor Cx to a source voltage to charge the capacitor, conditionally couples two or more capacitors Cx together to transfer charge from a higher-voltage capacitor to a lower-voltage capacitor, or conditionally couples capacitor Cx to a voltage sink to discharge the capacitor, all under the control of real-time capacitor voltage measurement. For many practical implementations, it is preferred to maintain the capacitor voltage within a target voltage of typically about 250 mV, but no more than about 500 mV. However, note that these two numbers are arbitrarily chosen for a particular implementation. More generally, a smaller voltage tolerance is better, but should be large enough to be unaffected by circuit-level transient noise.

[0109] For example, Figure 8 FIG is a schematic diagram of a first embodiment of a multi-stage DC to DC converter circuit 800 including a capacitor voltage balancing circuit according to the present invention. Figure 6 The control circuitry shown in FIG. 8 and the connection of the voltage detection and correction signal generation circuit 804 to the capacitor Cx are shown. One aspect of the capacitor voltage balancing circuit shown is a switch-resistor network 802 comprising a pair of switches SWx and resistors Rx connected in series, which are also connected to the main switches of the DC-to-DC converter circuit (a 5-stage circuit in this example). Each pair of switch SWx and resistor Rx is connected to at least one main switch In the embodiment shown, the innermost pair of main switches Both are spanned by a single parallel pair of switch SWx and resistor Rx (SW4 and R4 in this example).

[0110] Figure 8 The switches SWx in FIG. 5 may be, for example, field effect transistors (particularly MOSFETs) and may be implemented on an integrated circuit "chip." Although a single switch symbol is shown for each switch SWx, one or more of the switches SWx may include a series stack of transistors (particularly MOSFETs), e.g., to handle higher voltages.

[0111] In one example embodiment, the resistor Rx has the values ​​shown in Table 6 (as a reference point, with these example resistors, the main switch With an on-resistance R of approximately 10 milliohms ON , which is approximately 2500 to 5000 times smaller than the resistance of the switch-resistor pair SWx-Rx of the capacitor voltage balancing circuit. In another example embodiment, each switch and resistor pair is configured to have a resistance of approximately 50 ohms. Note that these resistor values ​​are selected for a particular embodiment. Higher or lower resistor values ​​can be used relative to the capacitor values ​​(e.g., C1, C2, C3) and the speed at which they can control the capacitor voltage.

[0112]

[0113]

[0114] Table 6

[0115] exist Figure 8 In the specific example shown, the outermost switches SW1 and SW7 are controlled to connect capacitor C3 to the input DC voltage source V1 and the output V2 for charging; the innermost switch SW4 is controlled to short-circuit capacitor C1 through resistor R4 for discharging; and the middle switches SW2, SW3, SW5, and SW6 are controlled to connect the corresponding capacitors together to transfer charge. Charge will always be transferred from the higher voltage capacitor to the lower voltage capacitor, thereby reducing the voltage of the higher voltage capacitor and increasing the voltage of the lower voltage capacitor.

[0116] The voltage detection and correction signal generation circuit 804 coupled to the capacitor Cx (also in Figure 6 ) continuously senses the deviation of the capacitor voltage relative to the corresponding reference value and generates a voltage with an “upward” (eg, Cx ∧ ) or "down" (e.g., Cx ∨ ) value. The voltage detection and correction signal generating circuit 804 can be implemented, for example, using an error amplifier or similar comparator to compare a reference voltage with the instantaneous voltage across the corresponding capacitor. However, one of ordinary skill in the art can utilize any of a variety of known analog and / or digital voltage measurement circuits to generate such a correction signal. In any case, it may be useful to use a hysteresis error amplifier or comparator, where the hysteresis voltage is the control tolerance. As is known in the art, hysteresis sets upper and lower thresholds to eliminate multiple transitions at frequencies that are too high. In the presence of noise on a slow-moving signal at the input of a buffer or comparator, hysteresis is typically used to eliminate output "jitter." In this example, the amount of hysteresis can be selected to be the same as the capacitor voltage control tolerance.

[0117] In the example shown, six capacitor steering signals (C3 ∧ / C3∨ 、C2 ∧ / C2 ∨ and C1 ∧ / C1 ∨ ), the combining circuit 806 combines some pilot signals and generates four control signals: and in, It is C3 ∨ and C2 ∧ The logical OR of the correction signals, and It's C2 ∨ and C1 ∧ The correction signals are logically ORed. The four control signals are coupled to the series-connected switches SWx (where x=7 in this example) of the switch-resistor network 802; the same control signal can be coupled to more than one switch. Note that the combination circuit 806 is shown as a separate component only to clearly illustrate the different functions provided by the combination circuit 806 and the voltage detection and correction signal generation circuit 804; however, the functions of the two circuits can be combined into a single directional correction circuit 808.

[0118] Capacitor voltage balancing circuit and main switch The normal operation of the capacitor voltage balancing circuit is parallel to the timing of the control signal generated by the main switch. In addition, the timing of the clock signal used for the main switch When the clocks of SWx are complementary (out of phase), the control signals of the capacitor balancing switches SWx on both sides of the inductor L1 are in phase.

[0119] In the illustrated 5-level multi-level DC-to-DC converter circuit 800, each generated control signal turns on a corresponding switch or switches to allow the corresponding capacitor to begin charging or discharge by directly connecting to a voltage source or sink or by allowing charge to be shared between the corresponding capacitors. Thus, for example, when switches SW1 and SW7 are turned on by When the control signal is turned on, capacitor C3 is coupled to V1 and V2 and starts to charge. When the voltage across capacitor C3 matches the corresponding reference voltage applied to the voltage detection and correction signal generating circuit 804, no voltage is generated. control signal, and switches SW1 and SW7 will return to the off state. As another example, when switch SW4 is When the control signal is turned on, the capacitor C1 is shorted through R4 and begins to discharge. When the voltage across the capacitor C1 matches the corresponding reference voltage applied to the detection and correction signal generating circuit 804, no signal is generated. As another example, if switches SW2 and SW6 are connected by When the combined control signal turns on, capacitors C2 and C3 are connected together and excess charge is transferred from the higher voltage capacitor to the lower voltage capacitor until the control signal returns to the off state.

[0120] Therefore, the voltage V across the capacitor Cx can be adjusted by one or more control signals from the orientation correction circuit 808. Cx "guided" upward (to a higher voltage) or downward (to a lower voltage) relative to each other toward equilibrium. Table 7 for Figure 8 The example 5-level multi-level DC to DC converter circuit 800 illustrates the control signals and the corresponding steering effects.

[0121]

[0122] Table 7

[0123] It should be clear that although Figure 8 The example of FIG. 8 shows a five-stage multi-stage DC-to-DC converter circuit 800, but the example circuit system for balancing the voltage across capacitor Cx can be extended to other multi-stage DC-to-DC converter circuits, including buck converter circuits, boost converter circuits, or buck-boost converter circuits (any of which can be inverting or non-inverting). The switch-based capacitor voltage balancing method and circuit system can be used with any stage of multi-stage DC-to-DC converter circuits and can be used with conventional multi-stage DC-to-DC converter circuits as well as circuits that use boundary region transitions (e.g., as 7A to 7C The invention is used in combination with a multi-stage DC to DC converter circuit (the state transition mode shown in FIG).

[0124] Figure 8 One advantage of a capacitor voltage balancing circuit of the type shown in is that the current through the switched resistor network 802 is independent of the load current. Another advantage is that for the specific example 5-level multi-level DC-to-DC converter circuit 800 having the resistor values ​​set forth in Table 6, the capacitor voltage balancing circuit maintains the capacitor voltage within the target voltage of Table 2, which is typically about 500 mV.

[0125] Capacitor pre-charge

[0126] Figure 8Another advantage of a capacitor voltage balancing circuit of the type shown in is that the circuit can be used for capacitor pre-charging during startup of a multi-stage DC to DC converter circuit. As part of the startup sequence of the multi-stage DC to DC converter circuit, the capacitors should be charged to corresponding target voltage levels (e.g., see the voltages in Table 2) before normal switching can begin. When the capacitor Cx is large (e.g., greater than about 20 μF), a considerable amount of time may be required to pre-charge. If the input voltage V1 is high (e.g., >3.6 V, when the main switch When using a single MOSFET), the input voltage ramp needs to be slow enough so that the capacitor voltage can rise proportionally to prevent the main switch from Voltage overstress on the .

[0127] Advantageously, when the main switch When the initial state is maintained (i.e., all V1 main switch groups are disconnected and all V2 main switch groups are turned on), the Figure 8 A capacitor voltage balancing circuit of the type shown in FIG is effective during the initial V1 ramp-up period to initialize capacitor Cx in a multi-stage DC-to-DC converter circuit during startup. During this time, the capacitor voltage will gradually stabilize to the specified target voltage. The length of time will depend on the capacitance of capacitor Cx—typically, it may take up to 3 milliseconds for the capacitor to reach the target voltage level.

[0128] As an example of precharging via a capacitor voltage balancing circuit, Figure 9 9 is a timing diagram 900 showing capacitor voltage (in relative volts) versus time (in milliseconds) for a 5-stage multi-stage DC-DC converter circuit. In this example, the multi-stage DC-DC converter circuit is set to output a target voltage V2 = -11V. During a pre-charge period 902 when all V1 main switch groups are off and all V2 main switch groups are on, the voltage detection and correction signal generation circuit 804 will detect that the voltage across capacitor C3 is low, thereby generating a pilot control signal This pilot signal will turn on switches SW1 and SW7, thereby connecting capacitor C3 to V1 and V2 (3V in this example). Note that V2 is connected to circuit ground through inductor L1, which appears as a short circuit at DC. Therefore, capacitor C3 begins to charge through switches SW1 and SW7. At the same time, the voltage detection and correction signal generation circuit 804 will detect the voltage across capacitors C2 and C1 and generate corresponding pilot control signals for switches SW2 to SW6, causing some of the charge on capacitor C3 to be transferred to capacitor C2 via switches SW2 and SW6, and causing some of the charge on capacitor C2 to be transferred to capacitor C1 via switches SW3 and SW5. In the graph shown, the voltage across capacitor C3 drops at a point when the charge is transferred to capacitors C2 and C1, but through the further action of the capacitor voltage balancing circuit, the voltage across capacitor C3 recovers. In this example, at approximately 2ms, the main switch Normal switching of V2 begins, and the output V2 transitions from 0V to a target voltage of −11V during a transition period 904 .

[0129] Because Figure 9 As shown, the capacitors C1 to C3 are precharged at a relatively slow and uniform voltage rate by the capacitor voltage balancing circuit, so the capacitor voltage rises proportionally, and thus prevents the main switch from Voltage overstress on the .

[0130] Capacitor Voltage Balancing - Second Embodiment

[0131] Figure 8 Capacitor voltage balancing circuitry of the type shown in FIG generally works well, but such circuits are considered "lossy" because the balancing current through the switched resistor network 802 will be dissipated as heat, reducing efficiency. An alternative voltage balancing solution is to use a lossless method in which chaotic state transitions of the multi-stage DC-to-DC converter circuit are allowed to occur during normal operation. The net effect of the chaotic state transitions is to increase or decrease the voltage across a particular capacitor.

[0132] For example, Figure 10 is used for Figure 6 1. A state transition diagram of a possible lossless capacitor voltage balancing state transition pattern for the 5-stage DC-to-DC converter circuit 600. Solid arrows indicate normal positive-going ordered state transitions when the capacitor voltages are balanced; annotated solid arrows indicate the direction (upward or downward) of the voltage change across the corresponding capacitor that occurs as a result of the transition. Thus, for example, the "V C3 ∧” means that the voltage across capacitor C3 increases due to the transition. Similarly, “V C2 ∧ 、V C3∨ " means that the voltage across capacitor C2 increases due to the transition, while the voltage across capacitor C3 decreases due to the transition. The absence of annotation on the solid arrow means that the voltage across the capacitor does not change substantially due to the positive transition. One cycle of state transitions is shown (but note that the bottom row of italicized numbers indicates the start of the next cycle).

[0133] When the capacitor voltage becomes unbalanced, one aspect of the present invention allows for a reverse disorder state transition to steer the capacitor voltage toward a balanced state. Figure 10 In one example embodiment, the disordered state transition is indicated by a dashed arrow. Figure 8 The voltage detection and correction signal generation circuit 804 can be used to continuously sense Figure 6 The capacitor voltage of the 5-level DC to DC converter circuit 600 is generated to have an "upward" value (eg, V Cx ∧ ) or "down" (V Cx∨ The generated voltage correction signal is then used to force the periodic state transition pattern to undergo a suitable disordered transition to reach a state that helps balance the capacitor voltage. Figure 10 In the figure, each dotted arrow indicates the corresponding voltage correction signal V Cx ∧ 、V Cx∨ Notes, corresponding to the voltage correction signal V Cx ∧ 、V Cx∨ Individually or in logical OR combinations, disordered state transitions are forced to attempt to balance the voltages across the corresponding capacitors.

[0134] For example, in Region 2, ST2 0100 will normally transition to ST3 0110 (remember the benefit of using Gray code). However, if the voltage detection and correction signal generation circuit 804 determines that the voltage across capacitor C2 is out of balance on the low side - and therefore needs to be directed to a higher voltage - then the generated correction signal V C2 ∧ Will force a transition from ST2 0100 back to ST3 1100.

[0135] As another example, in region 2 state ST2 0010, if the generated voltage correction signal indicates that the voltage across capacitors C1 and C3 should both be directed higher (ie, the voltage correction signal is V C1∧ and V C3 ∧ ), a disordered state transition from ST2 0010 to ST3 0110 will occur because V C1 ∧ The control signal makes the disordered decision condition true: "V C1 ∧ ORV C3∨ ” (Therefore, V C3 ∧ The next state transition will be forward, from ST3 0110 to ST2 0010. If the voltage correction signal V C1 ∧ If this continues to exist, another disorder state transition will occur in the reverse direction from ST2 0010 to ST3 0110 (unless continuous disorder state transitions are prevented, as discussed below).

[0136] Note that, optionally, "chained" disordered state transitions can be allowed. For example, if V C3V exists, ST2 0010 is forced to return to ST3 0110, but if V C3∨ If there is a disordered state transition path from ST3 0110 to ST2 0100, there is also a disordered state transition path from ST3 0110 to ST2 0100. Depending on the desired rate of capacitor voltage balancing, such chained disordered state transitions may be allowed or not. For example, in the case of high load current, it may be necessary to prohibit back-to-back (chained) disordered state transitions to slow down the voltage balancing rate.

[0137] from Figure 8 The voltage correction signal generated by the voltage detection and correction signal generation circuit 804 can be applied to a combination circuit or a lookup table to change the normal generation of the positive transition state. Figure 10 The logic of can be summarized as allowing the transition from the current state to the forward state to proceed unless a specific generated voltage correction signal or signals are received (i.e., Figure 10 The signal after the equal sign) in which case the transition direction changes from the current state to the reverse state.

[0138] It should be understood that Figure 10 The pattern of disordered state transition shown in FIG may vary for different embodiments, and the present invention is not limited to Figure 10 However, in general, if a reflected binary code (e.g., Gray code) for the state bit sequence is specified as a design requirement to reduce the magnitude of switching losses and voltage transients, the pattern of disordered state transitions is constrained. Figure 10In the example shown in , for the region 2 and region 3 transitions, there are no other possible out-of-order state transitions because there are only two options for the Gray code transition for a particular state. However, for regions 1 and 4, there are four options for any ST1 / ST2 transition and any ST4 / ST5 transition.

[0139] The advantage of allowing chaotic state transitions is that the current in inductor L1 is used to balance the capacitor voltage, so efficiency is not degraded - that is, the process is essentially lossless.

[0140] The lossless capacitor voltage balancing method and circuit can be used with any stage of a multi-stage DC to DC converter circuit, including a buck converter circuit, a boost converter circuit, or a buck-boost converter circuit (any of which can be inverting or non-inverting), and can be used with conventional multi-stage DC to DC converter circuits as well as circuits that use boundary region transitions (e.g., 7A to 7C In addition, the lossless capacitor voltage balancing method and circuit can be used in conjunction with a multi-stage DC to DC converter circuit such as Figure 8 For example, if one or more capacitors are completely out of balance, which can happen under high output current loads, then the capacitors are placed in a balanced state. Figure 8 It may be useful to connect the switched resistor network 802 to the circuit for asynchronous capacitor voltage balancing. However, at lower load levels, it may be useful to disconnect the switched resistor network 802 and instead utilize lossless chaotic state transitions. Another approach is to include a circuit configuration (i.e., the switched resistor network 802 and the logic for lossless chaotic state transitions) and set the capacitor voltage tolerance for lossless voltage balancing at a lower value (e.g., 250 mV) while setting the capacitor voltage tolerance for lossy voltage balancing at a higher value (e.g., 500 mV). By doing so, if the lossless chaotic state transition capacitor voltage balancing cannot maintain the voltage limit within the higher value, the lossy switched resistor network voltage balancing circuit will complement the lossless balancing technique and work simultaneously.

[0141] Process control of disorderly transitions

[0142] In a normal switching flow for a 5-level DC-DC converter circuit, there are 8 state transitions per cycle in each of regions 1 to 4. For a 5-level DC-DC converter circuit configured to use boundary regions, there are 16 state transitions per cycle in boundary regions 1-2, boundary regions 2-3, and boundary regions 3-4. When the capacitor voltage is guided by a lossless capacitor voltage balancing method, disordered state transitions are introduced as described above, thus achieving more state transitions per cycle. The number of disordered state transitions allowed for each complete 8-transition or 16-transition cycle will determine how quickly the capacitor voltage can move toward the corresponding target value.

[0143] It may happen that the voltages across multiple capacitors may become unbalanced at the same time. In a simple capacitor voltage balancing scheme, one capacitor may be balanced before attempting to balance the other capacitors. For example, in the example above, while attempting to balance the voltage V across capacitor C1, C1 , the state transition can switch back and forth between ST2 0010 and ST3 0110. This means that there is also - but ignored - V C3 ∧ The control signal will continue to be ignored during the switching sequence. Unregulated state transitions will allow switching back and forth between ST2 0010 and ST3 0110, and V C1 The voltage will be directed towards its target voltage at the maximum rate. However, the voltage V across capacitor C3 C3 is not balanced and will drop lower and lower because of V C3 ∧ The decision state of the control signal is not in the ST2 0010 and ST3 0110 states, but in the ST2 1000 and ST3 1100 states. Therefore, this scenario may occur in V C1 While restoring balance, V C3 Loss of balance. Even worse, if the capacitance of C1 is greater than that of C3, more transition state switching cycles will be required to balance V C1 , so V C3 Lose balance faster.

[0144] One solution to the transition state switching problem is to impose a limit on the number of disordered state transition sequences that are disordered reverse state transitions followed by forward state transitions (i.e., switching between two transition states). Such a limit will allow each capacitor the opportunity to have its voltage steered as needed, rather than having to voltage balance one capacitor and then another. For example, if only one disordered state transition sequence is allowed per complete Region 1 cycle, then V in the above example would be C3The voltage will be guided towards its target voltage at a slower rate because many of the state transitions will not guide V C3 voltage (e.g., ST2 1000 to ST1 0000), and some state transitions may even C3 The voltage is led lower (e.g., ST1 0000 to ST2 0100). Note that in a complete cycle of normal positive transitions, all capacitors will see an equal number of upward and downward transitions, so having only one disordered state transition per complete normal transition cycle will not have any significant negative impact on the capacitor voltage (i.e., only a small change in the capacitor voltage).

[0145] Thus, the improved capacitor balancing scheme does not attempt to balance any single capacitor voltage first and then proceed to balance the voltage of another capacitor; instead, all capacitors are given a somewhat simultaneous opportunity to achieve voltage balancing, thereby reducing the overall voltage deviation from the corresponding capacitor voltage target. Furthermore, an upper limit (e.g., 1 to 4) can be imposed on the number of consecutive chaotic state transition sequences allowed for the same capacitor. Limiting the number of consecutive chaotic state transition sequences allowed also allows the state transitions to traverse all states in a cycle, giving each capacitor the opportunity to balance through the appropriate chaotic transitions relevant to that particular capacitor. For example, such an improved scheme can be implemented by having a chaotic state transition sequence counter that only allows N chaotic state transition sequences before resuming the positive transition, after which the counter is reset. In some embodiments, N can be the same for all chaotic state transition sequences (e.g., a count of 1 or 2). In other embodiments, N can be based on the current state, such that some states allow more chaotic transition sequences than other states. In some embodiments, N can be allowed to vary depending on the degree to which the capacitor voltages are out of balance. For example, there may be two levels of capacitor voltage tolerance detection. If the capacitor voltages are out of balance by, for example, 250 mV, a lower number N may be used. If the capacitor voltages are out of balance by, for example, 500 mV, a larger number N may be used.

[0146] It can be noted that while the current in inductor L1 is beneficial in balancing the capacitor voltages, the inductor current depends on the load current, so the speed at which the capacitor voltages can be balanced varies with the load current. If the load current is high, the balancing current is also high, so the capacitor voltages can move faster and reach their respective target voltages more quickly. However, when the load current is low, the current available to move the capacitor voltages is very small. For example, a sudden step change in load current from high to low can cause the voltages across the capacitors to become unbalanced—but the resulting low load current results in a longer time to balance the capacitor voltages.

[0147] Therefore, one aspect of an embodiment of the present invention is a method for adaptively adjusting and varying the number of chaotic transition sequences per cycle and / or consecutive chaotic state transition sequences based on the load current to optimize the rate of lossless capacitor voltage balancing. For example, if a chaotic state transition sequence counter is used as described above, N can be varied based on the load current. For example, for low load currents, N can be set to 4 or 5 to allow for more chaotic transition sequences, and for low load currents, N can be set to 1 or 2 to allow for fewer chaotic transition sequences.

[0148] More generally, for high load current situations, embodiments of the present invention can introduce a minimum number of chaotic state transition sequences per cycle, such as two, one, or even none (i.e., any chaotic state transition sequence is skipped in a particular cycle, effectively enabling only a fractional number of chaotic state transition sequences per cycle). As a result, the speed at which the capacitor voltage can move is controlled by the frequency of any chaotic state transition sequence per cycle. Limiting the number of chaotic state transition sequences per cycle can be beneficial because, without limiting, the capacitor voltage may move too quickly if too many chaotic state transition sequences are allowed in a cycle. When the capacitor voltage moves faster than the capacitor balancing control loop delay, oscillations may result.

[0149] For low load current situations, a more chaotic sequence of state transitions per cycle may be allowed to move the capacitor voltage faster; otherwise, the capacitor voltage may move too slowly and the capacitor may spend too much time in an undesirable overvoltage condition.

[0150] Figure 6A method is included in which the frequency of the disordered state transition sequence is adjusted according to the load current to manage the rate at which the capacitor voltage reaches equilibrium. The load current detection and correction signal generation circuit 606 is therefore connected to sense the load current at the output of the DC to DC converter circuit 600 and generate a load correction (LC) signal. The LC signal can be applied to the clock and control circuit 602 to limit the generation of the disordered state transition sequence according to the load current. For example, the LC signal can adjust (gate) the disordered state transition sequence counter mentioned above to change the value of N so that low load current conditions allow more disordered transition sequences per cycle and high load current conditions allow fewer disordered transition sequences per cycle. It should be understood that many different circuits can be used to adjust the disordered state transition sequence counter up or down according to the load current, etc.

[0151] Adjusting the frequency of the disordered state transition sequence according to the load current can be used with any stage of the multi-stage DC to DC converter circuit and can be used with conventional multi-stage DC to DC converter circuits and circuits using boundary region transitions (e.g. 7A to 7C The invention is used in combination with a multi-stage DC to DC converter circuit (the state transition mode shown in FIG).

[0152] In summary, various embodiments of the present invention may include one or more of the following: limiting the total number of disordered state transition sequences per cycle; limiting the number of consecutive disordered state transition sequences; and / or limiting the number of disordered state transition sequences per cycle and / or consecutive disordered state transition sequences based on load.

[0153] Clock and Control Circuit Examples

[0154] Those skilled in the art will appreciate that, based on the above disclosure, there are numerous ways to implement logic circuits for boundary region transition, lossy capacitor voltage balancing, capacitor pre-charging during startup, lossless capacitor voltage balancing, and / or state transition flow control. As an example, Figure 11 is used for Figure 6 Schematic diagram of one embodiment of clock and control circuitry for a multi-stage DC-to-DC converter circuit of the type shown in .

[0155] Figure 11 The clock and control circuitry includes a multi-waveform and clock generator (referred to as "generator circuit") 1102 coupled to an input of a first multiplexer 1104. In this example, generator circuit 1102 outputs a system clock and a plurality of triangular waveforms, any of which can be selected by first multiplexer 1104 under the control of a waveform select signal. Note that while this example uses a triangular waveform, other waveforms, such as a sawtooth waveform, may be used for specific applications.

[0156] In order to finely control the duty cycle timing, Figure 11 The example circuit has two selectable pulse width modulation (PWM) clock signal paths. In the first "error amplifier" path used for both the in-region (i.e., non-boundary region) case and the boundary region case, the output of the first multiplexer 1104 is coupled to one input of the first comparator 1106, and the other input of the first comparator 1106 is coupled to the error amplifier 1108. The input of the error amplifier 1108 is the reference voltage V REF and the feedback voltage V proportional to V2 FB For example, in one embodiment, V FB =- 1 / 6V2; therefore, V REF Controlling from 0V to 2V will enable V2 to be set from 0V to -12V. Reference voltage V REF It does not need to be static and can be set dynamically, for example, to obtain the desired value of V2. If necessary, the output voltage V EAOut This can be smoothed by filter 1110 and provide a stable closed-loop feedback circuit.

[0157] Reference voltage V REF and feedback voltage V FB 1-2_LOW to REGION 1-2_HIGH and vice versa).

[0158] The output voltage V of the error amplifier 1108 EAOut This is fed into a first comparator 1106 along with the selected triangle waveform from the first multiplexer 1104 to generate a PWM waveform that determines the appropriate duty cycle for the main output switch.

[0159] For the implementation of boundary region transitions, it has been found useful to utilize multiple triangular waveforms of different peak voltages to generate the necessary PWM clock signals required to dynamically change the duty cycle (particularly with respect to sub-regions). For example, Figure 12 The following timing diagram is shown: Figure 11 The three triangular waveforms 1102a, 1102b, and 1102c generated by the generator circuit 1102 are added according to the error voltage V EAOut As shown in the example, each of the triangle waveforms 1102a, 1102b, and 1102c has a voltage higher than the settable threshold voltage V for a different length of time. X Therefore, for the selected VX , selecting waveform 1102b will produce a wider pulse than selecting waveform 1102a; similarly, selecting waveform 1102c will produce a narrower pulse than selecting waveform 1102a. For example, when a 6% duty cycle is required for the multi-stage DC-to-DC converter circuit, waveform 1102c may be used, while when a 17% duty cycle is required, waveform 1102b may be used (see also Tables 4A and 4B above). As another example, when a 17% duty cycle is required, waveform 1102b may be used, while when a 6% duty cycle is required for the error amplifier path, waveform 1102a may be used. It should be appreciated that generator circuit 1102 and first multiplexer 1104 can be configured to generate and select other numbers of multiple waveforms.

[0160] When the error amplifier 1108 output voltage V EAOut In contrast, switching between triangular waveforms with different amplitudes enables substantially instantaneous changes from wide pulse width to narrow pulse width at region boundaries and thus minimizes output voltage transient steps at region boundary transition points. For one example embodiment, when the error amplifier output voltage V EAOut Near the peak, waveforms 1102a and 1102b are used for super-regions 1-2 and 3-4, and when the error amplifier output voltage V EAOut Near the trough, waveforms 1102a and 1102c are used for super-region 2-3.

[0161] In a second "fixed bias" path for the boundary region case, a second multiplexer 1116 is coupled to one input of a second comparator 1118, the other input of which is coupled to the output of the generator circuit 1102 (in this example, from Figure 12 The second multiplexer 1116 allows selection of one of a plurality of fixed bias voltages from the bias voltage generator 1117 for application to the second comparator 1118. The selected fixed bias, together with the waveform 1102a, will generate a narrow pulse equivalent to the previously described boundary region duty cycle (e.g., 6%) to control the main switch of the multi-stage DC to DC converter circuit, thereby setting the boundary region duty cycle value on a region-by-region basis. In the example shown, the fixed bias voltage corresponds to the fixed bias voltage described above with respect to 7A to 7B The fixed bias voltage may be selected by calculation and then fine-tuned by simulation and / or calibration. Fine-tuning the fixed bias voltage may adjust the fixed pulse width to minimize output voltage transient steps at boundary transitions within the super-regions.

[0162] The outputs of the first comparator 1106 and the second comparator 1118 are coupled to respective inputs of a third multiplexer 1114. The waveforms from the first comparator 1106 in the "error amplifier" path or the second comparator 1118 in the "fixed bias" path are passed by the third multiplexer 1114 as PWM signals to the edge-to-pulse generator 1120. In the illustrated embodiment, in non-boundary regions, the third multiplexer 1114 selects only the output of the first comparator 1106, and the first multiplexer 1104 is configured to select only the triangle waveform 1102a. In boundary regions, the third multiplexer 1114 switches between the output of the first comparator 1106 and the output of the second comparator 1118. More specifically, in the illustrated embodiment, the first multiplexer 1104 is configured to select waveform 1102b for boundary regions 1-2 and 3-4. For boundary region 2-3, the first multiplexer 1104 is configured to select waveform 1102c. The second comparator 1118 always outputs a fixed pulse width. For boundary regions 1-2 and 3-4, Vbias2 is selected by the second multiplexer 1116 (see Figure 12 ). Along with the triangle waveform 1102a, the second comparator 1118 generates a small fixed pulse width. For the boundary region 2-3, Vbias3 is selected by the second multiplexer 1116 (see Figure 12 Together with the triangle waveform 1102a, the second comparator 1118 generates a narrow fixed pulse width.

[0163] Therefore, only the "error amplifier" path will be used to determine the duty cycle for the operation of the multi-stage DC to DC converter circuit. Outside the boundary region, the third multiplexer 1114 selects only the first comparator 1106, so each PWM clock pulse is truly pulse-width modulated (i.e., with a variable pulse width). However, within the boundary region, the circuit switches between the "fixed bias" path and the "error amplifier" path. In the example shown, only every other clock pulse is truly pulse-width modulated (i.e., a variable-width pulse width from the first comparator 1106), while the clock pulse from the second comparator 1118 has a fixed pulse width.

[0164] In the illustrated embodiment, the boundary regions require additional synchronization. For example, Figure 7A (and Figure 7E , for region1-2_low and region1-2_high), state transitions occur between super-regions with clock synchronization, as indicated in the following list:

[0165] For Region 1-2_Low, the ST1-ST2 transition is a variable pulse width, while the ST2-ST3 transition is a fixed pulse width;

[0166] For Region 1-2_High, the ST1-ST2 transition is fixed pulse width, while the ST2-ST3 transition is variable pulse width;

[0167] For Region 2-3_Low, the ST2-ST3 transition is a variable pulse width, while the ST3-ST4 transition is a fixed pulse width;

[0168] For Region 2-3_High, the ST2-ST3 transition is a fixed pulse width, while the ST3-ST4 transition is a variable pulse width;

[0169] For Region 3-4_Low, the ST3-ST4 transition is a variable pulse width, while the ST4-ST5 transition is a fixed pulse width;

[0170] • For Region 3-4_High, the ST3-ST4 transition is fixed pulse width, while the ST4-ST5 transition is variable pulse width.

[0171] The edge-to-pulse generator 1120 converts each edge (rising or falling) of the PWM waveform into a single small rising / falling pulse. The small pulse clock output of the edge-to-pulse generator 1120 clocks the rising-edge-triggered state register 1122 to a determined duty cycle. The state register 1122 sends Figure 6 The switches in the V1 group output switch control signals; the complementary version of the same signal is sent to the Figure 6 In the example shown, 4 bits of the switch control signal are applied to the V2 switch group (inverter not shown). Figure 6 or Figure 8 Figure 1 shows the switches of a 5-level DC-to-DC inverting buck-boost converter circuit of the type shown in FIG. The additional 2 bits are used to allow differentiation between the different states in Region 1 and Region 4. Since all four Region 1 states are "0000" and all four Region 4 states are "1111", using the additional 2 bits for differentiation ensures that each of the four states can correctly transition to the next Region 2 or Region 3 state.

[0172] A state machine 1124 coupled to the state register 1122 contains logic for generating a next-state bit sequence for the switch control signal according to the logic described above for various aspects of the present invention. The next state of the state machine 1124 will depend not only on the current state but also on all other inputs. The state machine 1124 can be implemented with combinatorial logic (including counters and registers), or as a lookup table, or a combination of combinatorial logic and a lookup table.

[0173] State machine 1124 also outputs select signals—waveform select, PWM select, and region select—for controlling the corresponding multiplexers 1104, 1114, 1116. In addition, state machine 1124 outputs the error amplifier polarity signal described above. The region select output from state machine 1124 includes bits for selecting sub-boundary regions and synchronizing region transitions to the PWM clock (see Table 3 above).

[0174] One input to the state machine 1124 for determining the next state is a set of N flow control signals from the digital control 1126 that specify, for example, limits on out-of-order state transitions. There may be any desired number of flow control lines to control the frequency of out-of-order state transitions. For example, referring to Figure 10 , there are a total of six groups of disordered state transitions for all regions. There is one group in Region 1, as shown by the dashed line from left to right. There are two groups in both Regions 2 and 3: one group shown by the dashed line from left to right, and the other group shown by the dashed line from right to left. In Region 4, there is one group shown by the dashed line from right to left. Any of these six groups can be independently disabled in real time to further limit the frequency of disordered state transitions. To enable / disable these six groups, there will be six non-coded flow control signals. Additional flow control signals (coded or non-coded) may be used to control how many consecutive disordered state transitions are allowed. As another example, one input to digital control 1126 can be, for example, the load current at the output of a multi-stage DC-to-DC converter circuit (if the load current input is in analog form, digital control 1126 may include an analog-to-digital converter subcircuit). Thus, the flow control signal can control the frequency of disordered state transitions to be based on the load current to manage the rate at which the capacitor voltage reaches equilibrium.

[0175] Another input to the state machine 1124 is a set of capacitor balance signals from the capacitor voltage balance control 1128, which is essentially similar to Figure 8 The voltage detection and correction signal generation circuit 804 operates to continuously sense the capacitor voltage and generate a corresponding correction signal. The correction signal has an "up" (eg, Cx ∧ ) or "down" (e.g., Cx ∨ ) value that is used to direct the next state value output of state machine 1124 for lossless capacitor voltage balancing, as described above.

[0176] Another input to the state machine 1124 is a set of zone status signals from the zone detector 1130, which is essentially a comparator. The input to the zone detector 1130 is the output voltage V of the error amplifier 1108. EAOutand a bias voltage from bias voltage generator 1117. Region detector 1130 compares the analog input voltages to determine the actual current region or sub-region and generates a digital control signal specifying the current region state (eg, see region states in Table 5 above).

[0177] for Figure 11 The example circuit and reference Figure 12 As shown in the error voltage V EAOut And the region transition of various bias voltages, at startup, the output voltage V2 is 0V, which is in region 1. Reference voltage V REF will slowly ramp up to its target voltage setting; therefore, V EAOut starts low. As V2 decreases toward more negative voltages, V EAOut Increase. At the same time, V REF With the feedback voltage V FB For comparison; as mentioned above, in the example shown, V FB =- 1 / 6V2. Once V FB Reach V REF , the output voltage will have reached the target. At the same time, the region detector 1130 continuously sets V EAOut is compared with the bias voltage from bias voltage generator 1117. Once V EAOut achieve Figure 12 If the 6% / 94% point of waveform 1102a in FIG. 1 is reached (eg, Vbias2), the region state transitions from Region 1 to Region 1-2_Low. V EAOut will continue to increase, and once V EAOut When the 6% / 94% point of waveform 1102b is reached (eg, Vbias1), the region state transitions from Region 1-2_Low to Region 1-2_High and the error amplifier polarity reverses, which causes V EAOut Once V EAOut Once the 6% / 94% point of waveform 1102a (e.g., Vbias2) is reached, the region state transitions from Region 1-2_High to Region 2. Similarly, once V EAOut Once the 94% / 6% point of waveform 1102a (e.g., Vbias3) is reached, the region state transitions from Region 2 to Region 2-3_Low. EAOut When the 94% / 6% point of waveform 1102c is reached (eg, Vbias4), the region state transitions from Region 2-3_Low to Region 2-3_High.

[0178] If the final V REFIf the voltage corresponds to region 4, this particular process can continue all the way to region 4; that is, the circuit will always start from 0V, enter region 1, and pass through the adjacent regions until it reaches the target region. Once it reaches the target region, if V REF If the value changes up or down, the state of the region will change accordingly. Note that the state of the region always moves between adjacent regions and will not skip regions.

[0179] Note that if there is sufficient error amplifier output voltage dynamic range, then no error amplifier polarity inversion is required. For example, if the error amplifier output linear range can be from 1V to 8V, then the 7V range can be simply subdivided into multiple regions (e.g., 1, 1-2, 2, 2-3, 3, 3-4, and 4) and demarcated using appropriate bias voltages.

[0180] application

[0181] The DC-to-DC converter circuit according to the present invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention can be fabricated as an integrated circuit (IC) in whole or in part (e.g., with off-chip inductors and / or capacitors), which can be packaged into IC packages and / or modules for ease of handling, manufacturing, and / or improved performance.

[0182] Embodiments of the present invention may be useful in a wide variety of larger radio frequency (RF) circuits and systems, such as display drivers, radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment. Such circuits may be useful in systems operating in some or all of the RF range (e.g., from about 3 kHz to about 300 GHz).

[0183] Radio system usage includes wireless RF systems (including base stations, relay stations, and handheld transceivers) that use various technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“ODFM”), Quadrature Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Worldwide Interoperability for Microwave Access (“WIMAX”), Global System for Mobile Communications (“GSM”), Enhanced Data Rates for GSM Evolution (EDGE), Long Term Evolution (“LTE”), 5G New Radio (NR), and other radio communication standards and protocols.

[0184] A wireless device can communicate with multiple wireless communication systems using one or more of the above-mentioned telecommunication protocols. A wireless device can also communicate with one or more satellites, such as navigation satellites (e.g., GPS) and / or communication satellites. A wireless device can be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer or tablet, or some other wireless communication unit or device. A wireless device may also be referred to as a mobile station, user equipment, access terminal, or some other terminology.

[0185] As an example of a system that can use the present invention to provide a variety of different DC voltage levels from a DC source, FIG13 is a block diagram of a typical prior art transceiver 1300 that can be used in a wireless device, such as a cellular phone. As shown, the transceiver 1300 includes a mix of RF analog circuits for transmitting and / or transforming signals directly on the RF signal path, non-RF analog circuits for operating needs outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuits for control and user interface requirements. In this example, the receiver path Rx includes an RF front end, an IF block, a back end, and a baseband section (note that in some implementations, the distinction between the various sections may be different).

[0186] The receiver path Rx receives an over-the-air RF signal via an antenna 1302 and a switch unit 1304, which may be implemented as an active switching device (e.g., a field-effect transistor or FET) or as a passive device that implements frequency domain multiplexing, such as a diplexer or duplexer. An RF filter 1306 passes the desired received RF signal to a low-noise amplifier (LNA) 1308, the output of which is combined with the output of a first local oscillator 1312 in a mixer 1310 to generate an intermediate frequency (IF) signal. The IF signal may be amplified by an IF amplifier 1314 and passed through an IF filter 1316 before being applied to a demodulator 1318, which may be coupled to a second local oscillator 1320. The demodulated output of the demodulator 1318 is converted to a digital signal by an analog-to-digital converter 1322 and provided to one or more system components 1324 (e.g., a display driver for a visual display (LED, OLED, LCD, etc.), video graphics circuitry, sound circuitry, a storage device, etc.). The converted digital signal may represent, for example, a video or still image, a sound, or a symbol such as text or other characters.

[0187] In the example shown, the transmitter path Tx includes baseband, backend, IF blocks, and RF front-end sections (again, the distinction between these sections may differ in some implementations). Digital data from one or more system components 1324 is converted to an analog signal by a digital-to-analog converter 1326, the output of which is applied to a modulator 1328, which may also be coupled to a second local oscillator 1320. The modulated output of modulator 1328 may pass through an IF filter 1330 before being amplified by an IF amplifier 1332. The output of IF amplifier 1332 is then combined with the output of first local oscillator 1312 in a mixer 1334 to generate an RF signal. The RF signal may be amplified by a driver 1336, the output of which is applied to a power amplifier (PA) 1338. The amplified RF signal may be coupled to an RF filter 1340, the output of which is coupled to antenna 1302 via a switch unit 1304. The operation of transceiver 1300 is controlled in a known manner by microprocessor 1342, which interacts with system control components (e.g., user interface, memory / storage, applications, operating system software, power control, etc.). Additionally, transceiver 1300 will typically include other circuitry, such as bias circuitry 1346 (which may be distributed throughout transceiver 1300 near transistor devices), electrostatic discharge (ESD) protection circuitry, test circuitry (not shown), a factory programming interface (not shown), etc. In modern transceivers, there is typically more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and / or signaling modes. Furthermore, it will be apparent to one of ordinary skill in the art that some components of transceiver 1300 may be positioned in a different order (e.g., filters) or omitted. Other components may (and typically are) added (e.g., additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.).

[0188] method

[0189] Another aspect of the present invention includes a method for generating a full range of output voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage. For example, Figure 14 A process flow diagram 1400 of a method for generating a full range of output voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage is provided. The method includes: setting a state of the converter circuit in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, at least one region being separated from at least one other region by a corresponding boundary region (block 1402); and setting a state of the converter circuit in a boundary region transition mode, the boundary region transition mode generating an output voltage within one or more of the corresponding boundary regions (block 1404).

[0190] The above-mentioned method and corresponding circuitry for implementing such a method may include one or more of the following: wherein a boundary region transition pattern alternates between state transitions within a first region of the region and state transitions within a second region of the region; wherein the boundary region transition pattern includes a plurality of state transitions encoded in a reflected binary code; wherein the pattern defining the regions has corresponding region duty cycles, and the boundary region transition pattern for the boundary region between the regions includes a first sub-region having a first duty cycle combination and a second sub-region having a second duty cycle combination, the first duty cycle combination and the second duty cycle combination being different from the region duty cycles; and / or the first duty cycle combination and the second duty cycle combination are selected so that the average output voltage at the transition between each region and the boundary region approximately matches the output voltage in the region and the output voltage near the boundary region.

[0191] Another aspect of the present invention includes a method for balancing capacitor voltages in a multi-stage DC to DC converter circuit. For example, Figure 15 A process flow diagram 1500 is provided for a first method of balancing capacitor voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage. In this example, the converter circuit includes an inductor, at least one capacitor selectively coupleable to the inductor, a voltage source, and / or a voltage sink via a plurality of series-coupled primary switches, and a control circuit configured to set the states of the primary switches in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges. The method includes: sensing a deviation in voltage across at least one capacitor (block 1502); generating a directional correction signal corresponding to the sensed deviation (block 1504); and applying the generated directional correction signal, alone or in combination, to selectively guide the voltage across at least one capacitor toward a balanced voltage state (block 1506).

[0192] The above-mentioned method and corresponding circuit for implementing such method may include one or more of the following: applying the generated directional correction signal alone or in combination to selectively guide the voltage across at least one capacitor toward a balanced voltage state by coupling one or more capacitors to a source voltage to charge such one or more capacitors and / or coupling two or more capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor and / or coupling one or more capacitors to a voltage sink to discharge such one or more capacitors; wherein the main switch includes a field effect transistor; wherein the multi-stage DC to DC converter circuit is a buck-boost multi-stage DC to DC converter circuit or a boost multi-stage DC to DC converter circuit or a buck multi-stage DC to DC converter circuit. one of the converter circuits; wherein the multi-stage DC to DC converter circuit is one of a 3-stage DC to DC converter circuit or a 4-stage DC to DC converter circuit or a 5-stage DC to DC converter circuit; sensing a deviation of the voltage across at least one capacitor, generating a directional correction signal corresponding to the sensed deviation, and applying the generated directional correction signal alone or in combination during a pre-charge period to selectively guide the voltage across at least one capacitor to charge the at least one capacitor to a corresponding selected initial voltage; and / or wherein each region is separated from at least one other region by a boundary region, further comprising configuring the control circuit to set the state of the main switch in a boundary region transition mode, the boundary region transition mode generating an output voltage in one or more boundary regions within the boundary region.

[0193] As another example, Figure 16 A process flow diagram 1600 is provided for a second method of balancing capacitor voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage. In this example, the converter circuit includes an inductor, at least one capacitor selectively coupleable to the inductor, a voltage source, and / or a voltage sink via a plurality of series-coupled switches, and a control circuit configured to set the states of the switches in at least two modes, the at least two modes defining respective regions, each of the respective regions defining a corresponding output voltage range, at least one mode having a positive orderly transition state change. The method includes: sensing a deviation in voltage across at least one coupled capacitor (block 1602); generating a directional correction signal corresponding to the sensed deviation (block 1604); and applying the generated directional correction signal, alone or in combination, to force at least one mode to undergo a negative disordered transition state change to selectively guide the voltage across the at least one coupled capacitor toward a balanced voltage state (block 1606).

[0194] The above-mentioned method and corresponding circuit for implementing such method may include one or more of the following: wherein the switch includes a field effect transistor; wherein the multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit or a boost multi-stage DC to DC converter circuit or a buck multi-stage DC to DC converter circuit; wherein the multi-stage DC to DC converter circuit is one of a 3-stage DC to DC converter circuit or a 4-stage DC to DC converter circuit or a 5-stage DC to DC converter circuit; wherein each mode consists of a cycle of positive orderly transition state changes, and also includes limiting the reverse disordered transition state changes to a selected number per cycle; wherein each mode consists of a cycle of positive orderly transition state changes, and also includes limiting continuous reverse disordered transition state changes to a selected number per cycle; wherein each mode consists of cycles of forward ordered transition state changes, further comprising limiting continuous reverse disordered transition state changes to a selected number per cycle based on the electrical load on the multi-stage DC to DC converter circuit; wherein each mode consists of cycles of forward ordered transition state changes, further comprising limiting continuous reverse disordered transition state changes to a selected number per cycle based on the electrical load on the multi-stage DC to DC converter circuit; and / or wherein each region is separated from at least one other region by a boundary region, further comprising configuring the control circuit to set the state of the switch in a boundary region transition mode that generates an output voltage within one or more boundary regions.

[0195] Manufacturing Techniques and Options

[0196] As used in this disclosure, the term "MOSFET" means any field effect transistor (FET) having an insulated gate and including metal or metalloid, insulator, and semiconductor structures. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metals or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0197] As used in this specification, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or alternating current in electrical circuits.

[0198] It will be readily apparent to those skilled in the art that various embodiments of the present invention may be implemented to meet various specifications. For example, it is expressly contemplated that any and all combinations of one or more of the inventions and / or methods described above and / or in the claims may be made and utilized to meet the requirements of a particular application.

[0199] Unless otherwise noted above, selecting appropriate component values ​​is a matter of design choice, and various embodiments of the present invention may be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments may be manufactured using any suitable substrate and process, including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, the present invention may be implemented in other transistor technologies, such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the above-described inventive concepts are particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes with similar characteristics. Fabrication of CMOS on SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or kept at a minimum, kept uniform across all cells, allowing them to be compensated).

[0200] Voltage levels can be adjusted and / or voltage and / or logic signal polarity can be inverted depending on the specific specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0201] in conclusion

[0202] A number of embodiments of the present invention have been described. It will be appreciated that various modifications may be made without departing from the scope of the present invention. For example, some of the steps described above may be order-independent and, therefore, may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the above-identified methods may be performed in a repetitive, serial, or parallel manner.

[0203] It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufacture, or compositions of matter set forth in the appended claims. (Note that parenthetical labels of claim elements are used for ease of reference to such elements and do not, by themselves, indicate a particular required ordering or enumeration of elements; further, such labels may be repeated in dependent claims to refer to additional elements without being construed as starting a conflicting sequence of labels).

Claims

1. A multi-stage DC-to-DC converter circuit for converting an input voltage into an output voltage, comprising a plurality of switches and a control circuit coupled to the plurality of switches, the control circuit being configured to set states of the plurality of switches in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, each adjacent pair of regions being separated by a corresponding boundary region, wherein: The control circuit is further configured to set, for each corresponding boundary region, a plurality of states of the plurality of switches in a boundary region transition pattern, the boundary region transition pattern comprising a plurality of states of the plurality of switches to generate an output voltage within the corresponding boundary region, wherein the plurality of states in the boundary region transition pattern follows a reflected binary code bit sequence such that each transition of the boundary region transition pattern changes only one bit position.

2. The multi-stage DC to DC converter circuit according to claim 1, wherein: The boundary region transition pattern alternates between state transitions within a first one of the regions that is adjacent to the boundary region and state transitions within a second one of the regions that is adjacent to the boundary region.

3. The multi-stage DC to DC converter circuit according to claim 1, wherein: The pattern of the defined area has a corresponding area duty cycle, and the boundary area transition pattern for the boundary area between adjacent pairs of areas includes a first sub-area having a first duty cycle combination and a second sub-area having a second duty cycle combination, wherein the first duty cycle combination and the second duty cycle combination are different from the area duty cycles.

4. The multi-stage DC to DC converter circuit according to claim 3, wherein: The first and second duty cycle combinations are selected such that an average output voltage at a transition between one of the regions and the corresponding boundary region approximately matches an output voltage of the one of the regions near the corresponding boundary region.

5. The multi-stage DC to DC converter circuit according to claim 1, wherein: The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

6. The multi-stage DC to DC converter circuit according to claim 1, wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

7. A multi-stage DC-to-DC converter circuit for converting an input voltage into an output voltage, comprising: a switch path comprising a first set of series-coupled switches coupled in series with a second set of series-coupled switches, wherein each pair of switches in the first set of series-coupled switches and the second set of series-coupled switches are separated by a respective node; an inductor having a first terminal coupled between the first set of series-coupled switches and the second set of series-coupled switches and a second terminal configurable as an input, an output, or a shunt to circuit ground; For corresponding nodes in the first group of series-coupled switches and the second group of series-coupled switches, corresponding capacitors couple the corresponding nodes in the first group of series-coupled switches to the corresponding nodes in the second group of series-coupled switches; and a control circuit coupled to switches in the first group of series-coupled switches and the second group of series-coupled switches, configured to set states of the coupled switches in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, each region having a region boundary relative to at least one adjacent region, and wherein the control circuit is further configured to set a plurality of states of the coupled switches in a boundary region transition pattern for the corresponding region boundary, the boundary region transition pattern comprising a plurality of state transitions of the coupled switches to generate output voltages near and at one or more region boundaries, wherein the plurality of state transitions follow a reflected binary code bit sequence such that each transition changes only one bit position.

8. The multi-stage DC to DC converter circuit according to claim 7, wherein: The boundary region transition pattern alternates between state transitions within a first region of the region adjacent to the region boundary and state transitions within a second region of the region adjacent to the region boundary.

9. The multi-stage DC to DC converter circuit according to claim 7, wherein: The pattern of defining the area has a corresponding area duty cycle, and the boundary area transition pattern for the area boundary between the areas includes a first sub-area having a first duty cycle combination and a second sub-area having a second duty cycle combination, wherein the first duty cycle combination and the second duty cycle combination are different from the area duty cycles.

10. The multi-stage DC to DC converter circuit according to claim 9, wherein: The first and second duty cycle combinations are selected such that an average output voltage at a transition between the region and a corresponding region boundary approximately matches an output voltage in the region near the region boundary.

11. The multi-stage DC to DC converter circuit according to claim 7, wherein: The switch path and the inductor are connected in one of a buck-boost configuration, a boost configuration, or a buck configuration to convert an input voltage to an output voltage.

12. The multi-stage DC to DC converter circuit according to claim 7, wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

13. The multi-level DC to DC converter circuit according to claim 7, wherein: The first group of series-coupled switches and the second group of series-coupled switches each include at least two series-coupled switches.

14. The multi-level DC to DC converter circuit according to claim 7, wherein: The series-coupled switches include field effect transistors.

15. A method of generating a full range of output voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage, comprising: setting a plurality of states of a plurality of switches within the converter circuit in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, each region being separated from at least one other region by a corresponding boundary region; as well as The states of a plurality of switches within the converter circuit are set in a boundary region transition pattern for the corresponding boundary region, the boundary region transition pattern comprising a plurality of state transitions of the plurality of switches to generate an output voltage within the corresponding boundary region, wherein the plurality of state transitions follow a reflected binary code bit sequence such that each transition changes only one bit position.

16. The method according to claim 15, wherein The boundary region transition pattern alternates between a state transition within a first region of the regions and a state transition within a second region of the regions.

17. The method according to claim 15, wherein: The pattern of the defined area has a corresponding area duty cycle, and the boundary area transition pattern for the corresponding boundary area between adjacent pairs of areas includes a first sub-area having a first duty cycle combination and a second sub-area having a second duty cycle combination, wherein the first duty cycle combination and the second duty cycle combination are different from the area duty cycles.

18. The method of claim 17, further comprising selecting the first and second duty cycle combinations so that an average output voltage at a transition between each region and the boundary region approximately matches an output voltage in each region near the boundary region.

19. A multi-stage DC-to-DC converter circuit for converting an input voltage into an output voltage, comprising: a plurality of main switches coupled in series; an inductor coupled to a node within the plurality of series-coupled primary switches; at least one capacitor coupled in parallel with the plurality of series-coupled main switches and selectively coupleable to the inductor and / or the voltage source and / or the voltage sink via the plurality of series-coupled main switches; a control circuit coupled to the main switch and configured to set a state of the main switch in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges; a switch-resistor network comprising a plurality of series-connected pairs of switches and resistors, each switch-resistor pair coupled in parallel with at least one corresponding primary switch of the plurality of series-coupled primary switches and coupled to at least one capacitor; as well as a directional correction circuit coupled to the at least one capacitor and the switched resistor network and configured to sense a deviation in the voltage across the at least one coupled capacitor and generate a corresponding directional correction signal to the switched resistor network, the corresponding directional correction signal, alone or in combination, dynamically changing a pattern of a charge state or a discharge state of the at least one capacitor to selectively steer the voltage across the at least one coupled capacitor toward a balanced voltage state, wherein the directional correction signal controls the switched resistor network to conditionally couple one or more capacitors to a voltage source to charge such one or more capacitors and conditionally couple two or more capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor; and / or conditionally coupling one or more capacitors to the voltage sink to discharge such one or more capacitors.

20. The multi-level DC to DC converter circuit according to claim 19, wherein: The main switch includes a field effect transistor.

21. The multi-level DC to DC converter circuit according to claim 19, wherein: The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

22. The multi-level DC to DC converter circuit according to claim 19, wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

23. The multi-level DC to DC converter circuit according to claim 19, wherein: The orientation correction circuit and the switched resistor network are configured to be activated during a pre-charge period to charge the at least one capacitor to a corresponding selected initial voltage.

24. The multi-level DC to DC converter circuit according to claim 19, wherein: Each region is separated from at least one region by a boundary region, and wherein the control circuit is further configured to set the state of the main switch in a boundary region transition mode to generate an output voltage in one or more of the boundary regions.

25. A multi-stage DC-to-DC converter circuit for converting an input voltage into an output voltage, comprising: a switching path comprising a first group of series-coupled main switches coupled in series with a second group of series-coupled main switches, wherein each pair of main switches in the first group of series-coupled main switches and the second group of series-coupled main switches are separated by a respective node; an inductor having a first terminal coupled between the first set of series-coupled main switches and the second set of series-coupled main switches and a second terminal configurable as an input, an output, or a shunt to circuit ground; For corresponding nodes in the first group of series-coupled main switches and the second group of series-coupled main switches, corresponding capacitors couple the corresponding node in the first group of series-coupled main switches to the corresponding node in the second group of series-coupled main switches; a control circuit coupled to the main switches of the first group of series-coupled main switches and the second group of series-coupled main switches, configured to set states of the coupled main switches in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges at a voltage output; a switch-resistor network comprising a plurality of series-connected pairs of switches and resistors, wherein each pair of switches and resistors is coupled in parallel with at least one corresponding main switch of the first group of series-coupled main switches or the second group of series-coupled main switches and is coupled to at least one capacitor; and a directional correction circuit coupled to at least one capacitor and at least one pair of switches in the switch resistor network, configured to sense a deviation in voltage across the at least one coupled capacitor and generate a corresponding directional correction signal to the switch resistor network, the corresponding directional correction signal, alone or in combination, dynamically changing a pattern of switch states of the at least one coupled pair of switches to selectively activate the at least one coupled pair of switches to guide the at least one coupled capacitor toward a balanced voltage state, wherein selective activation of at least one of the coupled pairs of switches conditionally couples one or more capacitors to a voltage source to charge such one or more capacitors, or conditionally couples two or more capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor, or conditionally couples one or more capacitors to a voltage sink to discharge such one or more capacitors.

26. The multi-level DC to DC converter circuit according to claim 25, wherein: The pairs of switches include field effect transistors.

27. The multi-level DC to DC converter circuit according to claim 25, wherein: The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

28. The multi-level DC to DC converter circuit of claim 25, wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

29. The multi-level DC to DC converter circuit of claim 25, wherein: The first group of series-coupled switches and the second group of series-coupled switches are configured to remain in an initial state during a pre-charge period of the multi-stage DC-to-DC converter circuit, and wherein the directional correction circuit and the switch resistance network are configured to be activated during the pre-charge period to charge at least one capacitor to a corresponding selected initial voltage.

30. The multi-level DC to DC converter circuit of claim 25, wherein: Each region is separated from at least one region by a boundary region, and wherein the control circuit is further configured to set the state of the coupled switches in a boundary region transition mode to generate an output voltage in one or more of the boundary regions.

31. A method of balancing capacitor voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage, the converter circuit comprising an inductor; at least one capacitor selectively coupleable to the inductor and / or a voltage source and / or a voltage sink via a plurality of series-coupled main switches; a switch-resistor network comprising a plurality of series-connected pairs of switches and resistors, each pair of switches and resistors coupled in parallel with at least one corresponding primary switch and coupled to at least one capacitor; and a control circuit configured to set the state of the main switch in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, the method comprising: sensing a deviation in voltage across the at least one capacitor; generating an orientation correction signal corresponding to the sensed deviation; and The generated directional correction signals are applied to the switched resistor network, alone or in combination, to dynamically change a pattern of a charge state or a discharge state of the at least one capacitor to selectively steer a voltage across the at least one capacitor toward an equilibrium voltage state.

32. The method according to claim 31, wherein Applying the generated directional correction signal, alone or in combination, to selectively guide the voltage across the at least one capacitor toward the equilibrium voltage state includes: coupling one or more capacitors to a voltage source to charge such one or more capacitors, and / or coupling two or more capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor, and / or coupling one or more capacitors to a voltage sink to discharge such one or more capacitors.

33. The method according to claim 31, wherein The main switch includes a field effect transistor.

34. The method according to claim 31, wherein The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

35. The method of claim 31 , wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

36. The method of claim 31 , further comprising applying the generated directional correction signal, alone or in combination, during a pre-charge period to selectively direct the voltage across the at least one capacitor to charge the at least one capacitor to a corresponding selected initial voltage.

37. The method of claim 31, wherein Each region is separated from at least one other region by a boundary region, and the method further includes setting, by the control circuit, a state of the main switch in a boundary region transition mode to generate an output voltage in one or more of the boundary regions.

38. A multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage, comprising: a plurality of main switches coupled in series; an inductor coupled to a node within the plurality of series-coupled primary switches; at least one capacitor coupled in parallel with the plurality of series-coupled main switches and selectively coupleable to the inductor, the voltage source, and / or the voltage sink via the plurality of series-coupled main switches; a control circuit coupled to the plurality of series-coupled main switches and configured to set states of the plurality of series-coupled main switches in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, at least one mode being configured to cause the plurality of series-coupled main switches to change switch states according to a forward ordered sequence; as well as A directional correction circuit is coupled to the at least one capacitor and the control circuit, and is configured to sense a deviation in the voltage across the at least one coupled capacitor and generate a corresponding directional correction signal, wherein the corresponding directional correction signal, alone or in combination, causes the switch state to change according to a reverse disordered sequence, wherein the reverse disordered sequence is opposite to the forward ordered sequence, and wherein the reverse disordered sequence causes the plurality of series-coupled main switches to guide the voltage across the at least one coupled capacitor toward a balanced voltage state.

39. The multi-level DC to DC converter circuit of claim 38, wherein: The main switch includes a field effect transistor.

40. The multi-level DC to DC converter circuit of claim 38, wherein: The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

41. The multi-level DC to DC converter circuit of claim 38, wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

42. The multi-level DC to DC converter circuit of claim 38, wherein: Each pattern consists of cycles of forward order transition state changes, and the reverse disorder transition state changes are limited to a selected number per cycle.

43. The multi-level DC to DC converter circuit of claim 38, wherein: Each pattern consists of a cycle of forward order transition state changes, and consecutive reverse disorder transition state changes are limited to a selected number per cycle.

44. The multi-level DC to DC converter circuit of claim 38, wherein: Each mode consists of cycles of forward ordered transition state changes, with reverse disordered transition state changes limited to a selected number per cycle, wherein the selected number is selected based on the electrical load on the multi-stage DC to DC converter circuit.

45. The multi-level DC to DC converter circuit of claim 38, wherein: Each mode consists of cycles of forward ordered transition state changes, with consecutive reverse disordered transition state changes limited to a selected number per cycle, wherein the selected number is selected based on the electrical load on the multi-stage DC to DC converter circuit.

46. ​​The multi-level DC to DC converter circuit of claim 38, wherein: Each region is separated from at least one region by a boundary region, and wherein the control circuit is further configured to set the states of the plurality of series-coupled main switches in a boundary region transition mode to generate an output voltage in one or more boundary regions among the boundary regions.

47. A multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage, comprising: a switch path comprising a first set of series-coupled switches coupled in series with a second set of series-coupled switches, wherein each pair of switches in the first set of series-coupled switches and the second set of series-coupled switches are separated by a respective node; an inductor having a first terminal coupled between the first set of series-coupled switches and the second set of series-coupled switches and a second terminal configurable as an input, an output, or a shunt to circuit ground; For corresponding nodes in the first group of series-coupled switches and the second group of series-coupled switches, corresponding capacitors couple the corresponding node in the first group of series-coupled switches to the corresponding node in the second group of series-coupled switches; a control circuit coupled to switches in the first and second sets of series-coupled switches, configured to set states of the coupled switches in at least two modes, the at least two modes defining respective regions at a voltage output having corresponding output voltage ranges, at least one mode having a positive-going orderly transition state change; and A directional correction circuit is coupled to at least one capacitor and the control circuit, and is configured to sense a deviation in the voltage across the at least one coupled capacitor and generate a corresponding directional correction signal, wherein the corresponding directional correction signal alone or in combination forces at least one mode to undergo a reverse disordered transition state change so as to selectively guide the voltage across the at least one coupled capacitor toward a voltage balance state.

48. The multi-level DC to DC converter circuit of claim 47, wherein: The switch includes a field effect transistor.

49. The multi-level DC to DC converter circuit of claim 47, wherein: The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

50. The multi-level DC to DC converter circuit of claim 47, wherein: The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

51. The multi-level DC to DC converter circuit of claim 47, wherein: Each pattern consists of cycles of forward order transition state changes, and the reverse disorder transition state changes are limited to a selected number per cycle.

52. The multi-level DC to DC converter circuit of claim 47, wherein: Each pattern consists of a cycle of forward order transition state changes, and consecutive reverse disorder transition state changes are limited to a selected number per cycle.

53. The multi-level DC to DC converter circuit of claim 47, wherein: Each mode consists of cycles of forward ordered transition state changes, with reverse disordered transition state changes limited to a selected number per cycle, wherein the selected number is selected based on the electrical load on the multi-stage DC to DC converter circuit.

54. The multi-level DC to DC converter circuit of claim 47, wherein: Each mode consists of cycles of forward ordered transition state changes, with consecutive reverse disordered transition state changes limited to a selected number per cycle, wherein the selected number is selected based on the electrical load on the multi-stage DC to DC converter circuit.

55. The multi-level DC to DC converter circuit of claim 47, wherein: Each region is separated from at least one region by a boundary region, and wherein the control circuit is further configured to set the state of the coupled switches in a boundary region transition mode to generate an output voltage in one or more of the boundary regions.

56. A method of balancing capacitor voltages in a multi-stage DC-to-DC converter circuit for converting an input voltage to an output voltage, the multi-stage DC-to-DC converter circuit comprising an inductor, at least one capacitor selectively coupleable to the inductor, a voltage source, and / or a voltage sink via a plurality of series-coupled switches, and a control circuit configured to set states of the series-coupled switches in at least two modes, the at least two modes defining respective regions having corresponding output voltage ranges, at least one mode having a positive-going ordered transition state change, the method comprising: sensing a deviation in voltage across at least one coupled capacitor; generating an orientation correction signal corresponding to the sensed deviation; as well as The generated directional correction signals are applied to the series coupled switches individually or in combination to force at least one mode to undergo a reverse disordered transition state change to selectively steer the voltage across the coupled at least one capacitor toward a balanced voltage state.

57. The method of claim 56, wherein The switch includes a field effect transistor.

58. The method of claim 56, wherein The multi-stage DC to DC converter circuit is one of a buck-boost multi-stage DC to DC converter circuit, a boost multi-stage DC to DC converter circuit, or a buck multi-stage DC to DC converter circuit.

59. The method of claim 56, wherein The multi-level DC to DC converter circuit is one of a 3-level DC to DC converter circuit, a 4-level DC to DC converter circuit, or a 5-level DC to DC converter circuit.

60. The method of claim 56, wherein Each pattern consists of cycles of forward order transition state changes, and the method further includes limiting reverse disorder transition state changes to a selected number per cycle.

61. The method of claim 56, wherein: Each pattern consists of a cycle of forward order transition state changes, the method further comprising limiting consecutive reverse disorder transition state changes to a selected number per cycle.

62. The method of claim 56, wherein: Each mode consists of cycles of forward ordered transition state changes, the method further comprising limiting reverse disordered transition state changes to a selected number per cycle based on electrical loading on the multi-stage DC-to-DC converter circuit.

63. The method of claim 56, wherein: Each mode consists of a cycle of forward ordered transition state changes, the method further comprising limiting consecutive reverse disordered transition state changes to a selected number per cycle based on electrical loading on the multi-stage DC-to-DC converter circuit.

64. The method of claim 56, wherein Each region is separated from at least one other region by a boundary region, and the method further includes setting, by the control circuit, the states of the series-coupled switches in a boundary region transition mode to generate an output voltage in one or more of the boundary regions.

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