Apparatus, System, and Method for Latch Reset Logic

Abstract

The present invention relates to an apparatus, system, and method for latch reset logic. A memory bank may have local latches coupled between a local data bus and the memory bank. Some of the local latches may be shared local latches coupled to a first memory bank and a second memory bank. The shared latches may latch data in response to a first clock signal and a second clock signal, and may be reset in response to a combined reset signal. A reset logic circuit may receive the clock signals and a first reset signal and a second reset signal. The reset logic circuit may provide the combined reset signal based on the first clock signal and the second clock signal and the reset signals. The clock signals may be column valid commands, and the reset signals are waveforms (e.g., falling edges) of row valid commands that are part of access operations on the first memory bank or the second memory bank.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly, to apparatuses, systems, and methods for latch reset logic. Background Art

[0002] The present invention generally relates to semiconductor devices, such as semiconductor memory devices. A semiconductor memory device may include a plurality of memory cells for storing information. The stored information may be encoded as binary data, and each memory cell may store a single bit of the information. A memory array may be organized into a plurality of banks. During a memory operation, one or more banks may be activated, and information may be read from or written to the memory cells of the activated bank, for example. To save space, power, etc., some components of the memory may be shared by multiple banks. Summary of the Invention

[0003] In one aspect, the present invention provides an apparatus including: a first memory bank; a second memory bank; a local latch circuit configured to hold stored data associated with the first memory bank or the second memory bank in response to a first clock signal or a second clock signal at an active level, and configured to reset the stored data in response to a combined reset signal at an active level; and a reset logic circuit configured to receive a first reset signal associated with the first memory bank, a second reset signal associated with the second memory bank, and provide the combined reset signal based on the first reset signal and the second reset signal, wherein the reset signal changes from an active level to an inactive level coinciding with the first clock signal or the second clock signal changing from an inactive level to an active level.

[0004] In another aspect, the present invention further provides an apparatus including: a first memory bank configured to be in a first row active state in response to a first row active command and in a first column active state in response to a first column active command; a second memory bank configured to be in a second row active state in response to a second row active command and in a second column active state in response to a second column active command; a reset logic circuit configured to provide a combined reset signal based on each of the first row active command, the first column active command, the second row active command, and the second column active command; and a local latch circuit configured to latch each of a first data of the first memory bank and a second data of the second memory bank and be reset in response to the reset signal.

[0005] On the other hand, the present invention further provides a device, comprising: a plurality of local latches, wherein the plurality of local latches includes a shared latch coupled to a first memory bank and a second memory bank, and wherein the shared latch is configured to latch data in response to a first clock signal or a second clock signal at an active level, and is configured to be reset based on a combined reset signal at an active level; and a reset logic configured to store a first row valid signal associated with the first memory bank in response to the first clock signal, and store a second row valid signal associated with the second memory bank in response to the second clock signal, wherein the reset logic is configured to provide the combined reset signal at an active level in response to a falling edge of the first row valid signal or the second row valid signal when the other of the first row valid signal or the second row valid signal is not stored at an active level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

[0007] Figure 2 is a block diagram of a memory including a shared local latch according to some embodiments of the present invention.

[0008] Figure 3 is a block diagram of a memory having a shared local latch according to some embodiments of the present invention.

[0009] Figure 4 is a block diagram of a memory having a shared write latch and a shared read latch according to some embodiments of the present invention.

[0010] Figure 5 is a block diagram of a memory having a shared latch and a non-shared latch according to some embodiments of the present invention.

[0011] Figure 6 is a schematic diagram of a reset logic and local latches according to some embodiments of the present invention.

[0012] Figure 7 is a schematic diagram of a reset logic and local latches according to some embodiments of the present invention.

[0013] Figure 8 is a timing diagram of an example operation of a reset logic and a reset latch according to some embodiments of the present invention. DETAILED DESCRIPTION

[0014] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of the invention or its application or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings which show, by way of illustration, specific illustrative embodiments in which the described system and method may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the invention. Additionally, for clarity purposes, details of certain features will not be discussed when they are obvious to those skilled in the art so as not to obscure the description of the embodiments of the invention. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the invention is defined only by the appended claims.

[0015] A memory device may include a memory array having a plurality of memory cells, each of the plurality of memory cells being located at an intersection of a word line (row) and a digit line (column). During an access operation, such as a read or write operation, a row may be activated and data may be read from or written to the memory cells along the activated row. The memory cells may be organized into banks. When performing an access operation, it may be directed to a particular bank, and one or more rows in the designated bank may be activated and data may be provided (or received) along the digit lines. The digit lines may be coupled to local latches which may receive (or provide) data from (or to) the global data bus. A clock signal may cause the local latches to latch data from the global bus (or from the memory bank), and a reset signal may cause the local latches to be reset when the stored value is no longer needed. The clock signal and the reset signal may be specific to one of the banks (e.g., a first reset signal for a first bank, a second reset signal for a second bank, etc.).

[0016] To improve the performance of the memory (e.g., reduce power consumption, reduce space, etc.), local latches may be shared between a pair of banks. Thus, the latches may need to respond to clock signals and reset signals for two banks. The two reset signals may be received by a reset logic circuit which may provide a combined reset signal. If the two reset signals change state rapidly (e.g., if the second signal activates soon after the first signal deactivates), then the reset logic may 'skip' the activation of the combined reset signal. For example, if the combined reset signal is stored in the reset logic, rapid changes in the inputs may result in metastability. Even if the two reset signals change state rapidly, it may be desirable to ensure that the combined reset signal is provided correctly.

[0017] The present invention relates to an apparatus, system, and method for latch reset logic. The reset logic may receive a first reset signal and a first clock signal associated with a first memory bank, and a second reset signal and a second clock signal associated with a second memory bank. The reset logic may provide a combined reset signal such that a falling edge of the combined reset signal may coincide with a rising edge of the first or second clock signal. In this way, a shared latch cannot receive a valid clock signal and a valid reset signal simultaneously, which may cause undesirable behavior in local latches. For example, the reset logic may have a first flip-flop circuit (FF circuit) that latches the first reset signal based on the first clock signal and a second FF circuit that latches the second reset signal based on the second clock signal. The combined reset signal may be provided based on values stored in the first FF circuit and the second FF circuit.

[0018] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0019] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. In Figure 1 an embodiment, the memory array 118 is shown as including eight memory banks BANK0 to BANK7. More or fewer banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In Figure 1 an embodiment, the row decoder 108 includes a respective row decoder for each memory bank, and the column decoder 110 includes a respective column decoder for each memory bank. The bit lines BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL is amplified by the sense amplifiers SAMP and transferred to a read / write amplifier through complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B) coupled to an error correction code (ECC) control circuit 120. Conversely, write data output from the ECC control circuit 120 is transferred to the sense amplifiers SAMP through the complementary main data lines MIOT / B, transfer gates TG, and complementary local data lines LIOT / B, and written to the memory cells MC coupled to the bit lines BL.

[0020] To manage the timing of various memory operations, each of the banks in the memory array 118 may be associated with a set of local latches 121. The local latches 121 may store data associated with the memory bank and may couple the stored data to a global data bus that couples the local latches 121 to the IO circuitry 122 (and to the DQ pads). For example, the IO circuitry 122 may receive data at the DQ pads and provide it along the global data bus to the local latches 121, which may then provide the data to the associated memory bank. The local latches 121 may receive a clock signal that causes them to latch the data along the global data bus. In some embodiments, the clock signal may be associated with a particular operation (e.g., a write signal, a read signal) and may be specific to a particular memory bank (e.g., a first clock is associated with a first memory bank, a second clock is associated with a second memory bank). Thus, the local latches may respond to the clock signal associated with the memory bank to which the latches are associated. Similarly, when the data in the local latches 121 is no longer needed, a reset signal may cause the latches to return to a neutral state. The reset signal may also be associated with a particular operation and / or memory bank, and certain local latches may respond to a particular one of the reset signals. In some embodiments, the reset signal may be a signal used by the memory for various operations, such as the precharge signal Pre used to turn off the word lines.

[0021] The clock and reset signals may represent the waveforms of one or more signals used by the memory as part of an access operation. In some embodiments, the reset signal may be a portion of the waveform of a signal used to activate a row in one of the selected memory banks. For example, the reset signal may be the falling edge (e.g., the transition from an active state to an inactive state) of a row activation command such as ACT or RAS. In some embodiments, the clock signal may be a column active command used to activate a digital line and thus read data from or write data along the digital line. For example, the clock signal may be a read signal RD or a write signal WT. Other signals and other waveforms may be used in other instances.

[0022] Some of the local latches 121 may be shared local latches that are associated with more than one bank. These local latches 121 may be activated to store data associated with any one of the banks associated with the shared latch. Thus, the shared local latch may respond to signals (e.g., clock signals and reset signals) associated with any one of the banks associated with the local latch. For example, if a particular local latch 121 is shared between a first memory and a second bank, the shared local latch may respond to both a first clock signal and a second clock signal. One or more reset logic circuits may receive a reset signal associated with the bank shared by the shared latch and may provide a combined reset signal to the shared latch. The reset logic and the operation of the reset logic and the combined reset signal are discussed in more detail herein.

[0023] The semiconductor device 100 may employ a plurality of external terminals, including: command and address (C / A) terminals coupled to a command and address bus to receive commands, addresses, and a CS signal; clock terminals for receiving clock CK and / CK; data terminals DQ for providing data; and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0024] The clock terminals are supplied with the external clocks CK and / CK that are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for the timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuits included in the input / output circuit 122, such as providing to the data receiver to time the reception of the written data.

[0025] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transferred to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 118 that contains the decoded row address XADD and column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more of the row address XADD, column address YADD, and bank address BADD to indicate the memory cell to be accessed.

[0026] The command may be provided to the command decoder 106 as an internal command signal via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0027] The device 100 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are supplied in a timely manner with the read command, read data is read from the memory cell corresponding to the row address and column address in the memory array 118. The read command is received by the command decoder 106, which provides an internal command such that the read data from the memory array 118 is provided to the ECC control circuit 120. The read command may also cause one or more parity bits associated with the read data to be provided to the ECC control circuit 120 along MIOT / B. The ECC control circuit 120 may use the parity bits to determine whether the read data contains any errors, and if any errors are detected, it may correct them to generate corrected read data. The corrected read data is stored in the local latch 121 associated with the bank indicated by the bank address. Then, the local latch 121 may provide the corrected read data to the IO circuit 122 along the global data bus. The corrected read data is output from the data terminal DQ to the outside of the device 100 via the input / output circuit 122. In some embodiments, the ECC circuit 120 may be omitted, and the read data may be provided directly to the local latch 121 (e.g., without parity bits).

[0028] The device 100 can receive an access command as a write command. When the write command is received and the bank address, row address, and column address are supplied in a timely manner with the write command, and the write data is supplied to the ECC control circuit 120 through the DQ terminals. The write data is provided along the global data bus and stored in the local latch 121 associated with the bank indicated by the bank address. The write data stored in the local latch 121 is written to the memory cell corresponding to the row address and column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command such that the write data is received by the data receiver in the input / output circuit 122. A write clock may also be provided to the external clock terminal for timing the reception of the write data by the data receiver in the input / output circuit 122. The write data is supplied to the ECC control circuit 120 via the local latch 121. The ECC control circuit 120 can generate several parity bits based on the write data, and the write data and the parity bits can be provided to the memory array 118 to be written to the memory cell MC. In some embodiments, the ECC control circuit 120 can be omitted, and the data in the local latch 121 can be provided to the bank.

[0029] Optionally, the ECC control circuit 120 can be used to ensure the fidelity of the data read from a specific group of memory cells to the data written to the memory cells of the group. The device 100 can include several different ECC control circuits 120, each of which is responsible for a different part of the memory cells MC of the memory array 118. For example, there can be one or more ECC control circuits 120 for each bank of the memory array 118.

[0030] Each ECC control circuit 120 may receive a certain number of data bits (from the IO circuit 122 or the memory array 118), and may use several parity bits based on the number of data bits to correct potential errors in the data bits. For example, as part of a write operation, the ECC control circuit 120 may receive 128 bits of data from the IO circuit 122, and may generate 8 parity bits based on the 128 data bits. The 128 data bits and 8 parity bits (e.g., a total of 136 bits) may be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 may receive 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 may use the 8 parity bits to determine whether any errors exist in the 128 read data bits, and if an error is found, it may correct it. For example, the ECC control circuit 120 may be able to locate and correct up to one error in the 128 data bits based on the 8 parity bits. Although various embodiments may be described with reference to an ECC circuit that uses 8 parity bits to find one error in 128 data bits, it should be understood that these are for illustrative purposes only, and in other example embodiments, other numbers of data bits, error bits, and parity bits may be used.

[0031] The device 100 may also receive a command to cause it to perform one or more refresh operations as part of the self-refresh mode. In some embodiments, the self-refresh mode command may be issued to the storage device 100 from the outside. In some embodiments, the self-refresh mode command may be periodically generated by components of the device. In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal AREF may also be activated. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated once immediately after the command input, and may thereafter be periodically activated at a desired internal timing. The refresh signal AREF may be used to control the timing of the refresh operation during the self-refresh mode. Thus, the refresh operation may continue automatically. The self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state. The refresh signal AREF is supplied to the refresh control circuit 116. The refresh control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which may refresh one or more word lines WL indicated by the refresh row address RXADD.

[0032] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, and the like, based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0033] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are provided to the input / output circuit 122. In an embodiment of the present invention, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present invention, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 such that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0034] Figure 2 is a block diagram of a memory including shared local latches according to some embodiments of the present invention. The memory 200 may be, for example Figure 1 a view of the memory of the memory device 100, highlighting the operation of the local latches and the reset logic. The memory 200 may be a simplified view, and various components of the memory 200 may be combined and / or simplified for clarity. For example, the C / A circuit 202 may include memory components such as a C / A input circuit (e.g., Figure 1 102), a row decoder, and a column decoder (e.g., Figure 1 108 and 110) and / or a command decoder (e.g., Figure 1 106).

[0035] Memory 200 includes a first memory bank (bank 0) 210, a second memory bank (bank 1) 212, a third memory bank (bank 2) 214, and a fourth memory bank (bank 3) 216. Each of the memory banks 210 to 216 includes a number of memory cells arranged at the intersections of corresponding rows and columns. The first bank 210 and the second bank 212 share a set of local latches 208, and the third bank 214 and the fourth bank 216 share a set of local latches 209. For clarity, only a single latch is shown in detail in each of the sets of local latches 208 and 209, although each of the sets of local latches 208 and 209 may include multiple such latches.

[0036] The local latch 208 has a first input / output terminal (labeled D / Q) coupled to the global DQ bus. The global DQ bus is in turn coupled to the DQ terminal 201 (and to Figure 2 input / output circuitry not shown). The local latch 208 has a second input / output terminal (labeled Q / D) coupled to the memory banks 210 and 212. The two input / output terminals are shown to indicate that data can flow through the latch in different directions based on the operation. For example, if the local latch 208 is used as part of a write operation, data can be provided along the global DQ bus, the first I / O terminal D / Q can be the input terminal, and the second I / O terminal Q / D can be the output terminal that provides the stored bit to the banks 210 / 212. If the local latch 208 is used as part of a read operation, data can come from one of the banks 210 / 212, and the second I / O terminal Q / D can act as the input while the first I / O terminal D / Q acts as the output terminal to the global DQ bus.

[0037] The C / A circuit 202 can provide various signals to the local latches 208 and 209. For example, the C / A circuit 202 can provide first, second, third, and fourth reset signals Rst0 to Rst4, each of which can be associated with a corresponding one of the four memory banks 210 to 216. Similarly, the C / A circuit 202 can provide clock signals Clk0 to Clk4, each of which can be associated with a corresponding one of the four memory banks 210 to 216. The clock signals Clk0 to Clk4 can represent any signals used to indicate that an access operation is being performed on the associated memory banks 210 to 216. For example, the clock signals Clk0 to Clk4 can be column active commands, such as read signals RD0 to RD4 or write signals WT0 to WT4. The reset signals and clock signals can be provided by the C / A circuit 202 in response to a memory bank address of one of the memory banks 210 to 216 and the received access command. For example, if a read command is received along with a memory bank address indicating the first memory bank 210, then signals Clk0 and Rst0 can be provided.

[0038] The first clock signal Clk0 and the second clock signal Clk1 are provided to the clock terminal CLK of the first local latch 208. In response to the activation of the first clock signal Clk0 or the second clock signal Clk1, the first local latch 208 can latch a certain value (e.g., from the global DQ bus or the first / second memory banks 210 / 212, depending on whether the local latch is used for a write operation or a read operation). The third clock signal Clk2 and the fourth clock signal Clk3 are provided to the clock terminal CLK of the second local latch 209. The second local latch 209 can latch a value (e.g., from the global DQ bus or the third / fourth memory banks 214 / 216, depending on whether the local latch is used for a write operation or a read operation). When the clock signal coupled to the clock terminal CLK of the local latch 208 is valid (e.g., at a high logic level), the local latch 208 can store the value on the input terminal D of the latch 208.

[0039] The C / A circuit 202 may also provide reset signals Rst0 to Rst3, each of which is associated with a corresponding one of the memory banks 210 to 216. The reset signals may indicate that a particular access operation has ended and that the values in the local latches 208 / 209 are no longer needed. For example, the precharge signal Pre may be used as a reset signal. For example, the falling edge of an access signal such as a row active command (e.g., an activation signal such as ACT or RAS) may be used as a reset signal. The first reset signal Rst0 and the second reset signal Rst1 are received by the first reset logic circuit 204, which provides a first combined reset signal Rst01 based on the two reset signals Rst0 and Rst1. The first reset logic 204 also receives clock signals Clk0 and Clk1 and uses these signals to time the combined reset signal Rst01. The combined reset signal Rst01 is provided to the reset terminal RST of the local latch 208. When the combined reset signal Rst01 is active (e.g., at a high logic level), the latch 208 may be reset to a neutral state. Whenever the first reset signal Rst0 or the second reset signal Rst1 is active, the reset logic circuit 204 may provide an activation of the combined reset signal Rst01. The reset logic circuit 204 may provide the combined reset signal Rst01 such that each falling edge of the combined reset signal Rst01 occurs approximately simultaneously with the rising edge of one of the clock signals Clk0 or Clk1. In some embodiments, the falling edge of the combined reset signal Rst01 may coincide with the rising edge of one of the clock signals Clk0 or Clk1. The second reset logic circuit 205 may operate in a manner similar to the reset logic circuit 204, except that the reset logic circuit 205 provides a second combined reset signal Rst23 based on the reset signals Rst2 and Rst3 and the clock signals Clk2 and Clk3.

[0040] Figure 3 is a block diagram of a memory having a shared local latch according to some embodiments of the present invention. In some embodiments, the memory 300 may be included in Figure 2 memory 200 of Figure 1 and / or Figure 2 memory device 100 of Figure 1 The memory 300 may represent a more detailed view of a pair of memory banks 310 and 312 that share a local latch 308 therebetween. For the sake of brevity, features and operations previously described with respect to Figure 3 memory 200 of

[0041] The local latch 308 includes a number of individual shared latches 330 (labeled 0 through N here), each of which is coupled to the first bank 310 and the second bank 312. In some embodiments, the number of local latches 330 may be based on the number of bits transmitted along the global data bus. Each of the individual shared latches 330 is commonly coupled to a combined reset signal Rst01, a first clock signal CLk0, and a second clock signal Clk1. In some embodiments, each of the local latches may be coupled to the two clock signals Clk0 and Clk1 through clock logic (not shown). For example, the first and second clock signals may be coupled to the inputs of an OR gate, which may jointly provide a combined clock signal Clk01 to each of the latches 330.

[0042] Figure 4 is a block diagram of a memory having shared write latches and shared read latches according to some embodiments of the present invention. In some embodiments, Figure 4 the memory 400 may be included in Figures 1 to 3 the memories 100, 200, and / or 300 of Figure 3 the memory 300, Figure 2 the memory 200, and / or Figure 1 the memory device 100 will not be repeated with respect to Figure 4 For the sake of brevity, the features and operations previously described with respect to Figure 4 the memory 400 shows a set of write latches 432 and a set of read latches 434 in the local latch 408.

[0043] The memory 400 has a set of shared write latches 432 that serve as part of the write operation to the first memory bank 410 and the second memory bank 412, and a set of shared read latches 434 that serve as part of the read operation to the first memory bank 410 and the second memory bank 412. The C / A circuit 402 may provide a first write clock WT0 and a second write clock WT1 that are respectively associated with the write operations to the first memory bank 410 and the second memory bank 412. The C / A circuit 402 may also provide a read clock RD0 and a read clock RD1 that are respectively associated with the read operations in the first and second banks 410 / 412.

[0044] The reset logic 404 may have a write reset logic 406 that provides a combined write reset signal Rst01_WT based on two reset signals Rst0 and Rst1 and two write clocks WT0 and WT1. The reset logic 404 includes a read reset logic 407 that provides a combined read reset signal Rst01_RD based on two reset signals Rst0 and Rst1 and two read clocks RD0 and RD1. The write latches 432 may jointly receive the combined write reset signal Rst01_WT and the write clocks WT0 and WT1. The read latches 434 may jointly receive the combined read reset signal Rst01_RD and the read clocks RD01 and RD1.

[0045] The write latches 432 may store data from the global DQ bus in response to the activation of either one of the write clocks WT0 or WT1. The data stored in the write latches 432 may be provided to the bank 410 or the bank 412 and written to the memory cells of the activated bank. Based on the activation of the first reset signal Rst0 or the second reset signal Rst1, the write reset logic 406 may provide the activation of the combined write reset signal Rst01_WT. The falling edge of the write reset signal Rst01_WT may occur approximately simultaneously with the rising edge of one of the write clock signals WT0 or WT1. The activation of the combined write reset signal Rst01_WT may cause the write latches 432 to be reset to a neutral state (e.g., to discard currently stored data).

[0046] The read latches 434 may store data from the bank 410 or the bank 412 in response to the activation of either one of the read clocks RD0 or RD1. Then, the data stored in the read latches may be read out to the DQ terminals 401 along the global DQ bus and provided from the memory 400. Based on the activation of the first reset signal Rst0 or the second reset signal Rst1, the read reset logic 407 may provide the activation of the combined read reset signal Rst01_RD. The falling edge of the read reset signal Rst01_RD may occur approximately simultaneously with the rising edge of one of the read clocks RD0 or RD1. The activation of the combined read reset signal Rst01_RD may cause the read latches 434 to be reset to a neutral state.

[0047] Figure 5 is a block diagram of a memory having shared latches and non-shared latches according to some embodiments of the present invention. In some embodiments, Figure 5 the memory 500 may be included in Figures 1 to 4 the memories 100, 200, 300, and / or 400 of Figure 4 the memory 400, Figure 3 the memory 300, Figure 2memory 200 and / or Figure 1 the features and operations described for memory device 100 will not be repeated with respect to Figure 5 repeated. Figure 5 memory 500 shows a set of local latches 508 that includes a shared latch 532 shared between two banks 510 and 512 and local latches 534 not shared between the banks. In some embodiments, local latches 508 may represent read latches (e.g., Figure 4 434 of Figure 4 432 of

[0048] Reset logic 504 includes shared reset logic 506 and bank-specific reset logic 507. Shared reset logic 506 may operate in a manner substantially similar to Figure 3 reset logic 304 of

[0049] Shared reset logic 506 provides a combined reset signal Rst01 when either of two reset signals Rst0 or Rst1 is active, where the timing is based in part on clock signals Clk0 and Clk1. Bank-specific reset logic 507 may provide a reset signal Rst1, the timing of which may be affected by clock signal Clk1. In some embodiments, bank-specific reset logic 507 may be omitted, and reset signal Rst1 may be passed directly from C / A circuit 502 to local latches 534. In some embodiments, in the case of using the waveform of the row active signal, bank-specific reset logic 507 may receive the row active signal and may generate reset signal Rst1 based on the row active signal.

[0050] In some embodiments, a set of local latches 508 may include various mixes of shared and non-shared local latches. Although only a single instance of a shared latch 532 and a non-shared latch 534 are shown, the local latches 508 may include any number of shared and non-shared latches. Similarly, although the non-shared latches 534 are coupled to the second bank 512, the local latches 508 may include a mix of latches coupled to the first bank 510, latches coupled to the second bank 512, or latches coupled to each bank. For example, the local latches 508 may include a shared read latch instead of separate write latches for the first bank 510 and the second bank 512 (or a shared write latch instead of a shared read latch).

[0051] Figure 6 is a schematic diagram of reset logic and local latches according to some embodiments of the present invention. In some embodiments, the reset logic 602 may be included in the Figure 2 reset logic 204 / 205 of Figure 3 304 of Figure 4 404 of Figure 5 and / or Figure 2 504 of Figure 3 Similarly, in some embodiments, the local latches 608 may be included in the Figure 4 local latches 208 / 209 of Figure 5 308 of Figure 6 408 of Figure 4 and / or Figure 4 508 of

[0052] The reset logic 602 includes a first flip-flop (FF) circuit 640 and a second FF circuit 642. The first FF circuit 640 has inputs coupled to a first row active command RAS_k0 and a first write clock WT_k0 (e.g., column active command), both of which are associated with operations in the first bank. The signal RAS_k0 being at an active level can be associated with an access operation in the first bank (e.g., bank 0). The signal RAS_k0 transitioning to an inactive level can indicate that the access operation has ended. Thus, the falling edge of RAS_k0 can serve as a reset signal (e.g., the falling edge of RAS_k0 can be similar to the activation of Rst0 of Figures 1 to 5 . The second FF circuit 642 can be coupled to a second row active command RAS_k1 and a second write clock WT_k1 (e.g., column access signal), both of which are associated with operations in the second bank. The falling edge of RAS_k1 can serve as a second reset signal. In some embodiments, the first FF circuit 640 and the second FF circuit 642 can be generally similar to each other. In some embodiments, the first FF circuit 640 and the second FF circuit 642 can be structurally identical but coupled to different inputs.

[0053] The first FF circuit 640 provides a first inverted reset signal RSTF_k0, and the second FF circuit 642 provides a second inverted reset signal RSTF_k1. The inverted reset signals RSTF_k0 and RSTF_k1 can typically be active when no reset signal is provided. For example, a logic gate such as NOR gate 644 provides a combined reset signal RST_k01 based on the two inverted reset signals RSTF_k0 and RSTF_k1 (e.g., similar to Rst01 of Figures 1 to 5 ). When both inputs of one of the FF circuits 640 and 642 become active, the output signal can become active until the first input becomes inactive. For example, when the first FF circuit 640 receives RAS_k0 and WT_k0 at an active level, the output RSTF_k0 can switch to an active level. As long as RAS_k0 is at an active level, the signal RSTF_k0 can remain at an active level. When the signal RAS_k0 transitions to an inactive level, the signal RSTF_k0 can also transition to an inactive level to indicate that a reset signal should be provided to the local latch 608.

[0054] The logic gate 644 can be a NOR gate that provides an active level (e.g., high logic level) total combined reset signal RST_k01 when both of the inverted signals RSTF_k0 and RSTF_k1 are inactive (e.g., low logic level). Thus, when one of the clock signals WT_k0 or WT_k1 becomes active, the associated inverted reset signal (RSTF_k0 or RSTF_k1) can become active, which in turn can cause the combined signal RST_k01 to become inactive.

[0055] The local latch 608 is shown as including clock logic, which in the example is the OR gate 650. The OR gate 650 receives two clock signals WT_k0 and WT_k1 and provides a combined clock signal WT_k01. The combined clock signal WT_k01 can be valid when either the first clock signal WT_k0 or the second clock signal WT_k1 is valid. The combined clock signal WT_k01 is provided to the clock terminal CLK of the shared latch 652. The reset terminal RST of the shared latch 652 is coupled to the combined reset signal RST_k01. The data terminal D of the latch 652 is coupled to a first signal A, which can be part of a global data bus. The output terminal Q of the latch 652 is coupled to a signal B, which can be provided to two banks coupled to the shared latch 652.

[0056] Figure 7 is a schematic diagram of the reset logic and the local latch according to some embodiments of the present invention. In some embodiments, the reset logic 702 can be included in Figure 2 the reset logic 204 / 205 of Figure 3 the 304 of Figure 4 the 404 of Figure 5 the 504 of and / or Figure 6 the 602 of. Similarly, in some embodiments, the local latch 708 can be included in Figure 2 the local latch 208 / 209 of Figure 3 the 308 of Figure 4 the 408 of Figure 5 the 508 of and / or Figure 6 the 608 of. The reset logic 702 and the local latch 708 can be Figure 6 the implementation of the reset logic 602 of Figure 6 and the local latch 608 of. For the sake of brevity, the details and operations described with respect to Figure 6 will not be repeated with respect to Figure 7 .

[0057] The reset logic 702 includes a first flip - flop circuit (e.g., Figure 6 the 640 of

[0058] which includes a first NAND gate 741, a second NAND gate 743, and an inverter 745. The first NAND gate has a first input terminal coupled to RAS_k0 and a second input terminal coupled to RSTF_k0. The second NAND gate 743 has a first input terminal coupled to the output of the first NAND gate 741 and a second input terminal coupled to WT_k0 through an inverter circuit 745. The output of the second NAND gate 743 is the signal RSTF_k0. The second flip - flop circuit can be generally similar, having NAND gates 747 and 748 and an inverter 749.The latch 752 includes first, second, and third inverters 761 to 763 and a NAND gate 764. The second inverter 762 has an input terminal coupled to the input D of the latch 752. The second inverter also has a first power terminal coupled to the clock terminal CK through the first inverter 761 and a second power terminal coupled to the clock terminal CK of the latch 752. The output of the second inverter 762 is provided to a node coupled to the input of the third inverter 763, and the third inverter 763 has an output provided to the output terminal Q of the latch 752. The output terminal Q is also coupled to one of the inputs of the "NAND" gate 764. The other input terminal of the NAND gate 764 may be an inverted input, which is coupled to the reset terminal Rst of the latch 752. The output of the NAND gate 764 is coupled to the node between the second inverter 762 and the third inverter 763.

[0059] Figure 8 is a timing diagram of an example operation of the reset logic and the reset latch according to some embodiments of the present invention. In some embodiments, the timing diagram 800 may represent Figure 2 the reset logic 204 / 205 of Figure 3 the 304 of Figure 4 the 404 of Figure 5 the 504 of Figure 6 the 602 of Figure 7 and / or the operation of the 702 of Figure 6 and 7 using the signal names of

[0060] Different segments of the timing diagram 800 show the signals that can be used by the reset logic, as well as the input data A and the output data B and the combined clock signal WT_k01. Except for data A and B, the signals are represented as idealized binary signals, which have a low logic level (e.g., an invalid state) and a high logic level (e.g., a valid state).

[0061] At the initial time t0, the second write clock WT_k1 rises to the valid level. The signal RAS_k1 may have risen to the valid level at a time before the initial time t0 and may remain at the valid level at time t0. Since both the signals RAS_k1 and WT_k1 are at the valid level, the first flip - flop circuit (e.g., Figure 6The 640) can be switched to provide a signal RSTF_k1 at an active level. At the initial time t0, the signals (RAS_k0 and WT_k0) associated with the first bank may both be inactive, so the signal RSTF_k0 may also be inactive. Therefore, at the initial time t0, since RSTF_k0 is inactive but RSTF_k01 is active, the combined reset signal RST_k01 can switch from active to inactive. Since one of the clock signals (WT_k1) is active, the combined clock signal WT_k01 may become active at time t0, which may cause the local latch to latch the value of signal A and provide the latched value as signal B. Since the example of the timing diagram 800 is for a write operation, the local latch can receive information A from the global DQ bus and provide it as signal B to the active bank (which is the second bank at t1).

[0062] At some point after time t0 (but before the first time t1), the signal RAS_k1 may fall from an active state to an inactive state. The transition of RAS_k1 from active to inactive can act as a reset signal (e.g., the activation of Rst1). This can cause the signal RSTF_k1 to also fall to an inactive state, which in turn causes the combined reset signal RST_k01 to rise to an active level. This can cause the local latch to reset, thus losing the previously saved value of signal A. Between time t0 and t1, the signal RAS_k0 can rise to an active level, but since the clock WT_k0 is not activated until time t1, the change in RAS_k0 before time t1 does not affect the value of the signal RSTF_k0.

[0063] At time t1, the clock signal WT_k0 becomes active. Since the signal RAS_k0 is already active, this can cause the inverted reset signal RSTF_k0 to become active. Since one of the inverted reset signals is active, the combined reset signal may become inactive. Since one of the clocks is active (WT_k0), the combined clock WT_k01 can become active. Therefore, the local latch can latch the new value of signal A and provide the new stored value as signal B. In this case, since the clock signal WT_k0 is associated with the first bank (e.g., bank 0), the local latch can provide the value to the first bank.

[0064] At the second time t2, the signal RAS_k0 can fall to an inactive level. The falling edge of RAS_k0 can act as a reset signal (e.g., the activation of Rst0). The falling edge of RAS_k0 can cause the inverted reset signal RSTF_k0 to fall to an inactive level. Since at t2, both the inverted reset signals RSTF_k0 and RSTF_k1 are inactive, the reset signal RST_k01 can become active. The signal RSTF_k0 becoming active can cause the local latch to reset.

[0065] At a third time t3, the clock signal WT_k1 can become active. Since the signal RAS_k1 is active at time t3, the signal RSTF_k1 can rise to an active level. The signal RSTF_k1 being active can in turn cause the combinational reset signal RST_k01 to become inactive again. In this way, even if the time between t2 and t3 is relatively short, activation of RST_k01 is provided appropriately, and the activation ends when the clock WT_k1 is activated at t3.

[0066] Of course, it should be understood that any one of the examples, embodiments, or processes described herein can be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed among separate devices or portions of a device in accordance with the present system, apparatus, and method.

[0067] Finally, the foregoing discussion is intended to be illustrative only of the present system and should not be construed as limiting the appended claims to any particular embodiment or set of embodiments. Thus, although the present system has been described in detail with reference to exemplary embodiments, it should also be understood that those of ordinary skill in the art can devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device, which comprises: a first memory bank; a second memory bank; a local latch circuit configured to hold stored data associated with the first memory bank or the second memory bank in response to a first clock signal or a second clock signal at an active level, and configured to reset the stored data in response to a combined reset signal at an active level; and a reset logic circuit configured to receive a first reset signal associated with the first memory bank, a second reset signal associated with the second memory bank, and provide the combined reset signal based on the first reset signal and the second reset signal, wherein a time when the reset signal changes from an active level to an inactive level coincides with a time when the first clock signal or the second clock signal changes from an inactive level to an active level.

2. The device according to claim 1, wherein the first clock signal is associated with an access operation in the first memory bank, and the second clock signal is associated with an access operation in the second memory bank.

3. The device according to claim 1, wherein the first reset signal is a falling edge of a first row valid signal associated with the first memory bank, and the second reset signal is a falling edge of a second row valid signal associated with the second memory bank.

4. The device according to claim 1, wherein the reset logic circuit comprises: a first flip-flop circuit configured to receive the first reset signal and the first clock signal and provide a first inverted reset signal; a second flip-flop circuit configured to receive the second reset signal and the second clock signal and provide a second inverted reset signal; and a logic circuit configured to provide the combined reset signal at an active level when both the first inverted reset signal and the second inverted reset signal are inactive.

5. The device according to claim 4, wherein the first flip-flop circuit is configured to provide the first inverted reset signal at an active level in response to the first clock signal, and provide the first inverted reset signal at an inactive level in response to the first reset signal, and wherein the second flip-flop circuit is configured to provide the second inverted reset signal at an active level in response to the second clock signal, and provide the second inverted reset signal at an inactive level in response to the second reset signal.

6. The device according to claim 1, further comprising clock logic configured to receive the first clock signal and the second clock signal and provide a combined clock signal based on the first clock signal and the second clock signal, wherein the local latch circuit is configured to hold the stored data in response to the combined clock signal.

7. The apparatus according to claim 1, further comprising a second local latch circuit, wherein the local latch circuit is a write local latch configured to receive data from a global data bus and provide the received data to the first memory bank or the second memory bank, and wherein the second local latch circuit is a read local latch configured to receive data from the first memory bank or the second memory bank and provide the received data to the global data bus.

8. An apparatus, which comprises: a first memory bank configured to be in a first row active state in response to a first row active command and in a first column active state in response to a first column active command; a second memory bank configured to be in a second row active state in response to a second row active command and in a second column active state in response to a second column active command; reset logic circuitry configured to provide a combined reset signal based on each of the first row active command, the first column active command, the second row active command, and the second column active command; and a local latch circuit configured to latch each of first data of the first memory bank and second data of the second memory bank and be reset in response to the reset signal.

9. The apparatus according to claim 8, wherein the row active command is an activation signal and the column active command is a write or read signal.

10. The apparatus according to claim 9, wherein the first row active command and the first column active command are generated in response to a received access command and a first bank address, and the second row active command and the second column active command are generated in response to a received access command and a second bank address.

11. The apparatus according to claim 8, wherein the reset logic circuitry comprises: a first flip-flop circuit configured to provide a first inverted reset signal based on the first row active command and the first column active command; a second flip-flop circuit configured to provide a second inverted reset signal based on the second row active command and the second column active command; and logic circuitry configured to provide the combined reset signal at an active level in response to the first inverted reset signal and the second inverted reset signal both being at an inactive level.

12. The apparatus according to claim 11, wherein the first flip-flop circuit is configured to provide the first inverted reset signal at an active level when both the first row active command and the first row active command are at an active level, and provide the first inverted reset signal at an inactive level when the first row active command becomes inactive, and wherein the second flip-flop circuit is configured to provide the second inverted reset signal at an active level when both the second row active command and the second column active command are at the active level, and to provide the second inverted reset signal at an inactive level when the second row active command goes inactive.

13. The apparatus of claim 8, wherein the local latch is a read latch configured to receive data from the first memory bank or the second memory bank and provide the received data to a global data bus, or a write latch configured to receive data from the global data bus and provide the received data to the first memory bank or the second memory bank.

14. The apparatus of claim 8, wherein the local latch is configured to store data in response to the first column active command or the second column active command at an active level.

15. An apparatus, which comprises: a plurality of local latches, wherein the plurality of local latches includes a shared latch coupled to a first memory bank and a second memory bank, and wherein the shared latch is configured to latch data in response to a first clock signal or a second clock signal at an active level, and to be reset based on a combined reset signal at an active level; and reset logic configured to store a first row active signal associated with the first memory bank in response to the first clock signal, and to store a second row active signal associated with the second memory bank in response to the second clock signal, wherein the reset logic is configured to provide the combined reset signal at an active level in response to a falling edge of the first row active signal or the second row active signal when the other of the first row active signal or the second row active signal is not stored at an active level.

16. The apparatus of claim 15, wherein the plurality of local latches includes a non-shared latch associated with the first memory bank, wherein the non-shared latch is configured to latch data in response to the first clock signal at an active level, and to be reset based on a first reset signal associated with the first memory bank.

17. The apparatus of claim 15, wherein the plurality of local latches includes a read latch and a write latch, wherein the read latch is configured to latch data from the first memory bank or the second memory bank in response to the first clock signal or the second clock, and to provide the latched data to a global data bus and be reset based on a combined read reset signal, and the write latch is configured to latch data from the global data bus in response to a third clock signal or a fourth clock signal, and to provide the latched data to the first memory bank or the second memory bank and be reset based on a combined write reset signal.

18. The apparatus according to claim 17, wherein the reset logic comprises: a read reset logic configured to provide the combined read reset signal based on the first row valid signal, the second row valid signal, the first clock signal, and the second clock signal; a write reset logic configured to provide the combined write reset signal based on the first row valid signal, the second row valid signal, the third clock signal, and the fourth clock signal.

19. The apparatus according to claim 17, wherein the first clock signal and the second clock signal are read column valid commands, and wherein the third clock signal and the fourth clock signal are write column valid commands.

20. The apparatus according to claim 15, wherein the reset logic comprises: a first flip-flop circuit configured to provide a first inverted reset signal at an active level in response to the first row valid signal and the first clock signal at an active level, and to provide the first inverted reset signal at an inactive level in response to the first row valid signal returning to an inactive level; a second flip-flop circuit configured to provide a second inverted reset signal at an active level in response to the second row valid signal and the second clock signal at an active level, and to provide the second inverted reset signal at an inactive level in response to the second row valid signal returning to an inactive level; and a logic circuit configured to provide the combined reset signal at an active level in response to both the first inverted reset signal and the second inverted reset signal being at an inactive level.

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