Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the invention provide a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device includes forming a gate trench on a semiconductor fin. The gate trench includes an upper portion surrounded by a plurality of first gate spacers and a lower portion surrounded by a plurality of second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is on a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate on the metal gate in the lower portion of the gate trench and a second portion of the gate dielectric layer remains to cover sidewalls of the first gate spacers and upper surfaces of the second gate spacers. The method includes removing the second portion of the gate dielectric layer while the gate remains substantially intact.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly, to methods for forming non-planar transistors. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components such as transistors, diodes, resistors, capacitors, and the like. This improvement in integration density is primarily due to the repeated reduction in minimum structural dimensions to fit more components into a given area.

[0003] FinFET devices are widely used in integrated circuits. FinFET devices have a three-dimensional structure, comprising a fin protruding from a substrate. A gate structure is provided to control charge carriers in the FinFET's conductive channel and may wrap around the fin. For example, in a tri-gate FET device, the gate structure wraps around three sides of the fin, forming a conductive channel on all three sides of the fin. Summary of the Invention

[0004] An object of the embodiments of the present invention is to provide a semiconductor device and a method for manufacturing the same to solve at least one of the above problems.

[0005] In one embodiment of the present invention, a method for manufacturing a semiconductor device is disclosed. The method includes forming a gate trench on a semiconductor fin. The gate trench includes an upper portion surrounded by a plurality of first gate spacers, and a lower portion surrounded by a plurality of second gate spacers and the first gate spacer. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is located on a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate on the metal gate in the lower portion of the gate trench, with a second portion of the gate dielectric layer maintaining coverage of the sidewalls of the first gate spacer and the upper surface of the second gate spacer. The method includes removing the second portion of the gate dielectric layer, while the gate remains substantially intact.

[0006] In another embodiment of the present invention, a method for manufacturing a semiconductor device is disclosed. The method includes removing a dummy gate structure covering a portion of a semiconductor fin. The method includes forming a metal gate on the portion of the semiconductor fin, wherein the metal gate is located on a first portion of a gate dielectric layer. The method includes depositing a metal material to form a gate contacting the metal gate and exposing a second portion of the gate dielectric layer. The method includes etching the second portion of the gate dielectric layer, exposing the gate during the etching. The gate remains substantially intact.

[0007] In another embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a first spacer located on the semiconductor fin. The semiconductor device includes a second spacer located on the semiconductor fin and extending further from the semiconductor fin than the first spacer. The semiconductor device includes a metal gate located on the semiconductor fin and sandwiched between the first spacers, which are further sandwiched between the second spacers. The semiconductor device includes a gate contacting an upper surface of the metal gate, wherein the gate does not extend over the first spacer or the second spacer.

[0008] An advantageous effect of an embodiment of the present invention is that the disclosed method for fabricating a semiconductor device forms a gate, such as a metal structure, on a metal gate to help protect underlying structures before selectively etching the portion of the gate dielectric layer uncovered by the gate, such as the metal structure. In this manner, more material of the gate, such as the metal structure, remains intact during the selective etching process, helping to prevent unintended overetching and damage to underlying layers. This prevents damage to the metal gate and maintains its critical dimensions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a perspective view of a FinFET device in some embodiments.

[0010] Figure 2 FIG. 1 is a flow chart of a method for fabricating a non-planar transistor device in some embodiments.

[0011] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 and Figure 20 In some embodiments, Figure 2 Cross-sectional views of a fin field effect transistor or a portion thereof manufactured by a method at various stages of manufacture.

[0012] Figure 21 FIG. 5 is a cross-sectional view of another FinFET device in some embodiments.

[0013] Figure 22 FIG. 5 is a cross-sectional view of another FinFET device in some embodiments.

[0014] The reference numerals are as follows:

[0015] AA,BB: Section

[0016] H1, H2: Depth

[0017] H3,H4: Height

[0018] L1, L2: channel length

[0019] W1, W2, W3: width

[0020] 100, 300A, 300B: FinFET devices

[0021] 102,302:Substrate

[0022] 104,404: Fins

[0023] 106,500: Quarantine area

[0024] 108,1100: Gate dielectric layer

[0025] 110: Gate

[0026] 112D: Drain region

[0027] 112S: Source region

[0028] 200:Method

[0029] 202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232: Steps

[0030] 406: pad oxide layer

[0031] 408: pad nitride layer

[0032] 410: Patterned mask

[0033] 411: Groove

[0034] 600, 600A, 600B, 600C: Virtual gate structure

[0035] 602: dummy gate dielectric layer

[0036] 604: dummy gate

[0037] 606: Mask

[0038] 700: lightly doped drain region

[0039] 702: first gate spacer

[0040] 702 / 704: Gate spacer

[0041] 704: second gate spacer

[0042] 704SU upper side wall

[0043] 800: Source / drain region

[0044] 900: interlayer dielectric layer

[0045] 902: Contact etch stop layer

[0046] 904: dielectric layer

[0047] 1000, 1000A, 1000B, 1000C: Gate trench

[0048] 1000L: lower groove

[0049] 1000U: Upper groove

[0050] 1001: Interface

[0051] 1100A: Part 1

[0052] 1100B: Part 2

[0053] 1102,2100,2102: work function layer

[0054] 1104: Covering layer

[0055] 1106: Adhesive layer

[0056] 1120: Area

[0057] 1520, 1520A, 1520B, 1520C, 1520D, 1702: Metal gate

[0058] 1600: Metal Structure

[0059] 1700: Wet etching solution

[0060] 1800: Dielectric Materials

[0061] 1900: Gate contact

[0062] 1902: Barrier

[0063] 1904:Seed layer

[0064] 1906: Filler Metal Layer

[0065] 2101,2201: dividing line

[0066] 2200:Metal filling layer

[0067] 2202: Dielectric filling layer DETAILED DESCRIPTION

[0068] The following detailed description is accompanied by accompanying drawings to facilitate an understanding of various aspects of the present invention. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity.

[0069] The following provides different embodiments or examples for implementing different structures of the embodiments of the present invention. The specific components and arrangements are provided to simplify the present disclosure and are not intended to limit the present invention. For example, a description of a first component being formed on a second component includes the two being in direct contact, or the two being separated by additional components rather than in direct contact. In addition, the same reference numerals may be repeatedly used in various embodiments of the present invention for simplicity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0070] In addition, spatially relative terms such as "below," "beneath," "lower side," "above," "upper side," or similar terms may be used to simplify the description of an element relative to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or at other angles, so directional terms are only used to describe the orientation shown in the diagram. Elements with the same reference number in the drawings may be composed of the same materials unless otherwise specified.

[0071] The terms "about" and "substantially" refer to a given value that varies within 5% (eg, a value ±1%, ±2%, ±3%, ±4%, or ±5%).

[0072] An embodiment of the present invention relates to a method for forming a fin field effect transistor device, and more particularly to a method for forming a replacement gate of a fin field effect transistor device. In some embodiments, a dummy gate structure is formed on the fin. A first gate spacer is formed around the dummy gate structure, and a second gate spacer is formed around the first gate spacer. After forming an interlayer dielectric layer around the second gate spacer, the dummy gate structure is removed. The upper portion of the first gate spacer is then removed, and the lower portion of the first trench is retained. After removing the upper portion of the first gate spacer, a gate trench is formed in the interlayer dielectric layer. The gate trench has a lower trench between the lower portions of the first gate spacer, and an upper trench on the lower trench, and the upper trench is wider than the lower trench. A gate dielectric layer, one or more work function layers, a cap layer formed as appropriate, and an adhesion layer are then sequentially formed in the gate trench. The adhesion layer is then selectively removed from the upper trench using a first wet etching process, the cap layer (if formed) that may be formed is selectively removed from the upper trench using a second wet etching process, and the work function layer is selectively removed from the upper trench using a third wet etching process. After the third wet etching process, the gate dielectric layer still extends along the trench. In addition, a portion of the gate dielectric layer, a retained portion of the work function layer, a retained portion of the cap layer, and a retained portion of the adhesion layer are located in the lower trench. The retained portions of the work function layer, the cap layer, and the adhesion layer may have a recessed upper surface that is lower than the interface between the upper trench and the lower trench. A gate is then formed in the trench to contact the recessed upper surface of the work function layer, the cap layer, and the adhesion layer. The gate may cover a portion of the gate dielectric layer in the lower trench, as well as the retained portions of the work function layer, the cap layer, and the adhesion layer in the lower trench. A fourth wet etching process is then performed to remove the gate dielectric layer not covered by the gate, while the gate remains substantially intact. In some embodiments, the work function layer, the capping layer, and the remaining portion of the adhesion layer may be collectively regarded as a metal gate.

[0073] The metal gates formed on the fins using the above method have a larger distance (e.g., spacing) between each other, thereby reducing metal gate leakage current in advanced process nodes. The multiple selective etching processes used in the above method can accurately control the end point of the etching process, avoid unwanted metal material from adhering to the gate spacer when forming the gate, and avoid the loading effect when etching back the various layers of the metal gate. In this way, the gate height of the metal gate can be precisely controlled. In addition, the critical dimensions of the metal gate and the sidewall profiles of the interlayer dielectric layer and the mask layer above can be maintained.

[0074] Figure 1Figure 1 is a perspective view of a fin field-effect transistor device 100 in various embodiments. The fin field-effect transistor device 100 includes a substrate 102 and a fin 104 that protrudes above the substrate 102. An isolation region 106 is formed on both sides of the fin 104, with the fin 104 protruding above the isolation region 106. A gate dielectric layer 108 is formed along the upper surface and sidewalls of the fin 104, and a gate 110 is located on the gate dielectric layer 108. A source region 112S and a drain region 112D are located in the fin 104 and on either side of the gate dielectric layer 108 and the gate 110. The source region 112S and the drain region 112D extend outward from the gate 110. Figure 1 Several cross-sections are provided for use in the subsequent figures. For example, cross-section BB extends along the longitudinal axis of gate 110 of FinFET device 100. Cross-section AA is perpendicular to cross-section BB and extends along the longitudinal axis of fin 104 and the direction of current flow between source region 112S and drain region 112D. Subsequent figures refer to these cross-sections for clarity.

[0075] Figure 2 Flowchart of method 200 for forming a non-planar transistor device in one or more embodiments of the present invention. For example, at least some steps of method 200 may be used to form a fin field effect transistor device (such as fin field effect transistor device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor, or the like. It is worth noting that method 200 is only used to illustrate and is not intended to limit the present invention. In summary, it should be understood that in Figure 2 Additional steps may be provided before, during, and after the method 200, and some other steps are only briefly described here. In some embodiments, the steps of the method 200 may be combined with Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 and Figure 19 Cross-sectional illustrations of a FinFET device are shown at various stages of fabrication, which are described in detail below.

[0076] In brief, method 200 begins with step 202 of providing a substrate. Method 200 then proceeds to step 204 of forming a fin. Method 200 then proceeds to step 206 of forming an isolation region. Method 200 then proceeds to step 208 of forming a dummy gate structure. The dummy gate structure may extend over the center portion of the fin. Method 200 then proceeds to step 210 of forming a lightly doped drain region and gate spacers. The gate spacers extend along the sidewalls of the dummy gate structure. Method 200 then proceeds to step 212 of growing source / drain regions. Method 200 then proceeds to step 214 of forming an interlayer dielectric layer. Method 200 then proceeds to step 216 of removing the dummy gate structure. Once the dummy gate structure is removed, the center portion of the fin is exposed again. Method 200 then proceeds to step 218 of depositing a gate dielectric layer, a work function layer, a capping layer, and an adhesion layer. Method 200 then proceeds to step 220 of removing a portion of the adhesion layer. Method 200 then proceeds to step 222 of removing a portion of the capping layer. Step 224 of method 200 then removes a portion of the work function layer. Step 226 of method 200 then forms a metal structure. This metal structure is sometimes referred to as a gate. Step 228 of method 200 then removes a portion of the gate dielectric material. Step 230 of method 200 then deposits a dielectric material. Step 232 of method 200 then forms a gate contact.

[0077] As mentioned above, Figures 3 to 19 Each shows a portion of a FinFET device 300 in FIG. Figure 2 Cross-sectional views of various stages of the method 200. The FinFET device 300 and Figure 1 The finFET device 100 shown is substantially similar except that it has multiple gate structures. For example, Figures 3 to 6 The FinFET device 300 is shown along the cross section BB (see Figure 1 ) is a cross-sectional view, and Figures 7 to 19 The FinFET device 300 is shown along the cross section AA (see FIG. Figure 1 ). Figures 3 to 19 The FinFET device 300 is shown, but it should be understood that the FinFET device 300 may include a plurality of other devices such as inductors, fuses, capacitors, coils, or the like, which are not shown. Figures 3 to 19 For the purpose of clarity of the accompanying drawings.

[0078] Figure 3 correspond Figure 2Step 202 of FIG. 2 is a cross-sectional view of a fin field effect transistor device 300 comprising a semiconductor substrate 302 at one of various stages of fabrication. The substrate 302 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., doped with p-type dopants or n-type dopants) or undoped. The substrate 302 may be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer may be provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as multi-layer substrates or compositionally graded substrates may also be used. In some embodiments, the semiconductor material of the substrate 302 may include silicon, germanium, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0079] Figure 4 correspond Figure 2 Step 204 is a cross-sectional view of the FinFET device 300 including the semiconductor fin 404 at one of various stages of fabrication. Figure 4 The embodiment shown (and subsequent figures) has only one fin, but it should be understood that the fin field effect transistor device 300 may include any number of fins, which also fall within the scope of the embodiments of the present invention. In some embodiments, the method of forming the fin 404 is to pattern the substrate 302, such as using photolithography and etching techniques. For example, a mask layer (such as a pad oxide layer 406 and a pad nitride layer 408 above it) can be formed on the substrate 302. The pad oxide layer 406 can be a thin film containing silicon oxide, and its formation method can be a thermal oxidation process. The pad oxide layer 406 can serve as an adhesion layer between the substrate 302 and the pad nitride layer 408 above it. In some embodiments, the composition of the pad nitride layer 408 can be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination of the above. For example, the method of forming the pad nitride layer 408 can be low pressure chemical vapor deposition or plasma assisted chemical vapor deposition.

[0080] The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques deposit a photoresist material (not shown), irradiate (expose) the photoresist material, and develop the photoresist material to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (such as the mask layer in this example) from subsequent process steps such as etching. For example, the photoresist material is used to pattern the pad oxide layer 406 and the pad nitride layer 408 to form a patterned mask 410, as shown in FIG. Figure 4 shown.

[0081] Then, a patterned mask 410 is used to pattern the exposed portion of the substrate 302 to form trenches 411 (or openings), thereby defining fins 404 between adjacent trenches 411. Figure 4 As shown. After forming a plurality of fins, the grooves may be located between adjacent fins. In some embodiments, the method for forming the fins 404 may be etching grooves in the substrate 302, and the etching method may adopt reactive ion etching, neutral beam etching, similar methods, or a combination thereof. The etching may be non-isotropic. In some embodiments, the grooves 411 may be strips parallel to each other (in a top view) and may be closely arranged with each other. In some embodiments, the grooves 411 may be continuous and surround the fins 404.

[0082] The patterning method of the fin 404 can be any suitable method. For example, the fin 404 can be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines photolithography with a self-aligned process, and the pattern spacing produced can be smaller than the pattern spacing obtained using a single direct photolithographic process. For example, one embodiment can form a sacrificial layer on a substrate and pattern the sacrificial layer using a photolithographic process. Using a self-aligned process, spacers can be formed along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or cores can then be used to pattern the fins.

[0083] Figure 5 correspond Figure 2 Step 206 is a cross-sectional view of the fin field effect transistor device 300 including the isolation region 500 at one of various stages of fabrication. The isolation region 500 may be composed of an insulating material that electrically isolates adjacent fins from each other. The insulating material may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition, flowable chemical vapor deposition (e.g., depositing a chemical vapor deposition-based material in a remote plasma system and then hardening the material to convert it into another material such as an oxide), a similar method, or a combination thereof. Other insulating materials and / or other formation processes may also be used. In the embodiment described, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed. A planarization process such as chemical mechanical polishing may remove any excess insulating material and make the upper surface of the isolation region 500 coplanar with the upper surface of the fin 404 (not shown, and the isolation region 500 will be recessed as shown). Figure 5 The planarization process can also remove the patterned mask 410 ( Figure 4 ).

[0084] In some embodiments, the isolation regions 500 include a liner layer, such as a liner oxide (not shown), at the interface between each isolation region 500 and the substrate 302 (or fin 404). In some embodiments, the liner oxide can reduce crystallization defects at the interface between the substrate 302 and the isolation region 500. Similarly, the liner oxide can also be used to reduce crystallization defects at the interface between the fin 404 and the isolation region 500. The liner oxide (e.g., silicon oxide) can be formed by thermally oxidizing a surface layer of the substrate 302, but other suitable methods can also be used to form the liner oxide.

[0085] Then the isolation region 500 is recessed to form a shallow trench isolation region 500, as shown in FIG. Figure 5 As shown. After the isolation region 500 is recessed, the upper portion of the fin 404 can protrude from between adjacent shallow trench isolation regions 500. The individual upper surfaces of the shallow trench isolation regions 500 can be flat surfaces (as shown), raised surfaces, recessed surfaces (such as dishing), or a combination thereof. The upper surface of the shallow trench isolation region 500 can be flat, raised, and / or recessed by suitable etching. The method for recessing the isolation region 500 can be an acceptable etching process, such as an etching process that is selective to the material of the isolation region 500. For example, the isolation region 500 can be recessed by wet etching or dry etching with dilute hydrofluoric acid.

[0086] like Figures 3 to 5 In the illustrated embodiment, one or more fins (such as fin 404) are formed, and the fins can be formed using a variety of different processes. For example, the top of substrate 302 can be replaced with a suitable material, such as an epitaxial material suitable for a desired type of semiconductor device (e.g., n-type or p-type). Substrate 302 with the epitaxial material on top can then be patterned to form fin 404 containing the epitaxial material.

[0087] In another example, a dielectric layer may be formed on the upper surface of the substrate, trenches may be etched through the dielectric layer, homoepitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer to form one or more fins.

[0088] In another example, a dielectric layer can be formed on the upper surface of the substrate, trenches can be etched through the dielectric layer, a heteroepitaxial structure of a material different from the substrate can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer, thereby forming one or more fins.

[0089] In embodiments where epitaxial material or epitaxial structure (e.g., heteroepitaxial structure or homoepitaxial structure) is grown, in-situ doping may be performed while the material or structure is grown to omit a previous or subsequent implantation process. However, in-situ doping and implantation doping may be used in conjunction with each other. In addition, there are advantages to epitaxially growing different materials in the n-type metal oxide semiconductor region and the p-type metal oxide semiconductor region. In various embodiments, the fin 104 may comprise silicon germanium (Si x Ge 1-x , x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, Group III-V semiconductor compounds, Group II-VI semiconductor compounds, or the like. For example, feasible materials for Group III-V semiconductor compounds include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, gallium indium arsenide, aluminum indium arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like.

[0090] Figure 6 correspond Figure 2 Step 208 of FIG. 1 is a cross-sectional view of the FinFET device 300 including a dummy gate structure 600 at one of various fabrication stages. In some embodiments, the dummy gate structure 600 includes a dummy gate dielectric layer 602 and a dummy gate 604. A mask 606 may be formed over the dummy gate structure 600. To form the dummy gate structure 600, a dielectric layer may be formed over the fin 404. For example, the dielectric layer may be silicon oxide, silicon nitride, a multilayer thereof, or the like, and may be formed by deposition or thermal growth.

[0091] A gate layer is formed on the dielectric layer, and a mask layer is formed on the gate layer. The gate layer can be deposited on the dielectric layer and then planarized using methods such as chemical mechanical polishing. A mask layer can be deposited on the gate layer. For example, the gate layer can be composed of polysilicon, but other materials can also be used. For example, the mask layer can be composed of silicon nitride or the like.

[0092] After forming layers such as a dielectric layer, a gate layer, and a mask layer, the mask layer may be patterned using acceptable photolithography and etching techniques to form a mask 606. The pattern of the mask 606 may then be transferred to the gate layer and the dielectric layer using acceptable etching techniques to form a dummy gate 604 and a dummy gate dielectric layer 602 thereunder, respectively. The dummy gate 604 and the dummy gate dielectric layer 602 cover the central portion (e.g., the channel portion) of the fin 404. The length direction of the dummy gate 604 (e.g., the channel portion) is substantially the same as that of the fin 404. Figure 1 The cross section BB) is substantially perpendicular to the length direction of the fin 404 (eg Figure 1 Section AA).

[0093] exist Figure 6In the example of FIG, the dummy gate dielectric layer 602 is formed on the fin 404 (e.g., on the upper surface and sidewalls of the fin 404) and on the shallow trench isolation region 500. In other embodiments, the dummy gate dielectric layer 602 may be formed by thermally oxidizing the material of the fin 404, and thus may be formed on the fin 404 instead of on the shallow trench isolation region 500. It should be understood that these other variations are still included within the scope of the embodiments of the present invention.

[0094] Figures 7 to 19 A cross-sectional view showing the subsequent processing and manufacturing method of the FinFET device 300 is shown, which is taken along Figure 1 The cross section AA is shown (along the longitudinal axis of the fin 404). In short, the dummy gate structures 600A, 600B and 600C are located Figures 7 to 11 For simplicity of description, dummy gate structures 600A, 600B, and 600C may be collectively referred to as dummy gate structure 600. It should be understood that more or less than three dummy gate structures may be formed on fin 404, which also falls within the scope of the embodiments of the present invention.

[0095] Figure 7 correspond Figure 2 Step 210 is a cross-sectional view of a fin field effect transistor device 300 having a plurality of lightly doped drain regions 700 formed in a fin 404 at one of various fabrication stages. The lightly doped drain regions 700 may be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask, such as a photoresist, to cover and protect areas of the fin field effect transistor device 300 from the plasma doping process. The plasma doping process may introduce n-type impurities or p-type impurities into the fin 404 to form lightly doped drain regions 700. For example, p-type impurities such as boron may be implanted into the fin 404 to form lightly doped drain regions 700 for p-type devices. In another example, n-type impurities such as phosphorus may be implanted into the fin 404 to form lightly doped drain regions 700 for n-type devices. In some embodiments, the LDD region 700 is adjacent to one of the channel regions of the FinFET device 300 (e.g., the central portion of the fin 404 covered by one of the dummy gate structures 600 ). Portions of the LDD region 700 may extend below the dummy gate structure 600 and into the channel region of the FinFET device 300 . Figure 7 A non-limiting example of a lightly doped drain region 700 is shown. Other configurations, shapes, and methods of forming the lightly doped drain region 700 are possible and fully within the scope of the embodiments of the present invention. For example, the lightly doped drain region 700 can be formed after forming the gate spacers 702 / 704, as described below. In some embodiments, the lightly doped drain region 700 can be omitted.

[0096] like Figure 7As shown, in some embodiments, after forming the lightly doped drain region 700, a first gate spacer 702 may be formed around the dummy gate structure 600 (e.g., along and in contact with the sidewalls of the dummy gate structure 600), and a second gate spacer 704 may be formed around the first gate spacer 702 (e.g., along and in contact with the sidewalls of the first gate spacer 702). For example, the first gate spacer 702 may be formed on both sidewalls of the dummy gate structure 600. The second gate spacer 704 may be formed on the first gate spacer 702. It should be understood that any number of gate spacers may be formed around the dummy gate structure 600 and still fall within the scope of the embodiments of the present invention.

[0097] The first gate spacer 702 may be a low-k spacer composed of a suitable dielectric material such as silicon oxide, silicon oxycarbonitride, or the like. The second gate spacer 704 may be composed of a nitride such as silicon nitride, silicon oxynitride, silicon carbonitride, or the like, or a combination thereof. The first gate spacer 702 and the second gate spacer 704 may be formed using any suitable deposition method, such as thermal oxidation, chemical vapor deposition, or the like. In various embodiments, the first gate spacer 702 and the second gate spacer 704 may be composed of different materials to improve etching selectivity in subsequent processes. The first gate spacer 702 and the second gate spacer 704 may be collectively referred to as gate spacers 702 / 704.

[0098] Figure 7 The shapes and formation methods of the first gate spacer 702 and the second gate spacer 704 shown in the following figures are for illustrative purposes only and are not intended to limit the present invention. Other shapes and formation methods are also possible. These and other variations are fully within the scope of the present invention.

[0099] Figure 8 correspond Figure 2 , step 212, is a cross-sectional view of a finFET device 300 including a plurality of source / drain regions 800 at one of various stages of fabrication. The source / drain regions 800 can be formed in recesses in the fin 404 adjacent to the dummy gate structure 600. For example, the source / drain regions 800 and the dummy gate structures 600 can be staggered. In other words, a source / drain region 800 is sandwiched between adjacent dummy gate structures 600, and / or a source / drain region 800 is adjacent to the dummy gate structure 600 on only one side. In some embodiments, the recessing method can be an anisotropic etching process using the dummy gate structure 600 as an etch mask, although any other suitable etching process can also be used.

[0100] The source / drain regions 800 may be formed by epitaxially growing semiconductor materials in the recesses using suitable methods such as metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, similar methods, or combinations thereof.

[0101] like Figure 8 As shown, the epitaxial source / drain regions 800 may have surfaces that are raised from the respective surfaces of the fins 404 (e.g., raised higher than the non-recessed portions of the fins 404) and may have crystal planes. In some embodiments, the source / drain regions 800 of adjacent fins may merge to form a continuous epitaxial source / drain region (not shown). In some embodiments, the source / drain regions 800 of adjacent fins are not merged together, but remain separate source / drain regions 800 (not shown). In some embodiments, when the fin field effect transistor device is an n-type fin field effect transistor device, the source / drain regions 800 may include silicon carbide, silicon phosphide, silicon carbon phosphide, or the like. In some embodiments, when the final fin field effect transistor device is a p-type fin field effect transistor, the source / drain regions 800 may include silicon germanium, and the p-type impurity may be boron or indium.

[0102] Dopants may be implanted into the epitaxial source / drain regions 800 to form the source / drain regions 800, followed by an annealing process. The implantation process may include forming and patterning a mask, such as a photoresist, to protect other regions of the fin field effect transistor device 300 from the implantation process. The impurity (e.g., dopant) concentration of the source / drain regions 800 may be approximately 1×10 19 cm -3 to about 1×10 21 cm -3 P-type impurities such as boron or indium may be implanted into the source / drain regions 800 of the p-type transistor. N-type impurities such as phosphorus or arsenic may be implanted into the source / drain regions 800 of the n-type transistor. In some embodiments, in-situ doping may be performed while the epitaxial source / drain regions 800 are being grown.

[0103] Figure 9 correspond Figure 2 Step 214 is a cross-sectional view of the fin field effect transistor device 300 including the interlayer dielectric layer 900 at one of the various fabrication stages. In some embodiments, a contact etch stop layer 902 is formed before forming the interlayer dielectric layer 900. Figure 9 The contact etch stop layer 902 can serve as an etch stop layer in subsequent etching processes and can include suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. It can be formed by suitable methods such as chemical vapor deposition, physical vapor deposition, combinations thereof, or the like.

[0104] An interlayer dielectric layer 900 is then formed on the contact etch stop layer 902 and the dummy gate structures 600 (e.g., dummy gate structures 600A, 600B, and 600C). In some embodiments, the interlayer dielectric layer 900 is composed of a dielectric material such as silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. After forming the interlayer dielectric layer 900, a dielectric layer 904 is formed on the interlayer dielectric layer 900. The dielectric layer 904 can serve as a protective layer to prevent or reduce the loss of the interlayer dielectric layer 900 during subsequent etching processes. The dielectric layer 904 can be composed of a suitable material such as silicon nitride, silicon carbonitride, or the like, and its formation method can be a suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. After forming the dielectric layer 904, a planarization process, such as a chemical mechanical polishing process, may be performed to achieve a flush top surface for the dielectric layer 904. The chemical mechanical polishing process may also remove the mask 606 and the contact etch stop layer 902 on the dummy gate 604. In some embodiments, after the planarization process, the top surface of the dielectric layer 904 may be flush with the top surface of the dummy gate 604.

[0105] A gate-last process (sometimes referred to as a replacement gate process) is then performed to replace the dummy gate 604 and the dummy gate dielectric layer 602 of each dummy gate structure 600 with an active gate (also referred to as a replacement gate or metal gate).

[0106] Figure 10 correspond Figure 2 Step 216 is to remove Figure 9 FIG3 is a cross-sectional view of the fin field effect transistor device 300 at one of various fabrication stages after the dummy gate structures 600A, 600B, and 600C are removed to form gate trenches 1000A, 1000B, and 1000C. The upper portion of the first gate spacer 702 can then be removed to laterally expand the upper portions of the gate trenches 1000A, 1000B, and 1000C, such that each gate trench 1000A, 1000B, and 1000C has an upper trench 1000U and a lower trench 1000L, with the upper trench 1000U being wider than the lower trench 1000L. Details of the method for forming the gate trenches 1000A to 1000C are described below. For simplicity of description, the gate trenches 1000A to 1000C may be collectively referred to as gate trench 1000.

[0107] In some embodiments, to remove the dummy gate structure 600, one or more etching steps may be performed to remove the dummy gate 604 and the dummy gate dielectric layer 602 directly below the dummy gate 604, thereby forming gate trenches 1000 (sometimes referred to as recesses) between respective first gate spacers 702. Each gate trench 1000 exposes the channel region of the fin 404. The dummy gate dielectric layer 602 serves as an etch stop when etching away the dummy gate 604. After removing the dummy gate 604, the dummy gate dielectric layer 602 may then be removed.

[0108] An anisotropic etching process, such as a dry etching process, is then performed to remove the upper portion of the first gate spacer 702. In some embodiments, the etchant used in the anisotropic etching process is selective to the material of the first gate spacer 702 (e.g., has a higher etching rate thereto), recessing the first gate spacer 702 (e.g., removing the upper portion) without substantially attacking the second gate spacer 704 and the dielectric layer 904. After removing the upper portion of the first gate spacer 702, the upper sidewalls 704SU of the second gate spacer 704 are exposed.

[0109] like Figure 10 As shown, after removing the upper portion of the first gate spacer 702, each trench 1000 has an upper trench 1000U and a lower trench 1000L. The lower trench 1000L is located between the remaining lower portions of the first gate spacer 702. The upper trench 1000U is above the lower trench 1000L and is defined by the upper sidewall 704SU of the second gate spacer 704 (e.g., bounded by the upper sidewall 704SU). Figure 10 An interface 1001 between the upper trench 1000U and the lower trench 1000L is shown. The interface 1001 is flush with the upper surface of the remaining lower portion of the first gate spacer 702. Each gate trench 1000 has a wider upper trench 1000U and a narrower lower trench 1000L as indicated by the symbol Y, and thus the gate trenches 1000 can sometimes be considered Y-shaped gate trenches.

[0110] In some embodiments, the width W1 of the upper trench 1000U (e.g., the distance between the upper sidewalls 704SU on both sides) may be between about 20 nm and about 30 nm, and the depth H1 (e.g., the distance between the upper surface of the second gate spacer 704 and the interface 1001) may be between about 20 nm and about 120 nm. The width W2 of the lower trench 1000L (e.g., the distance between the sidewalls of the lower portion of the first gate spacer 702 that remains) may be between about 10 nm and about 20 nm, and the depth H2 (e.g., the distance between the lower surface of the gate trench 1000 and the interface 1001) may be between about 20 nm and about 40 nm. As described in subsequent processes, the metal gate (e.g., Figure 15 The metal gate 1520 of FIG. 1 is formed in the lower trench 1000L. For example, the gate material (such as Figure 16 A metal structure 1600 such as tungsten can be used to fill the lower trench 1000L to form the gate of the metal gate. Therefore, the size of the lower trench 1000L can determine the size of the metal gate and the size of the gate.

[0111] Figure 11 correspond Figure 2 Step 218 is a cross-sectional view of the FinFET device 300 at one of various fabrication stages, including a gate dielectric layer 1100, a work function layer 1102, an optional capping layer 1104, and an adhesion layer 1106. The gate dielectric layer 1100, the work function layer 1102, the optional capping layer 1104, and the adhesion layer 1106 are sequentially formed in the gate trench 1000.

[0112] For example, the gate dielectric layer 1100 is conformally deposited in the gate trench 1000, such as on the upper surface and sidewalls of the fin 404, on the upper surface of the gate spacer 702 / 704, and on the upper surface of the dielectric layer 904. In some embodiments, the gate dielectric layer 1100 comprises silicon oxide, silicon nitride, or a multilayer thereof. In an embodiment, the gate dielectric layer 1100 comprises a high dielectric constant dielectric material. In these embodiments, the dielectric constant of the gate dielectric layer 1100 may be greater than about 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or a combination thereof. The gate dielectric layer 1100 may be formed by molecular beam deposition, atomic layer deposition, plasma assisted chemical vapor deposition, or the like. In one example, the thickness of the gate dielectric layer 1100 may be between about to about In another example, the thickness of the gate dielectric layer 1100 may be between about 5 nm and about 25 nm.

[0113] Then, a work function layer 1102 may be conformally formed on the gate dielectric layer 1100. In some embodiments, the work function layer 1102 may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. Figure 11In the example shown, work function layer 1102 is an n-type work function layer. In this description, a work function layer may be referred to as a work function metal. Exemplary p-type work function metals that may be included in the gate structure for a p-type device include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals that may be included in the gate structure for an n-type device include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type work function materials, or combinations thereof. The work function value is related to the material composition of the work function layer. Therefore, the material of the work function layer can be selected to adjust the work function value to achieve a target threshold voltage of the device to be formed. The work function layer may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other suitable processes. In one example, the thickness of the p-type work function layer may be between about to about and the thickness of the n-type work function layer can be between about to about In another example, the thickness of the p-type work function layer may be between about 5 nm and about 25 nm, and the thickness of the n-type work function layer may be between about 5 nm and about 25 nm.

[0114] Then, a capping layer 1104 may be formed on the work function layer 1102 as appropriate. If the capping layer 1104 is formed, it can protect the underlying work function layer 1102 from oxidation. In some embodiments, the capping layer 1104 is a silicon-containing layer such as a silicon layer, a silicon oxide layer, or a silicon nitride layer, and can be formed by a suitable method such as atomic layer deposition, molecular beam deposition, chemical vapor deposition, or the like. In one example, the thickness of the capping layer 1104 may be between about 100 nm and 100 nm. to about In another example, the thickness of the capping layer 1104 may be between about 5 nm and about 25 nm. In some embodiments, the capping layer 1104 may be omitted.

[0115] Thereafter, an adhesion layer 1106 may be formed on the cap layer 1104 or on the work function layer 1102 (if the cap layer 1104 is omitted). The adhesion layer 1106 may serve as an adhesion layer between the underlying layer (such as the cap layer 1104) and the gate material subsequently formed on the adhesion layer 1106. The adhesion layer 1106 may be composed of a suitable material such as titanium nitride, and may be formed by a suitable deposition method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In one example, the thickness of the adhesion layer 1106 may be between about 5 nm and about 25 nm. Figure 11As shown, the adhesion layer 1106 can fill the remaining portion of the lower trench 1000L, depending on the width W2 of the lower trench 1000L and the thickness of the layers previously formed in the gate trench (such as the work function layer 1102 and the cap layer 1104). In addition, the adhesion layer 1106 can fill the entire gate trench 1000, depending on the width W1 of the upper trench 1000U, the width W2 of the lower trench 1000L, and the thickness of the layers previously formed in the gate trench (such as the work function layer 1102 and the cap layer 1104).

[0116] Figures 12 to 19 The subsequent process steps for forming the metal gate of the FinFET device 300 are shown. Figures 12 to 19 Only a portion of the FinFET device 300 is shown. Specifically, Figures 12 to 19 Display Figure 11 1120 in FIG. 1120. For example, Figure 12 Shown in Figure 11 An adhesive layer 1106 is formed on the region 1120 .

[0117] Figure 13 correspond Figure 2 Step 220 is a cross-sectional view of region 1120 of the fin field effect transistor device 300 at one of various fabrication stages after a portion of the adhesion layer 1106 in region 1120 is removed. In some embodiments, a portion of the adhesion layer 1106 is removed from the upper trench 1000U of the gate trench 1000 using an adhesion layer pullback process. In some embodiments, a wet etching process, such as an adhesion layer pullback process, is performed to selectively remove the adhesion layer 1106 from the upper trench 1000U without attacking (e.g., damaging or removing) underlying layers, such as the capping layer 1104. The wet etching process may terminate at the capping layer 1104. In some embodiments, the wet etching process utilizes a chemical agent including an acid and an oxidizing agent. For example, the chemical agent may be a mixture of hydrogen chloride and hydrogen peroxide, wherein the hydrogen chloride serves as the acid and the hydrogen peroxide serves as the oxidizing agent. In some embodiments, the volume ratio of hydrogen chloride to hydrogen peroxide in the mixture may be between approximately 1:1 and 1:20 for the wet etching process. The wet etching process may be performed at a temperature between about 40° C. and about 70° C. for about 1 minute to about 5 minutes. However, the etching endpoint may also be determined by an endpoint detection process.

[0118] like Figure 13 As shown, after the adhesive layer pull-back process, at least a portion of the capping layer 1104 is exposed in the upper trench 1000U, while the remaining portion of the adhesive layer 1106 still fills the lower trench 1000L.

[0119] Figure 14 correspond Figure 2Step 220 is a cross-sectional view of region 1120 of the fin field effect transistor device 300 at one of multiple manufacturing stages after removing a portion of the cap layer 1104 in region 1120. In some embodiments, a capping process is used to remove a portion of the capping layer 1104 from the upper side trench 1000U. In some embodiments, a wet etching process such as a capping process is performed to remove the capping layer 1104 from the upper side trench 1000U. In some embodiments, a wet etching process is performed to remove the capping layer 1104 from the upper side trench 1000U, which may use a fluorine-containing chemical. For example, the fluorine-containing chemical may be a mixture of hydrofluoric acid and water (such as deionized water). In some embodiments, the volume ratio of hydrofluoric acid to water in the mixture is between about 1:100 and 1:2000 for use in a wet etching process. The temperature of the wet etching process may be between about 20°C and about 40°C and last for about 3 minutes to about 6 minutes. As Figure 14 As shown, after the cap layer penetration process, the work function layer 1102 in the upper trench 1000U is exposed. In some embodiments, the etching selectivity of the fluorine-containing chemical may not be high, so a wet etching process such as the cap layer penetration process is performed in a timed mode. In other words, the timing of the wet etching process can be controlled (for example, the wet etching process is performed for a predetermined time) to remove the cap layer 1104 in the upper trench without substantially attacking the work function layer 1102 and / or the gate dielectric layer 1100.

[0120] like Figure 14 As shown, the capping process can also cause portions of the work function layer 1102, capping layer 1104, and adhesion layer 1106 in the lower trench 1000L to be recessed. Thus, the work function layer 1102, capping layer 1104, and adhesion layer 1106 in the lower trench have curved (e.g., recessed) upper surfaces that are lower than the interface 1001 between the upper trench 1000U and the lower trench 1000L.

[0121] Figure 15 correspond Figure 2Step 224 is a cross-sectional view of region 1120 of the fin field effect transistor device 300 at one of various fabrication stages after a portion of the work function layer 1102 in region 1120 is removed. In some embodiments, a portion of the work function layer 1102 is removed from the upper trench 1000U. In some embodiments, a wet etching process is performed to selectively remove the work function layer 1102 from the upper trench 1000U without attacking the underlying gate dielectric layer 1100. In some embodiments, the chemical used in the wet etching process includes a base and an oxidizing agent. For example, the chemical may be a mixture of ammonium hydroxide and hydrogen peroxide, wherein the ammonium hydroxide serves as the base and the hydrogen peroxide serves as the oxidizing agent. In some embodiments, the volume ratio of ammonium hydroxide to hydrogen peroxide in the mixture may be between about 1:1 and 200:1 for the wet etching process. The temperature of the wet etching process may be between about 40°C and about 70°C and last for about 1 minute to about 5 minutes (or an endpoint detection process may be used to stop the etching).

[0122] like Figure 15 As shown, after the wet etching process, the first portion 1100A of the gate dielectric layer 1100 is exposed in the upper trench 1000U, while the work function layer 1102, the capping layer 1104 and the adhesion layer 1106 cover and contact the second portion 1100B of the gate dielectric layer 1100 in the lower trench 1000L. Figure 15 Also shown is a height H3 between the lowest position (e.g., near the substrate 302) of the curved upper surfaces of the work function layer 1102, cap layer 1104, and adhesion layer 1106 in the lower trench and the interface 1001 between the upper trench 1000U and the lower trench 1000L. In some embodiments, height H3 ranges from approximately 3 nm to approximately 12 nm. In some embodiments, the remaining portions of the various layers in the lower trench 1000L, such as the work function layer 1102, cap layer 1104, and adhesion layer 1106, at least partially form the metal gate 1520. In summary, the distance that the upper surface of the metal gate 1520 is lower than the first gate spacer 702 is height H3.

[0123] Figure 16 correspond Figure 2 Step 226 of FIG. 2 illustrates a cross-sectional view of region 1120 of FinFET device 300 at one of various fabrication stages after forming metal structure 1600 in region 1120. Metal structure 1600 may comprise a suitable metal, such as tungsten, and may be formed by suitable methods such as physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or the like. Besides tungsten, other suitable materials such as copper, gold, cobalt, combinations thereof, multiple layers thereof, alloys thereof, or the like may also be used for metal structure 1600.

[0124] like Figure 16As shown, a metal material, such as tungsten, is deposited in the gate trench 1000, contacting the curved upper surfaces of the work function layer 1102, cap layer 1104, and adhesion layer 1106 (or only adhesion layer 1106) in the lower trench 1000L to form a metal structure 1600. In various embodiments, a portion of the gate dielectric layer 1100 (such as the first portion 1100A, which may include one or more high-k dielectric materials) covers the gate spacers 702 / 704 to prevent the gate spacers 702 / 704 from adhering to the metal material during the formation of the metal structure 1600. This metal material adhering is generally considered a loss of selectivity. Even if there is a small amount of selectivity loss along the gate dielectric layer 1100 in the upper trench 1000U, the wet etching solution that selectively removes the gate dielectric layer 1100 can effectively remove a portion of the gate dielectric layer 1100, while the metal structure 1600 (and the underlying work function layer 1102 and cap layer 1104) remain substantially intact. The wet etching solution will be described in detail below. In addition, when forming the metal structure 1600, the gate dielectric layer 1100 covers the upper surface of the first gate spacer 702, which can also minimize the metal material (so-called antennas) formed on the upper surface of the first gate spacer 702. These antennas degrade the insulating properties of the dielectric material to be filled in the gate trench. Dielectric materials are generally used to electrically insulate the gate contact from adjacent gate contacts. By minimizing the amount of unwanted metal material attached to the metal structure of the gate spacers 702 / 704 , the insulating properties of the dielectric material can be subsequently filled into the gate trench 1000 without degrading the dielectric material, thereby improving the overall performance of the FinFET device 300 (e.g., reducing leakage current).

[0125] Figure 17 correspond Figure 2 In step 228, the gate dielectric layer 1100 (eg, Figure 16 A cross-sectional view of a region 1120 of the FinFET device 300 after the first portion 1100A is shown at one of various stages of fabrication. A wet etching solution 1700 (e.g., Figure 17A wet etching process (marked with an X) removes portions of the gate dielectric layer 1100. In one embodiment, the wet etching solution 1700 selectively removes material from the gate dielectric layer 1100 at a rate greater than that of the metal structure 1600, thereby effectively removing the gate dielectric layer 1100 within the upper trench 1000U. Thus, while the precise composition of the wet etching solution 1700 depends at least in part on the materials selected for the metal structure 1600 and the gate dielectric layer 1100, in one embodiment, the metal structure 1600 comprises tungsten and the gate dielectric layer 1100 comprises one or more high-k dielectric materials, the wet etching solution 1700 may include an etchant and an oxidizer in a solvent. It should be understood that the wet etching solution 1700 and corresponding process conditions, described in detail below, can be used on metal structures 1600 and gate dielectric layers 1100 made of materials other than tungsten and high-k dielectric materials, and this also falls within the scope of the present invention.

[0126] For example, the etchant may be an amine, and its chemical formula may be R—NH 2 , R—NH—R ', NR 1 R 2 R 3 , combinations thereof, or the like, wherein R, R', R 1 、R 2 and R 3 Each of the alkyl, phenyl, or similar functional groups may be used. In other embodiments, the etchant may be an amine such as tetramethylammonium hydroxide, ammonium hydroxide, tetrabutylammonium hydroxide, combinations thereof, or the like. However, any suitable etchant may be used.

[0127] An oxidizing agent may be used in conjunction with the etchant to help control the corrosion potential between the metal structure 1600 and the gate dielectric layer 1100 material. In the aforementioned example where the metal structure 1600 comprises tungsten and the gate dielectric layer 1100 comprises one or more high-k dielectric materials, the oxidizing agent may be a fluorine-based acid such as hydrofluoric acid, fluorinated antimonic acid, or the like. In some embodiments, the oxidizing agent may be a mixture of a fluorine-based acid and one or more other acids (e.g., perchloric acid, chloric acid, hypochlorous acid, chlorous acid, periodic acid, iodic acid, hypoiodous acid, iodous acid, perbromic acid, bromic acid, hypobromous acid, bromous acid, nitric acid, combinations thereof, or the like). However, any suitable oxidizing agent may be used.

[0128] If necessary, a stabilizer may be added to the oxidant to stabilize the oxidant. In one embodiment, the stabilizer may be a chelating agent such as ethylenediaminetetraacetic acid, 1,2-cyclohexane dinitrosotetraacetic acid, histidine, diethylenetriaminepentaacetic acid, combinations thereof, or the like. However, any suitable stabilizer may be used.

[0129] In one embodiment, the etchant, oxidant, and stabilizer are placed in a solvent to mix, process, and uniformly apply the wet etching solution 1700. In one embodiment, the solvent can be an organic solvent such as ethylene glycol, diethylene glycol, 1-(2-hydroxyethyl)-2-pyrrolidone, dimethyl sulfoxide, sulfolane, combinations thereof, or the like. However, any suitable solvent can be used.

[0130] In a specific embodiment, the concentration of the etchant in the solvent may be between about 0.5% by volume and about 15% by volume, such as about 2% by volume. Furthermore, the concentration of the oxidant in the solvent may be between about 3% by volume and about 20% by volume, and the concentration of the stabilizer may be between about 0.1% by volume and about 5% by volume (such as about 1% by volume). The solvent may constitute the remainder of the wet etching solution 1700, and thus its concentration may be between about 5% by volume and 90% by volume, such as about 60% by volume. However, any suitable concentration may be used.

[0131] By using the etchants, oxidants, stabilizers, and solvents described herein, the selectivity of the wet etching solution to the gate dielectric layer 1100 (e.g., a high-k dielectric material) and the metal structure 1600 (e.g., tungsten) can be adjusted. In some embodiments, the selectivity of the wet etching solution 1700 to the gate dielectric layer 1100 (e.g., a high-k dielectric material) and the metal structure 1600 (e.g., tungsten) can be between about 4 and about 9, such as about 5. However, any suitable selectivity can be used.

[0132] The wet etching solution 1700 contacts the gate dielectric layer 1100 (eg, Figure 16 The first portion 1100A is shown with the metal structure 1600. In one embodiment, the wet etching solution 1700 may be applied by immersion, spraying, puddle treatment, a combination thereof, or the like. During the etching process, the temperature of the wet etching solution 1700 is maintained between approximately 25°C and approximately 70°C (e.g., approximately 50°C) for approximately 1 minute to approximately 10 minutes (e.g., approximately 4 minutes). However, any suitable process conditions may be employed.

[0133] At the end of the etching process (e.g., the end of a timed etching process), the wet etching solution 1700 is removed, and portions of the gate dielectric layer 1100 are removed downwardly into the lower trench 1000L. However, the wet etching solution 1700 has a high selectivity for the material of the gate dielectric layer 1100, and the material of the metal structure 1600 can remain substantially intact. Thus, the metal structure 1600 still extends from the lower trench 1000L into the upper trench 1000U. The metal structure 1600 can have a height H4, which can be between the height of the first gate spacer 702 and the height of the second gate spacer 704. For example, the height H4 can be between approximately 5 nm and approximately 25 nm, such as approximately 10 nm. Similarly, the width W3 of the metal structure 1600 can be between approximately 2 nm and approximately 10 nm, such as approximately 4 nm. However, any suitable dimensions can be used.

[0134] By selectively etching the gate dielectric layer 1100 without etching the metal structure 1600, the metal structure 1600 remains at the end of the wet etching process. As a result, the probability of the underlying layers (such as the work function layer 1102, the cap layer 1104, and the adhesion layer 1106) being exposed to the wet etching solution 1700 is lower, and the probability of damaging these underlying layers is also lower. These underlying layers may constitute at least a portion of the metal gate. With the reduced possibility of damage, the probability of defects can be reduced, thereby increasing process reliability. In addition, in some embodiments, the etchant, oxidant, stabilizer, solvent, and parameters used in the etching process can be selected as described herein so that the wet etching solution 1700 selectively etches the gate dielectric layer 1100 without etching the metal structure 1600, the work function layer 1102, the cap layer 1104, and the adhesion layer 1106.

[0135] In some embodiments, the metal structure 1600 forms a gate. Figure 17 As shown, the gate, such as metal structure 1600, contacts (e.g., physically contacts) the metal gate 1520. Specifically, in the metal gate 1520, the retained work function layer 1102 and the retained cap layer 1104 each have a U-shaped cross-section. An adhesion layer 1106 is vertically positioned between the gate, such as metal structure 1600, and the cap layer 1104, and horizontally positioned between the two inner sidewalls of the U-shaped work function layer 1102 and the two inner sidewalls of the U-shaped gate dielectric layer 1100. The gate, such as metal structure 1600, is exposed to a wet etching solution 1700, and the wet etching process etches the second portion 1100B of the gate dielectric layer 1100, while leaving the gate, such as metal structure 1600, substantially intact.

[0136] Figure 18 correspond Figure 2Step 228 is a cross-sectional view of the region 1120 of the fin field effect transistor device 300 containing the dielectric material 1800 at one of various stages of fabrication. The dielectric material 1800, such as silicon oxide, silicon nitride, a low-k dielectric material, or the like, is formed in the gate trench 1000 by a suitable method such as physical vapor deposition, chemical vapor deposition, or the like. In some other embodiments, a semiconductor material such as silicon may be filled into the gate trench 1000, and a gate contact (such as Figure 19 After the gate contact 1900 is formed, the semiconductor material is replaced with dielectric material 1800. For example, after the gate contact is formed, the semiconductor material can be removed by an etching process using an etchant that is selective to the semiconductor material. After the semiconductor material is removed, dielectric material 1800 is formed to fill the space previously occupied by the semiconductor material.

[0137] Figure 19 correspond Figure 2 Step 230 is a cross-sectional view of region 1120 of FinFET device 300 including gate contact 1900 at one of various fabrication stages. Gate contact 1900 is formed in dielectric material 1800 (e.g., extending through dielectric material 1800) to electrically couple to a gate, such as metal structure 1600. In the aforementioned example where dielectric material 1800 is deposited prior to forming gate contact 1900 (also referred to as a contact plug), photolithography and etching are used to form a contact opening in dielectric material 1800 to expose the gate, such as metal structure 1600. Once the contact opening is formed, a barrier layer 1902, a seed layer 1904, and a fill metal layer 1906 are sequentially formed in the contact opening to form gate contact 1900.

[0138] Barrier layer 1902 comprises a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, or the like may also be used. Barrier layer 1902 may be formed using a chemical vapor deposition process such as plasma-assisted chemical vapor deposition. However, other processes such as sputtering, metal-organic chemical vapor deposition, or atomic layer deposition may also be used.

[0139] Seed layer 1904 is formed on barrier layer 1902. Seed layer 1904 may comprise copper, titanium, tantalum, titanium nitride, tantalum nitride, the like, or combinations thereof, and may be deposited by atomic layer deposition, sputtering, physical vapor deposition, or the like. In some embodiments, seed layer 1904 is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers of different materials. For example, seed layer 1904 may comprise a titanium layer and a copper layer on the titanium layer.

[0140] A fill metal layer 1906 is deposited on the seed layer 1904 and fills the remainder of the contact opening. The fill metal layer 1906 may be a metal-containing material such as copper, aluminum, tungsten, or the like, a combination thereof, or multiple layers thereof, and may be formed by electroplating, electroless plating, or other suitable methods. After forming the fill metal layer 1906, a planarization process such as chemical mechanical polishing may be performed to remove the upper surface of the dielectric layer 904 (see FIG. 1 ). Figure 11 ) and the excess portions of the barrier layer 1902, the seed layer 1904, and the fill metal layer 1906 above the upper surface of the second gate spacer 704. Thus, the remaining portions of the barrier layer 1902, the seed layer 1904, and the fill metal layer 1906 may form the gate contact 1900.

[0141] Figure 20 The cross-sectional view of the FinFET device 300 after forming the gate contacts 1900 electrically coupled to the respective metal gates 1702 is shown. As shown, the metal gates 1520A, 1520B, and 1520C formed on the fin 404 replace the dummy gate structures 600A, 600B, and 600C, respectively. Figure 9 ). Metal gates 1520A to 1520C may sometimes be collectively referred to as metal gate 1520. It should be understood that additional processes may be performed to complete the fabrication of the FinFET device 300, such as forming source / drain contacts and forming a metal layer on the dielectric layer 904. For simplicity of description, these structures are not described in detail herein.

[0142] As semiconductor manufacturing processes continue to advance, the distance (e.g., spacing) between adjacent metal gates 1520 is becoming increasingly closer. For advanced process nodes, such as 5nm or smaller technologies, the small spacing between the metal gates 1520 can cause metal gate leakage current, which can reduce device reliability. When forming a gate, such as the metal structure 1600, the gate dielectric layer 1100 can protect the gate spacer 702 / 704 to reduce or eliminate the amount of metal material (gate, such as the metal structure 1600) attached to the gate spacer 702 / 704. In summary, the degradation or damage of the insulating properties of the dielectric material 1800 can be minimized, which helps to increase the reliability of the device.

[0143] exist Figure 20 In the example, the metal gates 1520 have the same structure (e.g., the film schemes in the metal gates are the same). In other embodiments, the metal gates 1520 may have different structures. For example, each metal gate 1520 may have a different work function layer to achieve a different threshold voltage, and / or the metal gates may be formed in different regions of the fin field effect transistor device 300 (e.g., an n-type device region or a p-type device region). Figure 21 shown.

[0144] Figure 21 FIG is a partial cross-sectional view of the fin field effect transistor device 300A. Figure 20 The fin field effect transistor device 300 shown is substantially similar except that the work function layer used for each metal gate is different. Figure 21 Only the portion of the FinFET device 300A adjacent to the metal gates 1520A, 1520B, and 1520C is shown. The metal gates 1520A, 1520B, and 1520C are separated by a separation line 2101, which may include additional structures (see FIG. Figure 20 ) between the metal gates 1520A, 1520B and 1520C, but are omitted in the drawings to simplify the drawings.

[0145] like Figure 21 As shown, the metal gate 1520A and Figure 20 The metal gate 1520A in FIG. 1 may include an n-type work function layer 1102. Figure 21 The metal gate 1520B includes two work function layers. For example, the metal gate 1520B includes a p-type work function layer 2100 that contacts (e.g., physically contacts) the gate dielectric layer 1100 and extends along the gate dielectric layer 1100, and includes an identical n-type work function layer 1102 that contacts (e.g., physically contacts) the p-type work function layer 2100 and a portion of the gate dielectric layer 1100 and extends along the p-type work function layer 2100 and a portion of the gate dielectric layer 1100. It is noteworthy that when the n-type work function layer 1102 of the metal gate 1520A has a U-shaped cross-section, the n-type work function layer 1102 of the metal gate 1520B has a laterally extending portion connected to the end of the U-shaped cross-section because the dual work function layer structure of the metal gate 1520B has less space for the n-type work function layer 1102. Figure 21 The metal gate 1520C and Figure 20 The metal gate 1520B is similar to the metal gate 1520B, the difference lies in the p-type work function layer 2102.

[0146] The present invention provides numerous advantages for forming a fin field effect transistor device having a metal gate 1520 with different film schemes (e.g., different work function layers). The term "film scheme" herein refers to the stacked structure and materials of the metal gate 1520 layers (e.g., gate dielectric layer 1100, n-type work function layer 1102, n-type work function layer 1102 and p-type work function layer 2100, n-type work function layer 1102 and p-type work function layer 2102, cap layer 1104, and adhesion layer 1106). Due to the different film schemes (e.g., different work function layers) of the metal gates in gate trenches 1000A to 1000C, different combinations of layers in the gate trenches have different etching rates, which can cause a loading effect (non-uniformity) when removing the layers in the gate trenches. In other words, the amount of layers removed in the gate trenches varies. This can result in inconsistent gate heights for the metal gates 1520A to 1520C in subsequent passes. In this way, different film configurations of different metal gates 1520A to 1520C can have different heights. The method disclosed herein forms a gate, such as metal structure 1600, on metal gate 1520 to help protect underlying structures before selectively etching the portion of gate dielectric layer 1100 not covered by gate, such as metal structure 1600. In this manner, more material of gate, such as metal structure 1600, remains intact during the selective etching process, helping to prevent unintended overetching and damage to underlying layers. This prevents damage to metal gate 1520 and maintains its critical dimensions.

[0147] Figure 22 FIG is a partial cross-sectional view of the FinFET device 300B. The FinFET device 300B and Figure 20 The FinFET device 300 shown is substantially similar, but has an additional metal gate 1520D. Figure 22 Only the portion of the FinFET device 300B adjacent to the metal gates 1520A and 1520D is shown. The metal gates 1520A and 1520D are separated by a separation line 2201, wherein the separation line 2201 may include additional structures such as the metal gates 1520B and 1520C (see FIG. Figure 20 ), but are omitted in the drawings to simplify the drawings.

[0148] like Figure 21 As shown, the metal gate 1520A and Figure 20The metal gate 1520A is the same as the metal gate 1520A, and its extension distance can define the channel length L1 of the corresponding transistor. However, the channel length L2 of the transistor defined by the extension distance of the metal gate 1520A is substantially greater than the channel length L1. Transistors with shorter channel lengths (such as transistors with metal gate 1520A) are sometimes considered to be short-channel transistors, while transistors with longer channel lengths (such as transistors with metal gate 1520D) are sometimes considered to be long-channel transistors. In the example of a long-channel transistor, the metal gate 1520D may also include a metal fill layer 2200 (such as tungsten) and a dielectric fill layer 2202 (such as silicon oxide, silicon nitride, a low-k dielectric material, or the like). Due to the longer channel length, each work function layer 1102, cap layer 1104, and adhesion layer 1106 of the metal gate 1520D may have a U-shaped cross-section, and the U-shaped metal fill layer 2200 may contact (e.g., physically contact) the adhesion layer 1106. Furthermore, the metal gate 1520D may include additional gates, such as metal structures 1600. Each gate, such as metal structures 1600, is electrically coupled to one of the ends of the combination of the U-shaped work function layer 1102, the cap layer 1104, the adhesion layer 1106, and the U-shaped metal fill layer 2200. In summary, one or more gate contacts 1900 may be formed to couple the gates, such as metal structures 1600.

[0149] In one embodiment of the present invention, a method for manufacturing a semiconductor device is disclosed. The method includes forming a gate trench on a semiconductor fin. The gate trench includes an upper portion surrounded by a plurality of first gate spacers, and a lower portion surrounded by a plurality of second gate spacers and the first gate spacer. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is located on a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate on the metal gate in the lower portion of the gate trench, with a second portion of the gate dielectric layer maintaining coverage of the sidewalls of the first gate spacer and the upper surface of the second gate spacer. The method includes removing the second portion of the gate dielectric layer, while the gate remains substantially intact.

[0150] In some embodiments, forming a gate trench on the semiconductor fin includes removing a dummy gate structure across a central portion of the semiconductor fin.

[0151] In some embodiments, the metallic material includes tungsten.

[0152] In some embodiments, removing the second portion of the gate dielectric layer includes removing the second portion of the gate dielectric layer with a wet etching solution, and the wet etching solution removes material of the gate dielectric layer at a rate greater than a rate of removing the metal material.

[0153] In some embodiments, the wet etching solution includes an etchant, an oxidant, and a stabilizer.

[0154] In some embodiments, the etchant is a fluoride-based acid, the oxidizer is perchloric acid, and the stabilizer is ethylenediaminetetraacetic acid.

[0155] In some embodiments, the etchant concentration in the solvent is between about 0.5% and about 15%, the oxidant concentration in the solvent is between about 3% and about 20%, and the stabilizer concentration in the solvent is between about 0.1% and about 5%.

[0156] In some embodiments, the gate dielectric layer includes one or more high-k dielectric materials.

[0157] In some embodiments, the metal gate further includes: one or more work function layers; an optional capping layer; and an adhesion layer.

[0158] In some embodiments, the step of forming a metal gate in the lower portion of the gate trench includes: removing a portion of the adhesion layer in the upper portion of the gate trench; removing a portion of the capping layer formed optionally in the upper portion of the gate trench; and removing a portion of one or more work function layers in the upper portion of the gate trench.

[0159] In another embodiment of the present invention, a method for manufacturing a semiconductor device is disclosed. The method includes removing a dummy gate structure covering a portion of a semiconductor fin. The method includes forming a metal gate on the portion of the semiconductor fin, wherein the metal gate is located on a first portion of a gate dielectric layer. The method includes depositing a metal material to form a gate contacting the metal gate and exposing a second portion of the gate dielectric layer. The method includes etching the second portion of the gate dielectric layer, exposing the gate during the etching. The gate remains substantially intact.

[0160] In some embodiments, the metal material includes tungsten, and the gate dielectric layer includes at least one high-k dielectric material.

[0161] In some embodiments, etching the second portion of the gate dielectric layer includes exposing the second portion of the gate dielectric layer and the gate to a wet etching solution configured to etch the material of the gate dielectric layer at a rate greater than that of the metal material.

[0162] In some embodiments, the wet etching solution includes an etchant, an oxidant, and a stabilizer.

[0163] In some embodiments, the etchant is a fluoride-based acid, the oxidizer is perchloric acid, and the stabilizer is ethylenediaminetetraacetic acid.

[0164] In some embodiments, the etchant concentration in the solvent is between about 0.5% and about 15%, the oxidant concentration in the solvent is between about 3% and about 20%, and the stabilizer concentration in the solvent is between about 0.1% and about 5%.

[0165] In some embodiments, the metal gate further includes: one or more work function layers; an optional capping layer; and an adhesion layer.

[0166] In some embodiments, the step of forming a metal gate in the lower portion of the gate trench includes: removing a portion of the adhesion layer in the upper portion of the gate trench; removing a portion of the capping layer formed optionally in the upper portion of the gate trench; and removing a portion of one or more work function layers in the upper portion of the gate trench.

[0167] In another embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a first spacer located on the semiconductor fin. The semiconductor device includes a second spacer located on the semiconductor fin and extending further from the semiconductor fin than the first spacer. The semiconductor device includes a metal gate located on the semiconductor fin and sandwiched between the first spacers, which are further sandwiched between the second spacers. The semiconductor device includes a gate contacting an upper surface of the metal gate, wherein the gate does not extend over the first spacer or the second spacer.

[0168] In some embodiments, the gate comprises tungsten.

[0169] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention may be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a gate trench on a semiconductor fin, the gate trench including an upper portion surrounded by a plurality of first gate spacers and a lower portion surrounded by a plurality of second gate spacers and a plurality of the first gate spacers; forming a metal gate in the lower portion of the gate trench, wherein the metal gate is located on a first portion of a gate dielectric layer; Depositing a metal material in the gate trench to form a first gate and a second gate on the metal gate in the lower portion of the gate trench, with a second portion of the gate dielectric layer maintaining coverage of sidewalls of the first gate spacers and upper surfaces of the second gate spacers; as well as The second portion of the gate dielectric layer is removed while the first gate and the second gate remain intact, wherein the step of removing the second portion of the gate dielectric layer includes removing the second portion of the gate dielectric layer with a wet etching solution, and the wet etching solution removes the material of the gate dielectric layer at a rate greater than the rate at which the metal material is removed, wherein the first gate and the second gate are laterally separated from each other by a metal fill layer of the metal gate.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming the gate trench on the semiconductor fin comprises: A dummy gate structure across a central portion of the semiconductor fin is removed. 3 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the metal material comprises tungsten. 4 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the wet etching solution comprises an etchant, an oxidant and a stabilizer. 5 . The method for manufacturing a semiconductor device according to claim 4 , wherein the etchant is a fluoride-based acid, the oxidant is perchloric acid, and the stabilizer is ethylenediaminetetraacetic acid. 6 . The method for manufacturing a semiconductor device according to claim 5 , wherein the etchant concentration in a solvent is between 0.5% and 15%, the oxidant concentration in the solvent is between 3% and 20%, and the stabilizer concentration in the solvent is between 0.1% and 5%. 7 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the gate dielectric layer comprises one or more high-k dielectric materials.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein the metal gate further comprises: one or more work function layers; a capping layer; as well as An adhesive layer.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein the step of forming the metal gate in the lower portion of the gate trench comprises: removing a portion of the adhesive layer in the upper portion of the gate trench; removing a portion of the capping layer in the upper portion of the gate trench; as well as A portion of the work function layer in the upper portion of the gate trench is removed.

10. A method for manufacturing a semiconductor device, comprising: removing a dummy gate structure covering a portion of a semiconductor fin; forming a metal gate on the portion of the semiconductor fin, wherein the metal gate is located on a first portion of a gate dielectric layer; Depositing a metal material to form a first gate and a second gate contacting the metal gate and exposing a second portion of the gate dielectric layer; and A second portion of the gate dielectric layer is etched to expose the first gate and the second gate during the etching, wherein the first gate and the second gate remain intact, wherein the step of etching the second portion of the gate dielectric layer includes exposing the second portion of the gate dielectric layer and the gate to a wet etching solution, and the wet etching solution is configured to etch the material of the gate dielectric layer at a rate greater than the rate of etching the metal material, wherein the first gate and the second gate are laterally separated from each other by a metal fill layer of the metal gate. 11 . The method for fabricating a semiconductor device as claimed in claim 10 , wherein the metal material comprises tungsten, and the gate dielectric layer comprises at least one high-k dielectric material. 12 . The method for manufacturing a semiconductor device as claimed in claim 10 , wherein the wet etching solution comprises an etchant, an oxidant, and a stabilizer. 13 . The method for manufacturing a semiconductor device according to claim 12 , wherein the etchant is a fluoride-based acid, the oxidant is perchloric acid, and the stabilizer is ethylenediaminetetraacetic acid. 14 . The method for manufacturing a semiconductor device according to claim 13 , wherein a concentration of the etchant in a solvent is between 0.5% and 15%, a concentration of the oxidant in the solvent is between 3% and 20%, and a concentration of the stabilizer in the solvent is between 0.1% and 5%.

15. The method for manufacturing a semiconductor device according to claim 10, wherein the metal gate further comprises: one or more work function layers; a capping layer; as well as An adhesive layer.

16. The method for manufacturing a semiconductor device according to claim 15 , wherein the step of forming the metal gate in the lower portion of the gate trench comprises: removing a portion of the adhesive layer in an upper portion of the gate trench; removing a portion of the capping layer in the upper portion of the gate trench; as well as A portion of the work function layer in the upper portion of the gate trench is removed.

17. A semiconductor device comprising: a semiconductor fin; a plurality of first spacers located on the semiconductor fin; a plurality of second spacers located on the semiconductor fin and extending further from the semiconductor fin than the plurality of first spacers; a metal gate located on the semiconductor fin and sandwiched between a plurality of the first spacers, wherein the plurality of the first spacers are further sandwiched between a plurality of the second spacers, wherein the metal gate is located on a gate dielectric layer; and A first gate and a second gate contact the upper surface of the metal gate, wherein the topmost surface of the gate dielectric layer is below the first gate and the second gate, and the first gate and the second gate are separated from the plurality of first spacers and the plurality of second spacers through the gate dielectric layer, wherein the first gate and the second gate are laterally separated from each other by a metal filling layer of the metal gate. The semiconductor device of claim 17 , wherein the first gate and the second gate comprise tungsten.

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