Semiconductor device and method for manufacturing the same

Abstract

Disclosed are a semiconductor device and a method for fabricating the same. The fabrication method includes dividing an interlayer dielectric layer into a plurality of portions, wherein the portions of the interlayer dielectric layer are separated from each other along a first lateral direction and a second lateral direction and respectively cover a plurality of epitaxial regions. The method includes performing an etching process to expose the plurality of epitaxial regions, wherein the etching process incorporates multiple stages, each stage including a separate etchant. The method also includes forming a plurality of conductive contacts to electrically couple to the plurality of epitaxial regions.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods for fabricating the same, and more particularly to conductive contacts formed in semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, and improvements in their productivity and performance are often needed. As semiconductor device features continue to shrink, the formation of conductive contacts in areas such as the source and drain terminals of transistors presents challenges. This often requires improvements to semiconductor manufacturing processes to improve the methods used to form these contacts. Summary of the Invention

[0003] An embodiment of the present disclosure is a method for fabricating a semiconductor device. The method includes exposing a first portion of an interlayer dielectric layer above a first group of multiple epitaxial regions. The method includes performing a first stage of an etching process to remove an upper portion of the first portion of the interlayer dielectric layer. The method includes performing a second stage of an etching process to remove isolation structures between adjacent epitaxial regions of the first group. The method includes performing a third stage of an etching process to remove a middle portion of the first portion of the interlayer dielectric layer, thereby exposing the first group of epitaxial regions.

[0004] Another embodiment of the present disclosure is a method for fabricating a semiconductor device. The method includes dividing an interlayer dielectric layer into a plurality of portions. The portions of the interlayer dielectric layer are separated from each other along a first lateral direction and a second lateral direction and respectively cover a plurality of epitaxial regions. The method includes performing an etching process to expose the plurality of epitaxial regions, wherein the etching process incorporates multiple stages, each stage including a separate etchant. The method also includes forming a plurality of conductive contacts to electrically couple to the plurality of epitaxial regions.

[0005] Another embodiment of the present disclosure is a semiconductor device. The semiconductor device includes multiple source / drain structures. The semiconductor device includes multiple conductive contacts, each electrically coupled to the multiple source / drain structures. The semiconductor device includes a mesh dielectric structure to separate the conductive contacts, wherein the conductive contacts are separated from each other along a first lateral direction and a second lateral direction, and the first lateral direction and the second lateral direction are perpendicular to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A FIG. 1 is a top view of an integrated circuit in some embodiments.

[0007] Figure 1B In some embodiments, Figure 1A A cross-sectional view of an integrated circuit.

[0008] Figure 1C In some embodiments, Figure 1A Another cross-sectional view of an integrated circuit.

[0009] Figure 1D In some embodiments, Figure 1A Another cross-sectional view of an integrated circuit.

[0010] Figure 2 In some embodiments, the production Figure 1A Flowchart of a method used in an integrated circuit.

[0011] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B ,and Figure 9C In some embodiments, Figure 1A Cross-sectional views of an integrated circuit at various stages of fabrication.

[0012] The description of the accompanying drawings is as follows:

[0013] 100: Integrated Circuits

[0014] 102, 104, 106: Direction

[0015] 110: Substrate

[0016] 112: Active fin structure

[0017] 120: Quarantine

[0018] 130: Non-active fin structure

[0019] 140, 140-1, 140-2: Dielectric structure

[0020] 150: Conductive contacts

[0021] 160: epitaxial area

[0022] 170: Gate structure

[0023] 172: Gate spacer

[0024] 180, 194: Interlayer dielectric layer

[0025] 180-1: Part One

[0026] 180-2: Part 2

[0027] 180-3: Part 3

[0028] 192: Conductive circuit

[0029] 196: Passivation layer

[0030] 200: Method

[0031] 201, 202, 203, 204, 205, 206, 207: Steps

[0032] 210: Isolation Structure

[0033] 220, 230, 240: Patterned layer

[0034] 520: Hard Mask

[0035] 601: Phase 1

[0036] 701: Phase 2

[0037] 801: Phase 3 DETAILED DESCRIPTION

[0038] A detailed description with accompanying drawings facilitates understanding of the embodiments of the present disclosure. The embodiments will be illustrated with accompanying drawings. In the drawings, similar numbers generally refer to identical, functionally similar, and / or structurally similar elements.

[0039] The following content provides different embodiments or examples that can implement different structures of the present disclosure. The following embodiments of specific components and arrangements are used to simplify the content of the present disclosure and are not intended to limit the present disclosure. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple examples of the present disclosure may repeatedly use the same reference numerals for simplicity, but elements with the same reference numerals in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0040] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify descriptions of an element's relative relationship to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or other angles, so directional terms are used only to describe the orientation shown in the diagram.

[0041] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, which utilize a multi-stage etching process to form conductive contacts in a semiconductor device in an integrated circuit. In various embodiments, a dielectric structure having a two-dimensional mesh structure is formed to isolate different gate structures from different groups of source / drain structures. Each stage may have etching selectivity between at least two structures / layers. For example, the multi-stage etching process includes a first stage, which is configured to isotropically etch the interlayer dielectric layer on multiple groups of source / drain structures at a higher rate, and to etch the metal-containing isolation structure separating each group of source / drain structures at a lower rate. The multi-stage etching process is followed by a second stage, which is configured to etch the metal-containing isolation structure and maintain the integrity of the retained interlayer dielectric layer. The multi-stage etching process is followed by a third stage, which is configured to anisotropically etch the retained interlayer dielectric layer. The multi-stage etching process described herein can significantly reduce the loss of hard masks used to define different groups, which is beneficial for increasing the process tolerance for forming conductive contacts.

[0042] Figure 1A FIG2 is a top view of a portion of an integrated circuit 100 at one of various fabrication stages in some embodiments. Integrated circuit 100 is typically a chip having a plurality of individual devices (e.g., transistors, capacitors, resistors, or the like) formed thereon. The techniques described herein can be applied to a variety of different types of semiconductor devices, including planar and three-dimensional devices.

[0043] During the fabrication phase, a plurality of conductive contacts (such as conductive contacts 150) may be formed in the integrated circuit 100. The two-dimensional mesh dielectric structure 140 may electrically isolate the conductive contacts from each other. Each conductive contact may be electrically connected to a set of source / drain structures. Figure 1B 、 Figure 1C ,and Figure 1D In the same manufacturing stage, the integrated circuit 100 is formed along different directions (eg Figure 1A For example, Figure 1B A cross-sectional view along direction 102, Figure 1C A cross-sectional view along direction 104, and Figure 1D A cross-sectional view is taken along direction 106 .

[0044] like Figure 1BAs shown in the cross-sectional view, the integrated circuit 100 includes a substrate 110 and a plurality of active fin structures 112. The substrate 110 can be made of a variety of different structures and materials. For example, the substrate 110 can be a bulk silicon substrate, a silicon-insulator-silicon substrate, a silicon-on-sapphire substrate, or other types of substrates. In addition, the composition of the substrate 110 can be made of a variety of different materials or combinations thereof. The active fin structure 112 includes one or more semiconductor materials and is formed on the substrate 110 (and protrudes from the substrate 110). For example, the composition of the active fin structure 112 can be made of silicon material, other suitable conductive materials, or a combination of the above. In various embodiments, the active fin structure 112 can extend entirely along a first lateral direction (such as directions 104 and 106), and the plurality of gate structures extend along a second lateral direction (such as direction 102) and parallel to the conductive contact 150, as described in detail below. The active fin structure 112 can be used to form transistors in the integrated circuit 100, such as fin field-effect transistors. As such, the active fin structures 112 are configured to conduct current in the respective transistors. These active fin structures are sometimes referred to as conductive channels or vias.

[0045] Integrated circuit 100 also includes isolation region 120. In some embodiments, isolation region 120 is a shallow trench isolation structure. Isolation region 120 can be formed by creating a trench in substrate 110, filling the trench with an insulating material (e.g., a dielectric material such as silicon oxide), and removing excess insulating material using a process such as chemical mechanical polishing. Active fin structures 112 typically have the same or similar size and shape.

[0046] The integrated circuit 100 also includes an inactive fin structure 130. For example, the inactive fin structure 130 may be a dummy fin. The inactive fin structure 130 is different from the conductive active fin structure 112 and therefore does not provide a current path. The inactive fin structure 130 may also provide a structure similar to the active fin structure 112 in the active area of ​​the integrated circuit 100 to reduce stress on the substrate 110. Figure 1B As shown, two active fin structures 112 are formed on a first side of an inactive fin structure 130, and more than two active fin structures 112 are formed on a second side (opposite to the first side) of the inactive fin structure 130. The active fin structures 112 are located on both sides of the inactive fin structure 130 and are parallel to the inactive fin structure 130.

[0047] The non-active fin structure 130 can further provide critical dimension consistency, thereby improving the ease and efficiency of manufacturing the integrated circuit 100, as well as improving the performance of the integrated circuit 100. In some embodiments, the non-active fin structure 130 and the active fin structure 112 can be the same or approximately the same size and shape. However, compared to the active fin structure 112, the non-active fin structure 130 can also be larger, smaller, thicker, thinner, taller, or shorter. The non-active fin structure 130 can be composed of a single film or a composite film, and its composition can be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon carbonitride, hafnium oxide, tantalum nitride, other suitable materials, or combinations thereof. In some embodiments, the width of the non-active fin structure 130 can be 10nm to 20nm, and the distance between the non-active fin structure 130 and the closest active fin structure 112 can also be 10nm to 20nm. However, dimensions outside of these ranges can be implemented.

[0048] The integrated circuit 100 also includes an epitaxial region 160. In various embodiments, the epitaxial region can be configured as a source structure or a drain structure of a corresponding transistor. In summary, the epitaxial region 160 can sometimes be regarded as a source / drain structure. Figure 1B As shown, epitaxial region 160 includes a first epitaxial region formed on active fin structure 112 and a second epitaxial region formed on active fin structure 112, wherein the first epitaxial region and the second epitaxial region are located on either side of the inactive fin structure 130. Epitaxial region 160 may be formed using an epitaxial growth process such as chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, other suitable processes, or combinations thereof. Epitaxial region 160 may be doped with suitable dopants, including n-type or p-type dopants such as arsine, phosphine, diborane, other suitable dopants, or combinations thereof.

[0049] The integrated circuit 100 also includes a conductive contact 150. The conductive contact 150 is electrically coupled to the epitaxial region 160 to input an electronic signal into the epitaxial region 160 or output an electronic signal from the epitaxial region 160. For example, the conductive contact 150 can be electrically coupled to an internal interconnect structure such as the conductive line 192 described below to connect the epitaxial region to a circuit in the integrated circuit 100. In some embodiments, the conductive contact 150 can be a self-aligned contact. The term self-aligned contact as used herein refers to a contact that can be formed without the need for a mask. The use of the dielectric structure 140 and / or the multi-stage etching process described below can help improve the method of forming the conductive contact 150, as described in detail below.

[0050] The integrated circuit 100 also includes an interlayer dielectric layer 180 and a dielectric structure 140. For a particular etchant in various embodiments, the interlayer dielectric layer 180 has a first etch rate, while the dielectric structure 140 has a second etch rate, so that different portions of the dielectric structure 140 can surround the conductive contact 150. For example, when etching the interlayer dielectric layer 180, the dielectric structure 140 can remain substantially intact. In summary, the interlayer dielectric layer 180 and the dielectric structure 140 can be composed of different materials or combinations of materials. In some embodiments, the dielectric structure 140 includes silicon nitride, and the interlayer dielectric layer 180 includes a low-k dielectric material such as silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. However, other materials can also be implemented to form the dielectric structure 140 and the interlayer dielectric layer 180. Due to the etching selectivity between the dielectric structure 140 and the interlayer dielectric layer 180, the use of the dielectric structure 140 may provide one or more advantages such as less hard mask loss, removal of metal oxide on the inactive fin structure 130, and better epitaxial landing control when forming the epitaxial region 160. Other possible advantages will be described in detail below. Figure 1A As shown in the top view of , the dielectric structure 140 may be a two-dimensional mesh structure including a plurality of portions surrounding one of the conductive contacts 150. In other words, the dielectric structure includes a plurality of meshes (or openings) each filled with a different portion of the interlayer dielectric layer 180.

[0051] exist Figures 1B to 1D In the cross-sectional view of FIG, the integrated circuit 100 includes a conductive line 192, an interlayer dielectric layer 194, and a passivation layer 196, which are not shown in FIG. Figure 1A 150 for clarity. These structures can transmit electronic signals to or from the conductive contacts 150, thereby electrically coupling the conductive contacts 150 to other areas of the integrated circuit 100. For example, the conductive line 192 can be a through-hole structure or a plug structure, and its composition can be a conductive material such as copper, aluminum, tungsten, other suitable materials, or a combination thereof. An interlayer dielectric layer 194 is formed adjacent to the conductive line 192 and provides the electrical isolation required for the conductive line 192. The interlayer dielectric layer 194 and the interlayer dielectric layer 180 include similar materials, so the relevant content is not repeated. The passivation layer 196 is typically a chip passivation layer, which can provide an external barrier used by the integrated circuit 100. For example, the passivation layer 196 can be formed by an oxidation process such as a thermal oxidation process, and its composition material can be silicon oxide, nickel, stainless steel, aluminum, other suitable materials, or a combination thereof. It should be understood that the integrated circuit 100 may include additional interconnect layers (not shown) between the interlayer dielectric layer 194 and the passivation layer 196 .

[0052] Figure 1CMultiple gate structures 170 of the integrated circuit 100 are shown. The gate structures 170 can be used as gates for corresponding transistors. Each gate structure 170 can be implemented as a high-k dielectric layer and a metal gate structure. In these embodiments, the stack includes a conductive metal material and a high-k dielectric material. The stack can also include a work function layer, a capping layer, and / or other layers to form a suitable high-k dielectric layer and metal gate structure for the intended application. The high-k dielectric layer and metal gate structure can be formed using a variety of suitable processes, including gate-first or gate-last implementation methods. Figure 1A As shown by the dashed line in FIG, the gate structure 170 is generally parallel (along Figure 1A The gate structure 170 extends parallel to the direction 102 and may be part of a parallel gate stack. However, the gate structure 170 may be implemented in a variety of ways, including polysilicon gate structures and other types of gate structures. The gate structure 170 is typically formed on the active fin structure 112.

[0053] Figure 1C Also shown are a plurality of gate spacers 172. Gate spacers 172 can be formed of a single layer or multiple layers of material, and can include high-k dielectric materials, low-k dielectric layers, or combinations thereof, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon carbonitride, hafnium oxide, tantalum nitride, other suitable materials, or combinations thereof. Gate spacers 172 generally provide electrical isolation for gate structure 170 to prevent leakage current and improve performance.

[0054] Figure 2 2 is a flow chart of a method 200 for fabricating an integrated circuit in some embodiments. For example, at least some steps of the method 200 may be used to form an integrated circuit (such as the integrated circuit 100) containing a plurality of fin field effect transistors, nanosheet transistors, nanowire transistors, vertical transistors, or the like. It is worth noting that the method 200 is only an example and does not limit the embodiments of the present disclosure. In summary, it should be understood that in Figure 2 Additional steps may be provided before, during, and after the method 200, and some other steps are only briefly described herein.

[0055] In some embodiments, the steps of method 200 may be respectively performed by integrated circuit 100 at Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B ,and Figure 9C The cross-sectional views of the various stages of production are shown. Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A ,and Figure 9A The cross-sectional view is taken along direction 102 ( Figure 1A ), Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B ,and Figure 9B The cross-sectional view is taken along direction 104 ( Figure 1A ),and Figure 3C 、 Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C 、 Figure 8C ,and Figure 9C Along direction 106 ( Figure 1A ).

[0056] Step 201 provides a partially formed integrated circuit ( Figures 3A to 3C ).like Figures 3A to 3C As shown, the integrated circuit 100 includes active fin structures 112 separated by shallow trench isolation regions 120, epitaxial regions 160 formed on the active fin structures 112, gate structures 170 surrounded by gate spacers 172, and inactive fin structures 130 located between two adjacent active fin structures 112. In addition, the partially formed integrated circuit 100 may include a dielectric structure 140 formed on the gate structure 170 (e.g., Figure 3B and Figure 3C As shown), an interlayer dielectric layer 180 is formed on the epitaxial region 160 (as shown Figures 3A to 3C ), and an isolation structure 210 is formed on the inactive fin structure 130. In some embodiments, the isolation structure 210 may be formed to isolate adjacent gate structures or gate portions, which will be removed later when forming the conductive contact 150 (see FIG. Figure 1B For example, the isolation structure 210 may include a metal oxide material such as hafnium oxide, aluminum oxide, zirconium oxide, other suitable materials, or combinations thereof.

[0057] Then, a plurality of patternable layers (such as patterned layers 220, 230, and 240) are formed on the integrated circuit 100 to pattern the interlayer dielectric layer 180. The patterned layers 220, 230, and 240 can be a bottom layer, an intermediate layer, and a photoresist, respectively, which can be subjected to an exposure process to generate patterns, and these patterns can be transferred to the interlayer dielectric layer 180 through one or more etching processes, such as Figures 3A to 3C In various embodiments, portions of the interlayer dielectric layer 180 are removed, and then a dielectric structure 140 is filled in to electrically isolate adjacent conductive contacts, which can sometimes be considered an MD structure. In summary, this dielectric structure 140 can sometimes be considered a cut MD.

[0058] like Figure 3A As shown, a first portion 180-1 (indicated by a dotted line) of the interlayer dielectric layer 180 on the side of the epitaxial region 160 is removed. In some embodiments, the extension direction of the first portion 180-1 is parallel to the length direction (such as directions 104 and 106) of the active fin structure 112 and the inactive fin structure 130. Figure 3B For example, a second portion 180-2 (also indicated by a dotted line) of the interlayer dielectric layer 180 on one of the sides of one of the gate structures 170 is removed. In some embodiments, the extension direction of the second portion 180-2 is parallel to the length direction of the gate structure 170 (such as direction 102). Figure 3C For example, a third portion 180 - 3 of the interlayer dielectric layer 180 on one side of the gate structure may be retained. In some embodiments, the extension direction of the third portion 180 - 3 is parallel to the length direction of the gate structure 170 (eg, direction 102 ).

[0059] In one of the various fabrication stages, step 202 forms the integrated circuit 100 including an additional dielectric structure 140 (sometimes referred to as a cut MD) to isolate different portions of the interlayer dielectric layer 180 ( Figures 4A to 4C ).like Figure 4A As shown, a dielectric material such as silicon nitride may be filled into the removed first portion 180-1 to form a dielectric structure 140-1. Figure 4B As shown, a dielectric material such as silicon nitride can be filled into the removed second portion 180-2 to form a dielectric structure 140-2. The dielectric structures 140-1 and 140-2 can conform to the contours and dimensions of the removed first portion 180-1 and the second portion 180-2, respectively. In addition, the dielectric structures 140-1 and 140-2 are made of the same material as the original dielectric structure 140 (formed on the gate structure 170), so the original and newly formed dielectric structures 140 can be considered as an integrally formed structure. In some embodiments, the dielectric structure 140 is formed as a two-dimensional mesh, and a plurality of isolated or cut interlayer dielectric layers 180 are located therein. The pins of this isolated interlayer dielectric layer 180 can be configured to define conductive contacts 150, such as Figure 1A shown.

[0060] In step 203, one of the various fabrication stages, the integrated circuit 100 includes two hard masks 520 ( Figures 5A to 5C In various embodiments, the hard mask 520 may surround Figure 1A The outline of the integrated circuit 100 is shown. In summary, Figures 5A to 5C The hard mask 520 in each cross-sectional view can be considered as a pair of portions on the interlayer dielectric layer 180 and / or dielectric structure 140 and aligned with their respective outer sidewalls. This hard mask can be positioned to surround a group of MD structures that may share similar formation conditions (e.g., similar etching conditions) and / or similar dimensions. In summary, the hard mask 520 can sometimes be considered a GMD hard mask.

[0061] To form the hard mask 520, a multi-layer or single-layer patterning scheme can be used. For example, a mask layer can be formed on the interlayer dielectric layer 180 and the dielectric structure 140. Then, a bottom layer can be formed on the mask layer, and an intermediate layer can be formed on the bottom layer. Then, a photoresist can be formed on the intermediate layer. The mask layer, the bottom layer, and the intermediate layer facilitate the photolithography process using the photoresist. For example, the mask layer can be a hard mask, and its composition can be made of a variety of suitable materials. The composition of the bottom layer can be made of a variety of suitable materials, including materials mainly composed of carbon, oxygen, and hydrogen. The composition of the intermediate layer can also be made of a variety of suitable materials, including materials mainly composed of silicon, oxygen, and nitrogen.

[0062] The pattern of the photoresist layer can be transferred to the intermediate layer, the underlying layer, and the mask layer by patterning the photoresist layer and removing portions of the intermediate layer, the underlying layer, and the mask layer. Removing portions of the intermediate layer, the underlying layer, and the mask layer can be performed using an etching technique, such as plasma etching, reactive ion etching, other suitable processes, or a combination thereof. Etching agents such as carbon tetrafluoride, nitrogen trifluoride, chlorine, or other suitable etching agents can be used.

[0063] In one of the various fabrication stages, step 204 performs a first stage 601 of an etching process on the integrated circuit 100 ( Figures 6A to 6C ).like Figures 6A to 6CAs shown, a portion of the interlayer dielectric layer (e.g., an upper portion) is removed to expose the isolation structure 210 (e.g., a metal-containing isolation structure). In various embodiments, the first stage 601 may include an isotropic dry etching process, wherein the etching chemistry includes hydrofluoric acid, ammonia, other suitable etching chemistries, or a combination thereof. In addition, the etching chemistry used in the first stage 601 has etching selectivity between the interlayer dielectric layer 180 and between the dielectric structure 140 and the hard mask 520. For example, when the etching chemistry is used in the first stage 601, the etching rate of the interlayer dielectric layer 180 is higher than the etching rate of the dielectric structure 140 and the hard mask 520, which facilitates multi-directional isotropic etching in the first stage 601 without significantly losing material of the isolation structure 210 and the hard mask 520. As a result, after step 204, only a small amount or no dielectric material of the interlayer dielectric layer 180 remains on the upper surface of the isolation structure 210.

[0064] In one of the various fabrication stages, step 205 performs a second stage 701 of an etching process on the integrated circuit 100 ( 7A to 7C ).like Figure 7A As shown, the exposed isolation structure 210 ( Figure 6A ). In addition, when removing the isolation structure 210, the second stage 701 can also remove the hard mask 520 at the same time ( Figures 6A to 6C ). In various embodiments, the second stage 701 may include an isotropic dry etching process, wherein each chemical agent may use boron trichloride or other suitable etching compounds. In addition, the etching chemical used in the second stage 701 has etching selectivity between the isolation structure 210 and the hard mask 520, and between the interlayer dielectric layer 180 and the dielectric structure 140. For example, when the etching chemical in the second stage 701 is used, the etching rate of the isolation structure 210 and the hard mask 520 is higher than the etching rate of the interlayer dielectric layer 180 and the dielectric structure 140, which is conducive to multi-directional isotropic etching in the second stage 701 without significantly losing material of the interlayer dielectric layer 180 and the dielectric structure 140. As a result, after step 205, only a small amount (or no) of the isolation structure 210 and the hard mask 520 on the upper surface of the isolation structure 210 and the upper surface of the interlayer dielectric layer 180 and the dielectric structure 140 remain.

[0065] In one of the various fabrication stages, step 206 performs a third stage 801 of an etching process on the integrated circuit 100 ( Figures 8A to 8C ).like Figures 8A to 8CAs shown, a portion of the interlayer dielectric layer 180 (such as the middle portion) is removed to expose the epitaxial region 160. Once the epitaxial region 160 is exposed, a portion of the interlayer dielectric layer 180 (such as the lower portion) may be retained. The lower portion of the interlayer dielectric layer 180 may be located between the epitaxial region 160 and the inactive fin structure 130, between the epitaxial region 160 and the inner sidewall of the dielectric structure 140, or below the epitaxial region 160. In various embodiments, the third stage 801 may include an anisotropic dry etching process, wherein the etching chemical includes a carbon fluoride such as hexafluorobutadiene, oxygen, argon, and other suitable etching compounds. In addition, the etching chemical used in the third stage 801 has an etching selectivity between the interlayer dielectric layer 180 and the dielectric structure 140, the inactive fin structure 130, and the gate spacer 172. For example, when the etching chemistry in the third stage 801 is used, the interlayer dielectric layer 180 can be etched directionally (e.g., vertically) at a higher rate, while the dielectric structure 140, the inactive fin structure 130, and the gate spacer 172 can be etched at a lower rate, thereby maintaining the profiles and dimensions of the dielectric structure 140, the inactive fin structure 130, and the gate spacer 172. As a result, no (or minimal) material is lost from the dielectric structure 140, the inactive fin structure 130, and the gate spacer 172 after step 206.

[0066] In one of the various fabrication stages, the integrated circuit 100 of step 207 includes the conductive contacts 150 (e.g., Figures 8A to 8C In various embodiments, one or more conductive materials may be formed on the exposed epitaxial region 160 to form a conductive contact 150. As described above, the conductive contact 150 physically contacts the epitaxial region to electrically connect the epitaxial region 160 to other structures. Figure 1A As shown, these conductive contacts can be formed separately, such as multiple islands separated (eg, electrically separated) by a mesh dielectric structure 140, and by Figures 9A to 9C In some embodiments, the extension direction of each conductive contact 150 may be parallel to the length direction of the gate structure. In addition, each conductive contact 150 may be coupled to a set of epitaxial regions 160, which may include a pair of merged epitaxial regions separated by an inactive fin structure, such as Figures 9A to 9C It should be understood that each conductive contact can be coupled to any number of epitaxial regions (the epitaxial regions can be combined or separated) and it falls within the scope of the embodiments of the present disclosure.

[0067] The conductive contact 150 may comprise a metal material. The metal material may comprise tungsten. In addition to tungsten, other metal materials such as copper, gold, cobalt, ruthenium, combinations thereof, multilayers thereof, alloys thereof, or the like may also be used to form the conductive contact 150. The conductive contact 150 may be formed using a variety of suitable processes, such as chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, other suitable processes, or combinations thereof. Prior to forming structures such as the conductive trace 192, interlayer dielectric layer 194, and passivation layer 196 described above, the exposed surface of the conductive contact 150 is smoothed using processes such as chemical mechanical polishing.

[0068] While the above description focuses on a three-stage etching process to expose the epitaxial region 160 (and subsequently to form the conductive contacts 150), it should be understood that in some other embodiments, the etching process used to form the epitaxial region 160 may include any number of stages. For example, by forming the two-dimensional mesh dielectric structure 140, different portions of the interlayer dielectric layer 180 covering different groups of epitaxial (source / drain) structures can be isolated, as shown in FIG. Figure 2 Step 202. A two-dimensional hard mask may then be formed around these different portions of the interlayer dielectric layer 180 (see FIG. Figure 2 By etching different portions of the interlayer dielectric layer 180 (e.g., using a single-stage anisotropic dry etching process), metal material can be filled into the etched portions to form conductive contacts. This anisotropic dry etching process can utilize an etching chemistry including a fluorocarbon such as hexafluorobutadiene, oxygen, argon, or other suitable etching compounds.

[0069] As described in detail above, embodiments of the present disclosure provide semiconductor devices and methods for fabricating the same, utilizing a multi-stage etching process to form conductive contacts within semiconductor devices within integrated circuits. The multi-stage etching process allows for the use of additional dielectric regions with higher etch selectivity, resulting in greater accuracy in this application. This can reduce hard mask loss, allow for the removal of metal oxide from inactive fin structures, and achieve a wider process tolerance, among other potential advantages.

[0070] An embodiment of the present disclosure is a method for fabricating a semiconductor device. The method includes exposing a first portion of an interlayer dielectric layer above a first group of multiple epitaxial regions. The method includes performing a first stage of an etching process to remove an upper portion of the first portion of the interlayer dielectric layer. The method includes performing a second stage of an etching process to remove isolation structures between adjacent epitaxial regions of the first group. The method includes performing a third stage of an etching process to remove a middle portion of the first portion of the interlayer dielectric layer, thereby exposing the first group of epitaxial regions.

[0071] In some embodiments, the method further includes forming conductive contacts to electrically couple to the first set of epitaxial regions.

[0072] In some embodiments, the first stage of the etching process includes an isotropic dry etching process, which includes an etching chemical selected from hydrofluoric acid, ammonia, or a combination thereof.

[0073] In some embodiments, the second stage of the etching process includes an isotropic dry etching process including an etching chemistry of boron trichloride.

[0074] In some embodiments, the third stage of the etching process includes an anisotropic dry etching process, wherein the etching chemical includes fluorocarbon, oxygen, argon, or a combination thereof, and the fluorocarbon includes hexafluorobutadiene.

[0075] In some embodiments, performing the first stage of the etching process further includes exposing the isolation structure.

[0076] In some embodiments, the isolation structure is located on the inactive fin structure between adjacent epitaxial regions.

[0077] In some embodiments, the second stage of the etching process further removes the hard mask layer surrounding the plurality of epitaxial regions.

[0078] In some embodiments, the method further includes forming a mesh dielectric structure to separate the plurality of epitaxial regions.

[0079] In some embodiments, the mesh dielectric structure includes a plurality of mesh holes filled with respective portions of the interlayer dielectric layer.

[0080] Another embodiment of the present disclosure is a method for fabricating a semiconductor device. The method includes dividing an interlayer dielectric layer into a plurality of portions. The portions of the interlayer dielectric layer are separated from each other along a first lateral direction and a second lateral direction and respectively cover a plurality of epitaxial regions. The method includes performing an etching process to expose the plurality of epitaxial regions, wherein the etching process incorporates multiple stages, each stage including a separate etchant. The method also includes forming a plurality of conductive contacts to electrically couple to the plurality of epitaxial regions.

[0081] In some embodiments, the first stage includes an isotropic dry etching process, which includes an etching chemical selected from hydrofluoric acid, ammonia, or a combination thereof.

[0082] In some embodiments, the method further includes removing a portion of an upper portion of the interlayer dielectric layer via the first stage.

[0083] In some embodiments, the second phase includes an isotropic dry etching process including an etching chemistry of boron trichloride.

[0084] In some embodiments, the method further comprises removing isolation structures between adjacent epitaxial regions in each of the plurality of epitaxial regions through the second stage.

[0085] In some embodiments, the third stage includes an anisotropic dry etching process, wherein the etching chemical includes fluorocarbon, oxygen, argon, or a combination thereof, and the fluorocarbon includes hexafluorobutadiene.

[0086] In some embodiments, the method further comprises removing, via a third stage, respective middle portions of a portion of the interlayer dielectric layer to expose the plurality of epitaxial regions.

[0087] In some embodiments, the step of dividing the interlayer dielectric layer into a plurality of parts further comprises forming a mesh dielectric structure to separate the plurality of epitaxial regions.

[0088] Another embodiment of the present disclosure is a semiconductor device. The semiconductor device includes multiple source / drain structures. The semiconductor device includes multiple conductive contacts, each electrically coupled to the multiple source / drain structures. The semiconductor device includes a mesh dielectric structure to separate the conductive contacts, wherein the conductive contacts are separated from each other along a first lateral direction and a second lateral direction, and the first lateral direction and the second lateral direction are perpendicular to each other.

[0089] In some embodiments, each conductive contact extends along one of the first lateral direction and the second lateral direction.

[0090] The features of the above-described embodiments are helpful for those skilled in the art to understand the present disclosure. Those skilled in the art will understand that the present disclosure can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also understand that these equivalent substitutions do not depart from the spirit and scope of the present disclosure and may be altered, replaced, or modified without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a dielectric structure adjacent to an interlayer dielectric layer and covering a gate structure; exposing a first portion of the interlayer dielectric layer above a first group of the plurality of epitaxial regions; performing a first stage of an etching process to remove an upper portion of the first portion of the interlayer dielectric layer such that a top surface of the interlayer dielectric layer is recessed from a top surface of the dielectric structure; performing a second stage of an etching process to remove an isolation structure between adjacent epitaxial regions of the first set of epitaxial regions, thereby exposing an inactive fin structure between the adjacent epitaxial regions; as well as A third stage of an etching process is performed to remove a middle portion of the first portion of the interlayer dielectric layer to expose the first set of epitaxial regions, wherein after the third stage of the etching process, a top surface of the first set of epitaxial regions is lower than a top surface of the inactive fin structure.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising: A conductive contact is formed to electrically couple to the first set of epitaxial regions.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first stage of the etching process includes an isotropic dry etching process, which includes an etching chemical such as hydrofluoric acid, ammonia, or a combination thereof.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The second stage of the etching process includes an isotropic dry etching process, which includes an etching chemical including boron trichloride.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The third stage of the etching process includes an anisotropic dry etching process, wherein the etching chemical includes fluorocarbon, oxygen, argon or a combination thereof, and the fluorocarbon includes hexafluorobutadiene.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The first stage of the etching process further includes exposing the isolation structure.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The isolation structure is located on the inactive fin structure.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The second stage of the etching process further includes removing a hard mask layer surrounding the plurality of epitaxial regions.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric structure is a mesh dielectric structure, and the mesh dielectric structure separates the plurality of epitaxial regions.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The mesh dielectric structure includes a plurality of mesh holes filled with respective portions of the interlayer dielectric layer.

11. A method for manufacturing a semiconductor device, comprising: forming a dielectric structure adjacent to an interlayer dielectric layer and covering a gate structure; dividing the interlayer dielectric layer into a plurality of portions, wherein the portions of the interlayer dielectric layer are separated from each other along a first lateral direction and a second lateral direction and respectively cover a plurality of epitaxial regions, wherein an inactive fin structure is located between adjacent epitaxial regions; performing an etching process to expose the plurality of epitaxial regions such that a top surface of the interlayer dielectric layer is recessed from a top surface of the dielectric structure, wherein the etching process combines a plurality of stages, each stage including a respective etchant, and wherein after the etching process, a top surface of the plurality of epitaxial regions is lower than a top surface of the inactive fin structure; as well as A plurality of conductive contacts are formed to be electrically coupled to the plurality of epitaxial regions respectively.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: A first stage of the stages includes an isotropic dry etching process, which includes an etching chemical such as hydrofluoric acid, ammonia, or a combination thereof.

13. The method for manufacturing a semiconductor device according to claim 12, further comprising: A portion of the upper side of the interlayer dielectric layer is removed through the first stage.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: A second stage of the process includes an isotropic dry etching process, which includes an etching chemical including boron trichloride.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising: An isolation structure between adjacent epitaxial regions of each of the plurality of epitaxial regions is removed through the second stage.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: A third stage of the stages includes an anisotropic dry etching process, wherein the etching chemical includes fluorocarbon, oxygen, argon, or a combination thereof, and the fluorocarbon includes hexafluorobutadiene.

17. The method for manufacturing a semiconductor device according to claim 16, further comprising: Part of the respective middle portions of the interlayer dielectric layer are removed through the third stage to expose the plurality of epitaxial regions.

18. The method for manufacturing a semiconductor device according to claim 11, wherein: The dielectric structure is a mesh dielectric structure, and the mesh dielectric structure separates the plurality of epitaxial regions.

19. A semiconductor device comprising: Multiple source / drain structures; an inactive fin structure located between adjacent source / drain structures, wherein top surfaces of the plurality of source / drain structures are lower than the top surface of the inactive fin structure; a plurality of conductive contacts, wherein the conductive contacts are electrically coupled to the plurality of source / drain structures; an interlayer dielectric layer located below the plurality of source / drain structures and the conductive contacts; and A mesh dielectric structure separates the conductive contacts, wherein the conductive contacts are separated from each other along a first lateral direction and a second lateral direction, and the first lateral direction and the second lateral direction are perpendicular to each other, wherein the mesh dielectric structure includes a plurality of meshes, and the meshes fill different portions of the interlayer dielectric layer.

20. The semiconductor device according to claim 19, wherein Each of the conductive contacts extends along one of the first lateral direction and the second lateral direction.

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