A semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device

Abstract

Embodiments of the present invention disclose a semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device. Among them, the semiconductor discharge tube includes: a semiconductor substrate, a plurality of conductive blocks, and two electrodes. In any device unit region of the semiconductor substrate, the first conductive block is electrically connected to the first diffusion region and the fourth diffusion region; the second conductive block is electrically connected to the first diffusion region and the fifth diffusion region; on the shortest current flow path from the third diffusion region to the nearest first short-circuit point through the first diffusion region, it sequentially passes through that part of the first diffusion region in contact with the fourth diffusion region, the second short-circuit point, and that part of the first diffusion region in contact with the fifth diffusion region; the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short-circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short-circuit point. The technical solution provided by the embodiments of the present invention can achieve the characteristics of low turn-on current and high holding current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device. Background Art

[0002] A semiconductor discharge tube (Thyristor Sure Suppresser, abbreviated as TSS), also known as a solid-state discharge tube, is a switching-type overvoltage protection device. The semiconductor discharge tube can be connected in parallel at both ends of the power-receiving equipment. When overvoltages such as lightning strikes and surge interferences occur, the semiconductor discharge tube will conduct to discharge the surge voltage and surge current, thereby protecting the subsequent power-receiving equipment and preventing the power-receiving equipment from being damaged due to high surge voltage.

[0003] The semiconductor discharge tube is made using the thyristor principle and relies on the breakdown current of the PN junction to trigger the device to conduct and discharge, and can pass a large surge current or pulse current. In the prior art, when the semiconductor discharge tube has the characteristics of low breakover current and low holding current, there is a problem of difficult turn-off; when the semiconductor discharge tube has the characteristics of high breakover current and high holding current, there is a problem of high residual voltage. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device to achieve the characteristics of low breakover current and high holding current.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor discharge tube, including:

[0006] A semiconductor substrate of a first conductivity type, the semiconductor substrate including at least one device unit area; in any device unit area, the semiconductor substrate is provided with a first diffusion area and a second diffusion area of a second conductivity type, and a third diffusion area of the first conductivity type, the first diffusion area and the second diffusion area are separated by a body area of the first conductivity type of the semiconductor substrate; the third diffusion area is in contact with both the first diffusion area and the body area of the semiconductor substrate; a fourth diffusion area and a fifth diffusion area of the first conductivity type are provided in the first diffusion area; the third diffusion area, the fourth diffusion area, and the fifth diffusion area are spaced apart, wherein the first conductivity type and the second conductivity type are different;

[0007] A first conductive block correspondingly arranged in any device unit area, the first conductive block being electrically connected to the first diffusion area and the fourth diffusion area;

[0008] A second conductive block correspondingly arranged in any device unit region, the second conductive block being electrically connected to the first diffusion region and the fifth diffusion region; on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short-circuit point, it successively passes through that part of the first diffusion region in contact with the fourth diffusion region, the second short-circuit point, and that part of the first diffusion region in contact with the fifth diffusion region; wherein, the first short-circuit point is the contact part between the first diffusion region and the second conductive block; the second short-circuit point is the contact part between the first diffusion region and the first conductive block; along the direction of the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short-circuit point, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short-circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short-circuit point;

[0009] Two electrodes, in any device unit region, the second conductive block and the second diffusion region are electrically connected to different electrodes.

[0010] Further, in any device unit region, a trench is provided on one side of the semiconductor substrate, the first diffusion region and the trench are on the same side of the semiconductor substrate, and the depth of the trench is greater than the depth of the first diffusion region; the third diffusion region and the fourth diffusion region are located on the first side of the trench; the fifth diffusion region is located on the second side of the trench opposite to the first side; the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region.

[0011] Further, in any device unit region, the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region; the body region extends to the relative region between the fourth diffusion region and the fifth diffusion region.

[0012] Further, in any device unit region, the first diffusion region and the second diffusion region are located on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite to each other along the thickness direction of the semiconductor substrate;

[0013] There are at least two device unit regions, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are on the same side of the semiconductor substrate;

[0014] In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region.

[0015] Further, in any device unit region, a plurality of first short-circuit points are arranged at intervals in the fifth diffusion region;

[0016] The third diffusion region is located at the junction of the first diffusion region and the body region of the semiconductor substrate; the doping concentration of the third diffusion region is greater than that of the body region.

[0017] In any device unit region, the depth of the fourth diffusion region is less than that of the first diffusion region; the depth of the fifth diffusion region is less than that of the first diffusion region.

[0018] In any device unit region, the first conductive block and the second conductive block are arranged at intervals.

[0019] The first conduction type is electron type, and the second conduction type is hole type; or, the first conduction type is hole type, and the second conduction type is electron type.

[0020] In a second aspect, an overvoltage protection device according to an embodiment of the present invention further includes a semiconductor discharge tube provided in any embodiment of the present invention.

[0021] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor discharge tube, including:

[0022] Providing a semiconductor substrate of a first conduction type, the semiconductor substrate including at least one device unit region;

[0023] In any device unit region, forming a first diffusion region and a second diffusion region of a second conduction type on the semiconductor substrate, the first diffusion region and the second diffusion region being separated by a body region of the first conduction type of the semiconductor substrate; wherein, the first conduction type and the second conduction type are different.

[0024] In any device unit region, forming a third diffusion region of a first conduction type on the semiconductor substrate, forming a fourth diffusion region and a fifth diffusion region of the first conduction type in the first diffusion region, the third diffusion region being in contact with both the first diffusion region and the body region of the semiconductor substrate; the third diffusion region, the fourth diffusion region and the fifth diffusion region are arranged at intervals.

[0025] Forming corresponding first and second conductive blocks in any device unit region, the first conductive block being electrically connected to the first diffusion region and the fourth diffusion region; the second conductive block being electrically connected to the first diffusion region and the fifth diffusion region; on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short-circuit point, successively passing through that part of the first diffusion region in contact with the fourth diffusion region, the second short-circuit point, and that part of the first diffusion region in contact with the fifth diffusion region; wherein, the first short-circuit point is the contact part between the first diffusion region and the second conductive block; the second short-circuit point is the contact part between the first diffusion region and the first conductive block; along the direction of the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short-circuit point, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short-circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short-circuit point.

[0026] Electrically connect the second conductive block and the second diffusion region in any device cell region to different electrodes.

[0027] Furthermore, the manufacturing method of the semiconductor discharge tube further includes:

[0028] In any device cell region, form a trench on one side of the semiconductor substrate, wherein the first diffusion region and the trench are on the same side of the semiconductor substrate, and the depth of the trench is greater than the depth of the first diffusion region; the third diffusion region and the fourth diffusion region are located on the first side of the trench; the fifth diffusion region is located on the second side of the trench opposite to the first side; the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region.

[0029] Furthermore, in any device cell region, the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region; the body region extends to the relative region between the fourth diffusion region and the fifth diffusion region.

[0030] Furthermore, in any device cell region, the first diffusion region and the second diffusion region are on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite to each other along the thickness direction of the semiconductor substrate;

[0031] There are at least two device cell regions, and the at least two device cell regions include an adjacent first device cell region and a second device cell region; the first diffusion region of the first device cell region and the second diffusion region of the second device cell region are on the same side of the semiconductor substrate;

[0032] In the adjacent first device cell region and second device cell region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region;

[0033] In any device cell region, a plurality of first short-circuit points are arranged at intervals in the fifth diffusion region;

[0034] The third diffusion region is located at the junction of the first diffusion region and the body region of the semiconductor substrate; the doping concentration of the third diffusion region is greater than the doping concentration of the body region;

[0035] In any device cell region, the depth of the fourth diffusion region is less than the depth of the first diffusion region; the depth of the fifth diffusion region is less than the depth of the first diffusion region;

[0036] In any device cell region, the first conductive block and the second conductive block are arranged at intervals;

[0037] The first conduction type is electron type, and the second conduction type is hole type; or, the first conduction type is hole type, and the second conduction type is electron type.

[0038] In the semiconductor discharge tube in the technical solution of the embodiment of the present invention, a fourth diffusion region is provided between the third diffusion region and the fifth diffusion region in any device unit region. The first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and the second conductive block is electrically connected to the first diffusion region and the fifth diffusion region. On the shortest current flow path from the third diffusion region to the nearest first short circuit point through the first diffusion region, the first diffusion region in contact with the fourth diffusion region, the second short circuit point, and the first diffusion region in contact with the fifth diffusion region are sequentially passed. Along the direction of the shortest current flow path from the third diffusion region to the nearest first short circuit point through the first diffusion region, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short circuit point. The second conductive block and the second diffusion region are electrically connected to different electrodes, so that the turning current of the semiconductor discharge tube is determined by the second diffusion region, the body region, the first diffusion region, and the fourth diffusion region, and the holding current of the semiconductor discharge tube is determined by the second diffusion region, the body region, the first diffusion region, and the fifth diffusion region, so as to achieve the characteristics of low turning current and high holding current. Description of the Drawings

[0039] Figure 1 It is a top view structural schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention;

[0040] Figure 2 It is a cross-sectional structural schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention;

[0041] Figure 3 It is an equivalent circuit diagram of a semiconductor discharge tube provided by an embodiment of the present invention;

[0042] Figure 4 It is a schematic diagram of the volt-ampere characteristic curve of a unidirectional semiconductor discharge tube provided by an embodiment of the present invention;

[0043] Figure 5 It is another top view structural schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention;

[0044] Figure 6 It is another cross-sectional structural schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention;

[0045] Figure 7 For a semiconductor discharge tube provided by an embodiment of the present invention along Figure 5 The cross-sectional structural schematic diagram in the C1C2 direction;

[0046] Figure 8 It is another top view structural schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention;

[0047] Figure 9 Schematic cross-sectional structure diagram of a semiconductor discharge tube along the C1C2 direction provided by an embodiment of the present invention Figure 8 in the

[0048] Figure 10 Another schematic cross-sectional structure diagram of a semiconductor discharge tube provided by an embodiment of the present invention

[0049] Figure 11 Equivalent circuit diagram of another semiconductor discharge tube provided by an embodiment of the present invention

[0050] Figure 12 Schematic diagram of the volt-ampere characteristic curve of a bidirectional semiconductor discharge tube provided by an embodiment of the present invention

[0051] Figure 13 Schematic structure diagram of an overvoltage protection device provided by an embodiment of the present invention

[0052] Figure 14 Flowchart of a manufacturing method of a semiconductor discharge tube provided by an embodiment of the present invention

[0053] Figure 15 Schematic cross-sectional structure diagram of the semiconductor discharge tube corresponding to steps 110 to 150

[0054] Figure 16 Flowchart of another manufacturing method of a semiconductor discharge tube provided by an embodiment of the present invention

[0055] Figure 17 Top view structure diagram of the semiconductor discharge tube corresponding to step 250

[0056] Figure 18 Schematic cross-sectional structure diagram of a semiconductor discharge tube in the prior art Detailed implementation manners

[0057] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, rather than all the structures.

[0058] An embodiment of the present invention provides a semiconductor discharge tube. Figure 1 Top view structure diagram of a semiconductor discharge tube provided by an embodiment of the present invention Figure 2 Schematic cross-sectional structure diagram of a semiconductor discharge tube provided by an embodiment of the present invention. The semiconductor discharge tube 100 includes: a semiconductor substrate 10, a first conductive block 20, a second conductive block 30, and two electrodes.

[0059] Among them, the semiconductor substrate 10 is of a first conduction type. The semiconductor substrate 10 includes at least one device unit region 11; in any device unit region 11, the semiconductor substrate 10 is provided with a first diffusion region 101 and a second diffusion region 102 of a second conduction type, and a third diffusion region 103 of a first conduction type. The first diffusion region 101 and the second diffusion region 102 are separated by a body region 104 of the first conduction type of the semiconductor substrate 10; the third diffusion regions 103 are all in contact with the first diffusion region 101 and the body region 104 of the semiconductor substrate 10; a fourth diffusion region 105 and a fifth diffusion region 106 of the first conduction type are provided in the first diffusion region 101; the third diffusion region 103, the fourth diffusion region 105, and the fifth diffusion region 106 are spaced apart, where the first conduction type and the second conduction type are different. Optionally, the first conduction type is an electron type (N type), and the second conduction type is a hole type (P type); or, the first conduction type is a hole type (P type), and the second conduction type is an electron type (N type). In any device unit region 11, the projection of the fourth diffusion region 105 on the semiconductor substrate 10 is located within the projection of the first diffusion region 101 on the semiconductor substrate 10. In any device unit region 11, the projection of the fifth diffusion region 106 on the semiconductor substrate 10 is located within the projection of the first diffusion region 101 on the semiconductor substrate 10.

[0060] In any device unit region 11, a first conductive block 20 is correspondingly provided. The first conductive block 20 is electrically connected to the first diffusion region 101 and the fourth diffusion region 105. In any device unit region 11, a second conductive block 30 is correspondingly provided. The second conductive block 30 is electrically connected to the first diffusion region 101 and the fifth diffusion region 106; in any device unit region 11, along the shortest current flow path (along the Figure 1 direction of A1A2 in) from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011, it sequentially passes through that part of the first diffusion region 101 in contact with the fourth diffusion region 105 (equivalent to Figure 2 1013 in), the second short-circuit point 1012, and that part of the first diffusion region 101 in contact with the fifth diffusion region 106 (equivalent to Figure 2 1014 in); where the first short-circuit point 1011 is the contact part between the first diffusion region 101 and the second conductive block 30; the second short-circuit point 1012 is the contact part between the first diffusion region 101 and the first conductive block 20; along the direction of the shortest current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011 (the same as Figure 1(wherein the directions of A1 and A2 are the same), the shortest distance D1 from the end of the fourth diffusion region 105 close to the third diffusion region 103 to the second short-circuit point 1012 is greater than the shortest distance D2 from the end of the fifth diffusion region 106 close to the fourth diffusion region 105 to the first short-circuit point 1011. Equivalent to the direction of the shortest current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011, the width D1 of the fourth diffusion region 105 is greater than the width D2 of the fifth diffusion region 106.

[0061] In any device unit region 11, the second conductive block 30 and the second diffusion region 102 are electrically connected to different electrodes. Figure 1 and Figure 2 Exemplarily, the case where the second conductive block 30 is electrically connected to the first electrode 40 and the second diffusion region 102 is electrically connected to the second electrode 50 is drawn.

[0062] Wherein, Figure 2 It can be a schematic cross-sectional structure diagram of the semiconductor discharge tube along Figure 1 the direction of A1A2 in Figure 1 and Figure 2 Exemplarily, the case where the semiconductor substrate 10 includes one device unit region 11 is drawn. Exemplarily, such as Figure 2As shown, taking the first conduction type as electron type (N-type) and the second conduction type as hole type (P-type) as an example, the second diffusion region 102 can be denoted as P1, the first diffusion region 101 can be denoted as P2, the third diffusion region 103 can be denoted as N2, the body region 104 can be denoted as N1, the fourth diffusion region 105 can be denoted as N3, and the fifth diffusion region can be denoted as N4. A positive voltage is applied to the electrode 50 and a negative voltage is applied to the electrode 40. The N1P1 junction is forward-biased and conducting, and the N2P2 junction is reverse-biased. When the voltage between the two electrodes is higher than the breakdown voltage of N2P2, the current passes through the P2 region and reaches the electrode 40. Since the width D1 is greater than the width D2, the voltage drop on the contact portion 1013 between the first diffusion region 101 and the fourth diffusion region 105 is greater than the voltage drop on the contact portion 1014 between the first diffusion region 101 and the fifth diffusion region 106. After the voltage drop on the contact portion 1013 between the first diffusion region 101 and the fourth diffusion region 105 reaches 0.7V in advance, the N3 region is turned on, and the semiconductor discharge tube TSS formed by P1N1P2N3 is turned on. After P1N1P2N3 is turned on, the current will flow through the first conductive block 20 above N3, re-enter the P2 region from the right side of the first conductive block 20, and reach the electrode 40. When the voltage drop on the contact portion 1014 below the N4 region reaches 0.7V, the N4 region is turned on, and the semiconductor discharge tube TSS formed by P1N1P2N4 is turned on. After P1N1P2N4 is turned on, the voltage between the two electrodes is clamped to a little more than 1V, and the current of P1N1P2N3 needs to pass through a resistor to reach the electrode 40, that is, the resistor of the contact portion 1014. There will be a voltage drop on the resistor, so the voltage drop on P1NIP2N3 will be lower than 1V, and this voltage cannot maintain the continuous conduction of P1NIP2N3, so P1N1P2N3 is turned off. Therefore, the turn-on current (i.e., the breakover current) is determined by P1N1P2N3, and the turn-off current (i.e., the holding current) is determined by P1N1P2N4. The technical solution of this embodiment uses the method of amplifying the gate to achieve a small turn-on current and a large turn-off current.

[0063] Figure 3 The equivalent circuit diagram of a semiconductor discharge tube provided by an embodiment of the present invention. Diode 1 corresponds to Figure 2 the PN junction formed by P1N1 in Figure 2 and the semiconductor discharge tube 2 corresponds to Figure 2 the semiconductor discharge tube formed by P1NIP2N3 in Figures 1 to 3 Exemplarily, the case where the semiconductor discharge tube is a unidirectional reverse cut-off type semiconductor discharge tube is drawn. Figure 4 The schematic diagram of the volt-ampere characteristic curve of a unidirectional semiconductor discharge tube provided by an embodiment of the present invention. Among them, the horizontal axis V represents the voltage between the two electrodes of the semiconductor discharge tube, and the vertical axis I represents the current of the semiconductor discharge tube, V RMis the off-state voltage of the semiconductor discharge tube 100, I RM is the leakage current of the semiconductor discharge tube 100, and the off-state voltage V RM represents the highest voltage at which the semiconductor discharge tube 100 is non-conductive. At this voltage, only a very small leakage current I RM exists. V BR is the breakdown voltage of the semiconductor discharge tube 100, which is the voltage when passing through a specified test current and represents the marking voltage at which the semiconductor discharge tube 100 starts to conduct. V BO is the turn-on voltage of the semiconductor discharge tube 100, I BO is the turn-on current of the semiconductor discharge tube 100. When the voltage across the semiconductor discharge tube 100 (for example, when Figure 2 a positive voltage is applied to the electrode 50 and a negative voltage is applied to the electrode 40 in BO ) rises to reach the turn-on voltage V BO (the corresponding current is the turn-on current I PP ), the semiconductor discharge tube 100 is fully conductive, presenting a very small impedance, and the voltage across the semiconductor discharge tube 100 immediately drops to a very low value. I H is the holding current of the semiconductor discharge tube 100, which is the minimum current for the semiconductor discharge tube 100 to continue to maintain the conductive state. Once the current flowing through the semiconductor discharge tube 100 is less than the holding current I H , the semiconductor discharge tube 100 returns to the cut-off state. V F is the reverse cut-off voltage of the semiconductor discharge tube 100. When the reverse voltage across the semiconductor discharge tube 100 (for example, when Figure 2 a negative voltage is applied to the electrode 50 and a positive voltage is applied to the electrode 40 in

[0064] ) exceeds the reverse cut-off voltage, the semiconductor discharge tube 100 will be broken down and damaged. BO ) is determined by P1N1P2N3, and the turn-off current (i.e., the holding current I H ) is determined by P1N1P2N4. By setting a larger D1, a smaller turn-on current I BO can be obtained. By setting a smaller D2, a larger holding current I H can be obtained, so as to achieve the characteristics of a low turn-on current I BO and a high holding current I H , thus solving the problem in the prior art that both the turn-on current I BO and the holding current I H of the semiconductor discharge tube are determined by P1N1P2N3, as shown in Figure 18 Figure 18 ​It is a schematic cross-sectional structure diagram of a semiconductor discharge tube in the prior art. When the width D3 of N3 is set to be relatively large, the breakdown current I BO and the holding current I H are both relatively small, resulting in the problem of difficult turn-off. When the width D3 of N3 is set to be relatively small, the breakdown current I BO and the holding current I H are both relatively large, resulting in the problem of high residual voltage.

[0065] In the semiconductor discharge tube in the technical solution of this embodiment, a fourth diffusion region is arranged between the third diffusion region and the fifth diffusion region in any device unit region. The first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and the second conductive block is electrically connected to the first diffusion region and the fifth diffusion region. On the shortest current flow path from the third diffusion region to the nearest first short-circuit point through the first diffusion region, it sequentially passes through the part of the first diffusion region in contact with the fourth diffusion region, the second short-circuit point, and the part of the first diffusion region in contact with the fifth diffusion region. Along the direction of the shortest current flow path from the third diffusion region to the nearest first short-circuit point through the first diffusion region, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short-circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short-circuit point. The second conductive block and the second diffusion region are electrically connected to different electrodes, so that the breakdown current of the semiconductor discharge tube is determined by the second diffusion region, the body region, the first diffusion region, and the fourth diffusion region, and the holding current of the semiconductor discharge tube is determined by the second diffusion region, the body region, the first diffusion region, and the fifth diffusion region, so as to achieve the characteristics of low breakdown current and high holding current.

[0066] Among them, the semiconductor substrate 110 can be an N-type semiconductor substrate, which can be formed by doping an appropriate amount of pentavalent elements such as arsenic, phosphorus, and antimony in a pure intrinsic semiconductor such as germanium or silicon. The semiconductor substrate 110 can also be a P-type semiconductor substrate, which can be formed by doping an appropriate amount of trivalent elements such as boron, indium, and gallium in a pure intrinsic semiconductor such as germanium or silicon. The N-type diffusion region can be doped with elements such as arsenic, phosphorus, or antimony, and the P-type diffusion region can be doped with elements such as boron, indium, or gallium. The first conductive block 20 can include at least one of the following metal materials: tungsten, copper, aluminum, etc. The second conductive block 30 can include at least one of the following metal materials: tungsten, copper, aluminum, etc. The material of the electrode can include at least one of the following metal materials: copper and aluminum, etc.

[0067] Optionally, on the basis of the above embodiment, Figure 5 It is a schematic top view structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention, Figure 6 It is a schematic cross-sectional structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention, Figure 7 It is a semiconductor discharge tube provided by an embodiment of the present invention along Figure 5Schematic cross-sectional structure diagram in the C1C2 direction. In any device unit region 11, a trench 107 is provided on one side of the semiconductor substrate 10. Among them, the first diffusion region 101 and the trench 107 are on the same side of the semiconductor substrate 10, and the depth of the trench 107 is greater than the depth of the first diffusion region 101; the third diffusion region 103 and the fourth diffusion region 105 are located on the first side of the trench 107; the fifth diffusion region 106 is located on the second side of the trench 107 opposite to the first side; the arrangement direction Y of the third diffusion region 103 and the fourth diffusion region 105 is perpendicular to the arrangement direction X of the fourth diffusion region 105 and the fifth diffusion region 106.

[0068] Among them, Figure 6 It can be a semiconductor discharge tube along Figure 5 Schematic cross-sectional structure diagram in the B1B2 direction. The depth direction of the trench 107 can be parallel to the thickness direction Z of the semiconductor substrate 10. The depth direction of the first diffusion region 101 can be parallel to the thickness direction Z of the semiconductor substrate 10. The trench 107 can penetrate the first diffusion region 101. The trench 107 may not penetrate the body region 104. The bottom of the trench 107 is located in the body region 104. The trench 107 has an isolation effect and can change the shape of the current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011, so that the shortest current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011 extends along Figure 5 the B1B2 direction in. The first direction X and the second direction Y can be perpendicular to the direction Z. Figure 5 The corresponding technical solution, compared with Figure 1 in which the third diffusion region 103, the fourth diffusion region 105 and the fifth diffusion region 106 are arranged in a straight line direction (such as the first direction X), can make the positions of the third diffusion region 103, the fourth diffusion region 105 and the fifth diffusion region 106 more compact, thereby reducing the size of the device.

[0069] Figure 6Exemplarily, the case where the first conduction type is hole type (P type) and the second conduction type is electron type (N type) is drawn. The second diffusion region 102 can be denoted as N1, the first diffusion region 101 can be denoted as N2, the third diffusion region 103 can be denoted as P2, the body region 104 can be denoted as P1, the fourth diffusion region 105 can be denoted as P3, the fifth diffusion region can be denoted as P4, a negative voltage is applied to the electrode 50, and a positive voltage is applied to the electrode 40. The N1P1 junction is forward-biased and conducting, and the N2P2 junction is reverse-biased. When the voltage between the two electrodes is higher than the breakdown voltage of N2P2, the current flows out from the electrode 40, passes through N2P2P1N1, and reaches the electrode 50. Since the width D1 is greater than the width D2, the voltage drop on the contact portion 1013 between the first diffusion region 101 and the fourth diffusion region 105 is greater than the voltage drop on the contact portion 1014 between the first diffusion region 101 and the fifth diffusion region 106. After the voltage drop on the contact portion 1013 between the first diffusion region 101 and the fourth diffusion region 105 reaches 0.7V in advance, the P3 region is turned on, and the semiconductor discharge tube TSS formed by N1P1N2P3 is turned on. The current flows out from the electrode 40, flows into the right side of the first conductive block 20 from the N2 region, flows through the first conductive block 20 above the P3, and reaches the electrode 50 through the semiconductor discharge tube TSS formed by N1P1N2P3. When the voltage drop on the contact portion 1014 below the P4 region reaches 0.7V, the P4 region is turned on, and the semiconductor discharge tube TSS formed by N1P1N2P4 is turned on. After N1P1N2P4 is turned on, the voltage between the two electrodes is clamped to more than 1V, and the current flowing out from the electrode 40 needs to pass through a resistor to reach N1P1N2P3, that is, the resistor of the contact portion 1014. There is a voltage drop on the resistor, so the voltage drop on N1P1N2P3 will be lower than 1V, and this voltage cannot maintain the continuous conduction of N1P1N2P3, so N1P1N2P3 is turned off. Therefore, the turn-on current (i.e., the breakdown current) is determined by N1P1N2P3, and the turn-off current (i.e., the holding current) is determined by N1P1N2P4. The turn-on current (i.e., the breakdown current I BO ) of the semiconductor discharge tube 100 is determined by N1P1N2P3, and the turn-off current (i.e., the holding current I H ) is determined by N1P1N2P4. By setting a larger D1, a smaller breakdown current I BO can be obtained. By setting a smaller D2, a larger holding current I H can be obtained, so as to achieve the characteristics of a low breakdown current I BO and a high holding current I H .

[0070] Optionally, on the basis of the above embodiments, Figure 8 FIG. XX is a top view structural schematic diagram of another semiconductor discharge tube provided by an embodiment of the present invention, Figure 9 FIG. XX is a schematic cross-sectional view of a semiconductor discharge tube provided by an embodiment of the present invention along Figure 8Schematic cross-sectional structure diagram in the C1C2 direction. In any device unit region 11, the arrangement direction Y of the third diffusion region 103 and the fourth diffusion region 105 is perpendicular to the arrangement direction X of the fourth diffusion region 105 and the fifth diffusion region 106; the body region 104 extends to the relative region between the fourth diffusion region 105 and the fifth diffusion region 106.

[0071] Among them, the semiconductor discharge tube is along Figure 8 The schematic cross-sectional structure diagram in the B1B2 direction in is the same as or similar to Figure 6 The same. The body region 104 extends to the relative region between the fourth diffusion region 105 and the fifth diffusion region 106, having an isolation effect, and changing the shape of the current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011, so that the shortest current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest first short-circuit point 1011 extends along Figure 8 the B1B2 direction in. Figure 8 For the corresponding technical solution, compared with Figure 1 in which the third diffusion region 103, the fourth diffusion region 105, and the fifth diffusion region 106 are arranged in a straight line direction (such as the first direction X), the positions of the third diffusion region 103, the fourth diffusion region 105, and the fifth diffusion region 106 can be made more compact, so that the size of the device can be reduced under the condition that the performances of the two solutions are the same.

[0072] Optionally, on the basis of the above embodiments, continue to refer to Figure 2 , in any device unit region 11, the first diffusion region 101 and the second diffusion region 102 are located on opposite sides of the semiconductor substrate 10; the first diffusion region 101 and the second diffusion region 102 are opposite to each other along the thickness direction Z of the semiconductor substrate 10.

[0073] Optionally, in any device unit region 11, the first diffusion region 101 and the second diffusion region 102 are located on the same side of the semiconductor substrate 10. In any device unit region 11, the first diffusion region 101 and the second diffusion region 102 are located on opposite sides of the semiconductor substrate 10. Compared with the solution where the first diffusion region 101 and the second diffusion region 102 are located on the same side of the semiconductor substrate 10, the device size can be reduced under the condition that the performances of the two solutions are the same.

[0074] Optionally, on the basis of the above embodiments, Figure 10 This is a schematic cross-sectional structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention, Figure 11 This is an equivalent circuit diagram of another semiconductor discharge tube provided by an embodiment of the present invention, Figure 12Schematic diagram of the volt-ampere characteristic curve of a bidirectional semiconductor discharge tube provided by an embodiment of the present invention. There are at least two device unit regions 11. The multiple device unit regions 11 can be arranged at intervals.

[0075] Optionally, on the basis of the above embodiment, continue to refer to FIG. 10. At least two device unit regions 11 include an adjacent first device unit region 11-1 and a second device unit region 11-2; the first diffusion region 101 of the first device unit region 11-1 and the second diffusion region 102 of the second device unit region 11-2 are located on the same side of the semiconductor substrate 10.

[0076] Among them, Figure 10 and Figure 11 Exemplarily, the case where the semiconductor discharge tube 100 is a bidirectional semiconductor discharge tube is drawn. As Figure 12 shown, the volt-ampere characteristic curve of the bidirectional semiconductor discharge tube is located in the first quadrant and the third quadrant and is symmetric about the origin. When a positive voltage is applied to the electrode 50, a negative voltage is applied to the electrode 40, and the voltage between the two electrodes is higher than the breakdown voltage V BR of the semiconductor discharge tube 100, one of the device unit regions 11 conducts; when a negative voltage is applied to the electrode 50, a positive voltage is applied to the electrode 40, and the voltage between the two electrodes is higher than the breakdown voltage V BR of the semiconductor discharge tube 100, the other device unit region 11 conducts. The two device unit regions 11 do not conduct simultaneously.

[0077] Optionally, on the basis of the above embodiment, continue to refer to Figure 10 , in the adjacent first device unit region 11-1 and second device unit region 11-2, the first diffusion region 101 and the second diffusion region 102 located on the same side of the semiconductor substrate 10 are connected and communicated as the same diffusion region.

[0078] Among them, as Figure 10 shown, the first diffusion region 101 of the first device unit region 11-1 and the second diffusion region 102 of the second device unit region 11-2 are connected and communicated as the same diffusion region, and the second diffusion region 102 of the first device unit region 11-1 and the first diffusion region 101 of the second device unit region 11-2 are connected and communicated as the same diffusion region.

[0079] Optionally, on the basis of the above embodiment, continue to refer to Figure 5 and Figure 6 , in any one of the device unit regions 11, a plurality of first short-circuit points 1011 are arranged at intervals in the fifth diffusion region 106 to increase the area of the fifth diffusion region 106 and improve the current-carrying capacity of the semiconductor discharge tube 100.

[0080] Among them, in any device unit area 11, a plurality of first short-circuit points 1011 are arranged in an array, and the distance between adjacent first short-circuit points 1011 is equal, that is, the first short-circuit points 1011 in each row are arranged at equal intervals; the first short-circuit points 1011 in each column are arranged at equal intervals.

[0081] The projection of the third diffusion region 103 on the semiconductor substrate 10 can be a rectangle or the like. The projection of the fourth diffusion region 104 on the semiconductor substrate 10 can be a rectangle or the like. The projection of the fifth diffusion region 106 on the semiconductor substrate 10 can be a rectangle or the like. The projection of the first short-circuit point 1011 on the semiconductor substrate 10 can be a circle or the like.

[0082] Optionally, on the basis of the above embodiments, continue to refer to Figure 1 and Figure 2 , the third diffusion region 103 is located at the junction of the first diffusion region 101 and the body region 104 of the semiconductor substrate. Compared with the scheme where the third diffusion region 103 is located inside the first diffusion region 101, the diffusion depth of the third diffusion region 103 can be reduced.

[0083] Optionally, the doping concentration of the third diffusion region 103 is greater than that of the body region 104. The third diffusion region 103 serves as a low breakdown point for adjusting the magnitude of the breakdown voltage V BR .

[0084] Optionally, on the basis of the above embodiments, continue to refer to Figure 2 , in any device unit area 11, the depth of the fourth diffusion region 105 is less than the depth of the first diffusion region 101. The depth direction of the fourth diffusion region 105 is parallel to the thickness direction Z of the semiconductor substrate 10. The depth direction of the first diffusion region 101 is parallel to the thickness direction Z of the semiconductor substrate 10.

[0085] Optionally, on the basis of the above embodiments, continue to refer to Figure 2 , in any device unit area 11, the depth of the fifth diffusion region 106 is less than the depth of the first diffusion region 101. The depth direction of the fifth diffusion region 106 is parallel to the thickness direction Z of the semiconductor substrate 10.

[0086] Optionally, on the basis of the above embodiments, continue to refer to Figure 1 and Figure 2 , in any device unit area 11, the first conductive block 20 and the second conductive block 30 are arranged at intervals. The first conductive block 20 and the second conductive block 30 are not electrically connected. The first conductive block 20 may include a metal material. The second conductive block 30 may include a metal material. The first conductive block 20 and the second conductive block 30 may be formed by patterning the same metal layer.

[0087] Optionally, on the basis of the above embodiments, continue to refer toFigure 10 , the semiconductor discharge tube further includes an insulating layer 60, the insulating layer 60 covers the side of the semiconductor substrate 10 where the first diffusion region 101 is provided, and exposes the first conductive block 20 and the second conductive block 30. The material of the insulating layer 60 may include at least one of the following: silicon oxide, silicon nitride, etc.

[0088] An embodiment of the present invention provides an overvoltage protection device. Figure 13 is a schematic structural diagram of an overvoltage protection device provided by an embodiment of the present invention. The overvoltage protection device includes the semiconductor diode 100 provided by any embodiment of the present invention.

[0089] Among them, as Figure 13 shown, the two output terminals of the power supply 200 are respectively electrically connected to the two input terminals of the circuit to be protected 300, and the two electrodes of the semiconductor discharge tube 100 are respectively electrically connected to the two input terminals of the circuit to be protected 300. The power supply 200 can be an AC power supply or a DC power supply. During normal operation, the semiconductor discharge tube 100 is cut off, and the power supply 200 can supply power to the circuit to be protected 300 normally. When overvoltage such as lightning strike and surge interference occurs at the two output terminals of the power supply 200, the semiconductor discharge tube 100 will conduct to discharge the surge current and surge voltage, avoiding damage to the circuit to be protected by overvoltage.

[0090] The overvoltage protection device provided by the embodiment of the present invention includes the semiconductor discharge tube in the above embodiment. Therefore, the overvoltage protection device provided by the embodiment of the present invention also has the beneficial effects described in the above embodiment, which will not be elaborated here.

[0091] An embodiment of the present invention provides a manufacturing method of a semiconductor discharge tube. Figure 14 is a flowchart of a manufacturing method of a semiconductor discharge tube provided by an embodiment of the present invention. Figure 15 is a schematic cross-sectional structure diagram of the semiconductor discharge tube corresponding to steps 110 to 150. The manufacturing method of the semiconductor discharge tube can be used to manufacture the semiconductor discharge tube provided by any embodiment of the present invention. On the basis of the above embodiment, the manufacturing method of the semiconductor discharge tube specifically includes the following steps:

[0092] Step 110, provide a semiconductor substrate of a first conductivity type, and the semiconductor substrate includes at least one device unit region.

[0093] Among them, Figure 15 exemplarily draw the case where the semiconductor substrate 10 includes one device unit region 11.

[0094] Step 120: In any device unit region, a first diffusion region and a second diffusion region of a second conductivity type are formed on a semiconductor substrate. The first diffusion region and the second diffusion region are separated by a body region of a first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different.

[0095] Among them, the first diffusion region 101 can be formed by processes such as oxidation, photolithography, diffusion process or ion implantation method. The second diffusion region 102 can be formed by processes such as diffusion process or ion implantation method. The N-type diffusion region is doped with elements such as arsenic, phosphorus or antimony, and the P-type diffusion region is doped with elements such as boron, indium or gallium. Optionally, as Figure 15 shown, in any device unit region, the first diffusion region 101 and the second diffusion region 102 are located on opposite sides of the semiconductor substrate 10; the first diffusion region 101 and the second diffusion region 102 are opposite to each other along the thickness direction Z of the semiconductor substrate 10.

[0096] Step 130: In any device unit region, a third diffusion region of a first conductivity type is formed on the semiconductor substrate. The third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate.

[0097] Among them, the third diffusion region 103 can be formed by processes such as oxidation, photolithography, diffusion process or ion implantation method. Optionally, the third diffusion region 1103 is located at the junction of the first diffusion region 101 and the body region 104 of the semiconductor substrate 10. Optionally, the doping concentration of the third diffusion region 103 is greater than that of the body region 104.

[0098] Step 140: In any device unit region, a fourth diffusion region and a fifth diffusion region of a first conductivity type are formed in the first diffusion region. The third diffusion region, the fourth diffusion region and the fifth diffusion region are arranged at intervals.

[0099] Among them, the fourth diffusion region 105 can be formed by processes such as oxidation, photolithography, diffusion process or ion implantation method. The fifth diffusion region 106 can be formed by processes such as oxidation, photolithography, diffusion process or ion implantation method. Optionally, in any device unit region 11, the depth of the fourth diffusion region 105 is less than the depth of the first diffusion region 101. Optionally, in any device unit region 11, the depth of the fifth diffusion region 106 is less than the depth of the first diffusion region 101. Optionally, in any device unit region 1, a plurality of first short-circuit points 1011 arranged at intervals are provided in the fifth diffusion region 106.

[0100] Optionally, based on the above embodiments, in any device unit region 11, the arrangement direction Y of the third diffusion region 103 and the fourth diffusion region 105 is perpendicular to the arrangement direction X of the fourth diffusion region 105 and the fifth diffusion region 106; the body region 104 extends to the relative region between the fourth diffusion region 105 and the fifth diffusion region 106.

[0101] It should be noted that step 140 can be before or after step 130, or the third diffusion region 103, the fourth diffusion region 105, and the fifth diffusion region 106 are formed simultaneously in the same process. The second diffusion region 102 can be formed before or after the third diffusion region 103, the fourth diffusion region 105, and the fifth diffusion region 106 are formed. The formation sequence of multiple diffusion regions can be set as needed, and the embodiments of the present invention do not limit this. Step 150: Form corresponding first conductive blocks and second conductive blocks in any device unit region. The first conductive block is electrically connected to the first diffusion region and the fourth diffusion region; the second conductive block is electrically connected to the first diffusion region and the fifth diffusion region; on the shortest current flow path from the third diffusion region to the nearest first short circuit point through the first diffusion region, it sequentially passes through that part of the first diffusion region in contact with the fourth diffusion region, the second short circuit point, and that part of the first diffusion region in contact with the fifth diffusion region; where the first short circuit point is the contact part between the first diffusion region and the second conductive block; the second short circuit point is the contact part between the first diffusion region and the first conductive block; along the direction of the shortest current flow path from the third diffusion region to the nearest first short circuit point through the first diffusion region, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short circuit point.

[0102] Among them, the first conductive block 20 and the second conductive block 30 can be formed by patterning the same metal layer. In any device unit region 11, the first conductive block 20 and the second conductive block 30 are arranged at intervals.

[0103] Step 160: Electrically connect the second conductive block and the second diffusion region in any device unit region to different electrodes.

[0104] Among them, as Figure 6 shown, the second conductive block 30 can be electrically connected to the electrode 40, and the second diffusion region 102 can be electrically connected to the electrode 50.

[0105] The manufacturing method of the semiconductor discharge tube provided by the embodiments of the present invention can be used to manufacture the semiconductor discharge tube provided by any embodiment of the present invention. Therefore, the manufacturing method of the semiconductor discharge tube provided by the embodiments of the present invention also has the beneficial effects described in the above embodiments, which will not be elaborated here.

[0106] The embodiments of the present invention provide another manufacturing method of a semiconductor discharge tube. Figure 16It is a flowchart of another manufacturing method of a semiconductor discharge tube provided by an embodiment of the present invention. Based on the above embodiment, the method includes:

[0107] Step 210: Provide a semiconductor substrate of a first conductivity type, the semiconductor substrate including at least one device unit region.

[0108] Step 220: In any device unit region, form a first diffusion region and a second diffusion region of a second conductivity type on the semiconductor substrate, the first diffusion region and the second diffusion region being separated by a body region of the first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different.

[0109] Step 230: In any device unit region, form a third diffusion region of the first conductivity type on the semiconductor substrate, the third diffusion region being in contact with both the first diffusion region and the body region of the semiconductor substrate.

[0110] Step 240: In any device unit region, form a fourth diffusion region and a fifth diffusion region of the first conductivity type in the first diffusion region, the third diffusion region, the fourth diffusion region, and the fifth diffusion region being arranged at intervals.

[0111] Step 250: In any device unit region, form a trench on one side of the semiconductor substrate, wherein the first diffusion region and the trench are on the same side of the semiconductor substrate, and the depth of the trench is greater than the depth of the first diffusion region; the third diffusion region and the fourth diffusion region are on the first side of the trench; the fifth diffusion region is on the second side of the trench opposite to the first side; the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region.

[0112] Wherein, the trench 107 can be formed by processes such as photolithography, dry etching, or wet etching. Figure 17 It is a top view structural schematic diagram of the semiconductor discharge tube corresponding to Step 250.

[0113] Step 260: Form corresponding first conductive block and second conductive block in any device unit region. The first conductive block is electrically connected to the first diffusion region and the fourth diffusion region; the second conductive block is electrically connected to the first diffusion region and the fifth diffusion region; on the shortest current flow path from the third diffusion region to the nearest first short-circuit point through the first diffusion region, it sequentially passes through the part of the first diffusion region in contact with the fourth diffusion region, the second short-circuit point, and the part of the first diffusion region in contact with the fifth diffusion region; wherein, the first short-circuit point is the contact part between the first diffusion region and the second conductive block; the second short-circuit point is the contact part between the first diffusion region and the first conductive block; along the direction of the shortest current flow path from the third diffusion region to the nearest first short-circuit point through the first diffusion region, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short-circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short-circuit point.

[0114] Step 270: Electrically connect the second conductive block and the second diffusion region in any device unit region to different electrodes.

[0115] Optionally, based on the above embodiment, there are at least two device unit regions, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are on the same side of the semiconductor substrate.

[0116] Optionally, based on the above embodiment, in the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region.

[0117] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor discharge tube, characterized in that, Comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate including at least one device unit region; In any one of the device unit regions, the semiconductor substrate is provided with a first diffusion region and a second diffusion region of a second conductivity type, and a third diffusion region of a first conductivity type. The first diffusion region and the second diffusion region are separated by a body region of the first conductivity type of the semiconductor substrate. The third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate. A fourth diffusion region and a fifth diffusion region of the first conductivity type are provided in the first diffusion region. The third diffusion region, the fourth diffusion region, and the fifth diffusion region are spaced apart, wherein the first conductivity type and the second conductivity type are different; A first conductive block correspondingly provided in any one of the device unit regions, the first conductive block being electrically connected to the first diffusion region and the fourth diffusion region; A second conductive block correspondingly provided in any one of the device unit regions, the second conductive block being electrically connected to the first diffusion region and the fifth diffusion region. On the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short circuit point, it successively passes through the part of the first diffusion region in contact with the fourth diffusion region, the second short circuit point, and the part of the first diffusion region in contact with the fifth diffusion region. Wherein, the first short circuit point is the contact part of the first diffusion region and the second conductive block; the second short circuit point is the contact part of the first diffusion region and the first conductive block. Along the direction of the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short circuit point, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short circuit point; Two electrodes, in any one of the device unit regions, the second conductive block and the second diffusion region are electrically connected to different electrodes.

2. The semiconductor discharge tube according to claim 1, wherein In any one of the device unit regions, a trench is provided on one side of the semiconductor substrate. The first diffusion region and the trench are on the same side of the semiconductor substrate, and the depth of the trench is greater than the depth of the first diffusion region. The third diffusion region and the fourth diffusion region are located on a first side of the trench. The fifth diffusion region is located on a second side of the trench opposite to the first side. The arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region.

3. The semiconductor discharge tube according to claim 1, wherein In any one of the device unit regions, the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region; the body region extends to the relative region between the fourth diffusion region and the fifth diffusion region.

4. The semiconductor discharge tube according to claim 1, characterized in that, In any one of the device unit regions, the first diffusion region and the second diffusion region are located on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite to each other along the thickness direction of the semiconductor substrate; The device unit regions are at least two, and the at least two device unit regions include a first device unit region and a second device unit region which are arranged adjacent to each other; a first diffusion region of the first device unit region and a second diffusion region of the second device unit region are located on the same side of the semiconductor substrate; In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region located on the same side of the semiconductor substrate are connected to form the same diffusion region.

5. The semiconductor discharge tube according to claim 1, wherein In any one of the device unit regions, a plurality of first short-circuit points arranged at intervals are provided in the fifth diffusion region; The third diffusion region is located at the junction of the first diffusion region and the body region of the semiconductor substrate; the doping concentration of the third diffusion region is greater than that of the body region; In any one of the device unit regions, the depth of the fourth diffusion region is less than the depth of the first diffusion region; the depth of the fifth diffusion region is less than the depth of the first diffusion region; In any one of the device unit regions, the first conductive block and the second conductive block are arranged at intervals; The first conduction type is electron type, and the second conduction type is hole type; or, the first conduction type is hole type, and the second conduction type is electron type.

6. An overvoltage protection device, characterized in that, Including the semiconductor discharge tube according to any one of claims 1-5.

7. A manufacturing method of a semiconductor discharge tube, characterized in that, Including: Providing a semiconductor substrate of a first conduction type, the semiconductor substrate including at least one device unit region; In any one of the device unit regions, a first diffusion region and a second diffusion region of a second conduction type are formed on the semiconductor substrate, and the first diffusion region and the second diffusion region are separated by a body region of the first conduction type of the semiconductor substrate; wherein, the first conduction type and the second conduction type are different; In any one of the device unit regions, a third diffusion region of a first conduction type is formed on the semiconductor substrate, a fourth diffusion region and a fifth diffusion region of the first conduction type are formed in the first diffusion region, and the third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate; the third diffusion region, the fourth diffusion region and the fifth diffusion region are arranged at intervals; In any one of the device unit regions, corresponding first and second conductive blocks are formed. The first conductive block is electrically connected to the first diffusion region and the fourth diffusion region; the second conductive block is electrically connected to the first diffusion region and the fifth diffusion region; on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short - circuit point, the first diffusion region in contact with the fourth diffusion region, the second short - circuit point, and the first diffusion region in contact with the fifth diffusion region are sequentially passed through; wherein, the first short - circuit point is the contact portion between the first diffusion region and the second conductive block; the second short - circuit point is the contact portion between the first diffusion region and the first conductive block; along the direction of the shortest current flow path from the third diffusion region through the first diffusion region to the nearest first short - circuit point, the shortest distance from the end of the fourth diffusion region close to the third diffusion region to the second short - circuit point is greater than the shortest distance from the end of the fifth diffusion region close to the fourth diffusion region to the first short - circuit point; The second conductive block and the second diffusion region in any one of the device unit regions are electrically connected to different electrodes.

8. The manufacturing method of the semiconductor discharge tube according to claim 7, wherein, Further comprising: In any one of the device unit regions, a trench is formed on one side of the semiconductor substrate. Among them, the first diffusion region and the trench are on the same side of the semiconductor substrate, and the depth of the trench is greater than the depth of the first diffusion region; the third diffusion region and the fourth diffusion region are located on the first side of the trench; the fifth diffusion region is located on the second side of the trench opposite to the first side; the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region.

9. The manufacturing method of the semiconductor discharge tube according to claim 7, characterized in that, In any one of the device unit regions, the arrangement direction of the third diffusion region and the fourth diffusion region is perpendicular to the arrangement direction of the fourth diffusion region and the fifth diffusion region; the body region extends to the relative region between the fourth diffusion region and the fifth diffusion region.

10. According to the method for manufacturing a semiconductor discharge tube as claimed in claim 7, wherein, In any one of the device unit regions, the first diffusion region and the second diffusion region are on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite to each other along the thickness direction of the semiconductor substrate; There are at least two device unit regions, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are on the same side of the semiconductor substrate; In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region; In any one of the device unit regions, a plurality of first short - circuit points are arranged at intervals in the fifth diffusion region; The third diffusion region is located at the junction of the first diffusion region and the body region of the semiconductor substrate; the doping concentration of the third diffusion region is greater than the doping concentration of the body region; In any of the device unit regions, the depth of the fourth diffusion region is less than the depth of the first diffusion region; the depth of the fifth diffusion region is less than the depth of the first diffusion region; In any of the device unit regions, the first conductive block and the second conductive block are arranged at intervals; The first conduction type is electron type, and the second conduction type is hole type; or, the first conduction type is hole type, and the second conduction type is electron type.

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