Light emitting device, optical device, and measuring device

Abstract

A light emitting device, an optical device, and a measuring device are provided. The light emitting device includes a wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser portion having a cathode electrode and an anode electrode, mounted on the wiring substrate and driven by a low side, wherein a cathode wiring connected to the cathode electrode and an anode wiring connected to the anode electrode are provided in the first wiring layer, a reference potential wiring connected to a reference potential is provided in the first wiring layer and the second wiring layer, and an area in which the reference potential wiring of the second wiring layer overlaps with the anode wiring is larger than an area in which the reference potential wiring of the second wiring layer overlaps with the reference potential wiring of the first wiring layer.

Description

Technical Field

[0001] This disclosure relates to a light-emitting device, an optical device, and a measuring device. Background Technology

[0002] Japanese Patent Application Publication No. 2008-252129 discloses a light-emitting device comprising: a ceramic substrate having light transmittance; a light-emitting element mounted on the surface of the ceramic substrate; a wiring pattern for supplying power to the light-emitting element; and a metallization layer comprising a reflective metal, the metallization layer being formed inside the ceramic substrate in such a way as to reflect light emitted from the light-emitting element. Summary of the Invention

[0003] In measuring the three-dimensional shape of an object based on the so-called Time of Flight (ToF) method, which utilizes the time of flight of light, it is necessary to reduce the inductance of the drive circuit that supplies the drive current to the laser unit and shorten the rise time of the light emitted from the laser unit.

[0004] The purpose of this disclosure is to enable a light-emitting device comprising a wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser unit mounted on the wiring substrate and driven on the low side, such that, compared to a case where the area of ​​overlap between the reference potential wiring of the second wiring layer and the anode wiring of the first wiring layer is smaller than the area of ​​overlap between the reference potential wiring of the second wiring layer and the reference potential wiring of the first wiring layer, more of the capacitance component between the wirings can be utilized as the driving current for driving the laser unit.

[0005] According to a first aspect of this disclosure, a light-emitting device is provided, comprising: a wiring substrate having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer; and a laser unit having a cathode electrode and an anode electrode, mounted on the wiring substrate and driven by a low side, wherein a cathode wiring connected to the cathode electrode and an anode wiring connected to the anode electrode are disposed on the first wiring layer, and a reference potential wiring connected to a reference potential is disposed on the first wiring layer and the second wiring layer, wherein the area of ​​the reference potential wiring of the second wiring layer overlapping with the anode wiring is larger than the area of ​​the reference potential wiring of the second wiring layer overlapping with the reference potential wiring of the first wiring layer.

[0006] According to the second aspect of this disclosure, the area of ​​the anode wiring is larger than the area of ​​the reference potential wiring of the first wiring layer.

[0007] According to a third aspect of this disclosure, the anode wiring has an area of ​​more than 50% of the area of ​​the wiring substrate.

[0008] According to the fourth aspect of this disclosure, the anode wiring has an area of ​​more than 75% of the area of ​​the wiring substrate.

[0009] According to the fifth aspect of this disclosure, the thickness of the insulating layer is less than 100 μm.

[0010] According to the sixth aspect of this disclosure, the laser section is a surface-emitting laser element array on a common semiconductor substrate, wherein a plurality of surface-emitting laser elements are formed.

[0011] According to the seventh aspect of this disclosure, the light-emitting device has an optical component that changes at least one of the direction and the spread angle of the light emitted from the laser section.

[0012] According to the eighth aspect of this disclosure, an optical device is provided, comprising: the light-emitting device; and a light-receiving unit that receives reflected light emitted from a laser unit included in the light-emitting device and reflected by a measured object, wherein the light-receiving unit outputs a signal corresponding to the time from when the light is emitted from the laser unit until it is received by the light-receiving unit.

[0013] According to the ninth aspect of this disclosure, a measuring device is provided, comprising: the optical device; and a three-dimensional shape determining unit, which determines the three-dimensional shape of the object being measured based on reflected light emitted from a laser unit included in the optical device and received by a light-receiving unit included in the optical device, the measuring device measuring the three-dimensional shape of the object being measured.

[0014] (Effect)

[0015] According to the first scheme, compared with the case where the area of ​​overlap between the reference potential wiring of the second wiring layer and the anode wiring of the first wiring layer is smaller than the area of ​​overlap between the reference potential wiring of the second wiring layer and the reference potential wiring of the first wiring layer, more of the capacitance component between the wirings can be used as the driving current for driving the laser unit.

[0016] According to the second scheme, compared with the case where the area of ​​the anode wiring is smaller than the area of ​​the reference potential wiring of the first wiring layer, it is easier to increase the area of ​​overlap between the reference potential wiring and the anode wiring of the second wiring layer.

[0017] According to the third scheme, compared with the case of less than 50% area, it is easier to increase the area of ​​overlap between the reference potential wiring and the anode wiring of the second wiring layer.

[0018] According to the fourth scheme, compared with the case of less than 75% area, it is easier to increase the area of ​​overlap between the reference potential wiring and the anode wiring of the second wiring layer.

[0019] According to the fifth scheme, the capacitance between wirings increases compared to cases where the insulation layer thickness exceeds 100 μm.

[0020] According to the sixth scheme, compared with the case of using an end-face emitting laser, it is easier to configure the laser element in a two-dimensional shape.

[0021] According to the seventh embodiment, compared with the case without optical components, it is possible to change at least one of the direction or spread angle of the light emitted from the light source for illumination.

[0022] According to the eighth scheme, an optical device capable of acquiring signals corresponding to three-dimensional shapes can be provided.

[0023] According to the ninth embodiment, a measuring device capable of measuring three-dimensional shapes can be provided. Attached Figure Description

[0024] Figure 1 This is a block diagram illustrating an example of the structure of a measuring device for measuring three-dimensional shapes.

[0025] Figure 2 It is a plan view of the light source.

[0026] Figure 3 This is a cross-sectional diagram illustrating the structure of a vertical cavity surface-emitting laser (VCSEL) in a light source.

[0027] Figure 4 (a) and Figure 4 (b) is a diagram illustrating an example of a light-diffusing component. Figure 4 (a) is a plan view. Figure 4 (b) is Figure 4 (a) A cross-sectional view at the IVB-IVB line.

[0028] Figure 5 This is a diagram illustrating an example of an equivalent circuit when a light source is driven via a low-side drive.

[0029] Figure 6 (a) and Figure 6 (b) is a diagram illustrating a capacitor. Figure 6 (a) is the equivalent circuit of the capacitor. Figure 6 (b) is the frequency characteristic of the capacitor's impedance.

[0030] Figure 7 (a) and Figure 7 (b) is a diagram illustrating an example of low ESL capacitors and non-low ESL capacitors. Figure 7 (a) is a low ESL capacitor. Figure 7(b) is a non-low ESL capacitor.

[0031] Figure 8 This is a diagram illustrating the driving current pulses supplied to the light source.

[0032] Figure 9 (a) to Figure 9 (c) is a diagram illustrating the light-emitting device applicable to this embodiment. Figure 9 (a) is a plan view. Figure 9 (b) is Figure 9 (a) is a cross-sectional view at line IXB-IXB. Figure 9 (c) is Figure 9 (a) Cross section at line IXC-IXC.

[0033] Figure 10 (a) to Figure 10 (c) is a diagram illustrating a light-emitting device not applicable to this embodiment, shown for comparison purposes. Figure 10 (a) is a plan view. Figure 10 (b) is Figure 10 (a) is a cross-sectional view at the XB-XB line. Figure 10 (c) is Figure 10 (a) Cross section at the XC-XC line. Detailed Implementation

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Among measuring devices that measure the three-dimensional shape of an object, there are devices that measure three-dimensional shape based on the so-called Time of Flight (ToF) method, which utilizes the time of flight of light. In the ToF method, the time from the moment light is emitted from the light source of the measuring device until the moment the illuminated light is reflected by the object being measured and received by the three-dimensional sensor (hereinafter referred to as the 3D sensor) of the measuring device is measured is measured to determine the three-dimensional shape of the object being measured. Furthermore, the object whose three-dimensional shape is measured is called the measured object. Moreover, measuring three-dimensional shape is sometimes referred to as three-dimensional measurement, 3D measurement, or 3D sensing.

[0036] This type of measuring device is incorporated into mobile information processing devices and used for facial authentication of users seeking access. Previously, mobile information processing devices used methods such as passwords, fingerprints, and iris scans to authenticate users. In recent years, there has been a search for more secure authentication methods. Therefore, a measuring device that measures three-dimensional shape is incorporated into mobile information processing devices. That is, a three-dimensional image of the user's face is acquired, access is determined, and the device (mobile information processing device) is only allowed to use the user if the user is authenticated as authorized.

[0037] Moreover, this type of measuring device is also suitable for situations such as Augmented Reality (AR) where the three-dimensional shape of the measured object is continuously measured.

[0038] In measuring devices that utilize the Time-of-Flight (ToF) method to measure three-dimensional shapes, a short rise time of light emitted from the laser unit (hereinafter referred to as the light source) is required. The shorter the rise time of light emitted from the light source, the higher the measurement accuracy. The smaller the inductance of the drive circuit supplying the drive current to the light source, the shorter the rise time of light emitted from the light source. That is, the larger the inductance of the drive circuit supplying the drive current, the more difficult it is for high-frequency (hereinafter referred to as high-frequency) drive current to flow, and the longer the rise time of light emitted from the light source will become.

[0039] The structures, functions, methods, etc. described in this embodiment are applicable to the measurement of the three-dimensional shape of the measured object other than facial authentication or augmented reality.

[0040] (Measuring device 1)

[0041] Figure 1 This is a block diagram illustrating an example of the structure of a measuring device 1 for measuring three-dimensional shapes.

[0042] The measuring device 1 includes an optical device 3 and a control unit 8. The control unit 8 controls the optical device 3. Furthermore, the control unit 8 includes a three-dimensional shape determination unit 81 that determines the three-dimensional shape of the object being measured. The control unit 8 is configured as a computer including a central processing unit (CPU), read-only memory (ROM), and random access memory (RAM). The ROM includes non-volatile, rewritable memory, such as flash memory. The three-dimensional shape determination unit 81 is configured by expanding a program or constant stored in the ROM into the RAM and executing the program by the CPU, thereby determining the three-dimensional shape of the object being measured.

[0043] The following is an explanation in sequence.

[0044] The optical device 3 includes a light-emitting device 4 and a 3D sensor 5.

[0045] The light-emitting device 4 includes a wiring board 10, a light source 20, a light-diffusing member 30, a driving part 50, a holding part 60, and capacitors 70A and 70B. Capacitor 70A is a capacitor that reduces the equivalent series inductance (ESL) (hereinafter referred to as a low-ESL capacitor), and capacitor 70B is a capacitor whose equivalent series inductance (ESL) is larger than that of capacitor 70A (hereinafter referred to as a non-low-ESL capacitor). As described later, the wiring board 10 includes capacitors (described later). Figure 5 , Figure 9 The capacitor 70C described in (a) to (c), said capacitor (described later) Figure 5 , Figure 9 (a) to Figure 9 The capacitor 70C described in (c) includes parasitic capacitance generated due to the structure of the wiring board 10. Additionally, Figure 1 In this document, one capacitor 70A and one capacitor 70B are each described, but there may be multiple capacitors or capacitors. Additionally, the light-emitting device 4 may include other circuit components such as capacitors or resistors to operate the drive unit 50. Without distinguishing between capacitors 70A, 70B, and 70C, they are referred to as capacitor 70 or simply capacitor. Capacitors (low ESL capacitors and non-low ESL capacitors) will be discussed later. A capacitor is sometimes called a capacitive element or a condenser. Furthermore, capacitors 70A and 70B are examples of capacitive elements. A capacitor containing parasitic capacitance (capacitor 70C) is an example of a capacitive component.

[0046] A light source 20, a driving unit 50, capacitors 70A and 70B, and a holding unit 60 are disposed on the surface of the wiring board 10. Additionally, Figure 1 In this configuration, the 3D sensor 5 is not disposed on the surface of the wiring board 10, but it may be disposed on the surface of the wiring board 10. Furthermore, the light diffusion member 30 is disposed on the holding portion 60. Here, "surface" refers to... Figure 1 The surface side of the paper. More specifically, in the wiring board 10, the area where the light source 20 is provided is referred to as the surface, surface side, or surface side.

[0047] The light source 20 is configured as a two-dimensional array of surface-emitting laser elements (see below). Figure 2As an example, the surface-emitting laser element is a vertical-cavity surface-emitting laser (VCSEL). Hereinafter, the surface-emitting laser element will be described using a VCSEL. The VCSEL will be referred to as a VCSEL. The light source 20 is disposed on the surface of the wiring board 10, and therefore emits light outward in a direction perpendicular to the surface of the wiring board 10. The light source 20 is an example of a laser unit.

[0048] The light diffusion member 30 allows light emitted from the light source 20 to enter and diffuse before exiting. The light diffusion member 30 is provided in a manner that covers the light source 20. That is, the light diffusion member 30 is provided at a predetermined distance from the light source 20 provided on the wiring board 10 via the holding portion 60 provided on the surface of the wiring board 10. Therefore, the light emitted from the light source 20 is diffused by the light diffusion member 30 and illuminates the object being measured. In other words, compared to the case without the light diffusion member 30, the light emitted from the light source 20 is diffused by the light diffusion member 30 and illuminates a wider range.

[0049] In the case of 3D measurement using the Time-of-Flight (ToF) method, the light source 20 is required to emit pulsed light (hereinafter referred to as emitted light pulse) with a frequency of 100 MHz or higher and a rise time of 1 ns or less via the drive unit 50. That is, the light source 20 is driven by a drive circuit that supplies a drive current pulse to emit the emitted light pulse. Furthermore, in the case of facial recognition, the distance of the irradiated light is approximately 10 cm to 1 m. The range of the irradiated light is approximately 1 m square. The distance of the irradiated light is referred to as the measurement distance, and the range of the irradiated light is referred to as the irradiation range or measurement range. The surface imaginary within the irradiation range or measurement range is referred to as the irradiation surface. In cases other than facial recognition, the measurement distance up to the object being measured and the irradiation range for the object being measured may be different from the above.

[0050] The 3D sensor 5 includes multiple photoreceiving cells and outputs a signal corresponding to the time from the moment light is emitted from the light source 20 until it is received by the 3D sensor 5. For example, each photoreceiving cell of the 3D sensor 5 receives a pulse of reflected light (hereinafter referred to as a received pulse) from the object being measured relative to the emitted light pulse from the light source 20, and stores a charge in each photoreceiving cell corresponding to the time until the light is received. The 3D sensor 5 is configured as a complementary metal-oxide-semiconductor (CMOS) structure element, where each photoreceiving cell includes two gates and corresponding charge storage portions. Furthermore, by alternately applying pulses to the two gates, the generated photoelectrons are rapidly transmitted to either of the two charge storage portions. In the two charge storage portions, a charge corresponding to the phase difference between the emitted and received light pulses is stored. Furthermore, the 3D sensor 5 outputs a digital value corresponding to the phase difference between the emitted light pulse and the received light pulse via an analog-to-digital (A / D) converter, corresponding to each photoreceiving cell. That is, the 3D sensor 5 outputs a signal corresponding to the time from the moment light is emitted from the light source 20 until it is received by the 3D sensor 5. In other words, a signal corresponding to the three-dimensional shape of the measured object is acquired from the 3D sensor 5. Therefore, it is required that the rise time of the emitted light pulse and the rise time of the received light pulse be short. That is, it is required that the rise time of the driving current pulse supplied to drive the light source 20 be short. Additionally, the A / D converter can be included within the 3D sensor 5 or located externally to the 3D sensor 5. The 3D sensor 5 is an example of a light-receiving unit.

[0051] Furthermore, when the 3D sensor 5 is, for example, a CMOS structure element as described above, the three-dimensional shape determination unit 81 of the control unit 8 acquires the digital value obtained for each photodetector cell, and calculates the distance up to the object being measured for each photodetector cell. Then, based on the calculated distance, the three-dimensional shape of the object being measured is determined, and the determination result is output.

[0052] As mentioned earlier, the control unit 8 is configured as a computer, and the three-dimensional shape determination unit 81 is implemented by a program. However, they may also include integrated circuits such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Furthermore, they may also include software such as programs and integrated circuits such as ASICs.

[0053] As explained above, the measuring device 1 diffuses the light emitted from the light source 20 to illuminate the object being measured, and uses the 3D sensor 5 to receive the reflected light from the object being measured. In this way, the measuring device 1 measures the three-dimensional shape of the object being measured.

[0054] Figure 1 In the diagram, the optical device 3 and the control unit 8 are shown separately, but they can also be integrated into one unit.

[0055] First, the light source 20, light diffusion member 30, driving unit 50, and capacitors (capacitor 70A, capacitor 70B, and capacitor 70C) constituting the light-emitting device 4 will be described.

[0056] (Structure of light source 20)

[0057] Figure 2 This is a plan view of light source 20. Light source 20 is composed of multiple VCSELs arranged in a two-dimensional array. Additionally, Figure 2 In this configuration, VCSELs are arranged at the grid points of a square grid, but other arrangements are also possible. As previously described, the light source 20 is configured as an array of surface-emitting laser elements, with VCSELs serving as surface-emitting laser elements. Here, the right direction of the paper is defined as the x-direction, and the top direction of the paper is defined as the y-direction. The direction perpendicular to both the x and y directions in a counterclockwise direction is defined as the z-direction. Furthermore, the term "surface" of the light source 20 refers to the surface side of the paper, i.e., the side facing the +z direction, and the term "back side" of the light source 20 refers to the back side of the paper, i.e., the side facing the -z direction. The plan view of the light source 20 is a view of the light source 20 viewed from the surface side. To further explain, in the light source 20, the area where the epitaxial layer that functions as the light-emitting layer (the active region 206 described later) is formed is referred to as the surface, surface side, or surface side of the light source 20.

[0058] VCSEL is a surface-emitting laser element as described below, namely, a surface-emitting laser element stacked on a semiconductor substrate 200 (see below). Figure 3 An active region, serving as the light-emitting area, is positioned between the lower and upper multilayer film reflectors on the surface, causing the laser light to be emitted in a direction perpendicular to the surface. Therefore, compared to using end-face emission type laser elements, VCSELs are easier to array in two dimensions. For example, the number of VCSELs included in the light source 20 can be 100 to 1000. Furthermore, multiple VCSELs are connected in parallel, thus being driven side-by-side. The number of VCSELs mentioned is just one example; it can be set according to the measurement distance or illumination range.

[0059] On the surface of the light source 20, a common anode electrode 218 shared by multiple VCSELs is provided. On the back side of the light source 20, a cathode electrode 214 is provided (see below). Figure 3That is, multiple VCSELs are connected in parallel. By driving multiple VCSELs in parallel, a stronger light can be emitted compared to driving VCSELs independently.

[0060] Here, the shape of the light source 20 as viewed from the surface side (denoted as the planar shape, and the same applies below) is assumed to be rectangular. Furthermore, the side facing the -y direction is called side 21A, the side facing the +y direction is called side 21B, the side facing the -x direction is called side 22A, and the side facing the +x direction is called side 22B. Side 21A and side 21B face each other. Side 22A and side 22B are connected to side 21A and side 21B respectively and face each other.

[0061] (The structure of VCSEL)

[0062] Figure 3 This is a diagram illustrating the cross-sectional structure of a VCSEL in light source 20. The VCSEL is a VCSEL with a λ-resonance structure. The upward direction of the paper is defined as the z-direction, the +z direction is called the upper side, and the -z direction is called the lower side.

[0063] A VCSEL is constructed by sequentially stacking an n-type lower distributed Bragg reflector (DBR) 202, an active region 206, and a p-type upper distributed Bragg reflector 208 on an n-type GaAs or other semiconductor substrate 200. The n-type lower distributed Bragg reflector 202 is formed by alternating layers of AlGaAs with different Al compositions. The active region 206 includes a quantum well layer sandwiched between an upper and lower separator layer. The p-type upper distributed Bragg reflector 208 is formed by alternating layers of AlGaAs with different Al compositions. Hereinafter, the distributed Bragg reflector will be referred to as a DBR.

[0064] The lower part of the n-type DBR202 is configured to make Al 0.9 Ga 0.1 A stack of As and GaAs layers in pairs. The thickness of each layer in the lower DBR202 is λ / 4n. r (where λ is the oscillation wavelength, n) r The medium has a refractive index and is stacked in 40 alternating layers. Silicon (Si) is doped as an n-type impurity, acting as a carrier. The carrier concentration is, for example, 3 × 10⁻⁶. 18 cm -3 .

[0065] The active region 206 is composed of a lower separator layer, a quantum well active layer, and an upper separator layer stacked together. For example, the lower separator layer is undoped Al. 0.6 Ga0.4 The As layer consists of an undoped InGaAs quantum well active layer and an undoped GaAs barrier layer, while the upper separator layer is undoped Al. 0.6 Ga 0.4 As layer.

[0066] The upper DBR208 of the p-type is configured to make the p-type Al 0.9 Ga 0.1 A stack of As and GaAs layers in pairs. The thickness of each layer of the upper DBR208 is λ / 4n. r The layers are stacked alternately in 29 cycles. Carbon (C) is doped as a p-type impurity, serving as the support. The support concentration is, for example, 3 × 10⁻⁶. 18 cm -3 Preferably, a contact layer containing p-type GaAs is formed on the uppermost layer of the upper DBR208, and a current-restricting layer 210 of p-type AlAs is formed on the lowermost layer of the upper DBR208 or inside thereof.

[0067] By etching the semiconductor layers from the upper DBR208 to the lower DBR202, a cylindrical mesa M is formed on the semiconductor substrate 200. As a result, the current-restricting layer 210 is exposed on the side of the mesa M. Through an oxidation process, an oxide region 210A formed from the side of the mesa M and a conductive region 210B surrounded by the oxide region 210A are formed in the current-restricting layer 210. Furthermore, in the oxidation process, the AlAs layer oxidizes faster than the AlGaAs layer, and the oxide region 210A is oxidized from the side of the mesa M towards the interior at a substantially constant rate. Therefore, the cross-sectional shape of the conductive region 210B is a circular shape that reflects the shape of the mesa M, with its center approximately aligned with the axis of the mesa M indicated by a chain line at a single point. In this embodiment, the mesa M has a cylindrical structure.

[0068] On the top layer of the mesa M, a ring-shaped p-side electrode 212 made of metal, such as Ti / Au, is formed. The p-side electrode 212 makes ohmic contact with the contact layer provided on the upper DBR 208. The inner side of the ring-shaped p-side electrode 212 becomes a light emission port 212A for laser light to be emitted outward. That is, the VCSEL emits light in the +z direction, which is perpendicular to the surface (+z direction side) of the semiconductor substrate 200. Furthermore, the axis of the mesa M becomes the optical axis. Furthermore, a cathode electrode 214, serving as the n-side electrode, is formed on the back side of the semiconductor substrate 200. In addition, the surface (+z direction side) of the upper DBR 208 inside the p-side electrode 212 is the light emission surface.

[0069] Furthermore, an insulating film 216 is provided to cover the surface of the platform M, except for the portion where the anode electrode 218 is connected to the p-side electrode 212 and the light emission port 212A. Also, the anode electrode 218 is provided in ohmic contact with the p-side electrode 212, except for the light emission port 212A. Additionally, the anode electrode 218 is shared by multiple VCSELs. That is, the p-side electrodes 212 of each of the multiple VCSELs constituting the light source 20 are connected in parallel via the anode electrode 218.

[0070] Figure 3 In the figure, the part of the anode electrode 218 is marked as [A] to indicate that it is the anode, and the part of the cathode electrode 214 is marked as [K] to indicate that it is the cathode.

[0071] VCSELs can oscillate in either a single transverse mode or multiple transverse modes. For example, the light output of a single VCSEL is 4mW to 8mW. Therefore, in the case where light source 20 contains 500 VCSELs, the light output of light source 20 is 2W to 4W.

[0072] (Structure of light diffusion component 30)

[0073] Figure 4 (a) and Figure 4 (b) is a diagram illustrating an example of the light diffusion member 30. Figure 4 (a) is a plan view. Figure 4 (b) is Figure 4 (a) A cross-sectional view at the IVB-IVB line. Figure 4 In (a), the rightward direction of the paper surface is defined as the x-direction, and the upward direction of the paper surface is defined as the y-direction. The direction perpendicular to both the x- and y-directions in a counterclockwise direction is defined as the z-direction. Furthermore, in the light diffusion member 30, the +z-direction side is referred to as the surface or surface side, and the -z-direction side is referred to as the back side or back side. Therefore, Figure 4 In (b), the right direction of the paper is the x direction, the back direction of the paper is the y direction, and the top direction of the paper is the z direction.

[0074] like Figure 4 As shown in (b), the light diffusion member 30 includes, for example, a resin layer 32, which has irregularities formed on the back (-z direction) side of the glass substrate 31, which has two parallel and flat surfaces, for light diffusion. The light diffusion member 30 expands the spread angle of the light incident from the VCSEL of the light source 20 and allows it to exit. That is, the irregularities formed in the resin layer 32 of the light diffusion member 30 refract or scatter the light, thereby making the incident light a beam with a wider spread angle and allowing it to exit. That is, as... Figure 4 (a) and Figure 4As shown in (b), the light diffusion member 30 causes light incident from the back side (-z direction side) and exiting the VCSEL with a spread angle θ to exit from the surface (+z direction side) with a spread angle φ larger than the spread angle θ (θ < φ). Therefore, when the light diffusion member 30 is used, the area of ​​the irradiated surface illuminated by the light emitted from the light source 20 is increased compared to the case where the light diffusion member 30 is not used. The spread angles θ and φ are the full width half maximum (FWHM).

[0075] Here, the planar shape of the light-diffusing member 30 is rectangular. Furthermore, the thickness (thickness in the z-direction) of the light-diffusing member 30 is t. d The thickness is 0.1 mm to 1 mm. In addition, the planar shape of the light diffusion member 30 can also be other shapes such as polygons or circles.

[0076] (Drive unit 50 and capacitors 70A and 70B)

[0077] To drive the light source 20 at a higher speed, low-side driving can be performed. Low-side driving refers to a structure in which driving elements such as MOS transistors are located downstream of the current path (hereinafter referred to as the current path) relative to the driven object such as VCSELs. Conversely, a structure in which the driving elements are located upstream is called high-side driving.

[0078] Figure 5 This is a diagram illustrating an example of the equivalent circuit when the light source 20 is driven by the low-side drive. Figure 5 The diagram shows the VCSEL of the light source 20, the driving unit 50, capacitors 70A, 70B, and 70C, and the power supply 82. As mentioned earlier, capacitor 70C is a parasitic capacitance generated due to the structure of the wiring board 10. Therefore, capacitor 70C is represented by a dashed line. Furthermore, Figure 5 In the middle, it was expressed together Figure 1 The control unit 8 is shown. Additionally, a power supply 82 is provided in the control unit 8. The power supply 82 generates a DC voltage that sets the positive side as the power supply potential and the negative side as the reference potential. The power supply potential is supplied to the power supply line 83, and the reference potential is supplied to the reference line 84. Furthermore, the reference potential may be the ground potential (sometimes referred to as GND). Figure 5 (marked as [G]).

[0079] As mentioned earlier, the light source 20 is composed of multiple VCSELs connected in parallel. The anode electrode 218 of the VCSEL (see reference) Figure 3 , Figure 5 The part marked [A] is connected to power cord 83.

[0080] The driving unit 50 includes an n-channel MOS transistor 51 and a signal generation circuit 52 for turning the MOS transistor 51 on and off. The drain of the MOS transistor 51 ( Figure 5 The cathode electrode 214 (marked as [D] in the middle) is connected to the VCSEL (reference). Figure 3 , Figure 5 The source of MOS transistor 51 is marked as [K]. Figure 5 The [S] symbol is connected to the reference line 84. Furthermore, the gate of the MOS transistor 51 is connected to the signal generation circuit 52. That is, the VCSEL and the MOS transistor 51 of the drive unit 50 are connected in series between the power supply line 83 and the reference line 84. The signal generation circuit 52, under the control of the control unit 8, generates a "H level" signal that sets the MOS transistor 51 to the on state and a "L level" signal that sets the MOS transistor 51 to the off state.

[0081] One terminal of each of capacitors 70A, 70B, and 70C is connected to power line 83. Figure 5 The other terminal of the VCSEL ([A]) is connected to the reference line 84. Figure 5 [G]).

[0082] Next, the driving method of the light source 20 driven by the low side will be explained.

[0083] First, assume the signal generated by the signal generation circuit 52 in the drive unit 50 is at "L level". At this time, the MOS transistor 51 is in the off state. That is, at the source of the MOS transistor 51 ( Figure 5 [S])-drain ( Figure 5 There is no current flowing between [D]). Therefore, there is also no current flowing in the VCSEL connected in series with the MOS transistor 51. That is, the VCSEL does not emit light.

[0084] At this time, capacitors 70A, 70B, and 70C are connected to power supply 82, and capacitors 70A, 70B, and 70C are connected to one terminal of power line 83. Figure 5 The [A] side terminal of the VCSEL becomes the power supply potential and is connected to the other terminal of the reference line 84. Figure 5 The [G] side terminal becomes the reference potential. Therefore, capacitors 70A, 70B, and 70C are charged by current flowing from power supply 82 (being supplied with charge).

[0085] Next, when the signal generated by the signal generation circuit 52 in the drive unit 50 becomes "H level", the MOS transistor 51 changes from the off state to the on state. Thus, a closed loop is formed between capacitors 70A, 70B, and 70C and the series-connected MOS transistor 51 and VCSEL, and the charge stored in capacitors 70A, 70B, and 70C is supplied to the series-connected MOS transistor 51 and VCSEL. That is, current flows through the VCSEL, and the VCSEL emits light. This closed loop is a drive circuit for supplying the drive current that makes the light source 20 emit light. Furthermore, since a drive current for making the light source 20 emit light is supplied to each capacitor 70A, 70B, and 70C, the drive circuit is configured for each capacitor 70A, 70B, and 70C. Additionally, the operation of supplying the drive current for making the light source 20 emit light is sometimes referred to as driving the light source 20.

[0086] Furthermore, when the signal generated by the signal generation circuit 52 in the drive unit 50 changes to "L level" again, the MOS transistor 51 changes from the on state to the off state. As a result, the closed loop formed by capacitors 70A, 70B, and 70C, along with the MOS transistor 51 and VCSEL connected in series, becomes an open loop, and no current flows to the VCSEL. Consequently, the VCSEL stops emitting light. Then, current flows from the power supply 82 (supplying charge) into capacitors 70A, 70B, and 70C, charging them.

[0087] As explained above, whenever the signal output by the signal generation circuit 52 changes to "H level" and "L level", the MOS transistor 51 repeatedly turns on and off, and the VCSEL repeatedly emits light and does not emit light. The repeated on and off of the MOS transistor 51 is sometimes referred to as a switch.

[0088] As described above, when the MOS transistor 51 is switched from the off state to the on state, the charge stored in capacitors 70A, 70B, and 70C is discharged all at once, thus supplying drive current to the VCSEL.

[0089] Here, capacitors (low ESL capacitors and non-low ESL capacitors) are explained.

[0090] Figure 6 (a) and Figure 6 (b) is a diagram illustrating a capacitor. Figure 6 (a) is the equivalent circuit of the capacitor. Figure 6 (b) shows the frequency response of the capacitor's impedance. Additionally, Figure 6 In (b), the horizontal axis represents frequency and the vertical axis represents impedance.

[0091] like Figure 6 As shown in (a), a capacitor is represented by an equivalent circuit consisting of a capacitor C, an equivalent series inductance ESL, and an equivalent series resistance ESR connected in series.

[0092] like Figure 6 As shown in (b), at low frequencies, the impedance of a capacitor depends on its capacitance C. That is, the capacitor is capacitive, and its impedance decreases with frequency. On the other hand, at high frequencies, the impedance of a capacitor depends on its equivalent series inductance ESL. That is, the capacitor is inductive, and its impedance increases with frequency. Furthermore, the frequency at which the capacitance C and the equivalent series inductance ESL achieve the same impedance is called the resonant frequency.

[0093] To shorten the rise time of the drive current pulse supplied to the light source 20, low impedance at high frequencies, i.e., low equivalent series inductance (ESL), is preferable. That is, to shorten the rise time of the drive current pulse supplied to the light source 20, a capacitor constructed to reduce the equivalent series inductance (ESL), i.e., a low-ESL capacitor, is preferable. For example... Figure 6 As shown in (b), low-ESL capacitors have lower impedance at high frequencies compared to non-low-ESL capacitors with a structure where the equivalent series inductance ESL is larger than that of low-ESL capacitors.

[0094] Figure 7 (a) and Figure 7 (b) is a diagram illustrating an example of a low ESL capacitor (capacitor 70A) and a non-low ESL capacitor (capacitor 70B). Figure 7 (a) is a low ESL capacitor (capacitor 70A). Figure 7 (b) are non-low ESL capacitors (capacitor 70B). They are two-terminal multilayer ceramic capacitors. Multilayer ceramic capacitors are like... Figure 7 of (a), Figure 7 As shown in (b), there is a structure having multiple layers of ceramic sheets 71, such as titanium oxide or barium titanate, with a planar rectangular shape, and internal wiring 72 provided on the surface of the ceramic sheet 71.

[0095] Figure 7The low-ESL capacitor 70A shown in (a) is configured such that current flows along the short side of a rectangular ceramic sheet 71. That is, the low-ESL capacitor has electrodes at both ends in the short side direction, forming a two-terminal stacked ceramic capacitor. When the direction of current flow in the ceramic sheet 71 (short side direction) is defined as the length L1, and the direction orthogonal to the current flow direction (long side direction) is defined as the width W1, the length L1 is smaller than the width W1 (L1 < W1). Thus, by shortening the current path, the equivalent series inductance ESL is reduced compared to the non-low-ESL capacitor described below. This type of low-ESL capacitor, where the width W1 is larger than the length L1, is sometimes called an LW-reverse type.

[0096] Figure 7 The non-low ESL capacitor 70B shown in (b) is configured such that current flows along the long side of a rectangular ceramic sheet 71. That is, the non-low ESL capacitor has electrodes at both ends along the long side, forming a two-terminal stacked ceramic capacitor. When the direction of current flow in the ceramic sheet 71 (long side direction) is defined as the length L2, and the direction orthogonal to the current flow direction (short side direction) is defined as the width W2, the length L2 is greater than the width W2 (L2 > W2). Therefore, the current path becomes longer, and thus the equivalent series inductance ESL becomes larger compared to a low ESL capacitor.

[0097] If a low-ESL capacitor with a small equivalent series inductance (ESL) is used, the impedance at high frequencies decreases, and the rise time of the drive current pulse supplied to the light source 20 becomes shorter. However, low-ESL capacitors are often those that occupy a large mounting area on the wiring board 10 but have a small rated capacitance. Therefore, if only a low-ESL capacitor 70A is used instead of a non-low-ESL capacitor 70B, for example, to drive a light source 20 of about 2W, multiple capacitors 70A will be used. In this case, the current path up to the VCSEL will be different for each capacitor 70A. If the current path becomes longer, the wiring inductance will increase, making it difficult to achieve the effect of using a low-ESL capacitor. In other words, by using multiple low-ESL capacitors 70A, the mounting area occupied on the wiring board 10 is increased, making it difficult to achieve the effect of a small equivalent series inductance (ESL).

[0098] On the other hand, in non-low ESL capacitors, ceramic sheets 71 with high dielectric constants are often used, which have a large rated capacitance despite a small mounting area on the wiring board 10. For example, to drive a light source 20 of about 2W, only one non-low ESL capacitor is needed. However, compared with low ESL capacitors, the equivalent series inductance ESL is large, making it difficult to shorten the rise time of the drive current pulse supplied to the light source 20.

[0099] Therefore, in this embodiment, a capacitor 70A, which is a low-ESL capacitor, and a capacitor 70B, which is a non-ESL capacitor, are used. Furthermore, the low-ESL capacitor 70A and the non-ESL capacitor 70B are connected in parallel. That is, the rise time of the drive current pulse supplied to the light source 20 is shortened by the low-ESL capacitor 70A, and the current for driving the light source 20 is supplied by the non-ESL capacitor 70B.

[0100] Furthermore, in this embodiment, by using a capacitor 70C that includes the parasitic capacitance generated by the structure of the wiring board 10, the rise time of the drive current pulse supplied to the light source 20 is further shortened. As will be described later, the equivalent series inductance ESL of the capacitor including the parasitic capacitance generated by the structure of the wiring board 10 is smaller than that of the low ESL capacitor. Therefore, by using the capacitor 70C that includes the parasitic capacitance, the rise time of the current pulse supplied to the light source 20 is further shortened. Thus, as will be explained below, in this embodiment, the parasitic capacitance generated by the structure of the wiring board 10 is increased.

[0101] Figure 8 This is a diagram illustrating the driving current pulses supplied to the light source 20. Figure 8 In the diagram, the horizontal axis represents time, and the vertical axis represents current.

[0102] like Figure 8 As shown, the initial rising portion α of the drive current pulse is supplied by capacitor 70C, which includes parasitic capacitance. Furthermore, the rising portion β of the drive current pulse is supplied by capacitor 70A, which is a low-ESL capacitor. Finally, the portion γ supplying the drive current is supplied by capacitor 70B, which is a non-low-ESL capacitor.

[0103] (Light-emitting device 4)

[0104] Next, the light-emitting device 4 will be described in detail.

[0105] Figure 9 (a) to Figure 9 (c) is a diagram illustrating the light-emitting device 4 applicable to this embodiment. Figure 9 (a) is a plan view. Figure 9 (b) is Figure 9 (a) is a cross-sectional view at line IXB-IXB. Figure 9 (c) is Figure 9 A cross-sectional view at line IXC-IXC in (a). Additionally, Figure 9 (a) is a view taken through the light-diffusing component 30. Here, Figure 9In (a), the rightward direction of the paper surface is defined as the x-direction, and the upward direction of the paper surface is defined as the y-direction. The direction perpendicular to both the x- and y-directions in a counterclockwise direction (the surface direction of the paper surface) is defined as the z-direction. Furthermore, for each component described below (wiring board 10, light diffusion component 30, etc.), the surface direction of the paper surface (+z direction) is referred to as the surface or surface side, and the back direction of the paper surface (-z direction) is referred to as the back side or back side. Hereinafter, the view of each component viewed from the surface side is referred to as a top view. In addition, Figure 9 (b) and Figure 9 In (c), the right direction of the paper is the x direction, the back direction of the paper is the y direction, and the top direction of the paper is the z direction.

[0106] like Figure 9 (a) and Figure 9 As shown in (b), a light source 20, a driving unit 50, a capacitor 70A, a capacitor 70B, and a holding unit 60 are provided on the surface of the wiring board 10. Furthermore, a light diffusion member 30 is provided on the holding unit 60.

[0107] The wiring board 10 is constructed by providing wiring layers on an insulating substrate (sometimes called an insulating layer) such as glass epoxy resin, wherein the wiring layers form wirings containing metals such as copper (Cu) foil. Furthermore, wiring refers to a conductor pattern used for electrical circuit connections, and its shape is not limited. Here, the wiring board 10 is described as a printed circuit board having four wiring layers. As an example, the substrate such as glass epoxy resin includes a glass composite substrate (CEM-3) or a glass epoxy board (FR-4).

[0108] like Figure 9 As shown in (a), in the light-emitting device 4, the light source 20 and the driving unit 50 are arranged on the wiring board 10 in a manner that is aligned along the x-direction.

[0109] like Figure 9 As shown in (a), the retaining part 60 includes a wall provided in a manner that surrounds the light source 20. Figure 9 In (a), the light source 20 is indicated by dashed lines. Figure 9 As shown in (b), the holding portion 60 holds the light diffusing member 30 via the wall. That is, the light diffusing member 30 is provided at a predetermined distance from the light source 20 provided on the wiring board 10 via the holding portion 60. Furthermore, the light diffusing member 30 is provided in a manner that covers the light source 20. Here, "the light diffusing member 30 covering the light source 20" means that the light diffusing member 30 is provided in the emission path of the light emitted from the light source 20, and the light emitted from the light source 20 passes through the light diffusing member 30. In other words, it means that when viewed from the surface side of the light diffusing member 30, the light source 20 and the light diffusing member 30 coincide.

[0110] The holding portion 60 is, for example, a molded component made of resin or the like. Furthermore, the holding portion 60 may be colored black, for example, to absorb light emitted from the light source 20. In this way, light emitted from the light source 20 that illuminates the holding portion 60 is absorbed by the holding portion 60. Therefore, the possibility of light illuminating the holding portion 60 passing through or being reflected by the holding portion 60 and illuminating the object being measured is suppressed.

[0111] Wiring board 10 Figure 9 (b) and Figure 9 As shown in (c), the wiring substrate 10 includes a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer from the surface side (+z direction side). The first wiring layer and the second wiring layer are insulated from each other by an insulating layer 11A, the second wiring layer and the third wiring layer are insulated from each other by an insulating layer 11B, and the third wiring layer and the fourth wiring layer are insulated from each other by an insulating layer 11C. Furthermore, when insulating layers 11A, 11B, and 11C are not distinguished, they are all referred to as insulating layer 11.

[0112] In the first wiring layer, there are electrically separated cathode wiring 12, anode wiring 13F, reference potential wiring 14-1F, reference potential wiring 14-2F, and reference potential wiring 14-3F. Additionally, Figure 9 In (a), a portion of the cathode wiring 12, anode wiring 13F, and reference potential wiring 14-3F, which are covered by the drive unit 50, is indicated by a single chain line.

[0113] On the second wiring layer, a reference potential wiring of 14M is provided. For example... Figure 9 As shown by the dashed line in (a), the reference potential wiring 14M is provided on the entire surface of the wiring substrate 10, i.e., the entire surface. Furthermore, the cathode wiring 12, the anode wiring 13F, the reference potential wiring 14-1F, the reference potential wiring 14-2F, and the reference potential wiring 14-3F are arranged so that they coincide with the reference potential wiring 14M when viewed from above. Figure 9 In (a), the edge of the reference potential wiring 14M is made wider such that it protrudes from the edge of any of the cathode wiring 12, anode wiring 13F, reference potential wiring 14-1F, reference potential wiring 14-2F, and reference potential wiring 14-3F. However, the edge of the reference potential wiring 14M may also not protrude from the edge of any of the cathode wiring 12, anode wiring 13F, reference potential wiring 14-1F, reference potential wiring 14-2F, and reference potential wiring 14-3F.

[0114] In the third wiring layer, a power supply potential wiring 13M is provided. The power supply potential wiring 13M can be provided on the entire surface of the wiring substrate 10, i.e., the entire surface, in the same way as the reference potential wiring 14M, or it can be provided in a way that connects to the anode wiring 13F to supply power supply potential to the anode wiring 13F.

[0115] In the fourth wiring layer, there is a signal wiring that sends signals from the control unit 8 to the drive unit 50 to the control signal generation circuit 52. Figure 9 (a) and Figure 9 In (b), signal wiring 15-1 and signal wiring 15-2 are shown as examples.

[0116] like Figure 9 (a) and Figure 9 As shown in (b), the cathode wiring 12 in the first wiring layer has a rectangular planar shape and is provided to connect the light source 20 and the driving unit 50. Furthermore, the light source 20 is provided at one end of the cathode wiring 12. That is, the light source 20 (VCSEL) is mounted on the cathode wiring 12 in such a way that the cathode wiring 12 is in contact with the cathode electrode 214 of the VCSEL constituting the light source 20. The other end of the cathode wiring 12 is connected to the drain of the MOS transistor 51 of the driving unit 50 (see reference 50). Figure 5 It is connected to the drive unit 50 in the manner of [D]).

[0117] The anode wiring 13F in the first wiring layer is arranged close to the three sides of the cathode wiring 12, namely the -x direction side and the ±y direction side. Furthermore, on the side 21A side of the light source 20, the anode electrode 218 constituting the VCSEL of the light source 20 (see reference) Figure 2 , Figure 3 It is connected to the anode wiring 13F via the bonding wire 23.

[0118] Furthermore, the anode wiring 13F has two openings, and reference potential wiring 14-1F and reference potential wiring 14-2F are provided inside each opening. Additionally, reference potential wiring 14-3F is provided at the end of the wiring substrate 10 on the x-direction side. Reference potential wiring 14-3F is connected to the drive unit 50 to be connected to the source of the MOS transistor 51 of the drive unit 50 (see reference). Figure 5 [S]).

[0119] like Figure 9 (b) and Figure 9 As shown in (c), the reference potential wiring 14-1F and reference potential wiring 14-3F in the first wiring layer are connected to the reference potential wiring 14M in the second wiring layer via through conductors 14-1V and 14-3V provided in the insulating layer 11A. Additionally, although not shown, reference potential wiring 14-2F and reference potential wiring 14M are connected via through conductors provided in the insulating layer 11A. The through conductor is a component that electrically connects the wiring on the surface side and the wiring on the back side of the insulating layer 11 by placing a conductive material such as copper (Cu) inside a through hole provided in the insulating layer 11. The through conductor is sometimes referred to as a through hole.

[0120] Furthermore, the anode wiring 13F in the first wiring layer and the power supply potential wiring 13M in the third wiring layer are connected by a through conductor 13V provided in the insulating layers 11A and 11B. In addition, the through conductor 13V is electrically separated from the reference potential wiring 14M in the second wiring layer.

[0121] And, as Figure 9 As shown in (a), in the first wiring layer of the wiring substrate 10, a capacitor 70A is provided between the anode wiring 13F and the reference potential wiring 14-1F, and a capacitor 70B is provided between the anode wiring 13F and the reference potential wiring 14-2F. As mentioned above, the reference potential wiring 14-1F and the reference potential wiring 14-2F are provided inside the two openings of the anode wiring 13F. Therefore, the capacitors 70A and 70B are surrounded by the anode wiring 13F. That is, the anode wiring 13F is provided in a manner that surrounds the capacitors 70A and 70B. Alternatively, the anode wiring 13F may surround only one of them, for example, only the capacitor 70A.

[0122] Here, the anode wiring 13F has two openings, and reference potential wiring 14-1F and reference potential wiring 14-2F are provided inside each opening. However, it is also possible to provide one opening in the anode wiring 13F, and provide a reference potential wiring that connects reference potential wiring 14-1F and reference potential wiring 14-2F into one inside it.

[0123] like Figure 9 As shown in (c), the parasitic capacitance generated between the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer is a capacitor 70C. The anode wiring 13F in the first wiring layer and the reference potential wiring 14M in the second wiring layer are insulated by the insulating layer 11A. Here, in order to increase the capacitance of the capacitor 70C, the area of ​​the anode wiring 13F is set to be large. For example, the area of ​​the reference potential wiring 14M in the second wiring layer overlapping with the anode wiring 13F in the first wiring layer is set to be larger than the area of ​​the reference potential wiring 14M in the second wiring layer overlapping with the reference potential wiring 14-3F in the first wiring layer.

[0124] Furthermore, in the first wiring layer, the area of ​​the anode wiring 13F is set to be larger than the areas of the reference potential wiring 14-1F, the reference potential wiring 14-2F, and the reference potential wiring 14-3F.

[0125] Furthermore, the anode wiring 13F in the first wiring layer of the wiring substrate 10 is provided such that it occupies more than 50% of the area of ​​the surface of the wiring substrate 10. Moreover, it is preferable that the anode wiring 13F in the first wiring layer of the wiring substrate 10 occupies more than 75% of the area of ​​the surface of the wiring substrate 10.

[0126] Furthermore, the thickness t of the insulating layer 11A c It is preferable to have a thickness of 100 μm or less to increase the capacitance of the capacitor 70C, which includes parasitic capacitance. More preferably, the thickness t of the insulating layer 11A is... c It is best to use a size below 80μm.

[0127] Figure 10 (a) to Figure 10 (c) is a diagram illustrating the light-emitting device 4' which is not applicable to this embodiment for comparison purposes. Figure 10 (a) is a plan view. Figure 10 (b) is Figure 10 (a) is a cross-sectional view at the XB-XB line. Figure 10 (c) is Figure 10 A cross-sectional view at line XC-XC in (a). Additionally, Figure 10 (a) is a view taken through the light-diffusing component 30. Figure 9 of (a), Figure 9 (b) and Figure 9 The components with the same function as the light-emitting device 4 shown in (c) of this embodiment are marked with the same symbols. Hereinafter, the description of the parts that are the same as those in the light-emitting device 4 will be omitted, and the different parts will be described.

[0128] In the light-emitting device 4', the anode wiring 13F and reference potential wiring 14F in the first wiring layer of the wiring substrate 10 differ from those in the light-emitting device 4. Specifically, the anode wiring 13F has a rectangular planar shape and is located on the side 21A (-y direction) of the light source 20. The anode wiring 13F is configured such that it is connected to the anode electrode 218 of the light source 20 via a bonding wire 23, and is also connected to one terminal of each of the capacitors 70A and 70B. Furthermore, the reference potential wiring 14F is configured to surround the cathode wiring 12 and the anode wiring 13F. Finally, the reference potential wiring 14F is connected to the reference potential wiring 14M of the second wiring layer via a through conductor 14V.

[0129] That is, in the light-emitting device 4', it is also arranged in the same way as the light-emitting device 4, such that, when viewed from above, the cathode wiring 12, anode wiring 13F, and reference potential wiring 14F in the first wiring layer of the wiring substrate 10 coincide with the reference potential wiring 14M in the second wiring layer of the wiring substrate 10. However, in the first wiring layer of the wiring substrate 10, in addition to the portion where the cathode wiring 12 and anode wiring 13F are provided, the reference potential wiring 14F is provided. Here, the area where the reference potential wiring 14M in the second wiring layer coincides with the anode wiring 13F in the first wiring layer is set to be smaller than the area where the reference potential wiring 14M in the second wiring layer coincides with the reference potential wiring 14-3F in the first wiring layer.

[0130] Furthermore, in the first wiring layer, the area of ​​the anode wiring 13F is set to be smaller than the area of ​​the reference potential wiring 14F.

[0131] Furthermore, the anode wiring 13F in the first wiring layer of the wiring substrate 10 is provided in such a way that it occupies less than 50% of the area of ​​the surface of the wiring substrate 10.

[0132] In the current design of the wiring board 10, the cathode wiring 12 and anode wiring 13F are generally placed in the portion where electrical connection is required in the first wiring layer, while the reference potential wiring 14F is placed in other portions. Thus, the area facing each other between the anode wiring 13F in the first wiring layer and the reference potential wiring 14F in the second wiring layer of the wiring board 10 is smaller than that of the light-emitting device 4. Therefore, the capacitor 70C (refer to...) containing parasitic capacitance... Figure 5 The capacitance is small. Therefore, in the light-emitting device 4', the capacitor 70C, which contains parasitic capacitance, is difficult to supply the portion of the driving current pulse that causes the light source 20 to emit light at the beginning of its rise ( Figure 8 The current (as shown in α). That is, in the light-emitting device 4', it is difficult to shorten the rise time of the driving current pulse supplied to the light source 20.

[0133] As explained above, in the light-emitting device 4 to which this embodiment is applied, the area of ​​the anode wiring 13F is set to be large, so that the area of ​​the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer facing each other with the insulating layer 11A sandwiched between them is increased. This increases the capacitance of the capacitor 70C, which contains the parasitic capacitance formed between the anode wiring 13F and the reference potential wiring 14M, thereby shortening the rise time of the driving current pulse supplied to the light source 20. In other words, in the light-emitting device 4, the parasitic capacitance (capacitive component) between the wirings sandwiched with the insulating layer 11 is utilized more extensively.

[0134] The light output of the light source 20 in the light-emitting device 4 is 2W to 4W. This high-output light source 20 generates significant heat. Therefore, efficient heat dissipation from the light source 20 is required. Consequently, the light source 20 can be placed on an insulating heat-dissipating substrate with a thermal conductivity greater than that of the wiring board 10, and the heat-dissipating substrate can be placed on the wiring board 10. Furthermore, the thermal conductivity of the insulating layer called FR-4 used in the wiring board 10 is approximately 0.4W / m·K. Therefore, as a heat-dissipating substrate, a substrate with a thermal conductivity of 10W / m·K or higher is preferred, and a substrate with a thermal conductivity of 50W / m·K or higher is even more preferred. A substrate with a thermal conductivity of 100W / m·K or higher can be exemplified by alumina (Al2O3) with a thermal conductivity of 20W / m·K to 30W / m·K. Moreover, as a substrate with a thermal conductivity of 50W / m·K or higher, silicon nitride (Si3N4) with a thermal conductivity of approximately 85W / m·K can be exemplified. Furthermore, aluminum nitride (AlN) with a thermal conductivity of 150 W / m·K to 250 W / m·K can be used as a substrate material for heat dissipation. These are sometimes referred to as ceramic materials. It is preferable that the entire heat dissipation substrate contains ceramic materials. Moreover, the heat dissipation substrate can also be other insulating materials with high thermal conductivity, such as undoped silicon (Si).

[0135] Furthermore, in the light-emitting device 4 to which this embodiment is applied, a capacitor 70A, which is a low ESL capacitor, and a capacitor 70B, which is a non-ESL capacitor, are used. However, if the capacitance of the capacitor 70C, which includes parasitic capacitance, is large, then the capacitor 70A, which is a low ESL capacitor, may not be used.

[0136] Furthermore, in the light-emitting device 4 to which this embodiment is applied, the parasitic capacitance generated between the anode wiring 13F in the first wiring layer of the wiring substrate 10 and the reference potential wiring 14M in the second wiring layer is used as capacitor 70C. Alternatively, a wiring layer (here referred to as a capacitor layer) supplying a reference potential may be provided in the insulating layer 11A at a position opposite to the anode wiring 13F, and the capacitor 70C may be used, comprising the anode wiring 13F and the capacitor layer. Another example of a capacitor comprising the anode wiring 13F and the capacitor layer being a capacitor component.

[0137] In addition, in the light-emitting device 4 applicable to this embodiment, a light source 20 and a driving part 50 are provided on the surface of the wiring board 10. However, the circuit board with the light source 20 and the circuit board with the driving part 50 can also be independently constructed, and they are connected by flexible flat cable (FFC) or flexible printed circuit (FPC).

[0138] Furthermore, in the light-emitting device 4 applicable to this embodiment, as an example of an optical component, a light-diffusing component 30 is used. This light-diffusing component 30 diffuses the incident light to change its spread angle in an amplified manner and then emits it. The optical component may also be a diffractive optical element (DOE) or the like, which causes the light to be emitted in a direction different from the incident direction. Moreover, the optical component may also be a transparent component such as a condenser lens, a microlens, or a protective cover.

Claims

1. A light emitting device comprising: a wiring substrate having a first wiring layer, and a second wiring layer which is adjacent to the first wiring layer via an insulating layer; and a laser portion having a cathode electrode and an anode electrode, which is mounted on the wiring substrate and is driven by a low-side drive, wherein a cathode wiring connected to the cathode electrode, and an anode wiring connected to the anode electrode are provided in the first wiring layer, a reference potential wiring connected to a reference potential is provided in the first wiring layer and the second wiring layer, an area in which the reference potential wiring of the second wiring layer coincides with the anode wiring is larger than an area in which the reference potential wiring of the second wiring layer coincides with the reference potential wiring of the first wiring layer.

2. The light emitting device according to claim 1, wherein an area of the anode wiring is larger than an area of the reference potential wiring of the first wiring layer.

3. The light emitting device according to claim 1 or 2, wherein the anode wiring has an area of 50% or more of an area of the wiring substrate.

4. The light emitting device according to claim 1 or 2, wherein the anode wiring has an area of 75% or more of an area of the wiring substrate.

5. The light emitting device according to claim 1 or 2, wherein a thickness of the insulating layer is 100 μm or less.

6. The light emitting device according to claim 1 or 2, wherein the laser portion is a surface-emitting laser element array in which a plurality of surface-emitting laser elements are formed on a common semiconductor substrate.

7. The light emitting device according to claim 1 or 2, wherein an optical member which changes at least one of a direction and an expansion angle of light emitted from the laser portion is provided.

8. An optical device comprising: the light emitting device according to any one of claims 1 to 7; and a light receiving portion which receives reflected light emitted from a laser portion included in the light emitting device and reflected by a measured object, the light receiving portion outputs a signal which corresponds to a time of light from emission from the laser portion until reception by the light receiving portion.

9. A measuring device comprising: the optical device according to claim 8; and a three-dimensional shape determining portion which determines a three-dimensional shape of a measured object based on reflected light from the measured object which is emitted from a laser portion included in the optical device and received by a light receiving portion included in the optical device, the measuring device measures the three-dimensional shape of the measured object.

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