A hardware protection circuit for photovoltaic inverter

Abstract

The invention provides a hardware protection circuit for a photovoltaic inverter, which can take into account the advantages of fault protection response time and effective hardware comprehensive protection when a hardware fault exists; the circuit comprises: a main power topology module, which is used for fault signal detection and sending the signal to a hardware protection signal sampling module; a drive control module, which is used for providing a drive signal to the main power topology module; a hardware protection signal sampling module, which is used for detecting the fault signal received from the main power topology module and sending the generated triggering hardware fault signal to a D-type trigger hardware protection execution module; a D-type trigger hardware protection execution module, which is used for blocking all drive signals after receiving the triggering hardware fault signal; and an MCU module, which is connected to the main power topology module, the drive control module, the hardware protection signal sampling module and the D-type trigger hardware protection execution module and is used for receiving signals from each functional module and providing timely feedback.

Description

Technical Field

[0001] The invention relates to the technical field of photovoltaic inverters and energy storage, and in particular to a hardware protection circuit for photovoltaic inverters. Background Art

[0002] The hardware protection circuits of traditional photovoltaic inverters, such as OCP overcurrent protection and bus OVP overvoltage protection, all connect the cathode of the diode at the protection design point and the anode of the diode at the output end of the switch tube drive circuit. When the hardware protection is not triggered, the protection design point is high, the diode is cut off, and the power switch circuit works normally. When the OCP or OVP fault is triggered, the corresponding protection design point level is converted from the normal high level to the low level, so the corresponding switch tube drive circuit output is clamped to a low level through the diode, thereby disconnecting the power circuit to achieve the function of the protection circuit.

[0003] However, the above inverter protection circuit also has the following disadvantages:

[0004] 1) The protection action time is slow, the actual protection working point is slightly higher than the design value, and there is a certain risk of damage to the hardware circuit;

[0005] 2) Due to the existence of the clamping diode, the hardware circuit is greatly affected by temperature. At high and low temperatures, the protection point action time varies greatly.

[0006] Therefore, if a single point failure occurs in the hardware (power switch tube failure), if the hardware protection is triggered and the fault cannot be completely disconnected, it will cause further risk of hardware damage. Summary of the invention

[0007] In view of the above problems, the present invention provides a hardware protection circuit for a photovoltaic inverter, which can take into account the advantages of fault protection response time and effective hardware comprehensive protection when a hardware fault exists.

[0008] The technical solution is as follows: A hardware protection circuit for a photovoltaic inverter, characterized in that it includes:

[0009] A main power topology module, connected to the hardware protection signal sampling module, for detecting fault signals and sending the signals to the hardware protection signal sampling module;

[0010] A drive control module, connected to the main power topology module, and used to provide a drive signal for the main power topology module;

[0011] A hardware protection signal sampling module is connected to the D-type trigger hardware protection execution module, and is used to detect the fault signal received from the main power topology module and send the generated trigger hardware fault signal to the D-type trigger hardware protection execution module;

[0012] A D-type trigger hardware protection execution module, connected to the drive control module, for blocking all drive signals after receiving a trigger hardware fault signal;

[0013] The MCU module is connected to the main power topology module, the drive control module, the hardware protection signal sampling module, and the D-type trigger hardware protection execution module, and is used to receive signals from each functional module and provide timely feedback.

[0014] It is further characterized by:

[0015] The main power topology module includes a battery BT1, a solar cell PV1, Hall sensors CT1-CT3, inductors L1-L4, MOS tubes Q1-Q9, a diode D1, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, and a comparator U1; the positive electrode of the battery BT1 is connected to one end of the inductor L1 through the Hall sensor CT1, the other end of the inductor L1 is connected to the drain of the MOS tube Q1 and the source of the MOS tube Q2, the drain of the MOS tube Q2 is connected to the negative electrode of the diode D1, the resistor R1, one end of the capacitor C1, the drain of the MOS tube Q4, and the drain of the MOS tube Q6, the other end of the resistor R1 is connected to one end of the resistor R2, and the positive input end of the comparator U1, the negative input end of the comparator U1 is connected to the output end of the comparator U1, the other end of the resistor R2 is grounded, the negative electrode of the battery BT1 is connected to the source of the MOS tube Q1 and then grounded, the positive electrode of the solar cell PV1 is connected to the negative electrode of the Hall sensor The cathode of the solar cell PV1 is connected to the source of the MOS tube Q3 and then to ground. The source of the MOS tube Q4 is connected to the drains of the MOS tube Q5 and the MOS tube Q8, and the connection end between the MOS tube Q4 and the MOS tube Q5 is connected to one end of the inductor L3 through the Hall sensor CT3. The source of the MOS tube Q6 is connected to the drains of the MOS tube Q7 and the MOS tube Q9 and one end of the inductor L4. The other end of the capacitor C1 is connected to the source of the MOS tube Q5 and the MOS tube Q7 and then to ground. The source of the MOS tube Q8 is connected to the source of the MOS tube Q9. The other end of the inductor L3 is connected to one end of the capacitor C2. The other end of the inductor L4 is connected to the other end of the capacitor C2. A signal source Grid is connected in parallel to both ends of the capacitor C2.

[0016] The drive control module includes resistors R3~R11, photoelectric couplers U2~U10, transistors Q10, transistors Q11, and capacitor C3; the MCU module includes MCU; the positive terminals of the photoelectric couplers U2~U10 are all connected to a 5V_W drive power supply, the negative terminals of the photoelectric couplers U2~U10 are respectively connected to different PWM output ports on the MCU after passing through the resistors R3~R11, and the connection terminals of the resistors R6 and R7 after being connected are connected to the same PWM output port on the MCU, the resistors R8 and R9 are connected to share the same PWM output port on the MCU, and the collectors of the photoelectric couplers U2~U10 are all connected to the power supply VCC and then grounded. The collector of the photoelectric coupler U2 is connected to the collector of the photoelectric coupler U3, and the emitters of the photoelectric couplers U2 to U10 are respectively connected to the gates of the MOS transistors Q3, Q1, Q2, Q4, Q7, Q6, Q5, Q8, and Q9, and all serve as driving signal terminals. The emitter of the transistor Q10 is grounded after passing through the power supply VCC, and the collector of the transistor Q10 is connected to the 5V_W driving power supply and one end of the capacitor C3. The base of the transistor Q10 is connected to the collector of the transistor Q11, and the emitter of the transistor Q11 is connected to the other end of the capacitor C3 and then grounded;

[0017] The hardware protection signal sampling module includes resistors R12 to R21, comparator U11, comparator U12_A, comparator U12_B, comparator U13, comparator U14_A, comparator U14_B, NAND gate U15_A, NAND gate U15_B, NAND gate U15_C, and NAND gate U15_D; one end of the resistor R12, resistor R14, resistor R17, and resistor R19 are connected to the positive electrode of the reference power supply VCC1, the other end of the resistor R12 is connected to one end of the resistor R13 and the positive input end of the comparator U11, and the other end of the resistor R13 is connected to the positive input end of the comparator U11. The other end of the resistor R14 is connected to one end of the resistor R15 and the positive input end of the comparator U12_A. The other end of the resistor R15 is connected to one end of the resistor R16 and the negative input end of the comparator U12_B. The other end of the resistor R16 is connected to the negative electrode of the reference power supply VCC1 and then to ground. The negative input end of the comparator U12_A is connected to the positive input end of the comparator U12_B. The output end of the comparator U12_A is connected to the output end of the comparator U12_B. The other end of the resistor R17 is connected to one end of the resistor R18 and the positive input end of the comparator U1 3, the other end of the resistor R18 is grounded; the other end of the resistor R19 is connected to one end of the resistor R20 and the positive input end of the comparator U14_A, the other end of the resistor R20 is connected to one end of the resistor R21 and the negative input end of the comparator U14_B, the negative input end of the comparator U14_A is connected to the positive input end of the comparator U14_B, the other end of the resistor R21 is grounded, and the output end of the comparator U14_A is connected to the output end of the comparator U14_B; the two PWM The output ports are respectively connected to the two input terminals of the NAND gate U15_A, the two PWM output ports corresponding to the resistor R6 and the resistor R8 are respectively connected to the two input terminals of the NAND gate U15_B, the two PWM output ports corresponding to the resistor R6 and the resistor R10 are respectively connected to the two input terminals of the NAND gate U15_C, the two PWM output ports corresponding to the resistor R8 and the resistor R11 are respectively connected to the two input terminals of the NAND gate U15_D, and the output terminals of the NAND gate U15_A, the NAND gate U15_B, the NAND gate U15_C, and the NAND gate U15_D are connected;

[0018] The D-type trigger hardware protection execution module includes a D trigger U16, resistors R22-R30, switch diodes D2-D4, MOS tubes Q12, MOS tubes Q13, and capacitor C4. The models of the switch diodes D2-D4 are all BAV70; the 1D pin end of the D trigger U16 is connected to the power supply VCC through the resistor R22, and is connected to the connection end between the output ends of the comparator U12_A and the comparator U12_B; the 2D pin end of the D trigger U16 is connected to the power supply VCC through the resistor R23, and is connected to the output end of the comparator U11; the D The 3D pin end of the D flip-flop U16 is connected to the power supply VCC through the resistor R24 ​​and is connected to the connection end between the output ends of the comparator U14_A and the comparator U14_B. The 4D pin end of the D flip-flop U16 is connected to the power supply VCC through the resistor R25 and is connected to the output end of the comparator U13. The 5D pin end of the D flip-flop U16 is connected to the power supply VCC through the resistor R26 and is connected to the connection end between the output ends of the NAND gate U15_A, the NAND gate U15_B, the NAND gate U15_C and the NAND gate U15_D. The D flip-flop U16 The pin end is connected to an input end of the switching diode D2, and the D flip-flop U16 The pin end is connected to the other input end of the switch diode D2, and the D trigger U16 The pin end is connected to an input end of the switching diode D3, and the D flip-flop U16 The pin end is connected to the other input end of the switch diode D3, and the D trigger U16 The pin end is connected to an input end of the switching diode D4, and the other input end of the switching diode D4 is vacant; the output ends of the switching diodes D2 to D4 are all connected to one end of the resistor R27 and the drain of the MOS tube Q12, the source of the MOS tube Q12 is grounded, and the gate of the MOS tube Q12 is connected to the reset pin end on the MCU after passing through the resistor R30, the other end of the resistor R27 is connected to one end of the resistor R28 and the gate of the MOS tube Q13, the other end of the resistor R28 is connected to the source of the MOS tube Q13 and then grounded, the drain of the MOS tube Q13 is connected to one end of the resistor R29, the LE pin end of the D trigger U16, and the base of the transistor Q11, and the D trigger U16 is connected to the LE pin end of the D trigger U16. The pin end is grounded, the other end of the resistor R29 is connected to the power supply VCC, the VCC pin end of the D flip-flop U16 is connected to one end of the capacitor C4 and then to the power supply VCC, and the GND pin end of the D flip-flop U16 is connected to the other end of the capacitor C4 and then to ground.

[0019] The beneficial effects of the present invention are that, through the correspondingly connected main power topology module, drive control module, hardware protection signal sampling module, D-type trigger hardware protection execution module, and MCU module, a fault trigger signal is obtained by detection, and a fault protection mechanism is executed in a timely manner in response, and the fault response is fast, and inverter overcurrent protection, DC bus overvoltage protection, photovoltaic component input current overcurrent protection, energy storage battery charging and discharging current overcurrent protection, and drive logic fault protection functions can be realized, hardware reliability is improved, and the influence of temperature drift on the performance of the hardware protection circuit is improved, thereby solving the problems of slow existing protection action time and the risk of further hardware damage caused by the inability to completely disconnect the fault if the hardware protection is triggered, and having good economic use value. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural block diagram of the present invention;

[0021] Figure 2 It is a circuit schematic diagram of the main power topology module in the present invention;

[0022] Figure 3 It is a circuit schematic diagram of the drive control module in the present invention;

[0023] Figure 4 It is a circuit schematic diagram of the hardware protection signal sampling module in the present invention;

[0024] Figure 5 It is a circuit schematic diagram of the D-type flip-flop hardware protection execution module in the present invention;

[0025] Figure 6 It is a packaging diagram of the D-type flip-flop in the present invention. DETAILED DESCRIPTION

[0026] like Figure 1 to Figure 6 As shown, the present invention provides a hardware protection circuit for a photovoltaic inverter, comprising:

[0027] The main power topology module 1 is connected to the hardware protection signal sampling module 3 and is used for fault signal detection and sending the signal to the hardware protection signal sampling module 3;

[0028] A drive control module 2 is connected to the main power topology module 1 and is used to provide a drive signal to the main power topology module 1;

[0029] The hardware protection signal sampling module 3 is connected to the D-type trigger hardware protection execution module 4, and is used to detect the fault signal received from the main power topology module 1, and send the generated trigger hardware fault signal to the D-type trigger hardware protection execution module 4;

[0030] A D-type trigger hardware protection execution module 4 is connected to the drive control module 2 and is used to block all drive signals after receiving a trigger hardware fault signal;

[0031] The MCU module 5 is connected to the main power topology module 1, the drive control module 2, the hardware protection signal sampling module 3, and the D-type trigger hardware protection execution module 4, and is used to receive signals from various functional modules and provide timely feedback.

[0032] Figure 2 In the embodiment, the main power topology module 1 includes a battery BT1, a solar cell PV1, Hall sensors CT1-CT3, inductors L1-L4, MOS tubes Q1-Q9, a diode D1, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, and a comparator U1; the positive electrode of the battery BT1 is connected to one end of the inductor L1 through the Hall sensor CT1, the other end of the inductor L1 is connected to the drain of the MOS tube Q1 and the source of the MOS tube Q2, the drain of the MOS tube Q2 is connected to the negative electrode of the diode D1, the resistor R1, one end of the capacitor C1, the drain of the MOS tube Q4, and the drain of the MOS tube Q6, the other end of the resistor R1 is connected to one end of the resistor R2, and the positive input end of the comparator U1, the negative input end of the comparator U1 is connected to the output end of the comparator U1, the other end of the resistor R2 is grounded, the negative electrode of the battery BT1 is connected to the source of the MOS tube Q1 and then to the ground, the positive input end of the solar cell PV1 is connected to the negative input end of the MOS tube Q1, and the negative input end of the MOS tube Q2 is connected to the negative input end of the MOS tube Q1. The positive electrode is connected to one end of the inductor L2 through the Hall sensor CT2, the other end of the inductor L2 is connected to the drain of the MOS transistor Q3 and the positive electrode of the diode D1, the negative electrode of the solar cell PV1 is connected to the source of the MOS transistor Q3 and then grounded, the source of the MOS transistor Q4 is connected to the drains of the MOS transistor Q5 and the MOS transistor Q8, and the connection end point between the MOS transistor Q4 and the MOS transistor Q5 is connected to one end of the inductor L3 through the Hall sensor CT3, the source of the MOS transistor Q6 is connected to the drains of the MOS transistor Q7 and the MOS transistor Q9, and one end of the inductor L4, the other end of the capacitor C1 is connected to the source of the MOS transistor Q5 and the MOS transistor Q7 and then grounded, the source of the MOS transistor Q8 is connected to the source of the MOS transistor Q9, the other end of the inductor L3 is connected to one end of the capacitor C2, the other end of the inductor L4 is connected to the other end of the capacitor C2, and the signal source Grid is connected in parallel to both ends of the capacitor C2;

[0033] Among them, the Hall sensor CT1 in the main power topology module 1 is a DC energy storage battery charging and discharging current detection Hall device, and its output signal IBAT_sense detection signal will be sent to the connection end between the negative input terminal of the comparator U12_A and the positive input terminal of the comparator U12_B in the hardware protection signal sampling module 3 to perform battery current hardware overcurrent detection; the Hall sensor CT2 is a PV photovoltaic component input current detection Hall device, and its output signal IPV_sense signal will be sent to the negative input terminal of the comparator U11 in the hardware protection signal sampling module 3 to perform PV component The Hall sensor CT3 is an AC inverter output current detection Hall device, and its output signal IINV_sense will be sent to the connection end between the negative input terminal of the comparator U14_A and the positive input terminal of the comparator U14_B in the hardware protection signal sampling module 3 to perform inverter overcurrent detection; and it also generates a VBUS_sense detection signal by detecting the voltage of the capacitor C1 through a resistor voltage divider network circuit and an op amp follower circuit, and the signal is sent to the negative input terminal of the comparator U13 in the hardware protection signal sampling module 3 for bus overvoltage detection.

[0034] Figure 3In the embodiment, the drive control module 2 includes resistors R3-R11, photoelectric couplers U2-U10, transistors Q10, transistors Q11, and capacitor C3; the MCU module 5 includes an MCU, and the MCU uses an existing general-purpose device; the positive terminals of the photoelectric couplers U2-U10 are connected to a 5V_W drive power supply, and the negative terminals of the photoelectric couplers U2-U10 are respectively connected to different PWM output ports on the MCU after passing through resistors R3-R11, and the connection terminals of the resistors R6 and R7 are connected to the same PWM output port on the MCU, wherein the different PWM output ports on the MCU are respectively recorded as PWM _503, PWM_504, PWM_603, PWM_701, PWM_703, PWM_705, PWM_706, that is, resistor R3 is connected to the PWM output port PWM_603 on the MCU, resistor R4 is connected to the PWM output port PWM_503 on the MCU, resistor R5 is connected to the PWM output port PWM_504 on the MCU, the connection endpoint between resistors R6 and R7 is connected to the PWM output port PWM_701 on the MCU, the connection endpoint between resistors R8 and R9 is connected to the PWM output port PWM_703 on the MCU, and resistor R10 is connected The PWM output port PWM_705 on the MCU, the resistor R11 is connected to the PWM output port PWM_706 on the MCU; the resistors R8 and R9 are connected to share the same PWM output port on the MCU, the collectors of the photocouplers U2 to U10 are connected to the power supply VCC and then grounded, and the collector of the photocoupler U2 is connected to the collector of the photocoupler U3, and the emitters of the photocouplers U2 to U10 are respectively connected to the MOS tubes Q3, MOS tube Q1, MOS tube Q2, MOS tube Q4, MOS tube Q7, MOS tube Q6, MOS tube Q5, MOS tube Q8, and MOS tube Q9. The gate of the S transistor Q9 is used as a driving signal terminal, and the driving signals are respectively recorded as Gate_603, Gate_503, Gate_504, Gate_701, Gate_704, Gate_703, Gate_702, Gate_705, and Gate_706; the emitter of the transistor Q10 is grounded after passing through the power supply VCC, the collector of the transistor Q10 is connected to the 5V_W driving power supply and one end of the capacitor C3, the base of the transistor Q10 is connected to the collector of the transistor Q11, and the emitter of the transistor Q11 is connected to the other end of the capacitor C3 and then grounded;

[0035] Among them, the base of the transistor Q11 is connected to the HW_STOP_C global control signal, and this signal is led out from one end of the resistor R29 in the D-type trigger hardware protection execution module 4. When the hardware circuit works normally, the HW_STOP_C global control signal is high level, providing a positive driving current for the base of the transistor Q10, and the transistor Q11 is saturated and turned on. Therefore, the base of the transistor Q10 is pulled to a low level, and there is a negative driving current at the base of the transistor Q10. The transistor Q10 will also be saturated and turned on. At this time, a 5V_W driving power supply is generated by the power supply 5V. When the hardware circuit triggers any fault, the HW_STOP_C global control signal is low level, and the transistor Q11 will be turned off at this time, so the transistor Q10 will also be turned off, and the 5V_W driving power supply for the driving circuit will be cut off.

[0036] Figure 3 In the figure, the marked VC_701 is only used as the voltage terminal of the power supply VCC. For example, VC_701 is the voltage terminal of the power supply VCC where the optocoupler U5 is located. Similar marks in other figures are not repeated.

[0037] Figure 4In the embodiment, the hardware protection signal sampling module 3 includes resistors R12 to R21, a comparator U11, a comparator U12_A, a comparator U12_B, a comparator U13, a comparator U14_A, a comparator U14_B, a NAND gate U15_A, a NAND gate U15_B, a NAND gate U15_C, and a NAND gate U15_D; one end of the resistor R12, the resistor R14, the resistor R17, and the resistor R19 are all connected to the positive electrode of the reference power supply VCC1, and the other end of the resistor R12 is connected to one end of the resistor R13 and the positive input end of the comparator U11. The other end of the resistor R13 is grounded, the other end of the resistor R14 is connected to one end of the resistor R15 and the positive input end of the comparator U12_A, the other end of the resistor R15 is connected to one end of the resistor R16 and the negative input end of the comparator U12_B, the other end of the resistor R16 is connected to the negative electrode of the reference power supply VCC1 and then grounded, the negative input end of the comparator U12_A is connected to the positive input end of the comparator U12_B, and the output end of the comparator U12_A is connected to the output end of the comparator U12_B; the other end of the resistor R17 is connected to one end of the resistor R18 and the comparator The positive input terminal of the comparator U13 is connected, and the other end of the resistor R18 is grounded; the other end of the resistor R19 is connected to one end of the resistor R20 and the positive input terminal of the comparator U14_A, and the other end of the resistor R20 is connected to one end of the resistor R21 and the negative input terminal of the comparator U14_B. The negative input terminal of the comparator U14_A is connected to the positive input terminal of the comparator U14_B, and the other end of the resistor R21 is grounded. The output terminal of the comparator U14_A is connected to the output terminal of the comparator U14_B; the two PWM output terminals connected to the resistors R4 and R5 are connected. The two PWM output ports connected to the resistor R6 and the resistor R8 are connected to the two input terminals of the NAND gate U15_B respectively, the two PWM output ports connected to the resistor R6 and the resistor R10 are connected to the two input terminals of the NAND gate U15_C respectively, the two PWM output ports connected to the resistor R8 and the resistor R11 are connected to the two input terminals of the NAND gate U15_D respectively, and the output terminals of the NAND gate U15_A, the NAND gate U15_B, the NAND gate U15_C, and the NAND gate U15_D are connected;

[0038] The reference power supply VCC1 (3VREF voltage) provides an analog voltage to the positive input terminal of the comparator U11 through the voltage-dividing resistors R12 and R13. The analog voltage value is the trigger threshold of the overcurrent of the PV module. The negative input terminal of the comparator U11 is connected to the IPV_sense signal generated by the Hall sensor CT2. The output of the comparator U11 is the HW_STOP_PV_OCP signal, which is sent to the 2D pin of the D flip-flop U16.

[0039] The reference power supply VCC1 (3VREF voltage) provides an analog voltage to the positive input terminal of the comparator U12_A and an analog voltage to the negative input terminal of the comparator U12_B through the voltage-dividing resistors R14, R15 and R16. The analog voltage value at the positive terminal of the comparator U12_A is the trigger threshold of the battery discharge overcurrent, and the analog voltage value at the negative terminal of the comparator U12_B is the trigger threshold of the battery charge overcurrent; the negative input terminal of the comparator U12_A and the positive input terminal of the comparator U12_B are short-circuited together and connected to the IBAT_sense detection signal generated by the Hall sensor CT1; the outputs of the comparators U12_A and U12_B are HW_STOP_BAT_OCP signals, which are sent to the 1D pin of the D-type flip-flop U16;

[0040] The reference power supply VCC1 (3VREF voltage) is provided to the positive input terminal of the comparator U14_A and the negative input terminal of the comparator U14_B via the voltage-dividing resistors R19, R20 and R21. The analog voltage value at the positive terminal of the comparator U14_A is the trigger threshold of the overcurrent in the positive half cycle of the inverter AC current. The analog voltage value at the negative terminal of the comparator U14_B is the trigger threshold of the overcurrent in the negative half cycle of the inverter AC current. The negative input terminal of the comparator U14_A and the positive input terminal of the comparator U14_B are short-circuited together and connected to the signal IINV_sense generated by the Hall sensor CT3. The outputs of the comparator U14_A and the comparator U12_4 are the HW_STOP_INV_OCP signal, which is sent to the 3D pin of the D flip-flop U16.

[0041] The reference power supply VCC1 (3VREF voltage) provides an analog voltage to the positive input terminal of the comparator U13 through the voltage-dividing resistors R17 and R18. The analog voltage value is the trigger threshold of the DC bus overvoltage. The negative input terminal of the comparator U13 is connected to the VBUS_sense detection signal output from the comparator U1. The output of the comparator U13 is the HW_STOP_BUS_OVP signal, which is sent to the 4D pin of the D-type flip-flop U16.

[0042] The outputs of NAND gate U15_A, NAND gate U15_B, NAND gate U15_C, and NAND gate U15_D are HW_STOP_LOGIC fault detection signals, and the HW_STOP_LOGIC fault detection signals are sent to the 5D pin end of the D flip-flop U16;

[0043] Let’s take PV module overcurrent as an example. Figure 4The working principle of the hardware fault sampling circuit is that only when the IPV_sense signal input voltage is higher than the positive trigger threshold of the comparator U11, the comparator U11 output action is triggered, and the HW_STOP_PV_OCP signal becomes a low level and is sent to the D-type trigger hardware protection execution module 4 circuit, triggering the output port 19 pin of the D-type trigger U16 to generate a high level to trigger the hardware fault.

[0044] Figure 5 In the embodiment, the D-type flip-flop hardware protection execution module 4 includes a D-type flip-flop U16, resistors R22-R30, switch diodes D2-D4, MOS tubes Q12, MOS tubes Q13, and capacitor C4. The switch diodes D2-D4 are all of BAV70 type; the MOS tube Q13 uses an NPN transistor BCR116; the D-type flip-flop U16 uses a Texas Instruments TI SN74HC563DW, which uses an industry-standard SOIC-20 SMD package with 8-way tri-state gate outputs and a total of 20 pins; among which pin Pin10 is the power ground GND, Pin20 is the power supply VCC, and Pin1 is The D-type flip-flop enable pin is normally low level valid. In the circuit of the present invention, it is directly connected to the power ground to ensure that the D-type flip-flop is enabled; Pin11 is LE, which is the latch control pin of the D flip-flop U16. Normally, the high level is valid. At this time, the output of the D flip-flop U16 It is the inverted signal of the input signal; Pin2-Pin9 are the input pins of the 8-way D-type trigger 100, which can collect 8 analog signals in total. The 5 types of hardware protection provided by the present invention use the Pin2-Pin6 pins of the D trigger U16, wherein the Pin2 pin is connected to the energy storage battery charging and discharging overcurrent detection signal, the Pin3 pin is connected to the photovoltaic PV input side overcurrent detection signal, the Pin4 pin is connected to the inverter output overcurrent detection signal, the Pin5 pin is connected to the DC bus overvoltage detection signal and the Pin6 pin is connected to the drive logic fault detection signal. Pin19-pin12 are 8-way D-type trigger output pins, providing a total of 8-way three-state gate logic output signals. The 5 types of hardware trigger signals provided by the present invention use 5 output pins, namely Pin19-Pin15, wherein Pin19 is an energy storage battery overcurrent trigger signal, which is connected to the fault execution circuit by connecting one input anode of the switch diode D2, Pin18 is a photovoltaic PV side input overcurrent trigger signal, which is connected to the fault execution circuit by connecting another input anode of the switch diode D2; Pin17 is an inverter output overcurrent trigger signal, which is connected to the fault execution circuit by connecting one anode of the switch diode D3, Pin16 is a DC bus overvoltage trigger signal, which is connected to the fault execution circuit by connecting another anode of the switch diode D3; Pin15 is a drive logic fault trigger signal, which is connected to the fault execution circuit by connecting one anode of the switch diode D4; the above 5 types of fault trigger signals are connected to the MOS tube Q13 after passing through the switch diode;

[0045] Figure 5 The D flip-flops U16A and U16B in the circuit are both used as D flip-flops U16; the 1D pin end of the D flip-flop U16 is connected to the power supply VCC via a resistor R22, and is connected to the connection end between the output ends of the comparators U12_A and U12_B; the 2D pin end of the D flip-flop U16 is connected to the power supply VCC via a resistor R23, and is connected to the output end of the comparator U11; the 3D pin end of the D flip-flop U16 is connected to the power supply VCC via a resistor R24, The 4D pin of the D flip-flop U16 is connected to the power supply VCC via a resistor R25 and is connected to the output end of the comparator U13. The 5D pin of the D flip-flop U16 is connected to the power supply VCC via a resistor R26 and is connected to the connection end between the output ends of the NAND gate U15_A, the NAND gate U15_B, the NAND gate U15_C and the NAND gate U15_D. The pin end is connected to one input end of the switching diode D2, and the D flip-flop U16 The pin end is connected to the other input end of the switching diode D2, and the D flip-flop U16 The pin end is connected to one input end of the switching diode D3, and the D flip-flop U16 The pin end is connected to the other input end of the switching diode D3, and the D flip-flop U16 The pin end is connected to an input end of the switching diode D4, and the other input end of the switching diode D4 is vacant; the output ends of the switching diodes D2 to D4 are all connected to one end of the resistor R27 and the drain of the MOS tube Q12, the source of the MOS tube Q12 is grounded, and the gate of the MOS tube Q12 is connected to the reset pin end on the MCU through the resistor R30 to provide a reset signal HW_RESET_P; the other end of the resistor R27 is connected to one end of the resistor R28 and the gate of the MOS tube Q13, the other end of the resistor R28 is connected to the source of the MOS tube Q13 and then grounded, the drain of the MOS tube Q13 is connected to one end of the resistor R29, the LE pin end of the D trigger U16, and the base of the triode Q11, and the connection point is the global control signal HW_STOP_C of the circuit of the present invention; the D trigger U16 The pin end is grounded, the other end of the resistor R29 is connected to the power supply VCC, the VCC pin end of the D flip-flop U16 is connected to one end of the capacitor C4 and then to the power supply VCC, the GND pin end of the D flip-flop U16 is connected to the other end of the capacitor C4 and then to the ground, and the capacitor C4 provides power supply filtering function for the D flip-flop U16.

[0046] In order to further understand the function of the circuit of the present invention, a brief explanation and discussion is given below for the specific application principle of the circuit. The following table is the function truth table of the D flip-flop U16, and in the truth table, L represents low; H represents high; and Z represents high impedance state; Represented as output Keep its original state value, the trigger will not change state, and the output will remain unchanged; × indicates an invalid state; the above definitions are all prior art;

[0047]

[0048] When the hardware protection circuit works normally, the D-type flip-flop needs to meet the following three conditions:

[0049] (1) Enable pin 1 of the D-type flip-flop It is a low level. In the present invention, Pin1 is directly connected to the power ground GND, so the enabling condition is met.

[0050] (2) The latch pin Pin11 LE of the D-type flip-flop is at a high level. In the present invention, Pin11 is pulled up to the power supply VCC through the resistor R29, so the condition is met.

[0051] (3) The input signal of the D-type flip-flop must be at a high level to make the level of the output Q a low level, so that the switching diodes D2, D3 and D4 are turned off. In the circuit designed by the present invention, the input signal Pin2 of the D-type flip-flop, i.e., the overcurrent detection signal of the energy storage battery charging and discharging, is pulled up to the power supply VCC through the resistor R22; the input signal Pin3, i.e., the overcurrent detection signal of the DC PV side input, is pulled up to the power supply VCC through the resistor R23; the input signal Pin4, i.e., the inverter output overcurrent detection signal, is pulled up to the power supply VCC through the resistor R24; the input signal Pin5, i.e., the DC bus overvoltage detection signal, is pulled up to the power supply VCC through the resistor R25; the input signal Pin6, i.e., the drive logic fault detection signal, is pulled up to the power supply VCC through the resistor R26; so in summary, the circuit designed by the present invention, for the D-type flip-flop input signal, is initially defaulted to a high level, so when the above 6 fault detection signals are all normal, the D-type flip-flop and the output inverting gate corresponding to the input Both output low level, so no fault condition is triggered;

[0052] The above three basic conditions are necessary conditions for the normal operation of the hardware circuit. When one of the hardware fault detection signals is triggered, the corresponding working state of the D-type flip-flop will change.

[0053] The following example illustrates the state change of the circuit of the present invention after the fault condition is triggered:

[0054] Assuming that the DC bus overvoltage detection signal detects a hardware-triggered overvoltage condition, the HW_STOP_BUS_OVP signal of Pin5 of the D-type flip-flop U16 will change from the initial high level to the low level. At this time, according to the truth table, when the signal of Pin5 is high, the corresponding output pin Pin16 of the D-type flip-flop U16 will change from the initial low level to the high level. This high level HW_STOP_BUS_P will first provide a high level to the gate of the MOS tube Q13 of the hardware fault execution circuit through the switching diode D3, so that The MOS tube Q13 is turned on. After the MOS tube Q13 is turned on, its drain, that is, the Pin11LE latch signal of the D-type flip-flop U16, is pulled low. After LE becomes low, the output state of the D-type flip-flop is latched at the high level at this time. In addition, this signal HW_STOP_C will be sent to the I / O of the main control MCU to tell the main control MCU that a hardware failure has occurred and block all power circuit drive signals. At the same time, this signal is also a global control signal in the hardware failure circuit, which will turn off the drive power supply of the power drive circuit to ensure that the inverter completely stops outputting to the outside. Figure 2It can also be seen that the circuit of the present invention will synchronously send any fault signal to the main control MCU after it is triggered, that is, the main MCU will not only know that the hardware has failed, but also can locate the specific fault location. This function will be of great help in hardware debugging. The other four fault situations are the same as the example and will not be repeated.

[0055] After a hardware failure occurs, the D flip-flop U16 will be locked in the fault state to ensure that the output port The HW_RESP_P signal is connected to the I / O control port of the main control MCU. When the inverter hardware is normal, this signal is low level. At this time, the MOS tube Q12 is cut off. When a hardware failure occurs, the software determines that the failure has occurred. When the input analog signal returns to the normal value, a high pulse signal will be sent from the I / O control port of the MCU to make the signal HW_RESP_P high. ET_P becomes high level. At this time, the gate level connected to MOS tube Q12 through resistor R20 is high, which will turn on MOS tube Q12, thereby pulling the cathodes of switching diodes D2, D3 and D4 connected to the output pins of D flip-flop U16 to a low level, and then turning off MOS tube Q13 of the fault execution circuit, so that the Pin11LE latch pin of the D-type flip-flop is restored to the high level VCC. At this time, the D-type flip-flop meets the three conditions of the normal state, that is, the input detection signal is high level, the latch signal LE is restored to a high level, and the enable signal It is always at a low level; at the same time, the signal connected to the drain of the MOS tube Q13, that is, the LE of the D-type flip-flop U16 is at a high level, so that the main control MCU knows that the hardware fault has been resolved through the level change of this hardware, so it provides various drive signals according to the previous normal working mode. So far, the D-type flip-flop has completed the reset function.

[0056] In summary, the present invention uses a D-type trigger as the core control of hardware fault protection, and provides a comprehensive protection mechanism for hardware fault types unique to photovoltaic inverters and energy storage inverters, including inverter overcurrent protection, DC bus overvoltage protection, photovoltaic component input current overcurrent protection, energy storage battery charging and discharging current overcurrent protection, and drive logic fault protection functions, and adds a software reset function after fault protection to restart the system. Compared with the existing technology, it achieves: improving the impact of temperature drift on the performance of the hardware protection circuit; providing a global hardware protection mechanism to improve hardware reliability; faster fault response, and the software reset signal needs to be restarted to eliminate the fault, avoiding frequent hiccup protection.

[0057] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0058] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A hardware protection circuit for a photovoltaic inverter, characterized in that: include: A main power topology module, connected to the hardware protection signal sampling module, for detecting fault signals and sending the signals to the hardware protection signal sampling module; A drive control module, connected to the main power topology module, and used to provide a drive signal for the main power topology module; A hardware protection signal sampling module is connected to the D-type trigger hardware protection execution module, and is used to detect the fault signal received from the main power topology module and send the generated trigger hardware fault signal to the D-type trigger hardware protection execution module; A D-type trigger hardware protection execution module, connected to the drive control module, for blocking all drive signals after receiving a trigger hardware fault signal; The MCU module is connected to the main power topology module, the drive control module, the hardware protection signal sampling module, and the D-type trigger hardware protection execution module, and is used to receive signals from each functional module and provide timely feedback; The main power topology module includes a battery BT1, a solar cell PV1, Hall sensors CT1-CT3, inductors L1-L4, MOS tubes Q1-Q9, a diode D1, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, and a comparator U1; the positive electrode of the battery BT1 is connected to one end of the inductor L1 through the Hall sensor CT1, the other end of the inductor L1 is connected to the drain of the MOS tube Q1 and the source of the MOS tube Q2, the drain of the MOS tube Q2 is connected to the negative electrode of the diode D1, the resistor R1, one end of the capacitor C1, the drain of the MOS tube Q4, and the drain of the MOS tube Q6, the other end of the resistor R1 is connected to one end of the resistor R2, and the positive input end of the comparator U1, the negative input end of the comparator U1 is connected to the output end of the comparator U1, the other end of the resistor R2 is grounded, the negative electrode of the battery BT1 is connected to the source of the MOS tube Q1 and then grounded, the positive electrode of the solar cell PV1 is connected to the negative electrode of the Hall sensor The cathode of the solar cell PV1 is connected to the source of the MOS tube Q3 and then to ground. The source of the MOS tube Q4 is connected to the drains of the MOS tube Q5 and the MOS tube Q8, and the connection end between the MOS tube Q4 and the MOS tube Q5 is connected to one end of the inductor L3 through the Hall sensor CT3. The source of the MOS tube Q6 is connected to the drains of the MOS tube Q7 and the MOS tube Q9 and one end of the inductor L4. The other end of the capacitor C1 is connected to the source of the MOS tube Q5 and the MOS tube Q7 and then to ground. The source of the MOS tube Q8 is connected to the source of the MOS tube Q9. The other end of the inductor L3 is connected to one end of the capacitor C2. The other end of the inductor L4 is connected to the other end of the capacitor C2. A signal source Grid is connected in parallel to both ends of the capacitor C2. The drive control module includes resistors R3~R11, photoelectric couplers U2~U10, transistors Q10, transistors Q11, and capacitor C3; the MCU module includes MCU; the positive terminals of the photoelectric couplers U2~U10 are all connected to a 5V_W drive power supply, the negative terminals of the photoelectric couplers U2~U10 are respectively connected to different PWM output ports on the MCU after passing through the resistors R3~R11, and the connection terminals of the resistors R6 and R7 after being connected are connected to the same PWM output port on the MCU, the resistors R8 and R9 are connected to share the same PWM output port on the MCU, and the collectors of the photoelectric couplers U2~U10 are all connected to the power supply VCC and then grounded. The collector of the photoelectric coupler U2 is connected to the collector of the photoelectric coupler U3, and the emitters of the photoelectric couplers U2 to U10 are respectively connected to the gates of the MOS transistors Q3, Q1, Q2, Q4, Q7, Q6, Q5, Q8, and Q9, and all serve as driving signal terminals. The emitter of the transistor Q10 is grounded after passing through the power supply VCC, and the collector of the transistor Q10 is connected to the 5V_W driving power supply and one end of the capacitor C3. The base of the transistor Q10 is connected to the collector of the transistor Q11, and the emitter of the transistor Q11 is connected to the other end of the capacitor C3 and then grounded; The hardware protection signal sampling module includes resistors R12 to R21, comparator U11, comparator U12_A, comparator U12_B, comparator U13, comparator U14_A, comparator U14_B, NAND gate U15_A, NAND gate U15_B, NAND gate U15_C, and NAND gate U15_D; one end of the resistor R12, resistor R14, resistor R17, and resistor R19 are all connected to the positive electrode of the reference power supply VCC1, the other end of the resistor R12 is connected to one end of the resistor R13 and the positive input end of the comparator U11, the other end of the resistor R13 is grounded, and the other end of the resistor R14 is connected to the resistor R15 The other end of the resistor R15 is connected to one end of the resistor R16 and the negative input end of the comparator U12_B. The other end of the resistor R16 is connected to the negative electrode of the reference power supply VCC1 and then grounded. The negative input end of the comparator U12_A is connected to the positive input end of the comparator U12_B, and the output end of the comparator U12_A is connected to the output end of the comparator U12_B; the other end of the resistor R17 is connected to one end of the resistor R18 and the positive input end of the comparator U13, and the other end of the resistor R18 is grounded; the other end of the resistor R19 is connected to the resistor R2 0 and the positive input terminal of the comparator U14_A are all connected, the other end of the resistor R20 is connected to one end of the resistor R21 and the negative input terminal of the comparator U14_B, the negative input terminal of the comparator U14_A is connected to the positive input terminal of the comparator U14_B, the other end of the resistor R21 is grounded, and the output terminal of the comparator U14_A is connected to the output terminal of the comparator U14_B; the two PWM output ports corresponding to the resistors R4 and R5 are respectively connected to the two input terminals of the NAND gate U15_A, and the two PWM output ports corresponding to the resistors R6 and R8 are respectively connected to the two input terminals of the NAND gate U15_B An input terminal, two PWM output ports corresponding to the resistor R6 and the resistor R10 are respectively connected to the two input terminals of the NAND gate U15_C, and two PWM output ports corresponding to the resistor R8 and the resistor R11 are respectively connected to the two input terminals of the NAND gate U15_D, and the output terminals of the NAND gate U15_A, the NAND gate U15_B, the NAND gate U15_C, and the NAND gate U15_D are connected; the negative input terminal of the comparator U11 is connected to the output signal terminal IPV_sense of the Hall sensor CT2, and the output terminal of the comparator U11 is connected to the 2D pin terminal of the D flip-flop U16 in the D-type flip-flop hardware protection execution module;The negative input terminal of the comparator U12_A and the positive input terminal of the comparator U12_B are both connected to the output signal terminal IBAT_sense of the Hall sensor CT1, and the output terminals of the comparator U12_A and the comparator U12_B are connected and then connected to the 1D pin terminal of the D flip-flop U16; the negative input terminal of the comparator U13 is connected to the output terminal of the comparator U1, and the output terminal of the comparator U13 is connected to the 4D pin terminal of the D flip-flop U16; the comparator U14_ A's negative input terminal and the positive input terminal of the comparator U14_B are connected to the output signal terminal IINV_sense of the Hall sensor CT3, the output terminals of the comparator U14_A and the comparator U14_B are connected to the 3D pin terminal of the D flip-flop U16; the output terminal of the NAND gate U15_A, the output terminal of the NAND gate U15_B, the output terminal of the NAND gate U15_C, and the output terminal of the NAND gate U15_D are connected to the 5D pin terminal of the D flip-flop U16; The D-type trigger hardware protection execution module includes a D trigger U16, resistors R22-R30, switch diodes D2-D4, MOS tubes Q12, MOS tubes Q13, and capacitor C4. The models of the switch diodes D2-D4 are all BAV70; the 1D pin end of the D trigger U16 is connected to the power supply VCC through the resistor R22, and is connected to the connection end between the output ends of the comparator U12_A and the comparator U12_B; the 2D pin end of the D trigger U16 is connected to the power supply VCC through the resistor R23, and is connected to the output end of the comparator U11; the D The 3D pin end of the D flip-flop U16 is connected to the power supply VCC through the resistor R24 ​​and is connected to the connection end between the output ends of the comparator U14_A and the comparator U14_B. The 4D pin end of the D flip-flop U16 is connected to the power supply VCC through the resistor R25 and is connected to the output end of the comparator U13. The 5D pin end of the D flip-flop U16 is connected to the power supply VCC through the resistor R26 and is connected to the connection end between the output ends of the NAND gate U15_A, the NAND gate U15_B, the NAND gate U15_C and the NAND gate U15_D. The 1 _ Q _ The pin end is connected to an input end of the switching diode D2, and the 2 _ Q _ The pin end is connected to the other input end of the switch diode D2, and the 3 _ Q _ The pin end is connected to an input end of the switching diode D3, and the 4 _ Q _ The pin end is connected to the other input end of the switch diode D3, and the 5 _ Q _ The pin end is connected to an input end of the switching diode D4, and the other input end of the switching diode D4 is vacant; the output ends of the switching diodes D2 to D4 are all connected to one end of the resistor R27 and the drain of the MOS tube Q12, the source of the MOS tube Q12 is grounded, and the gate of the MOS tube Q12 is connected to the reset pin end on the MCU after passing through the resistor R30, the other end of the resistor R27 is connected to one end of the resistor R28 and the gate of the MOS tube Q13, the other end of the resistor R28 is connected to the source of the MOS tube Q13 and then grounded, the drain of the MOS tube Q13 is connected to one end of the resistor R29, the LE pin end of the D trigger U16, and the base of the transistor Q11, and the D trigger U16 is connected to the LE pin end of the D trigger U16. The pin end is grounded, the other end of the resistor R29 is connected to the power supply VCC, the VCC pin end of the D flip-flop U16 is connected to one end of the capacitor C4 and then to the power supply VCC, and the GND pin end of the D flip-flop U16 is connected to the other end of the capacitor C4 and then to ground.

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