Cache device, cache, system, data processing method, device and medium

Abstract

The present application discloses a cache device, an instruction cache, an instruction processing system, a data processing method, an apparatus and a medium, and relates to the field of cloud computing. The cache device specifically includes: a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a push port; the write port group is used to write cache data to a set storage address in the first queue and / or the second queue; the read port is used to read all cache data from the first queue and / or the second queue at one time; the push port is used to push cache data into the first queue and / or the second queue; the first pop-up port is used to pop up cache data from the first queue; the second pop-up port is used to pop up cache data from the second queue. The technical solution of the embodiment of the present application greatly saves the number of cache devices and reduces complex logic control under the premise of realizing the missing instruction processing function.

Description

Technical Field

[0001] The present application relates to the field of computer hardware, and in particular to cloud computing technology, and specifically to a cache device, an instruction cache, an instruction processing system, a data processing method, an apparatus, and a medium. Background Art

[0002] The cores in a multi-core processor obtain instructions from an external instruction storage device through an instruction cache (icache). icache is connected to the external instruction storage device through a bus. The bus responds to the read operation issued by icache with a random delay. After the bus responds to the current read operation, icache can initiate a new read operation. During the delay time, the core may miss the instruction from icache, which requires caching the read operation that has not yet been initiated.

[0003] In the prior art, a FIFO (First Input First Output) memory is generally used to cache instruction missing flags that have not been initiated in icache, and another FIFO is used to cache instruction missing flags that have been responded to by the bus but have not been written back. At present, the register group is mainly used to synchronously cache instruction missing flags that have been initiated and responded to by the bus but have not been written back. When the next instruction fetch miss occurs, the instruction missing flag cached in the register group is queried to determine whether the corresponding instruction fetch request needs to be initiated. At the same time, another group of registers is used to record which cores have instruction fetch misses. When the corresponding instructions are written back through the bus, they can be written back to these cores accordingly.

[0004] In the process of implementing the present application, the inventors found that the prior art has the following defects: in order to realize the function of retrieving missing instructions, more FIFOs and register groups are required, and the control is cumbersome; in addition, duplicate information is cached in the FIFO and register groups, resulting in unnecessary waste of resources. Summary of the invention

[0005] The embodiments of the present application provide a cache device, an instruction cache, an instruction processing system, a data processing method, an apparatus and a medium, which simplifies the hardware cost required to implement the missing instruction retrieval function by designing a cache device with a new structure.

[0006] In a first aspect, an embodiment of the present application provides a cache device, including: a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port, and a push port;

[0007] The write port group is used to write cache data to a set storage address in the first queue and / or the second queue;

[0008] The read port is used to read all cached data from the first queue and / or the second queue at one time;

[0009] The push port is used to push cache data into the first queue and / or the second queue;

[0010] The first pop-up port is used to pop cached data from the first queue;

[0011] The second pop-up port is used to pop cached data from the second queue.

[0012] One embodiment of the above application has the following advantages or beneficial effects: by setting a pop-up port for two queues, the cache device can store both the instruction missing flag that has not been initiated and the instruction missing flag that has been responded to by the bus but has not been written back when an instruction missing occurs, thereby greatly saving the number of cache devices. In addition, by setting a write port group and a read port, the same structure can be used to cache the core flag of the processing core that matches the instruction missing flag, without using a register group to store the above information, thereby reducing complex logical control.

[0013] Optionally, the write port group specifically includes: a write data port and a write address port;

[0014] The write data port is used to receive the written cache data;

[0015] The write address port is used to receive the storage address written by the cache data written by the write address port in the first queue and / or the second queue.

[0016] One embodiment of the above application has the following advantages or beneficial effects: by setting a write data port and a write address port, the required cache data can be written at the set storage address of the first queue or the second queue, and then when an instruction retrieval request for the same missing instruction is received from different processing cores of a multi-core processor, the information of the above processing cores can be written to the same storage address, thereby maximizing the reuse of limited storage space and improving processing performance.

[0017] Optionally, the write port group further includes: a write mask port;

[0018] The write mask port is used to receive mask information of cache data written by the write address port;

[0019] The mask information is used to indicate data bits of cache data written to the storage address, and the write mask port has the same bit width as the write data port.

[0020] One embodiment of the above application has the following advantages or beneficial effects: by setting a write mask port, the corresponding cache data can be accurately written to a specific data bit in the storage address in the cache device, and then the identification information of the processing core that sends an instruction retrieval request for the missing instruction can be updated and stored, thereby maximizing the reuse of limited storage space and improving processing performance.

[0021] Optionally, it also includes: a first empty and full state flag bit group, and a second empty and full state flag bit group;

[0022] The first empty and full status flag bit group is used to indicate the storage status of the cache data in the first queue;

[0023] The second empty and full status flag bit group is used to indicate the storage status of the cache data in the second queue.

[0024] One embodiment in the above application has the following advantages or beneficial effects: by setting a first empty and full status flag bit group and a second empty and full status flag bit group, the function of the cache device can be further enriched, and the storage status of each queue in the cache device can be known in real time, and then processing operations matching different storage statuses can be performed.

[0025] In a second aspect, an embodiment of the present application further provides an instruction cache, comprising: a first cache device and a second cache device as described in any embodiment of the present application.

[0026] One embodiment of the above application has the following advantages or beneficial effects: by setting the first cache device and the second cache device of the above new structure in the instruction cache, the performance of the instruction cache can be further optimized, especially in the instruction fetching scenario, the retrieval function of the missing instructions that requires multiple FIFOs and multiple register groups to cooperate in the prior art can be realized, eliminating more complex control logic and simplifying the design of the instruction cache. In addition, it can avoid the multi-core processor from sending repeated instruction fetching requests to the external instruction storage device, thereby greatly reducing many unnecessary delays of the multi-core processor, thereby improving the performance of the multi-core processor.

[0027] In a third aspect, an embodiment of the present application further provides an instruction processing system, comprising: an instruction cache, a multi-core processor, and an external instruction memory as described in any embodiment of the present application;

[0028] The instruction cache is connected to the external instruction memory and multiple processing cores of the multi-core processor respectively, and the instruction cache is connected to the external instruction memory through a bus.

[0029] Optionally, the multi-core processor is used to provide a missing instruction identifier to an instruction cache when an instruction fetch miss occurs;

[0030] The external instruction memory is used to store instructions;

[0031] The instruction cache is used to send the missing instruction identifier to the external instruction memory, and obtain the instruction responded and written back by the external instruction memory through the bus.

[0032] Optionally, the first cache device is used to use the first queue to cache instruction fetch miss flags that have occurred but have not been responded to by the external instruction memory, and to use the second queue to cache instruction fetch miss flags that have been responded to by the external instruction memory but have not been written back;

[0033] The second cache device is used to use the first queue or the second queue to store the core identifier of the processing core matching the instruction fetch miss identifier in accordance with the storage address of the instruction fetch miss identifier in the first cache device.

[0034] One embodiment of the above application has the following advantages or beneficial effects: by using the instruction cache described in any embodiment of the present application in an instruction processing system, the missing instruction retrieval function that requires multiple FIFOs and multiple register groups to cooperate in the prior art can be realized, eliminating more complex control logic and simplifying the design of the instruction cache. In addition, it can avoid the multi-core processor from sending repeated instruction fetch requests to the external instruction storage device, thereby greatly reducing many unnecessary delays of the multi-core processor, thereby improving the performance of the multi-core processor.

[0035] In a fourth aspect, an embodiment of the present application further provides a data processing method, which is executed by an instruction cache in the instruction processing system described in any embodiment of the present application, comprising:

[0036] When it is detected that the external instruction memory is in an idle state, taking out the missing instruction identifier from the first queue of the first cache device, popping it out through the first pop-up port, and providing it to the external instruction memory;

[0037] When a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier is detected, the first target missing instruction identifier is taken out from the second queue of the first cache device and ejected through the second eject port of the first cache device;

[0038] fetching the first target cache data matching the first target missing instruction identifier from the second cache device, and popping it out through a second pop-up port of the second cache device;

[0039] A first target core identifier of a first target processing core matching the first target instruction fetch miss identifier is identified according to the first target cache data, and the write-back instruction is sent to the first target processing core.

[0040] One embodiment of the above application has the following advantages or beneficial effects: through the two queues set in the first buffer and the pop-up ports for different queues, the instruction missing identifiers that have not been initiated and the instruction missing identifiers that have been responded to by the bus but not yet written back can be popped out respectively, which greatly saves the number of cache devices used by the instruction cache; in addition, through the pop-up port of the second buffer, the core identifier of the processing core that matches the instruction missing identifier can be synchronously popped out without using a register group to store the above information, thereby reducing complex logical control.

[0041] Optionally, also include:

[0042] When it is detected that a second target processing core has a fetch instruction miss for a second target missing instruction identifier, reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first cache device;

[0043] If the second target missing instruction identifier is not stored in the first queue and the second queue of the first cache device, storing the second target missing instruction identifier in the first queue and the second queue at the same time;

[0044] Generate second target cache data according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data;

[0045] The second target cache data is pushed into the first queue or the second queue of the second cache device through the push port of the second cache device.

[0046] One embodiment of the above application has the following advantages or beneficial effects: by setting a first cache device in a high-speed instruction cache, when an instruction miss occurs, the instruction miss flag that has not been initiated and the instruction miss flag that has been responded to by the bus but has not been written back can be stored at the same time, which greatly saves the number of cache devices used. In addition, through the write port group and the read port in the second cache device, the core flag of the processing core that matches the instruction miss flag can be synchronously cached or read without using a register group to store the above information, thereby reducing complex logical control.

[0047] Optionally, after reading all missing instruction identifiers stored in the first queue and the second queue from the read port of the first cache device, the method further includes:

[0048] If the second target missing instruction identifier is stored in the first queue or the second queue of the first cache device, obtaining a target storage address of the second target missing instruction identifier in the first cache device;

[0049] Generate third target cache data and target mask information according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data;

[0050] The target storage address, the third target cache data and the target mask information are written through the write port group of the second cache device to store the core identifier of the second target processing core matching the second target instruction fetch miss identifier in the second cache device.

[0051] One embodiment of the above application has the following advantages or beneficial effects: through the write port group in the second cache device, when receiving instruction retrieval requests for the same missing instruction from different processing cores of the multi-core processor, the information of the above processing cores can be written to the same storage address, which reuses the limited storage space to the greatest extent and improves the processing performance. In addition, it can avoid the multi-core processor from sending repeated instruction fetch requests to the external instruction storage device, thereby greatly reducing many unnecessary delays of the multi-core processor, thereby improving the performance of the multi-core processor.

[0052] Optionally, at least one of the following is also included:

[0053] If there is no cache data in the first queue of the first cache device, setting the empty state identification bit in the first empty and full state flag bit group of the first cache device to a target level value;

[0054] If the first queue of the first cache device is full, setting the full state identification bit in the first empty and full state flag bit group of the first cache device to a target level value;

[0055] If there is no cache data in the second queue of the first cache device, setting the empty state identification bit in the second empty and full state flag bit group of the first cache device to a target level value; and

[0056] If the second queue of the first cache device is full, the full state identification bit in the second empty and full state flag bit group of the first cache device is set to a target level value.

[0057] Optionally, also include:

[0058] If it is detected that the full state identification bit in the first empty and full state flag bit group or the second empty and full state flag bit group of the first cache device is a target level value, then no instruction fetch request from any processing core in the multi-core processor is received.

[0059] In a fifth aspect, an embodiment of the present application further provides a data processing device, which is executed by an instruction cache in the instruction processing system described in any embodiment of the present application, and includes:

[0060] A first pop-up processing module is used to take out the missing instruction identifier from the first queue of the first cache device and pop it out through the first pop-up port to provide it to the external instruction memory when detecting that the external instruction memory is in an idle state;

[0061] A second pop-up processing module is used to, when detecting a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier, take out the first target missing instruction identifier from the second queue of the first cache device and pop it out through the second pop-up port of the first cache device;

[0062] A third pop-up processing module, configured to fetch the first target cache data matching the first target missing instruction identifier from the second cache device, and pop it out through a second pop-up port of the second cache device;

[0063] A write-back instruction sending module is used to identify the first target core identifier of the first target processing core that matches the first target instruction fetch miss identifier based on the first target cache data, and send the write-back instruction to the processing core that matches the first target core identifier.

[0064] One embodiment of the above application has the following advantages or beneficial effects: through the two queues set in the first buffer and the pop-up ports for different queues, the instruction missing identifiers that have not been initiated and the instruction missing identifiers that have been responded to by the bus but not yet written back can be popped out respectively, which greatly saves the number of cache devices used by the instruction cache; in addition, through the pop-up port of the second buffer, the core identifier of the processing core that matches the instruction missing identifier can be synchronously popped out without using a register group to store the above information, thereby reducing complex logical control.

[0065] In a sixth aspect, an embodiment of the present application further provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute any method described in any one of the embodiments of the present application.

[0066] One embodiment of the above application has the following advantages or beneficial effects: through the two queues set in the first buffer and the pop-up ports for different queues, the instruction missing identifiers that have not been initiated and the instruction missing identifiers that have been responded to by the bus but not yet written back can be popped out respectively, which greatly saves the number of cache devices used by the instruction cache; in addition, through the pop-up port of the second buffer, the core identifier of the processing core that matches the instruction missing identifier can be synchronously popped out without using a register group to store the above information, thereby reducing complex logical control.

[0067] Other effects of the above optional manner will be described below in conjunction with specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present application.

[0069] Figure 1 is a schematic diagram of the structure of a cache device provided in the first embodiment of the present application;

[0070] Figure 2 is a schematic diagram of the structure of an instruction cache provided by the second embodiment of the present application;

[0071] Figure 3 is a structural diagram of an instruction processing system provided in the third embodiment of the present application;

[0072] Figure 4 is a flow chart of an implementation of a data processing method provided in the fourth embodiment of the present application;

[0073] Figure 5 is a flow chart of an implementation of a data processing method provided in the fifth embodiment of the present application;

[0074] Figure 6 It is a structural diagram of a data processing device provided in the sixth embodiment of the present application. DETAILED DESCRIPTION

[0075] The following is a description of exemplary embodiments of the present application in conjunction with the accompanying drawings, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0076] First embodiment

[0077] Figure 1A structural schematic diagram of a cache device provided for the first embodiment of the present application. The cache device provided in this embodiment can be used in an instruction cache and stores information such as an instruction fetch miss identifier that has occurred but has not been responded to by the bus, an instruction fetch miss identifier that has been responded to by the bus but has not been written back, and a core identifier of a processing core that matches the instruction fetch miss identifier.

[0078] like Figure 1 As shown, the cache device may specifically include: a first queue, a second queue, a write port group, a read port, a first eject port, a second eject port, and a push port.

[0079] The write port group is used to write cache data to a set storage address in the first queue and / or the second queue;

[0080] The read port is used to read all cached data from the first queue and / or the second queue at one time;

[0081] The push port is used to push cache data into the first queue and / or the second queue;

[0082] The first pop-up port is used to pop cached data from the first queue;

[0083] The second pop-up port is used to pop cached data from the second queue.

[0084] Specifically, the first queue and the second queue are similar to the existing FIFO memory, which are first-in first-out queues and can realize the basic functions of the existing FIFO memory. The purpose of setting two queues is to use a cache device to simultaneously store: instruction fetch miss flags that have occurred but have not been responded to by the bus, and instruction fetch miss flags that have been responded to by the bus but have not been written back, so as to further reduce the use of storage devices.

[0085] Specifically, the instruction fetch missing flag may be the identification information (also referred to as identity information) of the instruction where the instruction fetch missing occurs. Generally, icache marks instructions through pc (program counter), which records the relative address of the instruction in the external instruction memory. Accordingly, the instruction fetch missing flag may be the pc corresponding to the instruction where the instruction fetch missing occurs.

[0086] The reason for setting a push port is that when an instruction fetch miss occurs, the missing instruction identifier corresponding to the instruction fetch miss satisfies both the condition that the instruction fetch miss occurs but has not been responded to by the bus, and the condition that the instruction fetch miss has been responded to by the bus but has not been written back. Therefore, the missing instruction identifier can be pushed into the first queue and the second queue at the same time through a push port. Typically, the first queue can be used to store the instruction fetch miss identifier that has occurred but has not been responded to by the bus, and the second pair of queues can be used to store the instruction fetch miss identifier that has been responded to by the bus but has not been written back.

[0087] The reason for setting two pop-up ports is that when it is detected that the external instruction storage device is idle, an instruction fetch miss flag that has occurred but has not been responded to by the bus can be obtained from the first queue, and the above instruction fetch miss flag can be popped out from the first pop-up port to provide it to the external instruction storage device for a corresponding instruction write back operation; since the external instruction storage device can only process one instruction read operation at the same time, when it is detected that the external instruction storage device feeds back a write back instruction, it means that the first instruction fetch miss flag stored in the current second queue that has been responded to by the bus but has not been written back has received the corresponding write back instruction, and therefore, the first instruction fetch miss flag in the second queue can be popped out through the second pop-up port to release cache space.

[0088] Through the two ejection ports of the above-mentioned one cache device, the functions of two FIFOs in the existing missing instruction retrieval function can be met, so as to save the number of cache devices and further reduce the size of the entire instruction cache.

[0089] Furthermore, by using a write port group, the core identifier of a processing core that matches an instruction fetch miss identifier can be synchronously written into a first queue or a second queue in a new cache device. Then, when a write-back instruction fed back by an external instruction cache is received, while the first instruction fetch miss identifier in the second queue of a cache device is popped out through a second pop-up port, the core identifier of a processing core that matches the above-mentioned instruction fetch miss identifier cached in the first queue or the second queue of the second cache device can be synchronously popped out through the first pop-up port or the second pop-up port to determine which processing cores the above-mentioned write-back instruction is specifically provided to, without the need to use a register group to store the above-mentioned information, thereby reducing complex logic control.

[0090] Furthermore, by using the read port to read out all cached data from the first queue and / or the second queue at one time, it is possible to quickly identify whether a new instruction fetch missing flag is sent by another processing core when the new instruction fetch missing flag is received, without introducing a new register group to repeatedly store the above information, thereby further reducing complex logic control.

[0091] It can be seen from the above analysis that by using the cache device with the above new structure, the function of retrieving existing missing instructions can be effectively realized on the basis of minimizing the hardware cost.

[0092] The technical solution of the embodiment of the present application, by setting a pop-up port for two queues, the cache device can store both the instruction missing flag that has not been initiated and the instruction missing flag that has been responded to by the bus but not yet written back when an instruction missing occurs, thereby greatly saving the number of cache devices. In addition, by setting a write port group and a read port, the same structure can be used to cache the core flag of the processing core that matches the instruction missing flag, without using a register group to store the above information, thereby reducing complex logical control.

[0093] On the basis of the above embodiments, the write port group may specifically include: a write data port and a write address port;

[0094] The write data port is used to receive the written cache data;

[0095] The write address port is used to receive the storage address written by the cache data written by the write address port in the first queue and / or the second queue.

[0096] Specifically, in the first queue or the second queue, different storage spaces correspond to different storage addresses. By setting the above-mentioned write port group, the cache data written in a certain storage address in the first queue or the second queue (the address has been written with cache data) can be modified to achieve that when multiple processing cores in a multi-core processor all have instruction fetch misses for the same instruction, there is no need to use multiple storage addresses to store the same instruction missing identifier multiple times for different processing cores. It is only necessary to update and store the core identifier of the processing core that has already been stored and matches the instruction fetch missing identifier.

[0097] In a specific example, a set of binary data matching the number of processing cores of the multi-core processor is used to represent the processing cores. For example, if the number of processing cores is 12, a set of 12-bit data can be used to represent the 12 processing cores at the same time, and different processing cores correspond to different data bits of the 12-bit data.

[0098] For example, the first data bit corresponds to processing core A, the second data bit corresponds to processing core B, the third data bit corresponds to processing core C, and so on. When the instruction cache receives an instruction missing flag sent by processing core A, a set of data 100000000000 can be constructed and pushed into a storage address (for example, storage address X) in a cache device of the above structure through a push port. When the instruction cache receives the same instruction missing flag sent by processing core C again, there is no need to store the instruction missing flag again for processing core C at a new storage address. It is only necessary to update the data stored at storage address X from 100000000000 to 101000000000, which can represent that instruction missing for the above instruction missing flag occurred in both processing core A and processing core C at the same time.

[0099] Typically, the required processing result can be obtained by performing an AND operation on the cache data written by the write port and the cache data currently stored at the corresponding storage address.

[0100] The advantage of this setting is that by setting the write data port and the write address port, the required cache data can be written at the set storage address of the first queue or the second queue, and then when the instruction retrieval request for the same missing instruction is received from different processing cores of the multi-core processor, the information of the above processing cores can be written to the same storage address, thereby maximizing the reuse of limited storage space and improving processing performance.

[0101] Based on the above embodiments, the write port group may further include: a write mask port;

[0102] The write mask port is used to receive mask information of cache data written by the write address port;

[0103] The mask information is used to indicate data bits of cache data written to the storage address, and the write mask port has the same bit width as the write data port.

[0104] For the application scenario described in the previous example, when the data stored at the storage address X needs to be updated from 100000000000 to 101000000000, it is only necessary to change the third bit of the cache data from 0 to 1. Therefore, in order to further simplify the internal write logic in the cache device, a write mask port can be introduced in the write port group. The mask information written in the write mask port determines which data bits in the cache data written in the write port need to be written to the corresponding storage address.

[0105] As mentioned above, if you want to write the third data bit of the cache data in the storage address X to 1, you can set the mask information of the form 001000000000 and the cache data of the form 001000000000. The third high level 1 input in the mask information indicates that the third bit 1 of the cache data is written to the corresponding storage address.

[0106] The advantage of this setting is that by setting the write mask port, the corresponding cache data can be accurately written to a specific data bit in the storage address in the cache device, and then the identification information of the processing core that sends the instruction retrieval request for the missing instruction can be updated and stored, thereby maximizing the reuse of limited storage space and improving processing performance.

[0107] On the basis of the above embodiments, it may further include: a first empty and full state flag bit group, and a second empty and full state flag bit group;

[0108] The first empty and full status flag bit group is used to indicate the storage status of the cache data in the first queue;

[0109] The second empty and full status flag bit group is used to indicate the storage status of the cache data in the second queue.

[0110] Specifically, the first empty and full status flag bit group may specifically include: a first empty status flag bit and a first full status flag bit, wherein the first empty status flag bit is used to be set to a target level value (typically, high level 1) when no cache data is stored in the first queue to indicate an empty storage state of the first queue, and the first empty status flag bit is used to be set to a target level value when the storage space of the first queue is full of cache data to indicate a full storage state of the first queue.

[0111] Similarly, the second empty and full status flag bit group may specifically include: a second empty status flag bit and a second full status flag bit, wherein the second empty status flag bit is used to be set to a target level value (typically, high level 1) when no cache data is stored in the second queue to indicate an empty storage state of the second queue, and the second empty status flag bit is used to be set to a target level value when the storage space of the second queue is full of cache data to indicate a full storage state of the second queue.

[0112] The advantage of this setting is that by setting the first empty and full status flag bit group and the second empty and full status flag bit group, the function of the cache device can be further enriched, and the storage status of each queue in the cache device can be known in real time, and then processing operations matching different storage statuses can be executed.

[0113] Second embodiment

[0114] Figure 2 This is a schematic diagram of the structure of an instruction cache provided in the second embodiment of the present application. The instruction cache provided in this embodiment uses two cache devices as provided in the embodiment of the present application.

[0115] like Figure 2 As shown, the instruction cache 210 includes a first cache device 211 and a second cache device 212 .

[0116] The first cache device 211 and the second cache device 212 have the same structure as the cache devices described in any embodiment of the present application.

[0117] Specifically, the first cache device and the second cache device both include: a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port, and a push port.

[0118] The write port group is used to write cache data to a set storage address in the first queue and / or the second queue.

[0119] The read port is used to read all cached data from the first queue and / or the second queue at one time.

[0120] The push port is used to push cache data into the first queue and / or the second queue.

[0121] The first pop-up port is used to pop cached data from the first queue.

[0122] The second pop-up port is used to pop cached data from the second queue.

[0123] Specifically, the write port group may include: a write data port and a write address port.

[0124] The write data port is used to receive the written cache data.

[0125] The write address port is used to receive the storage address written by the cache data written by the write address port in the first queue and / or the second queue.

[0126] Specifically, the write port group further includes: a write mask port;

[0127] The write mask port is used to receive mask information of the cache data written by the write address port.

[0128] The mask information is used to indicate data bits of cache data written to the storage address, and the write mask port has the same bit width as the write data port.

[0129] Specifically, it also includes: a first empty and full state flag bit group, and a second empty and full state flag bit group;

[0130] The first empty and full status flag bit group is used to indicate the storage status of the cache data in the first queue;

[0131] The second empty and full status flag bit group is used to indicate the storage status of the cache data in the second queue.

[0132] The first empty and full status flag bit group specifically includes a first empty status flag bit and a first full status flag bit, and the second empty and full status flag bit group specifically includes a second empty status flag bit and a second full status flag bit.

[0133] By setting the first cache device and the second cache device of the new structure in the instruction cache, the performance of the instruction cache can be further optimized, especially in the instruction fetching scenario, the retrieval function of the missing instructions that requires multiple FIFOs and multiple register groups to cooperate in the prior art can be realized, eliminating more complex control logic and simplifying the design of the instruction cache. In addition, it can avoid the multi-core processor from sending repeated instruction fetch requests to the external instruction storage device, thereby greatly reducing many unnecessary delays of the multi-core processor, thereby improving the performance of the multi-core processor.

[0134] Third embodiment

[0135] Figure 3 A schematic diagram of the structure of an instruction processing system provided for the third embodiment of the present application. By using the instruction cache as described in any embodiment of the present application and by using the instruction cache as a bridge between a multi-core processor and an external instruction memory, when an instruction fetch miss occurs in one or more processing cores of the multi-core processor, the corresponding missing instruction identifier and the core identifier of the processing core where the instruction fetch miss occurs can be cached to implement the missing instruction retrieval function.

[0136] like Figure 3 As shown, the instruction processing system specifically includes the instruction cache 310 as described in any embodiment of the present application, the multi-core processor 320, and the external instruction memory 330. The instruction cache 310 may specifically include: the first cache device 311 and the second cache device 312 as described in any embodiment of the present application.

[0137] The instruction cache 310 is respectively connected to multiple processing cores (in Figure 3 In the example, processing core 1, processing core 2, ..., processing core N) are connected to external instruction memory 330, and instruction cache 310 is connected to external instruction memory 330 through a bus.

[0138] The multi-core processor 320 is used to provide a missing instruction identifier to the instruction cache 310 when an instruction fetch miss occurs;

[0139] The external instruction memory 330 is used to store instructions;

[0140] The instruction cache 310 is used to send the missing instruction identifier to the external instruction memory 330, and obtain the instruction responded and written back by the external instruction memory 330 through the bus.

[0141] Optionally, the first cache device 311 is used to use the first queue to cache instruction fetch miss flags that have occurred but have not been responded to by the external instruction memory, and to use the second queue to cache instruction fetch miss flags that have been responded to by the external instruction memory but have not been written back;

[0142] The second cache device 312 is used to use the first queue or the second queue to store the core identifier of the processing core matching the instruction fetch miss identifier in accordance with the storage address of the instruction fetch miss identifier in the first cache device.

[0143] When the processing core needs to fetch instructions for processing, it requests instructions from the external instruction memory 330 through the instruction cache 310. When the external instruction memory 330 responds to the instruction fetch request through the bus, it writes the instructions matching the instruction fetch request back to the instruction cache 310 through the bus, and the instruction cache 310 provides it to the processing core that issued the instruction fetch request. The instruction cache 310 can only respond to the same instruction fetch request at a time, and other instruction fetch requests are randomly delayed. When the processing core detects that an instruction fetch miss occurs, the instruction fetch miss identifier matching the instruction fetch miss is provided to the instruction cache 310 for caching, and the instruction cache 310 fetches the missing instructions at an appropriate time and feeds them back to the matching processing core.

[0144] Specifically, in order to cooperate with the use of the first cache device 311, the second cache device 312 uses only one queue. As an example but not a limitation, only the second queue in the second cache device 312 can be used to store the core identifier of the processing core that matches the instruction fetch miss identifier. Accordingly, when it is necessary to read cache data from the read port of the second cache device 312, only the cache data is read from the second queue; when it is necessary to write cache data from the write port group of the second cache device 312, only the set data bit of the cache data in the set storage address in the second queue can be written; when it is necessary to push cache data through the push port of the second cache device 312, the above-mentioned pushed cache data is only pushed into the second queue; when it is necessary to pop cache data from the second queue of the second cache device 312, it can only be popped out through the second pop-up port. At the same time, only the second empty and full state flag bit group in the second cache device 312 is used to indicate the empty and full storage state of the second queue.

[0145] Of course, it is understandable that the first queue in the second cache device 312 can also be used to store the core identifier of the processing core that matches the instruction fetch miss identifier, and this embodiment does not limit this.

[0146] Specifically, when the instruction cache 310 detects that the external instruction memory 330 is in an idle state:

[0147] Taking out the missing instruction identifier from the first queue of the first cache device 311, and popping it out through the first pop-up port to provide it to the external instruction memory 330;

[0148] When the instruction cache 310 detects the write-back instruction fed back by the external instruction memory 330 for the first target missing instruction identifier, the instruction cache 310 executes:

[0149] Taking out the first target missing instruction identifier from the second queue of the first cache device 311, and popping it out through the second pop-up port of the first cache device 311;

[0150] Taking out the first target cache data matching the first target missing instruction identifier from the second cache device 312, and popping it out through the first pop-up port or the second pop-up port of the second cache device 312;

[0151] A first target core identifier of a first target processing core matching the first target instruction fetch miss identifier is identified according to the first target cache data, and the write-back instruction is sent to the first target processing core.

[0152] When the instruction cache 310 detects that a second target processing core has a missing instruction fetch for the second target missing instruction identifier, the instruction cache 310 executes:

[0153] Reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first cache device;

[0154] If the second target missing instruction identifier is not stored in the first queue and the second queue of the first cache device, the second target missing instruction identifier is stored in the first queue and the second queue at the same time; second target cache data is generated according to the second target processing core and the mapping relationship between the preset processing core and the corresponding data bits in the cache data; the second target cache data is pushed into the first queue or the second queue of the second cache device through the push port of the second cache device;

[0155] If the second target missing instruction identifier is stored in the first queue or the second queue of the first cache device, obtaining a target storage address of the second target missing instruction identifier in the first cache device;

[0156] Generate third target cache data and target mask information according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data;

[0157] The target storage address, the third target cache data and the target mask information are written through the write port group of the second cache device to store the core identifier of the second target processing core matching the second target instruction fetch miss identifier in the second cache device.

[0158] The technical solution of the embodiment of the present application can realize the missing instruction retrieval function that requires multiple FIFOs and multiple register groups to cooperate in the prior art in the instruction cache system by setting the first cache device and the second cache device of the new structure in the instruction cache, thereby eliminating more complex control logic and simplifying the design of the instruction cache. In addition, it can avoid the multi-core processor from sending repeated instruction fetch requests to the external instruction storage device, thereby greatly reducing many unnecessary delays of the multi-core processor, thereby improving the performance of the multi-core processor.

[0159] Fourth embodiment

[0160] Figure 4 : is a flowchart of a data processing method provided in the fourth embodiment of the present application. This embodiment can be applied to the case of implementing the processing of missing instructions. The method can be executed by a data processing device, which is implemented in software and / or hardware, and is preferably configured in an instruction cache in an instruction processing system as described in any embodiment of the present application, and the instruction cache is used in conjunction with a multi-core processor and an external instruction memory. Figure 4 As shown, the method specifically includes the following:

[0161] S410: When it is detected that the external instruction memory is in an idle state, take out a missing instruction identifier from a first queue of a first cache device, pop it out through a first pop-up port, and provide it to the external instruction memory.

[0162] As mentioned above, the first queue of the first cache device caches an instruction fetch miss flag that has occurred but has not been responded to by the bus, that is, an instruction fetch miss flag that has not been sent to the external instruction memory. Therefore, when it is detected that the external instruction memory is in an idle state, it means that the current external instruction memory is not performing an instruction reading operation, and the missing instruction flag can be taken out from the first queue of the first cache device, and after being ejected through the first eject port, the ejected missing instruction flag is provided to the external instruction memory, so that the external instruction memory writes back the instruction corresponding to the missing instruction flag.

[0163] S420: When a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier is detected, the first target missing instruction identifier is taken out from the second queue of the first cache device, and is ejected through the second eject port of the first cache device.

[0164] In this embodiment, the second queue of the first cache device caches instruction fetch miss flags that have been responded to by the bus but not yet written back. That is, the instruction fetch miss flags cached in the second queue are instruction fetch miss flags that have been sent to the external instruction memory through the bus but have not received the write-back instruction fed back by the external instruction memory.

[0165] Among them, since the external instruction storage device can only process one instruction read operation at the same time, when it is detected that the external instruction storage device feeds back a write-back instruction, it means that the first instruction fetch miss identifier stored in the current second queue that has been responded to by the bus but has not yet been written back has received the corresponding write-back instruction. Therefore, the first instruction fetch miss identifier in the second queue can be popped out through the second pop-up port to release cache space.

[0166] S430: Take out the first target cache data matching the first target missing instruction identifier from the second cache device, and pop it out through the first pop-up port or the second pop-up port of the second cache device.

[0167] In this embodiment, when an instruction fetch miss flag indicating an instruction fetch miss occurs is stored through the first cache device, the core flag of the processing core that matches the instruction fetch miss flag is synchronously written into the second cache device, and then when a write-back instruction fed back from the external instruction cache is received, while the first instruction fetch miss flag (that is, the first target missing instruction flag) in the second queue of the first cache device is popped out through the second pop-up port, the core flag of the processing core that matches the above-mentioned instruction fetch miss flag cached in the first queue or the second queue of the second cache device (that is, the first target core flag) can be synchronously popped out through the first pop-up port or the second pop-up port to determine which processing cores the above-mentioned write-back instruction is specifically provided to, without using a register group to store the above-mentioned information, thereby reducing complex logic control.

[0168] Specifically, the kernel identifier of the first target kernel identifier is included in the first target cache data, the number of data bits of the first target cache data matches the number of processing cores of the multi-core processor, and different processing cores correspond to different data bits of the first target cache data. According to the specific data value (0 or 1) of the data bit in the first target cache data, it can be determined which processing cores have instruction fetch misses for the first target missing instruction identifier.

[0169] S440: Identify, according to the first target cache data, a first target core identifier of a first target processing core that matches the first target instruction fetch miss identifier, and send the write-back instruction to the first target processing core.

[0170] Specifically, the processing core where the instruction fetch miss occurs can be identified by the data value 1, and then the position where the 1 appears in the first target cache data can be identified, and then based on the mapping relationship between the data bit and the processing core, one or more first target core identifiers can be identified, and the write-back instruction fed back by the external instruction memory can be provided to the above-mentioned first target processing core.

[0171] In an embodiment of the present application, by setting a first cache device in a high-speed instruction cache, when an instruction miss occurs, both the instruction miss flag that has not been initiated and the instruction miss flag that has been responded to by the bus but has not yet been written back can be stored simultaneously, thereby greatly saving the number of cache devices used. In addition, through the write port group and the read port in the second cache device, the core flag of the processing core that matches the instruction miss flag can be synchronously cached or read without using a register group to store the above information, thereby reducing complex logical control.

[0172] Fifth embodiment

[0173] Figure 5is a flow chart of a data processing method provided by the fifth embodiment of the present application. This embodiment is optimized based on the above embodiment, and the operation of storing the missing instruction identifier and the processing core where the instruction fetch miss occurs when the instruction fetch miss occurs is concretized, such as Figure 5 The method specifically comprises:

[0174] S510: When it is detected that the external instruction memory is in an idle state, take out a missing instruction identifier from a first queue of a first cache device, pop it out through a first pop-up port, and provide it to the external instruction memory.

[0175] S520: When a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier is detected, the first target missing instruction identifier is taken out from the second queue of the first cache device, and is ejected through the second eject port of the first cache device.

[0176] S530: Take out the first target cache data matching the first target missing instruction identifier from the second cache device, and pop it out through the first pop-up port or the second pop-up port of the second cache device.

[0177] S540: Identify, according to the first target cache data, a first target core identifier of a first target processing core that matches the first target instruction fetch miss identifier, and send the write-back instruction to the first target processing core.

[0178] S550: When it is detected that a second target processing core has a fetch instruction miss for a second target missing instruction identifier, read all missing instruction identifiers stored in the first queue and the second queue from a read port of the first cache device.

[0179] In this embodiment, because a read port that can read all cached data in the first queue and the second queue at one time is set in the first cache device, it is possible to directly determine whether the second target missing instruction identifier has been sent by other processing cores except the second target processing core through all cached data read from the read port, so as to avoid repeated storage of the same missing instruction identifier.

[0180] S560, determine whether the first queue or the second queue of the first cache device stores a second target missing instruction identifier: if so, execute S570; otherwise, execute S580.

[0181] S570, obtaining the target storage address of the second target missing instruction identifier in the first cache device, and executing S590.

[0182] If the second target missing instruction identifier is stored in the first queue or the second queue of the first cache device, it means that the above-mentioned second target missing instruction identifier has been sent by other processing cores. Therefore, it is only necessary to add the core identifier of the second target processing core and store it at the target storage address in the second cache.

[0183] It needs to be explained again that, taking the use of the second queue by the second cache as an example, the information stored in the second queue of the second cache corresponds one-to-one to the information stored in the second queue of the first cache, that is, at the same storage address, a missing instruction identifier A is stored in the second queue of the first cache, while the core identifiers of all processing cores that send the missing instruction identifier A are stored in the second queue of the second cache.

[0184] S580. Store the second target missing instruction identifier in the first queue and the second queue at the same time, and execute S5110.

[0185] If the second target missing instruction identifier is not stored in the first queue or the second queue of the first cache device, it means that the second target missing instruction identifier has not been sent by other processing cores. Therefore, the second target missing instruction identifier satisfies both the condition that the instruction fetch miss occurs but has not been responded to by the bus, and that the instruction has been responded to by the bus but has not been written back. Therefore, the second target missing instruction identifier can be pushed into the first queue and the second queue of the first cache device through the push port of the first cache device.

[0186] In this embodiment, the first queue can be used to store instruction fetch miss flags that have occurred but have not been responded to by the bus, and the second queue can be used to store instruction fetch miss flags that have been responded to by the bus but have not been written back.

[0187] S590. Generate third target cache data and target mask information according to the second target processing core and the mapping relationship between the preset processing core and the corresponding data bits in the cache data, and execute S5100.

[0188] In a specific example, if the multi-core processor includes 12 processing cores, the 12 processing cores correspond to 12 data bits of cache data stored in the second cache device. According to the mapping relationship between the preset processing cores and the corresponding data bits in the cache data, the second target processing core is the third bit of the 12 data bits. Therefore, the third target cache data and the target mask information of the form of 001000000000 can be constructed to determine that the third bit in the target storage address is adjusted to 1, so as to additionally store the core identifier of the second target processing core at the target storage address.

[0189] S5100. Write the target storage address, the third target cache data, and the target mask information through the write port group of the second cache device to store the core identifier of the second target processing core that matches the second target instruction fetch miss identifier in the second cache device.

[0190] S5110: Generate second target cache data according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data.

[0191] Because the second target missing instruction identifier has not been stored by the first cache device, the mapping relationship between the kernel and the corresponding data bits in the cache data can be directly processed to generate the corresponding second target cache data.

[0192] Continuing with the previous example, the second target processing core is the third bit of the 12 data bits, so the second target cache data of the form 001000000000 can be constructed.

[0193] S5120: Push the second target cache data into the first queue or the second queue of the second cache device through the push port of the second cache device.

[0194] The technical solution of the embodiment of the present application, by setting a first cache device in a high-speed instruction cache, can simultaneously store an instruction missing flag that has not been initiated and an instruction missing flag that has been responded to by the bus but has not been written back when an instruction miss occurs, thereby greatly saving the number of cache devices used. In addition, through the write port group and the read port in the second cache device, the core flag of the processing core that matches the instruction missing flag can be synchronously cached or read without using a register group to store the above information, thereby reducing complex logic control;

[0195] In addition, through the write port group in the second cache device, when receiving instruction retrieval requests for the same missing instruction from different processing cores of the multi-core processor, the information of the above processing cores can be written to the same storage address, which reuses the limited storage space to the maximum extent and improves the processing performance. In addition, it can avoid the multi-core processor from sending repeated instruction fetch requests to the external instruction storage device, thereby greatly reducing many unnecessary delays of the multi-core processor, thereby improving the performance of the multi-core processor.

[0196] On the basis of the above embodiments, at least one of the following may also be included:

[0197] If there is no cache data in the first queue of the first cache device, setting the empty state identification bit in the first empty and full state flag bit group of the first cache device to a target level value;

[0198] If the first queue of the first cache device is full, setting the full state identification bit in the first empty and full state flag bit group of the first cache device to a target level value;

[0199] If there is no cache data in the second queue of the first cache device, setting the empty state identification bit in the second empty and full state flag bit group of the first cache device to a target level value; and

[0200] If the second queue of the first cache device is full, the full state identification bit in the second empty and full state flag bit group of the first cache device is set to a target level value.

[0201] Correspondingly, the method may further include: if it is detected that the full status identification bit in the first empty and full status flag bit group or the second empty and full status flag bit group of the first cache device is a target level value, then no longer receiving an instruction fetch request from any processing core in the multi-core processor.

[0202] Sixth embodiment

[0203] Figure 6 FIG. 4 shows a schematic diagram of the structure of a data processing device provided in the sixth embodiment of the present application. Figure 6 As shown, the data processing device 600 is executed by an instruction cache in an instruction processing system provided by any embodiment of the present application, and the device includes:

[0204] A first pop-up processing module 610 is used to take out a missing instruction identifier from a first queue of a first cache device and pop it out through a first pop-up port to provide it to the external instruction memory when detecting that the external instruction memory is in an idle state;

[0205] A second pop-up processing module 620 is configured to, when detecting a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier, take out the first target missing instruction identifier from the second queue of the first cache device and pop it out through the second pop-up port of the first cache device;

[0206] A third pop-up processing module 630 is used to fetch the first target cache data matching the first target missing instruction identifier from the second cache device and pop it out through a second pop-up port of the second cache device;

[0207] The write-back instruction sending module 640 is used to identify the first target core identifier of the first target processing core that matches the first target instruction fetch miss identifier based on the first target cache data, and send the write-back instruction to the processing core that matches the first target core identifier.

[0208] In this embodiment, through the two queues set in the first buffer and the pop-up ports for different queues, the instruction missing flags that have not been initiated and the instruction missing flags that have been responded to by the bus but not yet written back can be popped up respectively, which greatly saves the number of cache devices used by the instruction cache; in addition, through the pop-up port of the second buffer, the core flag of the processing core that matches the instruction missing flag can be synchronously popped out without using a register group to store the above information, thereby reducing complex logical control.

[0209] Based on the above embodiments, the present invention may further include a first missing instruction identifier writing module, which is used to:

[0210] When it is detected that a second target processing core has a fetch instruction miss for a second target missing instruction identifier, reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first cache device;

[0211] If the second target missing instruction identifier is not stored in the first queue and the second queue of the first cache device, storing the second target missing instruction identifier in the first queue and the second queue at the same time;

[0212] Generate second target cache data according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data;

[0213] The second target cache data is pushed into the first queue or the second queue of the second cache device through the push port of the second cache device.

[0214] Based on the above embodiments, a second missing instruction identifier writing module may also be included, which is used to:

[0215] After reading all missing instruction identifiers stored in the first queue and the second queue from the read port of the first cache device, if the second target missing instruction identifier is stored in the first queue or the second queue of the first cache device, obtaining a target storage address of the second target missing instruction identifier in the first cache device;

[0216] Generate third target cache data and target mask information according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data;

[0217] The target storage address, the third target cache data and the target mask information are written through the write port group of the second cache device to store the core identifier of the second target processing core matching the second target instruction fetch miss identifier in the second cache device.

[0218] Based on the above embodiments, at least one of the following is also included:

[0219] A first empty state flag bit setting module, configured to set an empty state flag bit in a first empty and full state flag bit group of the first cache device to a target level value if there is no cached data in the first queue of the first cache device;

[0220] A first full state flag bit setting module, configured to set a full state flag bit in a first empty and full state flag bit group of the first cache device to a target level value if the first queue of the first cache device is full;

[0221] A second empty state flag bit setting module, configured to set the empty state flag bit in the second empty and full state flag bit group of the first cache device to a target level value if there is no cached data in the second queue of the first cache device; and

[0222] The second full state flag bit setting module is used to set the full state flag bit in the second empty and full state flag bit group of the first cache device to a target level value if the second queue of the first cache device is full.

[0223] On the basis of the above embodiments, the present invention may further include an instruction fetch request abandonment processing module, which is used to:

[0224] If it is detected that the full state identification bit in the first empty and full state flag bit group or the second empty and full state flag bit group of the first cache device is a target level value, then no instruction fetch request from any processing core in the multi-core processor is received.

[0225] According to an embodiment of the present application, the present application further provides a readable storage medium on which a computer program is stored. When the program is executed by a processor, the data processing method provided in all the application embodiments of the present application is implemented: that is, when the program is executed by a processor, the following is implemented:

[0226] When it is detected that the external instruction memory is in an idle state, a missing instruction identifier is taken out from the first queue of the first cache device, and is popped out through the first pop-up port to be provided to the external instruction memory; when a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier is detected, the first target missing instruction identifier is taken out from the second queue of the first cache device, and is popped out through the second pop-up port of the first cache device; first target cache data matching the first target missing instruction identifier is taken out from the second cache device, and is popped out through the first pop-up port or the second pop-up port of the second cache device; based on the first target cache data, a first target core identifier of a first target processing core matching the first target instruction fetch missing identifier is identified, and the write-back instruction is sent to the first target processing core.

[0227] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, - but not limited to - electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, RAM, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0228] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0229] The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wire, optical cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

[0230] Computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a LAN or WAN, or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0231] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0232] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A cache device, characterized in that: include: A first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port, and a push port; The write port group is used to write cache data to a set storage address in the first queue and / or the second queue; The read port is used to read all cached data from the first queue and / or the second queue at one time; The push port is used to push cache data into the first queue and / or the second queue; The first pop-up port is used to pop cached data from the first queue; The second pop-up port is used to pop cached data from the second queue.

2. The cache device according to claim 1, characterized in that: The write port group specifically includes: a write data port and a write address port; The write data port is used to receive the written cache data; The write address port is used to receive the storage address written by the cache data written by the write address port in the first queue and / or the second queue.

3. The cache device according to claim 2, characterized in that: The write port group further includes: a write mask port; The write mask port is used to receive mask information of cache data written by the write address port; The mask information is used to indicate data bits of cache data written to the storage address, and the write mask port has the same bit width as the write data port.

4. The cache device according to any one of claims 1 to 3, characterized in that: Also includes: a first empty and full state flag bit group, and a second empty and full state flag bit group; The first empty and full status flag bit group is used to indicate the storage status of the cache data in the first queue; The second empty and full status flag bit group is used to indicate the storage status of the cache data in the second queue.

5. An instruction cache, characterized in that: include: A first cache device and a second cache device; Wherein, the first cache device and the second cache device are both cache devices as described in any one of claims 1-4.

6. An instruction processing system comprising: The instruction cache, multi-core processor, and external instruction memory as claimed in claim 5; The instruction cache is connected to the external instruction memory and multiple processing cores of the multi-core processor respectively, and the instruction cache is connected to the external instruction memory through a bus.

7. The system according to claim 6, characterized in that: The multi-core processor is used to provide a missing instruction identifier to the instruction cache when an instruction fetch miss occurs; The external instruction memory is used to store instructions; The instruction cache is used to send the missing instruction identifier to the external instruction memory, and obtain the instruction responded and written back by the external instruction memory through the bus.

8. The system according to claim 7, characterized in that: The first cache device is used to use the first queue to cache instruction fetch miss flags that have occurred but have not been responded to by the external instruction memory, and to use the second queue to cache instruction fetch miss flags that have been responded to by the external instruction memory but have not been written back; The second cache device is used to use the first queue or the second queue to store the core identifier of the processing core matching the instruction fetch miss identifier in accordance with the storage address of the instruction fetch miss identifier in the first cache device.

9. A data processing method, executed by an instruction cache in the instruction processing system of claim 6, characterized in that: include: When it is detected that the external instruction memory is in an idle state, taking out the missing instruction identifier from the first queue of the first cache device, popping it out through the first pop-up port, and providing it to the external instruction memory; When a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier is detected, the first target missing instruction identifier is taken out from the second queue of the first cache device and ejected through the second eject port of the first cache device; fetching the first target cache data matching the first target missing instruction identifier from the second cache device, and popping it out through the first pop-up port or the second pop-up port of the second cache device; A first target core identifier of a first target processing core matching the first target missing instruction identifier is identified according to the first target cache data, and the write-back instruction is sent to the first target processing core.

10. The method according to claim 9, characterized in that Also includes: When it is detected that a second target processing core has a fetch instruction miss for a second target missing instruction identifier, reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first cache device; If the second target missing instruction identifier is not stored in the first queue and the second queue of the first cache device, storing the second target missing instruction identifier in the first queue and the second queue at the same time; Generate second target cache data according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data; The second target cache data is pushed into the first queue or the second queue of the second cache device through the push port of the second cache device.

11. The method according to claim 10, characterized in that After reading all missing instruction identifiers stored in the first queue and the second queue from the read port of the first cache device, the method further includes: If the second target missing instruction identifier is stored in the first queue or the second queue of the first cache device, obtaining a target storage address of the second target missing instruction identifier in the first cache device; Generate third target cache data and target mask information according to the second target processing core and a mapping relationship between a preset processing core and corresponding data bits in the cache data; The target storage address, the third target cache data and the target mask information are written through the write port group of the second cache device to store the core identifier of the second target processing core matching the second target missing instruction identifier in the second cache device.

12. The method according to any one of claims 9 to 11, characterized in that: Also includes at least one of the following: If there is no cache data in the first queue of the first cache device, setting the empty state identification bit in the first empty and full state flag bit group of the first cache device to a target level value; If the first queue of the first cache device is full, setting the full state identification bit in the first empty and full state flag bit group of the first cache device to a target level value; If there is no cache data in the second queue of the first cache device, setting the empty state identification bit in the second empty and full state flag bit group of the first cache device to a target level value; as well as If the second queue of the first cache device is full, the full state identification bit in the second empty and full state flag bit group of the first cache device is set to a target level value.

13. The method according to claim 12, characterized in that Also includes: If it is detected that the full state identification bit in the first empty and full state flag bit group or the second empty and full state flag bit group of the first cache device is a target level value, then no instruction fetch request from any processing core in the multi-core processor is received.

14. A data processing device executed by an instruction cache in the instruction processing system according to claim 6, characterized in that: include: A first pop-up processing module is used to take out the missing instruction identifier from the first queue of the first cache device and pop it out through the first pop-up port to provide it to the external instruction memory when detecting that the external instruction memory is in an idle state; A second pop-up processing module is used to, when detecting a write-back instruction fed back by the external instruction memory for the first target missing instruction identifier, take out the first target missing instruction identifier from the second queue of the first cache device and pop it out through the second pop-up port of the first cache device; A third pop-up processing module, configured to fetch the first target cache data matching the first target missing instruction identifier from the second cache device, and pop it out through a second pop-up port of the second cache device; A write-back instruction sending module is used to identify a first target core identifier of a first target processing core that matches the first target missing instruction identifier based on the first target cache data, and send the write-back instruction to the processing core that matches the first target core identifier.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 9 to 13.

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