Flash simulation circuit and operation method thereof

Abstract

The present invention provides a Flash simulation circuit and an operation method thereof, comprising: a Flash control logic unit, which is configured to provide an on-chip Flash operation command to an on-chip Flash simulation unit; an on-chip Flash simulation unit, which is configured to equivalently replace an on-chip Flash, and according to the on-chip Flash operation command, uses a BLOCK RAM module as an on-chip Flash, simulates the behavior of the BLOCK RAM module through a control logic, obtains an on-chip Flash behavior simulation effect, and provides the on-chip Flash behavior simulation effect to the Flash control logic unit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an FPGA storage device and an operating method thereof. Background Art

[0002] In the process of chip development, before the chip is taped out, an FPGA platform is often used as a prototype product of the chip to be provided to software personnel or customers for further development of root (boot) programs or application software.

[0003] FPGA can use logic units and internal block memory to directly implement the digital logic and static random access memory of the chip, but the embedded Flash contained in the chip (referred to as on-chip Flash, or simply Flash) cannot be directly implemented at present. Because the control timing of embedded Flash is complex, it is usually managed by controller logic. The typical SOC chip architecture containing embedded Flash is as follows: Figure 1 As shown in the figure. Due to the complexity of programming timing and application management, software developers need accurate Flash behavior to verify software functions and evaluate software performance during the development process. One of the current methods is to perform simulation verification directly in the EDA environment, but if the software needs to be repeatedly modified and debugged, it will be inconvenient and inefficient. Another method is to use external Flash on the FPGA platform board, such as Figure 2 To achieve equivalent implementation, but this method uses a lot of IO and the speed is subject to the quality of the platform board. In addition, if the timing control of the external Flash is inconsistent with the chip, it is difficult to provide useful help for software personnel to control the Flash.

[0004] The existing FPGA equivalent Flash solution cannot accurately simulate the read and write behavior and performance of Flash, and cannot help software developers verify the software control Flash function and evaluate the Flash-related operating performance during the development process. There is an urgent need for a simple and effective way to solve such problems. Summary of the invention

[0005] The object of the present invention is to provide a Flash simulation circuit and an operation method thereof, so as to solve the problem that the existing FPGA cannot accurately simulate the read and write behavior and performance of Flash.

[0006] In order to solve the above technical problems, the present invention provides a Flash simulation circuit, comprising:

[0007] A Flash control logic unit configured to provide an on-chip Flash operation command to an on-chip Flash emulation unit; and

[0008] The on-chip Flash emulation unit is configured to perform the following actions:

[0009] According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, and the BLOCK RAM module is simulated to obtain the on-chip Flash behavior simulation effect;

[0010] as well as

[0011] Provides on-chip Flash behavior simulation effects to the Flash control logic unit.

[0012] Optionally, in the Flash simulation circuit, the Flash simulation circuit is integrated and implemented in an FPGA chip, and the FPGA chip further includes a control unit;

[0013] The control unit generates an on-chip Flash operation command, and provides the on-chip Flash behavior simulation effect to the Flash control logic unit through a bus interface;

[0014] The Flash control logic unit provides the on-chip Flash behavior simulation effect to the control unit through the bus interface;

[0015] The control unit determines whether the on-chip Flash is normal according to the on-chip Flash behavior simulation effect.

[0016] Optionally, in the Flash simulation circuit, the simulation behavior includes:

[0017] The read operation is configured to read the data corresponding to the on-chip Flash address in the BLOCK RAM module;

[0018] The programming operation is configured to write data to the address of the corresponding on-chip Flash in the BLOCK RAM module;

[0019] The page erase operation is configured to write the initial value after erasure to the entire area of ​​the corresponding on-chip Flash page in the BLOCK RAM module; and

[0020] The chip erase operation is configured to write the initial value after erasure to the entire area of ​​the corresponding on-chip Flash in the BLOCK RAM module.

[0021] Optionally, in the Flash simulation circuit, the on-chip Flash simulation unit further includes:

[0022] The interface module is configured to connect the Flash control logic unit, the timing module and the behavioral equivalent logic module.

[0023] Receive or detect on-chip Flash operation commands,

[0024] Receive or detect timing end signals and simulate the effects of on-chip Flash behavior.

[0025] Providing the on-chip Flash operation command to the timing module and the behavior equivalent logic module, and providing the on-chip Flash behavior simulation effect to the Flash control logic unit according to the timing end signal;

[0026] The timing module is configured to receive or detect on-chip Flash operation commands.

[0027] Timing according to the on-chip Flash operation command, and

[0028] After the timing ends, a timing end signal is provided to the interface module;

[0029] Behavioral equivalent logic module, configured to receive or detect on-chip Flash operation commands,

[0030] According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, the behavior of the BLOCK RAM module is simulated, the on-chip Flash behavior simulation effect is obtained, and the on-chip Flash behavior simulation effect is provided to the interface module.

[0031] Optionally, in the Flash simulation circuit, the interface module includes:

[0032] The read operation flag signal line is configured to output a high level to the behavioral equivalent logic module when detecting that the on-chip Flash operation command is a read operation command;

[0033] The programming operation flag signal line is configured to output a high level to the behavioral equivalent logic module when detecting that the on-chip Flash operation command is a programming operation command;

[0034] The page erase operation flag signal line is configured to output a high level to the behavior equivalent logic module when detecting that the on-chip Flash operation command is a page erase operation command;

[0035] A chip erase operation flag signal line is configured to output a high level to a behavioral equivalent logic module when detecting that the on-chip Flash operation command is a chip erase operation command; and

[0036] The timing signal flag line is configured to output a high level to the timing module after detecting an on-chip Flash operation command.

[0037] Optionally, in the Flash simulation circuit, performing a read operation includes:

[0038] The behavioral equivalent logic module reads the data corresponding to the on-chip Flash address in the BLOCK RAM module and sends it to the interface module;

[0039] After receiving or detecting the timing end signal, the interface module puts the data on the data line, and the Flash control logic unit reads the data on the data line to simulate the read behavior and read speed of the on-chip Flash.

[0040] Optionally, in the Flash simulation circuit, performing a page erase operation includes:

[0041] The behavioral equivalent logic module writes all the areas in the BLOCK RAM module corresponding to a page of the on-chip Flash into the initial value after the on-chip Flash page is erased, and sets an erase mark for each address in the entire page to retrieve whether the address has been erased during programming, and notifies the interface module after completion;

[0042] After receiving or detecting the timing end signal, the interface module notifies the Flash control logic unit that the page erase operation is completed, so as to simulate the page erase speed of the on-chip Flash and the behavior that all data are initialized to fixed values ​​after simulating the page erase.

[0043] Optionally, in the Flash simulation circuit, performing a chip erase operation includes:

[0044] The behavioral equivalent logic module writes the initial value of the erased Flash chip into the entire area of ​​the BLOCK RAM module corresponding to the on-chip Flash, sets an erase mark for each address in the entire chip to retrieve whether the address has been erased during programming, and notifies the interface module after completion;

[0045] After receiving or detecting the timing end signal, the interface module notifies the Flash control logic unit that the chip erase operation is completed to simulate the chip erase speed of the on-chip Flash and the behavior that all data are initialized to fixed values ​​after the chip erase.

[0046] Optionally, in the Flash simulation circuit, performing a program-erase operation includes:

[0047] The behavioral equivalent logic module detects the mark at the address of the corresponding on-chip Flash in the BLOCK RAM module to determine whether the address has been erased and not programmed. If so, data is written to the address and a programming mark is set for the address. Otherwise, data is not written to the address. After completion, the interface module is notified.

[0048] After receiving or detecting the timing end signal, the interface module will notify the Flash control logic unit that the programming operation is completed to simulate the programming speed of the on-chip Flash and the behavior of being unable to be written without being erased or being able to be written after being erased.

[0049] The present invention also provides an operating method of a Flash analog circuit, comprising:

[0050] The Flash control logic unit provides the on-chip Flash operation command to the on-chip Flash emulation unit;

[0051] The on-chip Flash simulation unit uses control logic and a BLOCK RAM module to replace the on-chip Flash equivalently. According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, and the BLOCK RAM module is simulated to obtain the on-chip Flash behavior simulation effect; and

[0052] The on-chip Flash simulation unit provides the on-chip Flash behavior simulation effect to the Flash control logic unit.

[0053] In the Flash simulation circuit and the operation method thereof provided by the present invention, a BLOCK RAM module is used to equivalently replace the on-chip Flash through an on-chip Flash simulation unit. According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, the behavior of the BLOCK RAM module is simulated, and the on-chip Flash behavior simulation effect is provided to the Flash control logic unit, so that the resources inside the FPGA (BLOCK RAM module) are used to simulate the equivalent embedded on-chip Flash, so that the entire circuit structure is simple, the operation method is convenient, and an accurate on-chip Flash model can be provided for software programmers to evaluate the performance and actual behavior of the Flash.

[0054] The timing module is used to perform timing operations for flash reading, programming, page erasing, and chip erasing, thereby simulating the actual operating speed of the flash.

[0055] The behavioral equivalent logic module can simulate behaviors that cannot be completed by programming without erasing, thereby helping to discover defects in software development and speeding up software development.

[0056] The BLOCK RAM module is an inherent resource within the FPGA. It does not require the addition of other resources and can easily simulate the storage data of the Flash, as well as facilitate erase marking or programming marking. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of the existing SOC chip architecture including embedded Flash;

[0058] Figure 2 It is a schematic diagram of using external Flash on the existing FPGA platform board;

[0059] Figure 3It is a schematic diagram of a Flash simulation circuit according to an embodiment of the present invention;

[0060] Figure 4 It is a schematic diagram of an on-chip Flash simulation unit in a Flash simulation circuit according to an embodiment of the present invention;

[0061] As shown in the figure: 10-Flash control logic unit; 20-on-chip Flash simulation unit; 21-interface module; 22-behavioral equivalent logic module; 23-timing module; 24-BLOCK RAM module; 30-control unit; 100-FPGA chip. DETAILED DESCRIPTION

[0062] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0063] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0064] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.

[0065] In addition, the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0066] The Flash simulation circuit and its operation method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0067] In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding feature in the first embodiment or a feature with the same or similar function, and the resulting embodiment also falls within the disclosure or description scope of the present application.

[0068] The core idea of ​​the present invention is to provide a Flash simulation circuit and an operation method thereof to solve the problem that the existing FPGA cannot accurately simulate the read and write behavior and performance of Flash.

[0069] To realize the above idea, the present invention provides a Flash simulation circuit and an operation method thereof, comprising: a Flash control logic unit provides an on-chip Flash operation command to an on-chip Flash simulation unit; the on-chip Flash simulation unit uses a BLOCK RAM module to equivalently replace the on-chip Flash, and according to the on-chip Flash operation command, uses the BLOCK RAM module as the on-chip Flash, simulates the behavior of the BLOCK RAM module, and obtains the on-chip Flash behavior simulation effect; and the on-chip Flash simulation unit provides the on-chip Flash behavior simulation effect to the Flash control logic unit.

[0070] An embodiment of the present invention provides a Flash simulation circuit, such as Figure 1 , 2 As shown, it includes: a Flash control logic unit 10, which is configured to provide an on-chip Flash operation command to an on-chip Flash simulation unit 20; the on-chip Flash simulation unit 20, which is configured to use a BLOCK RAM module 24 to equivalently replace the on-chip Flash (or simply referred to as Flash), and according to the on-chip Flash operation command, use the BLOCK RAM module 24 as the on-chip Flash, simulate the behavior of the BLOCK RAM module 24, obtain the on-chip Flash behavior simulation effect, and provide the on-chip Flash behavior simulation effect to the Flash control logic unit 10.

[0071] In one embodiment of the present invention, in the Flash simulation circuit, as Figure 1 As shown, the Flash simulation circuit is integrated in the FPGA chip 100, and the FPGA chip also includes a control unit 30; the control unit 30 generates an on-chip Flash operation command, and provides the on-chip Flash operation command to the Flash control logic unit 10 through a bus interface; after the on-chip Flash simulation unit 20 generates an on-chip Flash behavior simulation effect, it sends it to the Flash control logic unit 10 through a control interface, so that the Flash control logic unit 10 provides the on-chip Flash behavior simulation effect to the control unit 30 through a bus interface; the control unit 30 determines whether the on-chip Flash is normal according to the on-chip Flash behavior simulation effect.

[0072] In one embodiment of the present invention, in the Flash simulation circuit, the simulation behavior includes: a read operation, which is configured to read out data corresponding to the on-chip Flash address in the BLOCK RAM module 24; a programming operation, which is configured to write data to the address corresponding to the on-chip Flash in the BLOCK RAM module 24; a page erase operation, which is configured to write the initial value after erasure to the entire area of ​​the on-chip Flash corresponding to a page of the BLOCK RAM module 24; and a chip erase operation, which is configured to write the initial value after erasure to the entire area of ​​the on-chip Flash corresponding to the BLOCK RAM module 24.

[0073] In one embodiment of the present invention, in the Flash simulation circuit, as Figure 2 As shown, the on-chip Flash simulation unit 20 also includes: an interface module 21, which is configured to connect the Flash control logic unit 10, the timing module 23 and the behavior equivalent logic module 22, receive or detect the on-chip Flash operation command, receive or detect the timing end signal and the on-chip Flash behavior simulation effect, provide the on-chip Flash operation command to the timing module 23 and the behavior equivalent logic module 22, and provide the on-chip Flash behavior simulation effect to the Flash control logic unit 10 according to the timing end signal; the timing module 23 is configured to receive or detect the on-chip Flash operation command, perform timing according to the on-chip Flash operation command, and provide the timing end signal to the interface module 21 after the timing ends; the behavior equivalent logic module 22 is configured to receive or detect the on-chip Flash operation command, according to the on-chip Flash operation command, use the BLOCK RAM module 24 as the on-chip Flash, simulate the behavior of the BLOCK RAM module 24, obtain the on-chip Flash behavior simulation effect, and provide the on-chip Flash behavior simulation effect to the interface module 21.

[0074] In one embodiment of the present invention, in the Flash simulation circuit, the interface module 21 includes: a read operation signal flag line, configured to detect that the on-chip Flash operation command is a read operation command, and then output a high level to the behavioral equivalent logic module 22; a programming operation flag signal line, configured to detect that the on-chip Flash operation command is a programming operation command, and then output a high level to the behavioral equivalent logic module 22; a page erase operation flag signal line, configured to detect that the on-chip Flash operation command is a page erase operation command, and then output a high level to the behavioral equivalent logic module 22; a chip erase operation flag signal line, configured to detect that the on-chip Flash operation command is a chip erase operation command, and then output a high level to the behavioral equivalent logic module 22; and a timing flag signal line, configured to output a high level to the timing module 23 after detecting the on-chip Flash operation command.

[0075] In one embodiment of the present invention, in the Flash simulation circuit, the read operation includes: the behavior equivalent logic module 22 reads the data corresponding to the on-chip Flash address in the BLOCK RAM module 24 and sends it to the interface module 21; after receiving or detecting the timing end signal, the interface module 21 puts the data on the data line, and the Flash control logic unit 10 reads the data on the data line to simulate the read behavior and read speed of the on-chip Flash. Thus, the actual read behavior and read speed of the Flash are accurately simulated.

[0076] In one embodiment of the present invention, in the Flash simulation circuit, the page erase operation includes: the behavior equivalent logic module 22 writes the area corresponding to a page of the on-chip Flash in the BLOCK RAM module 24 to the initial value after the on-chip Flash page is erased (usually all 1s), sets an erase mark for each address in the entire page (using the value of the write register as a mark, each register bit corresponds to each address of the Flash), so as to retrieve whether the address has been erased during programming, and notifies the interface module 21 after completion; after receiving or detecting the timing end signal, the interface module 21 notifies the Flash control logic unit 10 that the page erase operation is completed, so as to simulate the page erase speed of the on-chip Flash and the behavior that all the data are initialized to fixed values ​​after the simulated page erase. Thus, the actual page erase speed of the Flash and the behavior that all the data are initialized to fixed values ​​after the simulated page erase are accurately simulated.

[0077] In one embodiment of the present invention, in the Flash simulation circuit, the chip erase operation includes: the behavior equivalent logic module 22 writes the initial value of the chip after the chip erase (usually all 1) to the area of ​​the entire chip corresponding to the on-chip Flash in the BLOCK RAM module 24, sets an erase mark for each address in the entire chip (using the value of the write register as a mark, each register bit corresponds to each address of the Flash), so as to retrieve whether the address has been erased during programming, and notify the interface module 21 after completion; after receiving or detecting the timing end signal, the interface module 21 notifies the Flash control logic unit 10 that the chip erase operation is completed, so as to simulate the chip erase speed of the on-chip Flash and the behavior that all the data are initialized to fixed values ​​after the chip erase. In this way, the actual chip erase speed of the Flash and the behavior that all the data are initialized to fixed values ​​after the chip erase are accurately simulated.

[0078] In one embodiment of the present invention, in the Flash simulation circuit, performing a programming and erasing operation includes: the behavior equivalent logic module 22 detects the mark at the address corresponding to the on-chip Flash in the BLOCK RAM module 24 to determine whether the address has been erased and not programmed, if so, writes data to the address and sets a programming mark for the address (using the value of the write register as a mark, each register bit corresponds to each address of the Flash), otherwise, does not write data to the address, and notifies the interface module 21 after completion; after receiving or detecting the timing end signal, the interface module 21 notifies the Flash control logic unit 10 that the programming operation is completed to simulate the programming speed of the on-chip Flash and simulate the behavior of not being erased and not being written or being able to be written after being erased. Thus, the actual programming speed of the Flash and the behavior of not being erased and not being written or being able to be written after being erased are accurately simulated.

[0079] The present invention also provides an operation method of a Flash simulation circuit, comprising: a Flash control logic unit 10 provides an on-chip Flash operation command to an on-chip Flash simulation unit 20; the on-chip Flash simulation unit 20 uses a BLOCK RAM module 24 to equivalently replace the on-chip Flash, and according to the on-chip Flash operation command, uses the BLOCK RAM module 24 as the on-chip Flash, simulates the behavior of the BLOCK RAM module 24, and obtains an on-chip Flash behavior simulation effect; and the on-chip Flash simulation unit 20 provides the on-chip Flash behavior simulation effect to the Flash control logic unit 10.

[0080] In the Flash simulation circuit and operation method thereof provided by the present invention, the BLOCK RAM module 24 is used to replace the on-chip Flash equivalently through the on-chip Flash simulation unit 20. According to the on-chip Flash operation command, the BLOCK RAM module 24 is used as the on-chip Flash, the behavior of the BLOCK RAM module 24 is simulated, and the on-chip Flash behavior simulation effect is provided to the Flash control logic unit 10, thereby realizing the use of the internal resources of the FPGA (BLOCK RAM module 24) to simulate the equivalent embedded on-chip Flash. The entire circuit structure is simple, the operation method is convenient, and an accurate on-chip Flash model can be provided to software programmers for evaluating the performance and actual behavior of the Flash.

[0081] The timing module 23 performs timing operations for Flash reading, programming, page erasing, and chip erasing, thereby simulating the actual operation speed of Flash, overcoming the problem that the existing FPGA cannot accurately simulate the reading and writing behavior and performance of Flash.

[0082] The behavior equivalent logic module 22 can simulate behaviors that cannot be completed by programming without erasing, thereby helping to discover defects in software development and speeding up software development.

[0083] The BLOCK RAM module 24 is an inherent resource within the FPGA, and does not require the addition of other resources. It can conveniently simulate the storage data of the Flash and is also convenient for performing erase marking or programming marking.

[0084] Under normal circumstances, Flash must follow the process of erasing and then writing, and the control timing of erasing and writing is relatively complicated. SRAM is relatively simple to use and can be implemented with a simple control timing. Therefore, using BLOCK RAM modules to replace Flash can overcome the inconvenience and low efficiency of FPGA simulation Flash.

[0085] The above scheme can be expanded to simulate the behavior of Flash test, and can also be adapted to simulate the behavior of other non-volatile memories similar to Flash (such as eeprom).

[0086] The present invention provides a circuit and method for simulating on-chip Flash using FPGA BLOCK RAM, using a synthesizable Flash model to equivalently replace the embedded Flash of the chip, and can accurately simulate the behavior of Flash reading, programming, page erasing, and chip erasing, thereby providing accurate Flash behavior for software development. The synthesizable Flash model includes an interface module, a timing module, a behavior equivalent logic module, and a BLOCK RAM module.

[0087] In summary, the above embodiments describe in detail different configurations of the Flash simulation circuit and its operation method. Of course, the present invention includes but is not limited to the configurations listed in the above embodiments. Any content that is transformed based on the configurations provided in the above embodiments belongs to the scope of protection of the present invention. Those skilled in the art can draw inferences from the above embodiments.

[0088] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0089] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A Flash simulation circuit, characterized in that: include: A flash control logic unit configured to provide an on-chip flash operation command to an on-chip flash emulation unit; as well as The on-chip Flash emulation unit is configured to perform the following actions: The BLOCK RAM module is used to replace the on-chip Flash equivalently. According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, and the BLOCK RAM module is simulated to obtain the on-chip Flash behavior simulation effect. as well as Provides on-chip Flash behavior simulation effects to the Flash control logic unit.

2. The Flash simulation circuit according to claim 1, characterized in that: The Flash simulation circuit is implemented in an FPGA chip, and the FPGA chip also includes a control unit; The control unit generates an on-chip Flash operation command, and provides the on-chip Flash behavior simulation effect to the Flash control logic unit through a bus interface; The Flash control logic unit provides the on-chip Flash behavior simulation effect to the control unit through the bus interface; The control unit determines whether the on-chip Flash is normal according to the on-chip Flash behavior simulation effect.

3. The Flash simulation circuit according to claim 1, characterized in that: The simulation behaviors include: The read operation is configured to read the data corresponding to the on-chip Flash address in the BLOCK RAM module; The programming operation is configured to write data to the address of the corresponding on-chip Flash in the BLOCK RAM module; The page erase operation is configured to write the initial value after erasure to the entire area of ​​the corresponding on-chip Flash page in the BLOCK RAM module; and The chip erase operation is configured to write the initial value after erasure to the entire area of ​​the corresponding on-chip Flash in the BLOCK RAM module.

4. The Flash simulation circuit as claimed in claim 3, characterized in that: The on-chip Flash simulation unit also includes: The interface module is configured to connect the Flash control logic unit, the timing module and the behavioral equivalent logic module. Receive or detect on-chip Flash operation commands, Receive or detect timing end signals and simulate the effects of on-chip Flash behavior. Provides on-chip Flash operation commands to the timing module and behavioral equivalent logic module, and Providing the on-chip Flash behavior simulation effect to the Flash control logic unit according to the timing end signal; The timing module is configured to receive or detect on-chip Flash operation commands. Timing according to the on-chip Flash operation command, and After the timing ends, a timing end signal is provided to the interface module; Behavioral equivalent logic module, configured to receive or detect on-chip Flash operation commands, According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, and the BLOCK RAM module is simulated to obtain the on-chip Flash behavior simulation effect, and Provides on-chip Flash behavior simulation effects to the interface module.

5. The Flash simulation circuit as claimed in claim 4, characterized in that: The interface module comprises: The read operation flag signal line is configured to output a high level to the behavioral equivalent logic module when detecting that the on-chip Flash operation command is a read operation command; The programming operation flag signal line is configured to output a high level to the behavioral equivalent logic module when detecting that the on-chip Flash operation command is a programming operation command; The page erase operation flag signal line is configured to output a high level to the behavior equivalent logic module when detecting that the on-chip Flash operation command is a page erase operation command; A chip erase operation flag signal line is configured to output a high level to a behavioral equivalent logic module when detecting that the on-chip Flash operation command is a chip erase operation command; and The timing signal flag line is configured to output a high level to the timing module after detecting an on-chip Flash operation command.

6. The Flash simulation circuit according to claim 4, characterized in that: The read operation includes: The behavioral equivalent logic module reads the data corresponding to the on-chip Flash address in the BLOCK RAM module and sends it to the interface module; After receiving or detecting the timing end signal, the interface module puts the data on the data line, and the Flash control logic unit reads the data on the data line to simulate the read behavior and read speed of the on-chip Flash.

7. The Flash simulation circuit according to claim 4, characterized in that: The page erase operation includes: The behavioral equivalent logic module writes all the areas in the BLOCK RAM module corresponding to a page of the on-chip Flash into the initial value after the on-chip Flash page is erased, and sets an erase mark for each address in the entire page to retrieve whether the address has been erased during programming, and notifies the interface module after completion; After receiving or detecting the timing end signal, the interface module notifies the Flash control logic unit that the page erase operation is completed, so as to simulate the page erase speed of the on-chip Flash and the behavior that all data are initialized to fixed values ​​after simulating the page erase.

8. The Flash simulation circuit according to claim 4, characterized in that: The chip erase operation includes: The behavioral equivalent logic module writes the initial value of the erased Flash chip into the entire area of ​​the BLOCK RAM module corresponding to the on-chip Flash, sets an erase mark for each address in the entire chip to retrieve whether the address has been erased during programming, and notifies the interface module after completion; After receiving or detecting the timing end signal, the interface module notifies the Flash control logic unit that the chip erase operation is completed to simulate the chip erase speed of the on-chip Flash and the behavior that all data are initialized to fixed values ​​after the chip erase.

9. The Flash simulation circuit according to claim 4, characterized in that: The program and erase operations include: The behavioral equivalent logic module detects the mark at the address of the corresponding on-chip Flash in the BLOCK RAM module to determine whether the address has been erased and not programmed. If so, data is written to the address and a programming mark is set for the address. Otherwise, data is not written to the address. After completion, the interface module is notified. After receiving or detecting the timing end signal, the interface module will notify the Flash control logic unit that the programming operation is completed to simulate the programming speed of the on-chip Flash and the behavior of being unable to be written without being erased or being able to be written after being erased.

10. A method for operating a Flash analog circuit, characterized in that: include: The Flash control logic unit provides the on-chip Flash operation command to the on-chip Flash emulation unit; The on-chip Flash simulation unit uses the BLOCK RAM module to replace the on-chip Flash equivalently. According to the on-chip Flash operation command, the BLOCK RAM module is used as the on-chip Flash, and the BLOCK RAM module is simulated to obtain the on-chip Flash behavior simulation effect. as well as The on-chip Flash simulation unit provides the on-chip Flash behavior simulation effect to the Flash control logic unit.

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