Display device

Abstract

A display device is disclosed, comprising a display panel, a timing controller, and a power management integrated circuit (PMIC). The timing controller is configured to control the operation of the display panel and store multiple fault modes to be displayed on the display panel to indicate that multiple defect phenomena have occurred. The PMIC is configured to provide a first power supply voltage to the timing controller and monitor whether multiple defect phenomena have occurred. When a first defect phenomenon among multiple defect phenomena is sensed, the PMIC is configured to store first fault data indicating that the first defect phenomenon has occurred and to turn off the display panel. When the first defect phenomenon is sensed, the timing controller controls the display panel to display a first fault mode corresponding to the first defect phenomenon among multiple fault modes before the display panel is turned off.

Description

Technical Field

[0001] Example embodiments relate generally to displaying images, and more particularly to a display device and a method of operating a display device. Background Art

[0002] In recent years, flat panel displays (FPDs) that can easily cover a large area and can be thin and lightweight have been widely used as display devices. For example, FPDs may include, but are not limited to, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs).

[0003] Typically, a display device includes a display panel and a timing controller. The display panel displays an image, and the timing controller controls the overall operation of the display panel. In addition, the display device may also include a power management integrated circuit (PMIC) to supply power to the timing controller. Due to various reasons, defects or failures may occur in the display device, and in the case where the defects and / or the causes of the defects are analyzed later, the defects and / or the causes of the defects may be recorded in the display device. Summary of the Invention

[0004] Aspects of exemplary embodiments of the present disclosure are directed to a display device capable of effectively analyzing and detecting defects or failures.

[0005] Aspects of exemplary embodiments of the present disclosure relate to a method of operating a display apparatus.

[0006] According to an exemplary embodiment, a display device includes a display panel, a timing controller, and a power management integrated circuit (PMIC). The display panel includes a plurality of pixels. The timing controller is used to control the operation of the display panel and store a plurality of fault modes to be displayed on the display panel. The plurality of fault modes are used to indicate that a plurality of defect phenomena have occurred when the display panel is driven. The PMIC is used to provide a first supply voltage to the timing controller and monitor whether a plurality of defect phenomena have occurred. When a first defect phenomenon among the plurality of defect phenomena is sensed, the PMIC is used to store first fault data indicating that the first defect phenomenon has occurred and to turn off the display panel. When the first defect phenomenon is sensed, the timing controller is used to control the display panel to display a first fault mode corresponding to the first defect phenomenon among the plurality of fault modes before the display panel is turned off by the PMIC.

[0007] In an exemplary embodiment, the timing controller may include a storage unit, a fault mode display controller, and an image processor. The storage unit may store a plurality of fault modes. When a first defect phenomenon is sensed, the fault mode display controller may read first fault data indicating that the first defect phenomenon has occurred from the PMIC, and may read a first fault mode corresponding to the first defect phenomenon from the storage unit based on the first fault data. The image processor may generate fault image data corresponding to the first fault mode.

[0008] In an exemplary embodiment, a PMIC may include a power supply, a sensor, and a storage unit. The power supply may generate a first supply voltage based on an external supply voltage. The sensor may monitor whether multiple defect phenomena have occurred. When a first defect phenomenon is sensed, the storage unit of the PMIC may store first fault data.

[0009] In an exemplary embodiment, the timing controller may include a first fault detection pin, the PMIC may include a second fault detection pin, and the timing controller may determine whether the first defect phenomenon has occurred by using the first fault detection pin and the second fault detection pin.

[0010] In an exemplary embodiment, when a first defect phenomenon is sensed, the PMIC may transition the voltage level of the second fault detection pin from the first level to the second level. The timing controller may check whether the voltage level of the second fault detection pin is at the second level through the first fault detection pin, and may read the first fault data from the PMIC when the voltage level of the second fault detection pin is at the second level.

[0011] In an exemplary embodiment, the display device may further include a second PMIC. The second PMIC may include a third fault detection pin and may generate a gate clock signal. The second fault detection pin and the third fault detection pin may be electrically coupled (e.g., connected) to each other so that the operation of shutting down the display panel is synchronized.

[0012] In an exemplary embodiment, the timing controller may determine whether the first defect phenomenon has occurred by periodically checking whether the PMIC stores the first fault data.

[0013] In an exemplary embodiment, the timing controller may read first fault data from the PMIC when the PMIC senses the first defect phenomenon and store the first fault data.

[0014] In an exemplary embodiment, the display panel may not be turned off immediately after sensing the first defect phenomenon. The timing controller may read the first fault data from the PMIC during a first time interval immediately after sensing the first defect phenomenon. The display panel may display the first fault mode during a second time interval after the first time interval and may be turned off after the second time interval.

[0015] In an exemplary embodiment, the PMIC may turn off the display panel by blocking the first power supply voltage to be supplied to the timing controller.

[0016] In an exemplary embodiment, the display device may further include a gate driver. The gate driver may be coupled (e.g., connected) to a plurality of gate lines of the display panel, may generate a plurality of gate signals based on a gate clock signal, and may apply the plurality of gate signals to the plurality of gate lines. The PMIC may supply the gate clock signal to the gate driver.

[0017] In an exemplary embodiment, the PMIC may turn off the display panel by blocking a gate clock signal to be supplied to the gate driver.

[0018] In an exemplary embodiment, the display device may further include a data driver. The data driver may be coupled (e.g., connected) to a plurality of data lines of the display panel, may generate a plurality of data voltages based on output image data provided by the timing controller, and may apply the plurality of data voltages to the plurality of data lines. The PMIC may supply a second power supply voltage to the data driver.

[0019] In an exemplary embodiment, the PMIC may turn off the display panel by blocking the second power supply voltage to be supplied to the data driver.

[0020] In an exemplary embodiment, the plurality of defect phenomena may include at least one selected from an overcurrent protection fault, a zero current detection fault, a temperature fault, and a communication fault.

[0021] According to an exemplary embodiment, in a method for operating a display device, power is supplied to a display device including a display panel, a timing controller, and a power management integrated circuit (PMIC). The display panel includes a plurality of pixels. The timing controller controls the operation of the display panel and stores a plurality of fault modes to be displayed on the display panel. The plurality of fault modes are used to indicate that a plurality of defect phenomena have occurred when the display panel is driven. Whether the plurality of defect phenomena have occurred is monitored by the PMIC. When a first defect phenomenon among the plurality of defect phenomena is sensed, the first defect mode among the plurality of fault modes is displayed on the display panel. The first fault mode corresponds to the first defect phenomenon. After the first fault mode is displayed on the display panel, the display panel is turned off.

[0022] In an exemplary embodiment, the timing controller may include a first fault detection pin, the PMIC may include a second fault detection pin, and the timing controller may determine whether the first defect phenomenon has occurred by using the first fault detection pin and the second fault detection pin.

[0023] In an exemplary embodiment, during display of a first fault pattern on a display panel, when a first defect phenomenon is sensed, first fault data indicating that the first defect phenomenon has occurred may be stored in a PMIC. When the first defect phenomenon is sensed, the voltage level of a second fault detection pin may be changed from a first level to a second level. Whether the voltage level of a second fault detection pin is at the second level may be checked via the first fault detection pin. When the voltage level of the second fault detection pin is at the second level, the first fault data may be read from the PMIC. A first fault pattern corresponding to the first defect phenomenon may be read based on the first fault data. Fault image data corresponding to the first fault pattern may be generated and provided to the display panel.

[0024] In an exemplary embodiment, the timing controller may determine whether the first defect phenomenon has occurred by periodically checking whether the PMIC stores first fault data indicating that the first defect phenomenon has occurred.

[0025] In an exemplary embodiment, during display of a first fault pattern on a display panel, when a first defect phenomenon is sensed, the first fault data may be stored in a PMIC. When the first defect phenomenon is sensed and the first fault data is stored in the PMIC, the first fault data may be read from the PMIC. A first fault pattern corresponding to the first defect phenomenon may be read based on the first fault data. Fault image data corresponding to the first fault pattern may be generated and provided to the display panel.

[0026] In a display device and a method for operating a display device according to an exemplary embodiment, multiple fault modes indicating that multiple defect phenomena have occurred can be pre-stored. When at least one selected from a plurality of defect phenomena is sensed by a monitoring operation while the display panel is driven, the corresponding fault mode can be displayed before the display panel is turned off. Therefore, users and engineers can identify or recognize the type or kind of defects or faults without any additional process. For example, if a defect occurs during use by a consumer, the fault analysis schedule can be shortened, and the cost of retrieving the product can be minimized or reduced. If a defect occurs during the manufacturing process, the type or kind of the defect can be easily identified and the defect rate can be calculated. Therefore, defects or faults can be effectively analyzed and detected without additional costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, which show non-limiting exemplary embodiments.

[0028] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment.

[0029] Figure 2 is a diagram for describing an operation of a display device according to an exemplary embodiment.

[0030] Figure 3 is a block diagram illustrating an example of a timing controller included in a display device according to an exemplary embodiment.

[0031] Figure 4 is used to describe Figure 3 Diagram of the operation of the timing controller.

[0032] Figure 5 is a block diagram illustrating an example of a PMIC included in a display device according to an exemplary embodiment.

[0033] Figure 6 is a block diagram illustrating an example of a timing controller and a PMIC included in a display device according to an exemplary embodiment.

[0034] Figure 7 is a timing chart for describing the operation of the display device according to an exemplary embodiment.

[0035] Figure 8 is a block diagram illustrating another example of a timing controller and a PMIC included in a display device according to an exemplary embodiment.

[0036] Figure 9 is a block diagram illustrating a display device according to an exemplary embodiment.

[0037] Figure 10 is a block diagram illustrating still another example of a timing controller and a PMIC included in a display device according to an exemplary embodiment.

[0038] Figure 11 is a flowchart illustrating a method of operating a display apparatus according to an exemplary embodiment.

[0039] Figure 12 and Figure 13 is a flowchart illustrating an example of displaying a failure mode in a method of operating a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0040] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout this application, the same reference numerals represent the same elements. As used herein, when describing embodiments of the present disclosure, the use of the term "may" refers to "one or more embodiments of the present disclosure."

[0041] Should be understood that, although the term first, second etc. can be used to describe various elements in this article, these elements should not be limited by these terms.These terms are used to distinguish an element from another element.For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.As used herein, the term "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to explain the inherent deviation of the measured value or calculated value that those of ordinary skill in the art will recognize.

[0042] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.) should be interpreted in a similar manner.

[0043] The terms used herein are for the purpose of describing exemplary embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, wholes, tasks, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, tasks, operations, elements, and / or components.

[0044] For ease of description, spatially relative terms such as "below," "beneath," "down," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It should be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the elements or features described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0046] It should also be noted that in some implementations, the functions, actions, or tasks indicated in the blocks (e.g., indicated by the blocks) may not occur in the order indicated in the flowchart (e.g., indicated by the flowchart). For example, the functions, actions, or tasks indicated in two blocks shown in succession may be performed substantially simultaneously or in parallel, or the functions, actions, or tasks indicated in the blocks may be performed in the reverse order, depending on the functions, actions, or tasks involved.

[0047] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment. Figure 2 is a diagram for describing an operation of a display device according to an exemplary embodiment.

[0048] refer to Figure 1 and Figure 2 The display device 10 includes a display panel 100 , a timing controller 200 , and a power management integrated circuit (PMIC) 500 . The display device 10 may further include a gate driver 300 and a data driver 400 .

[0049] The display panel 100 is configured to operate (e.g., display an image) based on output image data DAT. The display panel 100 is coupled (e.g., connected) to a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL may extend in a first direction DR1, and the plurality of data lines DL may extend in a second direction DR2 that intersects (e.g., is substantially perpendicular to) the first direction DR1.

[0050] The display panel 100 includes a plurality of pixels PX arranged in a matrix. Each of the plurality of pixels PX may be electrically coupled (e.g., connected) to a corresponding one of a plurality of gate lines GL and a corresponding one of a plurality of data lines DL. The display panel 100 may include a display area including the plurality of pixels PX and a peripheral area surrounding the display area.

[0051] In some exemplary embodiments, the display panel 100 may be a liquid crystal display (LCD) panel, and each of the plurality of pixels PX may be a pixel including a liquid crystal and a drive transistor for an LCD panel. In other exemplary embodiments, the display panel 100 may be an organic light-emitting display (OLED) panel, and each of the plurality of pixels PX may be a pixel including an organic light-emitting diode and a drive transistor for an OLED panel. In still other exemplary embodiments, the display panel 100 may be a micro light-emitting diode (LED) display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display (QLED) panel. However, exemplary embodiments are not limited thereto, and the display panel 100 and the plurality of pixels PX may be implemented in various suitable manners.

[0052] In some exemplary embodiments, the plurality of pixels PX may include a plurality of red pixels that output (e.g., emit) red light, a plurality of green pixels that output green light, and a plurality of blue pixels that output blue light. In other exemplary embodiments, the plurality of pixels PX may include a plurality of yellow pixels that output yellow light, a plurality of cyan pixels that output cyan light, and a plurality of magenta pixels that output magenta light. In still other exemplary embodiments, the plurality of pixels PX may further include a plurality of white pixels that output white light, or the plurality of pixels PX may include pixels that output light of other colors.

[0053] The timing controller 200 controls the operation of the display panel 100, the gate driver 300, the data driver 400, and the PMIC 500. The timing controller 200 receives input image data IDAT and input control signals ICONT from an external device (e.g., a host device or a graphics processor). The input image data IDAT may include a plurality of pixel data for a plurality of pixels PX. The input control signals ICONT may include a master clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

[0054] The timing controller 200 is configured to generate output image data DAT based on input image data IDAT. For example, the timing controller 200 may selectively perform image quality compensation, spot compensation, adaptive color correction (ACC), and / or dynamic capacitance compensation (DCC) (e.g., perform one or more of these) on the input image data IDAT to generate output image data DAT.

[0055] The timing controller 200 is configured to generate, based on the input control signal ICONT, a first control signal for controlling the PMIC 500 and the gate driver 300, and a second control signal DCONT for controlling the data driver 400. For example, the first control signal may include a vertical start control signal STV, a gate clock control signal CPV, etc. The second control signal DCONT may include a horizontal start signal, a data clock signal, a polarity control signal, a data load signal, etc.

[0056] The PMIC 500 is configured to generate a first power supply voltage OV1 and a second power supply voltage OV2 based on an external power supply voltage VEXT. The first power supply voltage OV1 may be supplied or provided to the timing controller 200 and may be used to drive or operate the timing controller 200. The second power supply voltage OV2 may be supplied or provided to the data driver 400 and may be used to drive or operate the data driver 400.

[0057] The PMIC 500 is used to generate a vertical start pulse STVP and a gate clock signal CKV based on an external power supply voltage VEXT, a vertical start control signal STV, and a gate clock control signal CPV. The vertical start pulse STVP and the gate clock signal CKV may be supplied or provided to the gate driver 300 and may be used to drive or operate the gate driver 300. Figure 1 Although one gate clock control signal CPV and one gate clock signal CKV are shown, multiple gate clock signals may be generated based on multiple gate clock control signals according to exemplary embodiments. Furthermore, an inverted gate clock signal having a phase opposite to that of the gate clock signal CKV may be generated together (e.g., an inverted gate clock signal and the gate clock signal CKV may be generated together).

[0058] The gate driver 300 is coupled (e.g., connected) to the display panel 100 through a plurality of gate lines GL. The gate driver 300 is configured to generate a plurality of gate signals GS based on a vertical start pulse STVP and a gate clock signal CKV to drive the display panel 100. For example, the gate driver 300 may sequentially apply or provide the plurality of gate signals GS to the display panel 100 through the plurality of gate lines GL.

[0059] The data driver 400 is coupled (e.g., connected) to the display panel 100 through a plurality of data lines DL. The data driver 400 is configured to generate a plurality of data voltages DV (e.g., analog voltages) based on output image data DAT (e.g., digital data) and a second control signal DCONT to drive the display panel 100. For example, the data driver 400 may sequentially apply or provide the plurality of data voltages DV to a plurality of lines (e.g., horizontal lines) in the display panel 100 through the plurality of data lines DL.

[0060] In some exemplary embodiments, the gate driver 300 may be an amorphous silicon gate (ASG) unit integrated at (eg, on) a peripheral region of the display panel 100. In other exemplary embodiments, the gate driver 300 may be provided at any suitable region outside the display panel 100.

[0061] In some exemplary embodiments, the timing controller 200 and the PMIC 500 may be mounted on a printed circuit board (PCB), and the data driver 400 may be mounted on a flexible PCB (FPCB). For example, the FPCB may electrically couple (e.g., connect) the PCB to the display panel 100. For example, the PCB and the FPCB may be electrically coupled (e.g., connected) via an anisotropic conductive film (ACF), and the FPCB and the display panel 100 may be electrically coupled (e.g., connected) via the ACF.

[0062] In some exemplary embodiments, the data driver 400 may be provided (e.g., mounted or directly mounted) on the display panel 100, or may be coupled (e.g., connected) to the display panel 100 via a tape carrier package (TCP) (e.g., may be connected to the display panel 100 in a TCP type or manner). In some embodiments, the data driver 400 may be integrated on the display panel 100 (e.g., integrated with the display panel 100).

[0063] In the display device 10 according to the exemplary embodiment, the PMIC 500 can be implemented by applying sensing circuit technology. For example, the PMIC 500 can sense or detect various appropriate parameters, such as voltage, current, temperature, time, data patterns, etc., and can perform compensation or correction operations (e.g., operations to change or vary voltage levels), reinforcement operations (e.g., operations to update data), protection operations (e.g., operations to shut down the display device 10 and / or display panel 100), etc., based on the specific phenomena (e.g., abnormalities and / or defects) that have been sensed or detected. For example, the PMIC 500 can perform one or more operations in response to sensing the occurrence of one or more phenomena, and the one or more operations can depend on (e.g., correspond to) the type or category of the one or more phenomena.

[0064] As described above, when at least one selected from a plurality of defect phenomena has occurred, in order to shut down the display panel 100 by applying the sensing circuit technology, the PMIC 500 monitors whether the plurality of defect phenomena has occurred. When at least one selected from a plurality of defect phenomena has occurred, the PMIC 500 stores the fault data FD indicating that the sensed defect phenomenon has occurred (refer to FIG. Figure 3 ), and close the display panel 100. Figure 5 A more detailed configuration and operation of the PMIC 500 will be described.

[0065] In some exemplary embodiments, the plurality of defect phenomena are not errors (or failures) associated with (or related to) electrical / physical connections between components included in the display device 10, but are operation (or driving) errors that occur when the display panel 100 is driven. For example, the plurality of defect phenomena may include errors associated with the operation of a driving circuit (e.g., the timing controller 200, the gate driver 300, the data driver 400, and the PMIC 500) included in the display device 10.

[0066] In some exemplary embodiments, the PMIC 500 may turn off the display panel 100 by blocking (or cutting off) the first power supply voltage OV1 supplied to the timing controller 200. In other exemplary embodiments, the PMIC 500 may turn off the display panel 100 by blocking the gate clock signal CKV supplied to the gate driver 300. In still other exemplary embodiments, the PMIC 500 may turn off the display panel 100 by blocking the second power supply voltage OV2 supplied to the data driver 400. In some embodiments, the PMIC 500 may turn off the display panel 100 by blocking two or more of the first power supply voltage OV1, the second power supply voltage OV2, and the gate clock signal CKV substantially simultaneously or in parallel.

[0067] In the display device 10 according to the exemplary embodiment, when the display panel 100 is turned off by applying the sensing circuit technology in a case where at least one selected from a plurality of defect phenomena has occurred, a failure mode for recognizing (or identifying) that the defect phenomenon has occurred may be displayed on the display panel 100 before the display panel 100 is turned off. Figure 2 As shown in “normal display” in FIG, if no defect phenomenon occurs after the display device 10 is powered on (or after power is supplied to the display device 10), the display device 10 and the display panel 100 can operate normally and can display images normally. Figure 2 As shown in the “Fault Mode” in FIG. 1 , if a specific defect phenomenon has occurred while driving the display device 10 and / or the display panel 100, a fault mode corresponding to the specific defect phenomenon may be displayed during a predetermined or set time interval, thereby notifying that the specific defect phenomenon has occurred (for example, in order to provide a notification that the specific defect phenomenon has occurred). Figure 2 As shown by “off” in FIG. 1 , if a specific defect phenomenon has occurred, the display panel 100 may be turned off after a predetermined or set time interval has elapsed.

[0068] As described above, in order to display a failure mode when at least one selected from a plurality of defect phenomena has occurred and before the display panel 100 is turned off, the timing controller 200 stores a plurality of failure modes to be displayed on the display panel 100, and the plurality of failure modes are used to indicate that the plurality of defect phenomena have occurred when the display panel 100 is driven. In some embodiments, one of the plurality of failure modes may be used to indicate that a corresponding one of the plurality of defect phenomena has occurred. When a specific defect phenomenon has occurred and is sensed by the PMIC 500, the failure data FD (refer to the FD data) stored in the PMIC 500 and indicating that the specific defect phenomenon has occurred may be read (or retrieved). Figure 3 ), the fault pattern corresponding to the fault data FD can be read, and the fault image data FDAT corresponding to the read fault pattern can be generated (reference Figure 3 ), and the failure image data FDAT may be provided to the data driver 400 and the display panel 100. Figure 3 A more detailed configuration and operation of the timing controller 200 will be described.

[0069] Figure 3 is a block diagram illustrating an example of a timing controller included in a display device according to an exemplary embodiment. Figure 4 is used to describe Figure 3 Diagram of the operation of the timing controller.

[0070] refer to Figure 3 and Figure 4 The timing controller 200 may include a storage unit 210 , a fault mode display controller 220 , and an image processor 230 . The timing controller 200 may further include a control signal generator 240 .

[0071] The storage unit 210 may store a plurality of fault modes FP, which are used to indicate that a plurality of defect phenomena have occurred. For example, the storage unit 210 may include a buffer, a register, and / or a memory. For example, the memory may include one or more various suitable non-volatile memories (such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.) and / or one or more various suitable volatile memories (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.).

[0072] In some exemplary embodiments, the plurality of defect phenomena may include at least one selected from an overcurrent protection fault (or error), a zero current detection fault, a temperature fault, and a communication fault. For example, an overcurrent protection fault may be caused (or occur) due to an electrical short circuit in a line, a zero current detection fault may be caused when current leaks into a portion where current should not flow, a temperature fault may be caused when the temperature inside the display device 10 and / or the temperature of a specific chip exceeds a predetermined or set range, and a communication fault may be caused by an inter-integrated circuit (I2C) communication error between the timing controller 200 and another component (e.g., the PMIC 500).

[0073] In some exemplary embodiments, when the plurality of defect phenomena include an overcurrent protection fault, a zero current detection fault, a temperature fault, and a communication fault, as Figure 4 As shown in FIG, the plurality of fault modes FP may include a first fault mode FP1 for indicating that an overcurrent protection fault FOCP has occurred, a second fault mode FP2 for indicating that a zero current detection fault FZCD has occurred, a third fault mode FP3 for indicating that a temperature fault FTEMP has occurred, and a fourth fault mode FP4 for indicating that a communication fault FI2C has occurred. However, the present disclosure is not limited thereto, and the plurality of defect phenomena may also include various other defect phenomena that may occur when the display panel 100 is driven, and the number of the plurality of fault modes FP may vary. In some embodiments, the number of the plurality of fault modes may be equal to the number of the plurality of defect phenomena.

[0074] In some exemplary embodiments, the plurality of fault modes FP may be substantially the same as any display mode pre-stored to drive the display panel 100. In other exemplary embodiments, the plurality of fault modes FP may be dedicated modes that simply represent a plurality of defect phenomena. For example, the first fault mode FP1 corresponding to the overcurrent protection fault FOCP may be a mode for displaying (e.g., for displaying) a white screen, and the third fault mode FP3 corresponding to the temperature fault FTEMP may be a mode for displaying a blue screen. However, exemplary embodiments are not limited thereto.

[0075] When a specific defect phenomenon is sensed by the PMIC 500, the fault mode display controller 220 may read the fault data FD indicating that the specific defect phenomenon has occurred from the PMIC 500, and may read a specific fault mode corresponding to the specific defect phenomenon from the storage unit 210 based on the fault data FD. Figure 3 An example is shown in which the specific defect phenomenon is the overcurrent protection fault FOCP and the fault mode display controller 220 reads the first fault mode FP1 corresponding to the overcurrent protection fault FOCP from the storage part 210 , but the present disclosure is not limited thereto.

[0076] The image processor 230 may generate output image data DAT based on the input image data IDAT, and may generate fault image data FDAT based on a specific fault pattern (e.g., based on the first fault pattern FP1). The output image data DAT and the fault image data FDAT may be provided to the display panel 100 through the data driver 400. The display panel 100 may display a normal image based on the output image data DAT, as shown by Figure 2 or a specific fault mode may be displayed based on the fault image data FDAT, as shown by Figure 2 This is shown in the "Failure Mode" section.

[0077] In some example embodiments, the image processor 230 may selectively perform image quality compensation, speckle compensation, ACC, and / or DCC (eg, perform one or more thereof) on the input image data IDAT.

[0078] The control signal generator 240 may generate a vertical start control signal STV, a gate clock control signal CPV, and a second control signal DCONT based on the input control signal ICONT.

[0079] Figure 5 is a block diagram illustrating an example of a PMIC included in a display device according to an exemplary embodiment.

[0080] refer to Figure 5 , the PMIC 500 may include a power supplier 510 , a sensor 530 , and a storage unit 540 . The PMIC 500 may further include a clock supplier 520 .

[0081] The power supply 510 may generate a first power supply voltage OV1 and a second power supply voltage OV2 based on an external power supply voltage VEXT. For example, the power supply 510 may include a voltage regulator such as a switching regulator, a linear regulator, or the like.

[0082] The clock supplier 520 may generate a vertical start pulse STVP and a gate clock signal CKV based on an external power supply voltage VEXT, a vertical start control signal STV, and a gate clock control signal CPV. For example, the clock supplier 520 may include a start pulse generator and a level shifter.

[0083] The sensor 530 can monitor whether multiple defect phenomena have occurred. For example, the sensor 530 can receive the first power supply voltage OV1, the second power supply voltage OV2, the vertical start pulse STVP, and the gate clock signal CKV, and can sense whether a voltage anomaly and / or a current anomaly has occurred. Therefore, the sensor 530 may include a voltage measurer (or meter) and / or a current measurer. For another example, the sensor 530 can receive the temperature signal TEMP and can sense whether a temperature anomaly has occurred. Therefore, the sensor 530 may include a temperature sensor. In some embodiments, the sensor 530 may include a timer for measuring time or time intervals, a pattern detector for detecting a specific data pattern, etc.

[0084] The sensor 530 may generate a sensing signal SEN indicating a result of a monitoring operation and / or a sensing operation. For example, when none of the plurality of defect phenomena are sensed (e.g., when none of the plurality of defect phenomena are sensed), the sensing signal SEN may have a first logic level. When at least one selected from the plurality of defect phenomena is sensed, the sensing signal SEN may have a second logic level.

[0085] When at least one (e.g., a specific defect phenomenon) selected from a plurality of defect phenomena is sensed by the sensor 530, the storage unit 540 may store the fault data FD indicating that the specific defect phenomenon has occurred. The fault data FD stored in the storage unit 540 may be output based on (e.g., in response to) a request from the timing controller 200. For example, Figure 3 Like the storage unit 210 in FIG, the storage unit 540 may include a buffer, a register and / or a memory, and the memory may include one or more various appropriate non-volatile memories (such as, EEPROM, flash memory, PRAM, RRAM, NFGM, PoRAM, MRAM, FRAM, etc.) and / or one or more various appropriate volatile memories (such as, DRAM, SRAM, etc.).

[0086] Figure 6 is a block diagram illustrating an example of a timing controller and a PMIC included in a display device according to an exemplary embodiment.

[0087] refer to Figure 6 , the timing controller 200 a may include a first fault detection pin FPIN1 , and the PMIC 500 a may include a second fault detection pin FPIN2 .

[0088] The first fault detection pin FPIN1 and the second fault detection pin FPIN2 may be electrically coupled (e.g., connected) to each other. The first fault detection pin FPIN1 and the second fault detection pin FPIN2 may be pins newly added to the timing controller 200a and the PMIC 500a, and are not included in conventional timing controllers and conventional PMICs. For example, the pins may be contact pads or contact pins, but the present disclosure is not limited thereto.

[0089] The timing controller 200a and the PMIC 500a may be Figure 1 The timing controller 200 and the PMIC 500 in the embodiment of the present invention can be configured as follows: Figure 3 The structure of the timing controller 200 and Figure 5 The structure of the PMIC 500 is substantially the same as that of the PMIC 500. For example, the first fault detection pin FPIN1 may be coupled (eg, connected) to Figure 3 The fault mode display controller 220 in the embodiment of the present invention and the second fault detection pin FPIN2 can be coupled (eg, connected) to Figure 5 Sensor 530 in.

[0090] exist Figure 6 In the example of FIG. 5 , the timing controller 200 a may determine whether a specific defect phenomenon has occurred by using the first fault detection pin FPIN1 and the second fault detection pin FPIN2 .

[0091] For example, when a specific defect phenomenon is sensed by the sensor 530, the PMIC 500a may transition the voltage level of the second fault detection pin FPIN2 from a first level (e.g., a high level) to a second level (e.g., a low level), and the timing controller 200a may check whether the voltage level of the second fault detection pin FPIN2 transitions from the first level to the second level (e.g., a low level) through the first fault detection pin FPIN1. Figure 6 Operation in ①).

[0092] When the timing controller 200a detects that the voltage level of the second fault detection pin FPIN2 transitions from the first level to the second level, the timing controller 200a may read the fault data FD (eg, Figure 6 For example, the timing controller 200a may transmit (or transfer) a single read request RREQ to the PMIC 500a, and the PMIC 500a may transmit the fault data FD to the timing controller 200a in response to the read request RREQ. For example, the communication scheme between the timing controller 200a and the PMIC 500a may be I2C communication.

[0093] Figure 7 is a timing chart for describing the operation of the display device according to an exemplary embodiment.

[0094] exist Figure 7 , “F / S” represents a fault condition, “I / F” represents an interface (eg, I2C communication) between the timing controller and the PMIC, and “D / O” represents a display operation of the display panel 100 .

[0095] refer to Figure 7 , a specific defect phenomenon is sensed at the first time point t1. Therefore, the fault condition F / S may have a normal state OK before the first time point t1 and a fault state NG after the first time point t1. For example, Figure 5 The level of the sensing signal SEN and / or Figure 6 The voltage level of the second fault detection pin FPIN2 can be Figure 7 The fault condition F / S corresponds.

[0096] Immediately after the specific defect phenomenon is sensed (e.g., immediately after the first time point t1), the display panel 100 may not be immediately shut down. The timing controller 200 may read the fault data FD indicating that the specific defect phenomenon has occurred and stored in the PMIC 500 from the PMIC 500 during the first time interval T1 after the specific defect phenomenon is sensed (e.g., immediately after the specific defect phenomenon is sensed). Therefore, the display panel 100 may display an image normally even during the first time interval T1, as before the specific defect phenomenon is sensed (e.g., before the first time point t1).

[0097] The timing controller 200 may generate fault image data FDAT corresponding to the read fault data FD, and the display panel 100 may display a fault pattern corresponding to the specific defect phenomenon based on the fault image data FDAT during a second time interval T2 after the first time interval T1. The display panel 100 may be turned off after the second time interval T2. Therefore, there may be a delay corresponding to the sum of the first time interval T1 and the second time interval T2 between the time when the specific defect phenomenon is sensed (e.g., the first time point t1) and the time when the display panel 100 is turned off.

[0098] In some exemplary embodiments, the second time interval T2 may be substantially the same as the length (e.g., duration) of one frame period in which the display panel 100 displays one frame image, or the second time interval T2 may be an integer multiple of the length of one frame period. The first time interval T1 may be shorter than the second time interval T2.

[0099] Figure 8 is a block diagram showing another example of a timing controller and a PMIC included in a display device according to an exemplary embodiment. Figure 6 Redundant description in the corresponding description.

[0100] refer to Figure 8 ,and Figure 6 The example is different. Figure 8 Each of the timing controller 200b and the PMIC 500b in the embodiment may not include a fault detection pin. The timing controller 200b and the PMIC 500b may be respectively Figure 1 The timing controller 200 and the PMIC 500 in the embodiment of the present invention can be configured as follows: Figure 3 The structure of the timing controller 200 and Figure 5 The structure of the PMIC 500 is basically the same as the structure.

[0101] exist Figure 8 In the example of FIG. 5 , the timing controller 200 b may determine whether a specific defect phenomenon has occurred by periodically checking whether the PMIC 500 b stores the fault data FD.

[0102] For example, the timing controller 200b may repeatedly (eg, at each predetermined or set cycle) transmit the read request PRREQ to the PMIC 500b and thus may periodically check whether the PMIC 500b stores the fault data FD (eg, Figure 8 ① in the).

[0103] When the PMIC 500b senses a specific defect phenomenon and stores the failure data FD, the PMIC 500b may transmit the failure data FD to the timing controller 200b (eg, Figure 8 ②).

[0104] Figure 9 is a block diagram showing a display device according to an exemplary embodiment. Figure 1 Redundant description in the corresponding description.

[0105] refer to Figure 9 The display device 10a includes a display panel 100, a timing controller 200, a first PMIC (PMIC1) 502, and a second PMIC (PMIC2) 504. The display device 10a may further include a gate driver 300 and a data driver 400.

[0106] In addition to the display device 10a including two PMICs 502 and 504, Figure 9 The display device 10a can be used with Figure 1 The display device 10 is substantially the same as the PMIC 502 and 504. Figure 1 The PMIC 500 in FIG. 5 is divided into (or separated into) two components. For example, PMIC 502 and 504 may include a Figure 1 Shown in and about Figure 1 All of the components of the PMIC 500 described are substantially the same or similar components and together perform the same Figure 1 Shown in and about Figure 1 All of the functions of the described PMIC 500 are substantially the same or similar functions.

[0107] The first PMIC 502 is configured to generate a first power supply voltage OV1 and a second power supply voltage OV2 based on an external power supply voltage VEXT. The second PMIC 504 is configured to generate a vertical start pulse STVP and a gate clock signal CKV based on the external power supply voltage VEXT, a vertical start control signal STV, and a gate clock control signal CPV. For example, the first PMIC 502 may include Figure 5 The power supply 510 in the embodiment of the present invention and the second PMIC 504 may include Figure 5 The clock provider 520 in FIG.

[0108] In addition, the first PMIC 502 and the second PMIC 504 monitor whether a plurality of defect phenomena have occurred. When at least one selected from the plurality of defect phenomena has occurred, the first PMIC 502 and the second PMIC 504 (e.g., the first PMIC 502 and the second PMIC 504 together) store fault data FD indicating that the sensed defect phenomenon has occurred and shut down the display panel 100. For example, each of the first PMIC 502 and the second PMIC 504 may include Figure 5 at least a portion of the sensor 530 and may include Figure 5 In some exemplary embodiments, Figure 5 The sensor 530 and the storage unit 540 may be included in only one of the first PMIC 502 and the second PMIC 504. In some exemplary embodiments, the first PMIC 502 and the second PMIC 504 are commonly included in Figure 5 Shown in and about Figure 5 The sensor 530 and the storage unit 540 are described.

[0109] Figure 10 is a block diagram showing another example of a timing controller and a PMIC included in a display device according to an exemplary embodiment. Figure 6Redundant description in the corresponding description.

[0110] refer to Figure 10 , the timing controller 200a may include a first fault detection pin FPIN1, the first PMIC 502a may include a second fault detection pin FPIN2, and the second PMIC 504a may include a third fault detection pin FPIN3. The first fault detection pin FPIN1, the second fault detection pin FPIN2, and the third fault detection pin FPIN3 may be electrically coupled (e.g., connected) to each other.

[0111] The timing controller 200a may be Figure 9 The timing controller 200 in the Figure 3 The structure of the timing controller 200 is substantially the same as the structure. The first PMIC 502a and the second PMIC 504a can be respectively Figure 9 The first PMIC 502 and the second PMIC 504 in the embodiment of the present invention may have (eg, may have in common) Figure 5 The structure of the PMIC 500 is substantially the same as that of the PMIC 500. For example, each of the second fault detection pin FPIN2 and the third fault detection pin FPIN3 may be coupled (eg, connected) to Figure 5 At least a portion of the sensor 530 in.

[0112] exist Figure 10 In the example of FIG. 5 , the timing controller 200 a may determine whether a specific defect phenomenon has occurred by using the first fault detection pin FPIN1 , the second fault detection pin FPIN2 , and the third fault detection pin FPIN3 .

[0113] For example, when a specific defect phenomenon is sensed by the sensor 530, one of the first PMIC 502a and the second PMIC 504a may transition the voltage level of one of the second fault detection pin FPIN2 and the third fault detection pin FPIN3 from the first level to the second level (e.g., the first PMIC 502a and the second PMIC 504a may transition the voltage level of the second fault detection pin FPIN2 and the third fault detection pin FPIN3 from the first level to the second level, respectively). When the voltage level of one of the second fault detection pin FPIN2 and the third fault detection pin FPIN3 is transitioned, the voltage levels of both the second fault detection pin FPIN2 and the third fault detection pin FPIN3 may be transitioned because the second fault detection pin FPIN2 and the third fault detection pin FPIN3 are electrically coupled (e.g., connected) to each other. The timing controller 200a may check whether the voltage levels of the second fault detection pin FPIN2 and the third fault detection pin FPIN3 are transitioned from the first level to the second level (e.g., the second fault detection pin FPIN2 and the third fault detection pin FPIN3 are electrically coupled (e.g., connected) to each other through the first fault detection pin FPIN1. Figure 10 ① in the).

[0114] When the timing controller 200 a detects that the voltage levels of the second fault detection pin FPIN2 and the third fault detection pin FPIN3 transition from the first level to the second level, the timing controller 200 a may read the fault data FD (e.g., Figure 10 ②).

[0115] exist Figure 10 In the example of FIG, the second fault detection pin FPIN2 and the third fault detection pin FPIN3 can be electrically coupled to each other (e.g., connected) to synchronize the operation of shutting down the display panel 100. As described above, the first PMIC 502a and the second PMIC 504a can perform different functions. For example, the first PMIC 502a can generate the supply voltages OV1 and OV2, and the second PMIC 504a can generate the gate clock signal CKV. Therefore, the second fault detection pin FPIN2 and the third fault detection pin FPIN3 can be electrically coupled to each other (e.g., connected) so that the supply voltages OV1 and OV2 and the gate clock signal CKV provided from the PMICs 502a and 504a are blocked substantially simultaneously or in parallel, thereby synchronizing the operation of shutting down the display panel 100.

[0116] Figure 11 is a flowchart illustrating a method of operating a display apparatus according to an exemplary embodiment.

[0117] refer to Figure 1 and Figure 11 In the method of operating a display device according to an exemplary embodiment, the display device 10 is powered on or supplied with power (task S100). For example, the PMIC 500 may generate and supply a first power supply voltage OV1, a second power supply voltage OV2, and a gate clock signal CKV, and thus may power on the display panel 100, the timing controller 200, the gate driver 300, and the data driver 400.

[0118] The PMIC 500 is used to monitor whether multiple defect phenomena have occurred (task S200). As described above, in some embodiments, the multiple defect phenomena are not errors or failures associated with the electrical / physical connections between components included in the display device 10, but rather operational errors or driving errors that may occur when the display panel 100 is driven. For example, the multiple defect phenomena may include errors associated with the operation of the driving circuit included in the display device 10. However, the present disclosure is not limited thereto, and the multiple defect phenomena may include other types or kinds of errors or failures.

[0119] When a specific defect phenomenon among multiple defect phenomena is sensed (task S300: yes), the specific defect mode among the multiple fault modes is displayed on the display panel 100 (task S400). For example, after the specific defect phenomenon among the multiple defect phenomena is sensed (e.g., in response to sensing the specific defect phenomenon among the multiple defect phenomena), the specific fault mode among the multiple fault modes can be displayed on the display panel 100. In some embodiments, if none of the multiple defect phenomena is sensed, the PMIC 500 continues to monitor whether the multiple defect phenomena have occurred (task S200). The multiple fault modes are stored in the timing controller 200 and are used to indicate that the multiple defect phenomena have occurred when the display panel 100 is driven. In some embodiments, the multiple fault modes can be stored in the timing controller 200 in advance (e.g., during the manufacturing process). However, the present disclosure is not limited to this, and the multiple fault modes can be stored in the timing controller 200 at any appropriate time. The specific fault mode corresponds to the specific defect phenomenon. After the specific failure mode is displayed on the display panel 100 , the display panel 100 is turned off (task S500 ).

[0120] Figure 12 and Figure 13 is a flowchart illustrating an example of displaying a failure mode in a method of operating a display device according to an exemplary embodiment.

[0121] refer to Figure 1 、 Figure 6 、 Figure 11 and Figure 12, the timing controller 200a may include a first fault detection pin FPIN1, the PMIC 500a may include a second fault detection pin FPIN2, and when a specific fault mode is displayed on the display panel 100 (task S400), the timing controller 200a may determine whether a specific defect phenomenon has occurred by utilizing the first fault detection pin FPIN1 and the second fault detection pin FPIN2.

[0122] For example, when a first defect phenomenon is sensed, fault data FD indicating that a specific defect phenomenon has occurred may be stored in the PMIC 500a (task S610), and the voltage level of the second fault detection pin FPIN2 of the PMIC 500a may be transitioned from a first level to a second level (task S620).

[0123] Furthermore, the timing controller 200a can check whether the voltage level of the second fault detection pin FPIN2 transitions from the first level to the second level (e.g., whether the voltage level of the second fault detection pin FPIN2 is at the second level) via the first fault detection pin FPIN1, and can read fault data FD from the PMIC 500a when the voltage level of the second fault detection pin FPIN2 transitions from the first level to the second level (in response to determining that the voltage level of the second fault detection pin FPIN2 transitions from the first level to the second level) (task S630). The timing controller 200a can read a specific fault mode corresponding to a specific defect phenomenon based on the read fault data FD (task S640), generate fault image data FDAC corresponding to the specific fault mode, and provide the fault image data FDAC corresponding to the specific fault mode to the data driver 400 and the display panel 100 (task S650). In some embodiments, the timing controller 200a can provide the fault image data FDAC to the data driver 400 and the display panel 100 by generating the fault image data FDAC corresponding to the specific fault mode.

[0124] When the PMIC is as reference Figure 9 and Figure 10 When divided into two PMICs as described, the operation showing a specific failure mode can be similar to that of the reference Figure 12 Described operations to perform.

[0125] refer to Figure 1 、 Figure 8 、 Figure 11 and Figure 13In some embodiments, each of the timing controller 200 b and the PMIC 500 b does not include a fault detection pin, and when a specific fault mode is displayed on the display panel 100 (task S400 ), the timing controller 200 b can determine whether a specific defect phenomenon has occurred by periodically checking whether the PMIC 500 b stores fault data FD.

[0126] For example, when a first defect phenomenon is sensed, fault data FD indicating that a specific defect phenomenon has occurred may be stored in the PMIC 500b (task S710). Task S710 may be associated with Figure 12 Task S610 in is basically the same.

[0127] When the PMIC 500b senses a specific defect phenomenon and stores the failure data FD, the timing controller 200b may read the failure data FD from the PMIC 500b through (or during) a periodic check operation on the PMIC 500b (task S720 ).

[0128] The timing controller 200b may read a specific failure mode corresponding to a specific defect phenomenon based on the read failure data FD (task S730), may generate failure image data FDAT corresponding to the specific failure mode, and may provide the failure image data FDAT corresponding to the specific failure mode to the data driver 400 and the display panel 100 (task S740). Tasks S730 and S740 may be respectively Figure 12 Tasks S640 and S650 in are substantially the same.

[0129] The present disclosure may be applied to various suitable devices and / or systems including display devices. For example, the present disclosure may be applied to systems such as personal computers (PCs), workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0130] The devices, controllers, circuits and / or any other related devices or components according to the embodiments of the present invention described herein can be implemented using any appropriate hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that, without departing from the scope of the exemplary embodiments of the present invention, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed to one or more other computing devices.

[0131] The above are examples of exemplary embodiments, and the present disclosure should not be construed as being limited thereto. Although some exemplary embodiments have been described, it will be readily understood by those of ordinary skill in the art that many appropriate modifications may be made in the exemplary embodiments without departing substantially from the spirit and scope of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims and their equivalents. Therefore, it should be understood that the above is an illustration of various exemplary embodiments, and the present disclosure should not be construed as being limited to the disclosed exemplary embodiments, and appropriate modifications to the disclosed exemplary embodiments as well as other exemplary embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A display device comprising: a display panel comprising a plurality of pixels; a timing controller configured to control the operation of the display panel and store a plurality of failure modes to be displayed on the display panel, the plurality of failure modes being used to indicate that a plurality of defect phenomena have occurred when the display panel is driven; as well as a power management integrated circuit configured to provide a first supply voltage to the timing controller and monitor whether the plurality of defect phenomena have occurred; wherein, when a first defect phenomenon among the plurality of defect phenomena is sensed, the power management integrated circuit is configured to store first fault data indicating that the first defect phenomenon has occurred and to shut down the display panel after a predetermined time interval has elapsed since the first defect phenomenon was sensed, and When the first defect phenomenon is sensed, the timing controller is configured to control the display panel to display a first failure mode corresponding to the first defect phenomenon among the multiple failure modes before the display panel is turned off by the power management integrated circuit.

2. The display device according to claim 1, wherein The timing controller includes: a storage unit configured to store the plurality of failure modes; a failure mode display controller configured to, when the first defect phenomenon is sensed, read the first failure data indicating that the first defect phenomenon has occurred from the power management integrated circuit, and read the first failure mode corresponding to the first defect phenomenon from the storage section based on the first failure data; and An image processor is configured to generate fault image data corresponding to the first fault mode.

3. The display device according to claim 2, wherein: The power management integrated circuit comprises: a power supply configured to generate the first supply voltage based on an external supply voltage; a sensor configured to monitor whether the plurality of defect phenomena have occurred; and The storage unit is configured to store the first fault data when the first defect phenomenon is sensed.

4. The display device according to claim 1, wherein: The timing controller includes a first fault detection pin, The power management integrated circuit includes a second fault detection pin, and The timing controller is configured to determine whether the first defect phenomenon has occurred by using the first fault detection pin and the second fault detection pin.

5. The display device according to claim 4, wherein: When the first defect phenomenon is sensed, the power management integrated circuit is configured to transition the voltage level of the second fault detection pin from a first level to a second level, and The timing controller is configured to check whether the voltage level of the second fault detection pin is at the second level through the first fault detection pin, and read the first fault data from the power management integrated circuit when the voltage level of the second fault detection pin is at the second level.

6. The display device according to claim 4, further comprising: The second power management integrated circuit includes a third fault detection pin and is configured to generate a gate clock signal, wherein the second fault detection pin and the third fault detection pin are electrically coupled to each other so as to synchronize the operation of shutting down the display panel.

7. The display device according to claim 1, wherein The timing controller is configured to determine whether the first defect phenomenon has occurred by periodically checking whether the power management integrated circuit stores the first fault data.

8. The display device according to claim 7, wherein: The timing controller is configured to read the first fault data from the power management integrated circuit when the power management integrated circuit senses the first defect phenomenon and store the first fault data.

9. The display device according to claim 1, wherein: The display panel is configured not to be turned off immediately after sensing the first defect phenomenon, The timing controller is configured to read the first fault data from the power management integrated circuit during a first time interval immediately after the first defect phenomenon is sensed, and The display panel is configured to display the first fault mode during a second time interval following the first time interval and to be turned off after the second time interval.

10. The display device according to claim 1, wherein The power management integrated circuit is configured to turn off the display panel by blocking the first power supply voltage to be supplied to the timing controller.

11. The display device according to claim 1, wherein: Also includes: a gate driver coupled to a plurality of gate lines of the display panel and configured to generate a plurality of gate signals based on a gate clock signal and apply the plurality of gate signals to the plurality of gate lines, The power management integrated circuit is configured to supply the gate clock signal to the gate driver.

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