Display device

Abstract

A display device includes gate lines extending in a first direction and data lines extending in a second direction intersecting the first direction; a first switching element including a first source electrode connected to a data line, a first drain electrode, and a first gate electrode connected to a gate line; and a second switching element including a second source electrode connected to a data line, a second drain electrode, and a second gate electrode connected to a gate line. An area of the first drain electrode overlapping the first gate electrode extends in the second direction, the second source electrode extends in the second direction and is parallel to the first drain electrode and the second drain electrode. An area of the second drain electrode overlapping the second gate electrode includes a first area extending in the first direction and a second area extending in the second direction.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments of the present invention relate to a display device, and more particularly, to a display device capable of reducing a range of a difference in kickback voltage between sub-pixels in a pixel. BACKGROUND

[0002] With the gradual development of multimedia technology, display devices are becoming increasingly important. Accordingly, various types of display devices, such as liquid crystal display (LCD) devices and organic light emitting display (OLED) devices, are currently used.

[0003] Among them, the LCD device is one of the most commonly used flat panel display devices. The LCD device includes two substrates at which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer disposed between the two substrates. The LCD device displays an image in such a manner that a voltage is applied to the field generating electrodes to generate an electric field across the liquid crystal layer, and liquid crystal molecules in the liquid crystal layer are aligned by the electric field to control polarization of incident light.

[0004] The LCD device can be an active matrix LCD device using a thin film transistor. Specifically, the thin film transistor is connected to the pixel electrode, and the pixel is driven by a voltage held by a capacitor of the thin film transistor.

[0005] The above information disclosed in this Background section is only for the purpose of understanding the background of the inventive concepts, and as such it may contain information that does not constitute prior art. SUMMARY

[0006] One or more exemplary embodiments of the inventive concepts can reduce a range of a difference in kickback voltage between sub-pixels in a pixel.

[0007] In one or more exemplary embodiments of the inventive concepts, a display device includes a display device capable of improving an aperture ratio of a pixel.

[0008] According to one or more exemplary embodiments of the present invention, it is possible to prevent an increase in a difference between a capacitance of a first gate leakage capacitor and a capacitance of a second gate leakage capacitor, thereby reducing a range of a difference in kickback voltage between a first sub-pixel area and a second sub-pixel area. As a result, it is possible to suppress a non-uniformity defect due to a difference in brightness on the display device.

[0009] According to one or more exemplary embodiments of the present invention, forming a plurality of contact holes overlapping with a through-hole of a color filter allows improving an aperture ratio of a pixel.

[0010] In addition, according to one or more exemplary embodiments of the present invention, the second switching element is spaced apart from the third switching element, and it is possible to more freely design a pixel.

[0011] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or can be learned by practice of the inventive concept.

[0012] According to one or more exemplary embodiments, a display device includes gate lines extending in a first direction on a substrate and data lines extending in a second direction crossing the first direction. The display device further includes a first switching element including a first source electrode connected to the data line, a first drain electrode spaced apart from the first source electrode, and a first gate electrode connected to the gate line, and a second switching element including a second source electrode connected to the data line, a second drain electrode spaced apart from the second source electrode, and a second gate electrode connected to the gate line, wherein an area of the first drain electrode overlapping the first gate electrode extends in the second direction. The second source electrode extends in the second direction and is disposed in parallel with the first drain electrode and the second drain electrode, and an area of the second drain electrode overlapping the second gate electrode includes a first area extending in the first direction and a second area extending in the second direction.

[0013] According to one or more exemplary embodiments, the second area of the second drain electrode and the second source electrode can face each other and can be arranged in parallel.

[0014] According to one or more exemplary embodiments, the second area of the second drain electrode can completely overlap the gate line, and a portion of the first area of the second drain electrode can not overlap the gate line.

[0015] According to one or more exemplary embodiments, the first switching element includes a first semiconductor region in which a first channel region is formed between the first source electrode and the first drain electrode, and the second switching element includes a second semiconductor region in which a second channel region is formed between the second area of the second drain electrode and the second source electrode.

[0016] According to one or more exemplary embodiments, a length direction of each of the first channel region and the second channel region can be parallel to the first direction.

[0017] According to one or more exemplary embodiments, a length of the first channel region can be a shortest distance between the first source electrode and the first drain electrode, and wherein a length of the second channel region can be a shortest distance between the second source electrode and the second drain electrode.

[0018] According to one or more exemplary embodiments, the first source electrode and the second source electrode can be directly disposed on the same layer and formed of the same material.

[0019] According to one or more example embodiments, the display device can further include a storage line disposed in parallel with the gate line, and a third switching element including a third source electrode connected to the storage line, a third drain electrode spaced apart from the third source electrode, and a third gate electrode connected to the gate line.

[0020] According to one or more example embodiments, the third drain electrode can be connected to the second drain electrode, and wherein the second region of the second drain electrode and the third source electrode can face each other and be arranged in parallel.

[0021] According to one or more example embodiments, the third switching element includes a third semiconductor region in which a third channel region can be formed between the second region of the second drain electrode and the third source electrode.

[0022] According to one or more example embodiments, a length direction of the third channel region can be parallel to the first direction.

[0023] According to one or more example embodiments, the display device can further include a color filter disposed on the first to third source electrodes and the first to third drain electrodes, and an insulating layer disposed on the color filter, wherein the color filter includes a first via hole exposing the first drain electrode and a second via hole exposing the third source electrode and the second drain electrode, and wherein the insulating layer includes a first contact hole exposing the first drain electrode, a second contact hole exposing the third source electrode, and a third contact hole exposing the second drain electrode.

[0024] According to one or more example embodiments, the first contact hole can overlap the first via hole, and the second contact hole and the third contact hole can overlap the second via hole.

[0025] According to one or more example embodiments, the first drain electrode can be connected to an adjacent first sub-pixel electrode through the first contact hole, the third source electrode can be connected to the storage line through the second contact hole, and the second drain electrode can be connected to an adjacent second sub-pixel electrode through the third contact hole.

[0026] The display device can further include a first conductive pattern extending from the third source electrode and overlapping the second contact hole and the second via hole, and a second conductive pattern extending from the second drain electrode and overlapping the third contact hole and the second via hole, wherein the first conductive pattern and the second conductive pattern are spaced apart from each other, the gate line is between the first conductive pattern and the second conductive pattern, and the first conductive pattern and the second conductive pattern do not overlap the gate line.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the specification, serve to illustrate the inventive concept.

[0029] Figure 1 This is a plan view of a display device according to an embodiment of the present invention.

[0030] Figure 2 This is a plan view illustrating the pixels of a display device according to an embodiment of the concept of the present invention.

[0031] Figure 3 This is a circuit diagram of the pixels of a display device according to an embodiment of the present invention.

[0032] Figure 4 yes Figure 3 A magnified planar view of the entire first color pixel.

[0033] Figure 5 yes Figure 3 A magnified planar view of a portion of the first color pixel.

[0034] Figure 6 It is along Figure 4 The cross-sectional view taken from line I-I'.

[0035] Figure 7 It is along Figure 4 The cross-sectional view taken from line II-II'.

[0036] Figure 8 , Figure 9 and Figure 10 This is a plan view illustrating a portion of the configuration of the switching element region of a first color pixel according to an embodiment of the present invention.

[0037] Figure 11 This is a plan view illustrating a second drain electrode according to an embodiment of the present invention.

[0038] Figure 12 This is a plan view illustrating a portion of the switching element region of a first color pixel according to an exemplary embodiment of the present invention.

[0039] Figure 13 It is along Figure 4 The cross-sectional view taken from line III-III'.

[0040] Figure 14 This is a plan view illustrating a pixel of a display device according to another embodiment of the concept of the present invention.

[0041] Figure 15is a plan view showing a gate line, a source electrode, and a drain electrode of one pixel according to another embodiment of the present inventive concept.

[0042] Figure 16 is a plan view showing a second drain electrode and a third drain electrode according to another embodiment of the present inventive concept.

[0043] Figure 17 is a cross-sectional view taken along line IV-IV' of Figure 14 . DETAILED DESCRIPTION

[0044] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments. It will be apparent, however, that various exemplary embodiments can be practiced without limitation to these specific details, or in conjunction with one or more equivalent arrangements. In the following description, for purposes of explanation, and not limitation, specific details are set forth in order to provide a thorough understanding of various exemplary embodiments. It will be apparent to one skilled in the art that various exemplary embodiments can be practiced in

[0045] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. For purposes of this disclosure, “at least one of X, Y, and Z” and “at least one of the group consisting of X, Y, and Z” can be interpreted to include only X, only Y, only Z, or any combination of at least two of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. Like numbers refer to like elements throughout. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms “first,” “second,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0047] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for descriptive purposes, and, thereby, to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including", "includes", "containing", "contains", or "containing", "contains" or variants thereof are used in either the detailed description and / or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as an open transition term without precluding any additional or other elements.

[0049] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are idealized illustrations and / or intermediate structures of exemplary embodiments. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, exemplary embodiments disclosed herein should not be construed as limited to the particular shapes of regions as illustrated and described, but are to include deviations in shapes that result from, for example, manufacturing. As such, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and, as a result, are not intended to limit the exemplary embodiments.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0053] InFigure 1 Hereinafter, a liquid crystal display device is described as an example of the display device 1 according to the exemplary embodiments of the disclosure, and the liquid crystal display device is simply referred to as a display device unless discrimination between the liquid crystal display device and the display device is required. However, it should be understood that the exemplary embodiments of the disclosure are not limited to the liquid crystal display device, and any other display device listed above or well known in the art can be employed without departing from the scope of the disclosure.

[0054] The display device 1 can include a display area DPA and a non-display area NDA. The display area DPA can be an effective area in which an image is displayed. The display area DPA can have, but is not limited to, a rectangular shape similar to the overall shape of the display device 1 when viewed from the top.

[0055] The display area DPA can include a plurality of pixels PX. The plurality of pixels PX can be arranged in a matrix when viewed from the top. The shape of each of the pixels PX can be, but is not limited to, a rectangle or a square when viewed from the top. Each of the pixels PX can have a rhombus shape having sides inclined with respect to the edges of the display device 1. The plurality of pixels PX can include pixels PX of different colors. For example, the plurality of pixels PX can include, but are not limited to, first color pixels PX of red, second color pixels PX of green, and third color pixels PX of blue. Stripe-type pixels and pentile-type pixels can be alternately arranged.

[0056] The non-display area NDA can be disposed around the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. The display area DPA can have a rectangular shape, and the non-display area NDA can be disposed adjacent to the four edges of the display area DPA. The non-display area NDA can form a bezel of the display device 1.

[0057] In the non-display area NDA, a driving circuit or a driving element for driving the display area DPA can be disposed. According to the exemplary embodiments of the disclosure, a pad area is disposed in a first non-display area NDA disposed adjacent to a first long side (a lower side in Figure 1 a second non-display area NDA disposed adjacent to a second long side (an upper side in Figure 1 of the display device 1. An external device EXD can be mounted on a pad electrode of the pad area. Examples of the external device EXD can include a connection film, a printed circuit board, a driving chip DIC, a connector, a wire connection film, etc. A scan driver SDR directly formed on the display substrate of the display device 1 can be disposed in a third non-display area NDA adjacent to a first short side (a left side in Figure 1 of the display device 1.

[0058] Figure 2 is a plan view showing a pixel of a display device according to an exemplary embodiment of the present disclosure.

[0059] In Figure 2 each of the pixels PX can include a plurality of color pixels SPX1, SPX2, and SPX3. According to exemplary embodiments of the present disclosure, the first color pixel SPX1 can be a red pixel, the second color pixel SPX2 can be a green pixel, and the third color pixel SPX3 can be a blue pixel. The data lines DL, the gate lines SL, and the storage lines CSTL1 and CSTL2 can pass through each of the color pixels SPX1, SPX2, and SPX3. The data lines DL can extend in the second direction DR2, and the gate lines SL can extend in the first direction DR1.

[0060] The first storage line CSTL1 can include a main storage line portion CSTL1_1 extending along the first direction DR1 and an auxiliary storage line portion CSTL1_2 connected to the main storage line portion CSTL1_1 and extending along the second direction DR2. There can be two auxiliary storage line portions CSTL1_2. One of the auxiliary storage line portions CSTL1_2 can be disposed between the data line DL connected to each of the color pixels SPX1, SPX2, and SPX3 and a sub-pixel electrode of each of the color pixels SPX1, SPX2, and SPX3, which will be described later. The other of the auxiliary storage line portions CSTL1_2 can be disposed between the sub-pixel electrode of each of the color pixels SPX1, SPX2, and SPX3 and the data line DL connected to an adjacent color pixel SPX1, SPX2, and SPX3. The second storage line CSTL2 can extend along the first direction DR1. The second storage line CSTL2 and the gate line SL can extend in the same direction.

[0061] Different data lines DL can pass through the color pixels SPX1, SPX2, and SPX3 of one pixel PX, respectively. The data lines DL passing through the color pixels SPX1, SPX2, and SPX3 can pass through the color pixels adjacent thereto in the second direction DR2, respectively.

[0062] The same gate line SL and the first storage line CSTL1 can commonly pass through each of the color pixels SPX1, SPX2, and SPX3 of one pixel PX. The second storage line CSTL2 can commonly pass through the color pixels SPX1, SPX2, and SPX3.

[0063] Each of the color pixels SPX1, SPX2, and SPX3 can be defined as a region between the data lines DL adjacent to each other in the first direction DR1. Also, in the second direction DR2, each of the color pixels SPX1, SPX2, and SPX3 is defined as a region from the first sub-pixel electrode 191 disposed on the upper side and the lower side of the gate line SL passing through it, respectively, to the second sub-pixel electrode 192.

[0064] Each of the color pixels SPX1, SPX2, and SPX3 can be divided into several regions. Sub-pixel regions FSPX1 and FSPX2 and a switching element region TA can be defined in each of the color pixels SPX1, SPX2, and SPX3. The first sub-pixel region FSPX1 can be defined as a region in which the first sub-pixel electrode 191 is disposed, and the second sub-pixel region FSPX2 can be defined as a region in which the second sub-pixel electrode 192 is disposed in the second direction DR2. Specifically, the first sub-pixel region FSPX1, the switching element region TA, and the second sub-pixel region FSPX2 can be adjacent to each other and can be arranged in this order in the second direction DR2. According to an exemplary embodiment of the present disclosure, the size of the second sub-pixel region FSPX2 can be greater than the size of the first sub-pixel region FSPX1 when viewed from the top. That is, as shown in FIG. 17, when the width of the first sub-pixel region FSPX1 is equal to the width of the second sub-pixel region FSPX2 in the first direction DR1, in the second direction DR2, the width of the second sub-pixel region FSPX2 can be greater than the width of the first sub-pixel region FSPX1. Figure 2

[0065] ​The first sub-pixel electrode 191 can be provided in the first sub-pixel region FSPX1 of each of the color pixels SPX1, SPX2, and SPX3, and the second sub-pixel electrode 192 can be provided in the second sub-pixel region FSPX2 of each of the color pixels SPX1, SPX2, and SPX3. The first storage line CSTL1 can be provided between the first sub-pixel electrode 191 and the second sub-pixel electrode 192, and the gate line SL can be provided between the first storage line CSTL1 and the second sub-pixel electrode 192. The second storage line CSTL2 can be provided between the second sub-pixel electrode 192 and the gate line SL. A main storage line portion CSTL1_1 of the first storage line CSTL1 can be provided between the first sub-pixel electrode 191 of each of the color pixels SPX1, SPX2, and SPX3 and the second sub-pixel electrode 192 in the second sub-pixel region FSPX2 of the color pixels SPX1, SPX2, and SPX3 adjacent to the first sub-pixel electrode 191 in the second direction DR2. An auxiliary storage line portion CSTL1_2 of the first storage line CSTL1 of each of the color pixels SPX1, SPX2, and SPX3 can be provided between the data line DL of each of the color pixels SPX1, SPX2, and SPX3 and the first sub-pixel electrode 191 in the first sub-pixel region FSPX1 of each of the color pixels SPX1, SPX2, and SPX3 and between the first sub-pixel electrode 191 in the first sub-pixel region FSPX1 of each of the color pixels SPX1, SPX2, and SPX3 and the data line DL of the color pixels SPX1, SPX2, and SPX3 adjacent to the first sub-pixel electrode 191 in the first direction DR1.

[0066] The voltage division reference line RL extending in the second direction DR2 can further pass through the third color pixel SPX3. As described below, the voltage division reference line RL can be electrically connected to the first storage line CSTL1, thereby transmitting a voltage applied through the voltage division reference line RL to the first storage line CSTL1. The first storage line CSTL1 is commonly connected to each of the color pixels SPX1, SPX2, and SPX3 of the pixel PX, and thus can apply the same storage voltage to each of the color pixels SPX1, SPX2, and SPX3 of the pixel PX.

[0067] A size of the third color pixel SPX3 can be greater than a size of each of the first color pixel SPX1 and the second color pixel SPX2 when viewed from the top. A width W3 of the third color pixel SPX3 in the first direction DR1 can be greater than widths W1 and W2 of the first color pixel SPX1 and the second color pixel SPX2, respectively, in the first direction DR1 when viewed from the top. This is to compensate for light loss in the first sub-pixel area FSPX1 and the second sub-pixel area FSPX2 of the third color pixel SPX3 due to the voltage division reference line RL passing through the third color pixel SPX3.

[0068] Figure 3 is a circuit diagram of a pixel of a display apparatus according to an exemplary embodiment of the disclosure.

[0069] In Figure 2 and Figure 3 A data line DL and a voltage division reference line RL crossing the gate line SL can be provided. The gate line SL can transmit a scan signal to each of the first, second, and third switching elements T1, T2, and T3. The data line DL can transmit a data voltage to each of the first and second switching elements T1 and T2. A constant reference voltage (or a voltage division reference voltage) can be applied to the voltage division reference line RL.

[0070] The first sub-pixel area FSPX1 can include a first liquid crystal capacitor Clc1, and the second sub-pixel area FSPX2 can include a second liquid crystal capacitor Clc2. The switching element area TA can include the first, second, and third switching elements T1, T2, and T3. Each of the first, second, and third switching elements T1, T2, and T3 can be a thin film transistor.

[0071] The first switching element T1 can include a first electrode connected to the data line DL, a second electrode connected to the first liquid crystal capacitor Clc1, and a gate electrode connected to the gate line SL. The second electrode of the first switching element T1 can be connected to the first sub-pixel electrode 191 of the first liquid crystal capacitor Clc1.

[0072] The second switching element T2 can include a first electrode connected to the data line DL, a second electrode connected to the second liquid crystal capacitor Clc2, and a gate electrode connected to the gate line SL. The second electrode of the second switching element T2 can be connected to the second sub-pixel electrode 192 of the second liquid crystal capacitor Clc2.

[0073] The third switching element T3 can include a first electrode connected to the voltage division reference line RL, a second electrode connected to the second liquid crystal capacitor Clc2, and a gate electrode connected to the gate line SL. A reference voltage for voltage division can be applied to the first electrode of the third switching element T3 through the voltage division reference line RL.

[0074] The first electrode of each of the first, second, and third switching elements T1, T2, and T3 can be a source electrode, and the second electrode of each of the first, second, and third switching elements T1, T2, and T3 can be a drain electrode. The first and second liquid crystal capacitors Clc1 and Clc2 can be connected to a common electrode, and a common voltage can be applied to the common electrode.

[0075] When a gate-on voltage is applied to the gate line SL, each of the first, second, and third switching elements T1, T2, and T3 can be turned on, and the first and second liquid crystal capacitors Clc1 and Clc2 can be charged by a data voltage transmitted through the data line DL. The data voltage applied to the first sub-pixel electrode 191 can be equal to the data voltage applied to the second sub-pixel electrode 192. The first liquid crystal capacitor Clc1 can be charged with a voltage equal to a difference between the common voltage and the data voltage, and the second liquid crystal capacitor Clc2 can be charged with a voltage equal to a difference between the data voltage divided by the third switching element T3 and the common voltage.

[0076] Since the third switching element T3 is connected in series with the second switching element T2 and the third switching element T3 is turned on, the data voltage transmitted to the second sub-pixel region FSPX2 can be divided by the second and third switching elements T2 and T3. The data voltage can be distributed based on the size (or capacity) of the channel of the second switching element T2 and the size of the channel of the third switching element T3. Accordingly, even if the data voltage transmitted to the first and second sub-pixel regions FSPX1 and FSPX2 through the data line DL is the same, the voltage charged on the first liquid crystal capacitor Clc1 can be different from the voltage charged on the second liquid crystal capacitor Clc2. For example, the voltage charged in the second liquid crystal capacitor Clc2 can be less than the voltage charged in the first liquid crystal capacitor Clc1. This can improve the quality of the image on the side of the display device 1.

[0077] The voltage level of the reference voltage applied to the first electrode of the third switching element T3 can be equal to or higher than the voltage level of the common voltage applied to the common electrode. For example, when the common voltage is about 7 V, the reference voltage applied to the first electrode of the third switching element T3 can be, but is not limited to, about 7 V to 11 V.

[0078] The first gate-drain capacitor Cgs1 can be formed between the second electrode of the first switching element T1 and the gate electrode of the first switching element T1. The second gate-drain capacitor Cgs2 can be formed between the second electrode of the second switching element T2 and the gate electrode of the second switching element T2. Each of the gate-drain capacitors Cgs1 and Cgs2 can be a parasitic capacitor.

[0079] Figure 4 is an enlarged plan view of the entire first color pixel of Figure 3 Figure 5 is an enlarged plan view of a portion of the first color pixel of Figure 3 Figure 6 is a cross-sectional view taken along line I-I' of Figure 4 Figure 7 is a cross-sectional view taken along line II-II' of Figure 4 In the following, since the structure of the first color pixel SPX1 is the same as that of the second color pixel SPX2, the first color pixel SPX1 will be described as an example.

[0080] In Figure 4 and Figure 5 , the first color pixel SPX1 can include a first switching element T1, a second switching element T2, and a third switching element T3.

[0081] The first source electrode SE1 of the first switching element T1 can be connected to the data line DL, and the first drain electrode DE1 of the first switching element T1 can be connected to the first sub-pixel electrode 191 through the first contact hole CNT1. The first switching element T1 can include a first gate electrode connected to the gate line SL. According to an exemplary embodiment of the present disclosure, the first gate electrode can be the gate line SL.

[0082] The first source electrode SE1 of the first switching element T1 can protrude from the data line DL and can extend in a first direction DR1. The first source electrode SE1 of the first switching element T1 can be directly connected to the data line DL. The first source electrode SE1 of the first switching element T1 can be integrally formed with the data line DL. The first source electrode SE1 of the first switching element T1 can have a curved shape such as a U shape. The first drain electrode DE1 of the first switching element T1 can be spaced apart from the first source electrode SE1 of the first switching element T1 in a second direction DR2. The first drain electrode DE1 of the first switching element T1 can have a polygonal shape when viewed from the top. A portion of the first drain electrode DE1 can protrude downward (toward the first source electrode SE1 of the first switching element T1) in the second direction DR2. The portion of the first drain electrode DE1 of the first switching element T1 that protrudes downward in the second direction DR2 can be surrounded by the first source electrode SE1 of the first switching element T1 when viewed from the top.

[0083] ​​​The second source electrode SE2 of the second switching element T2 can be connected to the data line DL. The second source electrode SE2 can be integrally formed with the first source electrode SE1. The second drain electrode DE2 of the second switching element T2 can be connected to the second sub-pixel electrode 192 through the second contact hole CNT2. The second switching element T2 can include a second gate electrode connected to the gate line SL. According to an exemplary embodiment of the disclosure, the second gate electrode can be the gate line SL.

[0084] The second source electrode SE2 can protrude from the data line DL and can extend in the first direction DR1. The second source electrode SE2 can be directly connected to the data line DL. The second source electrode SE2 can be integrally formed with the data line DL. In addition, the second source electrode SE2 can be integrally formed with the first source electrode SE1 of the first switching element T1. The second drain electrode DE2 can be spaced apart from the second source electrode SE2 in the first direction DR1.

[0085] The third source electrode SE3 of the third switching element T3 can be connected to the voltage division reference line RL through the third contact hole CNT3. The third drain electrode DE3 of the third switching element T3 can be connected to the second sub-pixel electrode 192 through the second contact hole CNT2 and can be integrally formed with the second drain electrode DE2. According to an exemplary embodiment of the disclosure, the second drain electrode DE2 and the third drain electrode DE3 can be formed by the same electrode pattern, and the second drain electrode DE2 and the third drain electrode DE3 can share the electrode pattern. The third switching element T3 can include a third gate electrode connected to the gate line SL. According to an exemplary embodiment of the disclosure, the third gate electrode can be the gate line SL.

[0086] The first color pixel SPX1 can include the first sub-pixel electrode 191 and the second sub-pixel electrode 192.

[0087] Most of the first sub-pixel electrode 191 can be disposed in the first sub-pixel area FSPX1, and most of the second sub-pixel electrode 192 can be disposed in the second sub-pixel area FSPX2. The first sub-pixel electrode 191 can be in contact with the first drain electrode DE1 through the first contact hole CNT1 and can be electrically connected to the first drain electrode DE1. The second sub-pixel electrode 192 can be in contact with the second drain electrode DE2 through the second contact hole CNT2 and can be electrically connected to the second drain electrode DE2.

[0088] The first sub-pixel electrode 191 can include a first trunk 191a disposed in the first sub-pixel area FSPX1, first branches 191b disposed in the first sub-pixel area FSPX1, and extending from the first sub-pixel area FSPX1 to the switching element area TA, the first branches 191b extending outward from the first trunk 191a and spaced apart from each other with a slit 191c therebetween.

[0089] The first trunk 191a can include a horizontal trunk portion extending in the first direction DR1 and a vertical trunk portion extending in the second direction DR2. The first trunk 191a can divide the first sub-pixel electrode 191 into auxiliary areas, i.e., domains. For example, the first trunk 191a can be formed in a cross shape. In this case, the first sub-pixel electrode 191 can be divided into four auxiliary areas by the first trunk 191a. The first branches 191b located in different auxiliary areas can extend in different directions. For example, the first branches 191b located in the upper right auxiliary area can extend obliquely in the upper right direction from the first trunk 191a, and the first branches 191b located in the lower right auxiliary area can extend obliquely in the lower right direction from the first trunk 191a. The first branches 191b located in the upper left auxiliary area can extend obliquely in the upper left direction from the first trunk 191a, and the first branches 191b located in the lower left auxiliary area can extend obliquely in the lower left direction from the first trunk 191a. The first extension portion 191d can extend from the first trunk 191a or the first branch 191b to the switching element area TA and can be electrically connected to the first drain electrode DE1 through the first contact hole CNT1.

[0090] The second sub-pixel electrode 192 can include a second trunk 192a disposed in the second sub-pixel area FSPX2, second branches 192b disposed in the second sub-pixel area FSPX2, and extending from the second sub-pixel area FSPX2 to the switching element area TA, the second branches 192b extending outward from the second trunk 192a and spaced apart from each other with a slit 192c therebetween.

[0091] The second trunk 192a, the second branch 192b, and the second extension portion 192d are substantially the same as the first trunk 191a, the first branch 191b, and the first extension portion 191d, respectively, and thus, redundant descriptions will be omitted.

[0092] The size of the first sub-pixel electrode 191 can be smaller than the size of the second sub-pixel electrode 192 when viewed from the top. Here, the size of each of the first and second sub-pixel electrodes 191 and 192 can be measured based on a width in the first direction DR1 and a width in the second direction DR2. The width of each of the first and second sub-pixel electrodes 191 and 192 in the first direction DR1 when viewed from the top can be formed from the width of a portion of the data line DL of each of the first and second sub-pixel electrodes 191 and 192 that is closest to the first color pixel SPX1 to a portion of the data line DL of each of the first and second sub-pixel electrodes 191 and 192 that is closest to a color pixel adjacent to the first color pixel SPX1 in the first direction DR1. The width of the first sub-pixel electrode 191 in the second direction DR2 when viewed from the top can be defined as the width of a portion of the first sub-pixel electrode 191 of the first color pixel SPX1 that is closest to the first storage line CSTL1 to a portion of the first sub-pixel electrode 191 that extends in the second direction DR2. The width of the second sub-pixel electrode 192 in the second direction DR2 when viewed from the top can be defined as the width of a portion of the second sub-pixel electrode 192 that is closest to the second storage line CSTL2 to a portion of the second sub-pixel electrode 192 that extends in the second direction DR2.

[0093] The first color pixel SPX1 can further include a shield line EFS. The shield line EFS can be disposed at the same level as the first and second sub-pixel electrodes 191 and 192 described above. The shield line EFS can be disposed to overlap at least a portion of each of the data line DL, the gate line SL, the first switching element T1, and the second switching element T2, and can form a parasitic capacitor together with the common electrode CE described later. By doing so, it is possible to prevent liquid crystals from not working properly.

[0094] As shown in FIG. 1A, in the first direction DR1, the width of the first sub-pixel electrode 191 can be substantially the same as the width of the second sub-pixel electrode 192. The width of the first sub-pixel electrode 191 in the second direction DR2 can be smaller than the width of the second sub-pixel electrode 192 in the second direction DR2. Figure 4 Hereinafter, the cross-sectional structure of the first color pixel SPX1 described above will be described with reference to FIGS. 1B, 1C, 1D, and 1E, which illustrate cross-sectional structures of the first color pixel SPX1 along the first direction DR1 and the second direction DR2.

[0095] Figure 4 Figure 5 Figure 6 Figure 7

[0096] In FIG. 1B, the first color pixel SPX1 includes the first and second sub-pixel electrodes 191 and 192, the first and second storage lines CSTL1 and CSTL2, the first and second switching elements T1 and T2, the data line DL, the gate line SL, and the shield line EFS. The first and second sub-pixel electrodes 191 and 192 can be disposed on the same horizontal plane as the first and second storage lines CSTL1 and CSTL2. The first and second switching elements T1 and T2 can be disposed on the same horizontal plane as the data line DL and the gate line SL. The shield line EFS can be disposed on the same horizontal plane as the first and second sub-pixel electrodes 191 and 192. Figure 4 Figure 5 Figure 6 Figure 7 ​​​​​​​​In the embodiment, the substrate can include a first substrate SUB1 and a second substrate SUB2 facing the first substrate SUB1. The plurality of pixels PX described above can be provided on the first substrate SUB1, and the common electrode CE can be provided on the second substrate SUB2. The liquid crystal layer 300 including the liquid crystal 310 can be provided between the pixel PX of the first substrate SUB1 and the common electrode CE of the second substrate SUB2.

[0097] The first substrate SUB1 can include an insulating material such as glass, quartz, and a polymer resin. The polymer material can include polyether sulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The first substrate SUB1 can include a metallic material.

[0098] The first conductive layer can be provided on the first substrate SUB1. The first conductive layer can include the gate line SL, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the storage lines CSTL1 and CSTL2. The first gate electrode GE1 can be a gate electrode of the first switching element T1, the second gate electrode GE2 can be a gate electrode of the second switching element T2, and the third gate electrode GE3 can be a gate electrode of the third switching element T3.

[0099] Each of the gate line SL, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the storage lines CSTL1 and CSTL2 can be formed of the first conductive layer. They can be provided on the same layer and can be formed of the same material. The first conductive layer can be formed of a single layer or multiple layers. When the first conductive layer is formed of a single layer, the first conductive layer can include one selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy thereof. In addition, when the first conductive layer is formed of multiple layers, the first conductive layer can be formed of the materials listed above. For example, the first conductive layer can be formed of two layers of molybdenum / aluminum-neodymium, molybdenum / aluminum, or copper / titanium.

[0100] Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 can be electrically connected to the gate line SL. The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 can be connected to each other. However, it is to be understood that the present disclosure is not limited thereto. According to an exemplary embodiment of the present disclosure, the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 can be the gate line SL.

[0101] The gate insulating layer GI can be disposed on the gate line SL, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the storage lines CSTL1 and CSTL2 to insulate them from each other. The gate insulating layer GI can include an inorganic insulating material such as a silicon compound and a metal oxide. For example, the gate insulating layer GI can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. The gate insulating layer GI can be formed of a single layer or multiple layers of different materials.

[0102] The semiconductor layer ACT is located on the gate insulating layer GI. The semiconductor layer ACT can include a first semiconductor region AP1, a second semiconductor region AP2, and a third semiconductor region AP3. The first semiconductor region AP1 can be defined as a region overlapping the first source electrode SE1, the first drain electrode DE1, and the first gate electrode GE1 of the first switching element T1. The second semiconductor region AP2 can be defined as a region overlapping the second source electrode SE2, the second drain electrode DE2, and the second gate electrode GE2 of the second switching element T2. The third semiconductor region AP3 can be defined as a region overlapping the third source electrode SE3, the third drain electrode DE3, and the third gate electrode GE3 of the third switching element T3.

[0103] The first semiconductor region AP1 to the third semiconductor region AP3 respectively include channel regions CH1, CH2, and CH3. The first channel region CH1 can be defined as a region overlapping the first gate electrode GE1 of the first switching element T1 and formed between the first source electrode SE1 and the first drain electrode DE1. The second channel region CH2 can be defined as a region overlapping the second gate electrode GE2 of the second switching element T2 and formed between the second source electrode SE2 and the second drain electrode DE2. The third channel region CH3 can be defined as a region overlapping the third gate electrode GE3 of the third switching element T3 and formed between the third source electrode SE3 and the third drain electrode DE3. In each of the first channel region CH1, the second channel region CH2, and the third channel region CH3, a channel (or channel region) can be formed due to the conductivity between the source electrode and the drain electrode being reversed when an electric field is applied through the gate electrode overlapping the channel. According to an exemplary embodiment of the present disclosure, the first semiconductor region AP1 to the third semiconductor region AP3 can be formed as a single pattern.

[0104] According to an example embodiment of the present disclosure, the semiconductor layer ACT can include a silicon-based semiconductor material such as amorphous silicon, polysilicon, and single crystal silicon. According to another example embodiment, the semiconductor layer ACT can include single crystal silicon, low-temperature polysilicon, or amorphous silicon, etc. In addition, the semiconductor layer ACT can also include an oxide semiconductor. The semiconductor layer ACT can include, for example, a binary compound (AB x ), a ternary compound (AB x C y ), and a quaternary compound (AB x C y D z ) including indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. The semiconductor layer ACT can also include ITZO (an oxide including indium, tin, and zinc) or IGZO (an oxide including indium, gallium, and zinc).

[0105] An ohmic pattern including an ohmic contact layer (not shown) can be further provided on the semiconductor layer ACT including the first to third semiconductor regions AP1 to AP3. The ohmic contact layer can be provided between the source and drain electrodes of each of the switching elements T1 to T3 and the semiconductor layer ACT to lower a Schottky barrier, i.e., a work function, between a metal and silicon, thereby lowering a contact resistance. The ohmic contact layer can be formed of amorphous silicon highly doped with an n-type impurity.

[0106] A second conductive layer can be provided on the gate insulating layer GI and the semiconductor layer ACT. The second conductive layer can include the data line DL, the source and drain electrodes of each of the switching elements T1, T2, and T3, and the voltage division reference line. Each of the data line DL, the source and drain electrodes of the first to third switching elements T1, T2, and T3, and the voltage division reference line can be formed of the second conductive layer. They can be formed of the same material and can be directly provided on the same layer.

[0107] The second conductive layer can be formed of a single layer or multiple layers. When the second conductive layer is formed of a single layer, the second conductive layer can include one selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy thereof. In addition, when the second conductive layer is formed of multiple layers, the second conductive layer can be formed of the materials listed above. For example, the second conductive layer can be formed of two layers of molybdenum / aluminum-neodymium, molybdenum / aluminum, or copper / titanium, or three layers of molybdenum / titanium / molybdenum or molybdenum / aluminum / molybdenum.

[0108] The first source electrode SE1 of the first switching element T1 can be electrically connected to the data line DL. The first source electrode SE1 of the first switching element T1 can be disposed on the semiconductor layer ACT and can be electrically connected to the first semiconductor region AP1. The first drain electrode DE1 of the first switching element T1 can be disposed on the semiconductor layer ACT and can be electrically connected to the first semiconductor region AP1.

[0109] The second source electrode SE2 of the second switching element T2 can be electrically connected to the data line DL. The second source electrode SE2 can be disposed on the semiconductor layer ACT and can be electrically connected to the second semiconductor region AP2. The second drain electrode DE2 of the second switching element T2 can be disposed on the semiconductor layer ACT and can be electrically connected to the second semiconductor region AP2.

[0110] The third source electrode SE3 of the third switching element T3 can be electrically connected to the first storage line CSTL1. According to an exemplary embodiment of the present disclosure, the third source electrode SE3 can be directly connected to the first storage line CSTL1 through the third contact hole CNT3. The third source electrode SE3 can be disposed on the semiconductor layer ACT and can be electrically connected to the third semiconductor region AP3. The third drain electrode DE3 of the third switching element T3 can be disposed on the semiconductor layer ACT and can be electrically connected to the third semiconductor region AP3.

[0111] When the second conductive layer is patterned together with the semiconductor layer ACT, the semiconductor layer ACT can be disposed under the second conductive layer in a similar shape, for example, under the data line DL, the first to third source electrodes SE1, SE2, and SE3, the first to third drain electrodes DE1, DE2, and DE3, and the voltage division reference line RL.

[0112] The color filter 112 can be disposed on the first switching element T1, the second switching element T2, and the third switching element T3 formed on the first substrate SUB1. The color filter 112 can include a red color filter, a green color filter, and a blue color filter. The red color filter can be disposed in the first color pixel SPX1, the green color filter can be disposed in the second color pixel SPX2, and the blue color filter can be disposed in the third color pixel SPX3. The red color filter, the green color filter, and the blue color filter can overlap each other at the boundaries of the color pixels SPX1, SPX2, and SPX3, but the present disclosure is not limited thereto. They can not overlap each other. Figure 6 A cross-section of the first color pixel SPX1, which can be a red color filter, is illustrated.

[0113] The insulating layer 113 can be disposed on the color filter 112. The insulating layer 113 can include an organic insulating material or an inorganic insulating material. According to an exemplary embodiment of the present disclosure, the insulating layer 113 can be a protective layer.

[0114] A third conductive layer can be provided on the insulating layer 113. The third conductive layer can include the first sub-pixel electrode 191, the second sub-pixel electrode 192, and the shield line EFS. Since Figure 6 and Figure 7 The first extension portion 191d of the first sub-pixel electrode 191 and the second extension portion 192d of the second sub-pixel electrode 192 are illustrated, and thus the first extension portion 191d and the second extension portion 192d will be described as examples of the first sub-pixel electrode 191 and the second sub-pixel electrode 192, respectively.

[0115] The first extension portion 191d, the second extension portion 192d, and the shield line EFS can be formed of a third conductive layer. The third conductive layer can be formed of a transparent material that transmits light. For example, the third conductive layer can be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). However, it should be understood that the present disclosure is not limited thereto. The third conductive layer can be formed of any material as long as the material is transparent and conductive.

[0116] The first drain electrode DE1 of the first switching element T1 can be electrically connected to the first extension portion 191d of the first sub-pixel electrode 191. The insulating layer 113 and the color filter 112 can include a first contact hole CNT1 passing therethrough in a thickness direction. The first extension portion 191d can be electrically connected to the first drain electrode DE1 of the first switching element T1 through the first contact hole CNT1.

[0117] The second drain electrode DE2 of the second switching element T2 can be electrically connected to the second extension portion 192d of the second sub-pixel electrode 192. The insulating layer 113 and the color filter 112 can include a second contact hole CNT2 passing therethrough in a thickness direction. The second extension portion 192d can be electrically connected to the second drain electrode DE2 of the second switching element T2 through the second contact hole CNT2.

[0118] The shield line EFS can be provided at the same level as the first sub-pixel electrode 191 and the second sub-pixel electrode 192, and can be provided on the insulating layer 113. The shield line EFS can be provided to overlap at least a portion of each of the data line DL, the gate line SL, the first switching element T1, and the second switching element T2.

[0119] The second substrate SUB2 facing the first substrate SUB1 can include the light-blocking member BM and the common electrode CE.

[0120] The second substrate SUB2 can be a transparent insulating substrate similar to the first substrate SUB1. In addition, the second substrate SUB2 can include a polymer or plastic having high heat resistance. The second substrate SUB2 can have flexibility.

[0121] The light-blocking member BM can be disposed on a surface of the second substrate SUB2 facing the first substrate SUB1. The light-blocking member BM can overlap the switching element region TA. The light-blocking member BM can include a light-blocking pigment such as carbon black or an opaque material such as chromium (Cr), and can include a light-sensitive organic material. However, it should be understood that the present disclosure is not limited thereto. For example, the light-blocking member BM can be disposed in the first substrate SUB1.

[0122] The common electrode CE can be disposed on a surface of the light-blocking member BM facing the first substrate SUB1. The common electrode CE can be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). The common electrode CE can be formed over the entire surface of the second substrate SUB2.

[0123] The liquid crystal layer 300 can be disposed between the first substrate SUB1 and the second substrate SUB2. The liquid crystal layer 300 can include liquid crystals 310 having dielectric anisotropy.

[0124] A common voltage is applied to the common electrode CE to form an electric field together with the first sub-pixel electrode 191 and the second sub-pixel electrode 192. In this case, the alignment of the liquid crystals 310 in the liquid crystal layer 300 changes according to the magnitude of the electric field, and thus the transmittance can be controlled.

[0125] Specifically, when an electric field is formed in the liquid crystal layer 300 between the first substrate SUB1 and the second substrate SUB2, the liquid crystals 310 rotate in a direction between the first substrate SUB1 and the second substrate SUB2, thereby adjusting the phase retardation of light passing through the liquid crystal layer 300. The amount of polarized light (e.g., light that has passed through the lower polarizer) passing through the upper polarizer (which can be disposed on the exit side and, for example, can be attached to the outer surface of the second substrate SUB2) changes depending on the change in the phase retardation caused by the rotation of the liquid crystals 310. Based on this, the transmittance can be controlled.

[0126] The structure of the second color pixel SPX2 can be the same as that of the first color pixel SPX1. As Figure 2 As shown in FIG. 11B, the third color pixel SPX3 is substantially the same as the first color pixel SPX1 except that the voltage division reference line RL is disposed and connected to the first storage line CSTL1 through the third contact hole CNT3.

[0127] Figure 8 、 Figure 9 and Figure 10 is a plan view showing a partial configuration of a switching element region of a first color pixel according to an exemplary embodiment of the present disclosure. Figure 11 is a plan view showing a second drain electrode according to an exemplary embodiment of the present disclosure.Figure 12 is a plan view showing a part of the configuration of a switching element region of a first color pixel according to an example embodiment of the present disclosure. Figure 13 is a cross-sectional view taken along Figure 4 line III-III'.

[0128] In Figure 8 , first to third source electrodes SE1, SE2, and SE3 and first to third drain electrodes DE1, DE2, and DE3 that overlap the gate line SL can be provided. A first gate-drain capacitor Cgs1 can be formed at a place where the first drain electrode DE1 of the first switching element T1 overlaps the gate line SL, and a second gate-drain capacitor Cgs2 can be formed at a place where the second drain electrode DE2 of the second switching element T2 overlaps the gate line SL.

[0129] Each of the first gate-drain capacitor Cgs1 and the second gate-drain capacitor Cgs2 can affect a kickback effect on a data drive signal (data voltage) by a gate drive signal (gate voltage) applied to the gate line SL. A kickback voltage due to the kickback effect can refer to a change in the data drive signal (data voltage) applied to the first sub-pixel electrode 191 and the second sub-pixel electrode 192 in a transition direction when the gate drive signal (gate voltage) drops from a high voltage to a lower voltage and the data drive signal is affected by a transition of the gate drive signal (gate voltage).

[0130] The kickback voltage (Vkb) of the data drive signal (data voltage) can be calculated by Equation 1 below:

[0131] [Equation 1]

[0132]

[0133] where Clc denotes a liquid crystal capacitance of a liquid crystal capacitor formed between the sub-pixel electrodes 191 and 192 and the common electrode CE, Cst denotes a storage capacitance of a storage capacitor formed between the storage lines CSTL1 and CSTL2 and the sub-pixel electrodes 191 and 192, and Cgs denotes a gate-drain capacitance of a gate-drain capacitor formed between the gate electrodes GE1, GE2, and GE3 and the drain electrodes DE1, DE2, and DE3 of the switching elements T1, T2, and T3. And, where Von is a gate-on voltage and Voff is a gate-off voltage.

[0134] According to Formula 1, the kickback voltage can be inversely proportional to a liquid crystal capacitance of a liquid crystal capacitor formed between the sub-pixel electrodes 191 and 192 and the common electrode CE and a storage capacitance of a storage capacitor formed between the storage lines CSTL1 and CSTL2 and the sub-pixel electrodes 191 and 192, and can be proportional to a gate-drain capacitance of a gate-drain capacitor formed between the gate electrodes GE1, GE2, and GE3 and the drain electrodes DE1, DE2, and DE3 of the switching elements T1, T2, and T3.

[0135] According to an exemplary embodiment of the disclosure, the first source electrode SE1 overlapping the gate line SL can be formed in a U shape when viewed from the top, and the first drain electrode DE1 overlapping the gate line SL can be formed in a bar shape when viewed from the top. The first channel region CH1 can be formed where the first drain electrode DE1 and the first source electrode SE1 face each other.

[0136] In addition, the second source electrode SE2 overlapping the gate line SL can be integrally formed with the first source electrode SE1, and the second source electrode SE2 can be the first source electrode SE1. The second drain electrode DE2 can be disposed to be spaced apart from and face the second source electrode SE2. A portion of the second drain electrode DE2 facing the second source electrode SE2 can be formed in parallel with the second source electrode SE2. The second channel region CH2 can be formed where the second source electrode SE2 and the second drain electrode DE2 face each other.

[0137] The second drain electrode DE2 can overlap the gate line SL, and the area thereof can include a first area extending in the first direction DR1 and a second area extending in the second direction DR2. The first area of the second drain electrode DE2 can be a first horizontal portion DE2_2 extending in the first direction DR1, and the second area of the second drain electrode DE2 can be a first vertical portion DE2_1 extending in the second direction DR2.

[0138] The third source electrode SE3 overlapping the gate line SL can be formed in a bar shape when viewed from the top, similar to the first drain electrode DE1 described above. The third drain electrode DE3 can be disposed to face the third source electrode SE3, and a portion of the third drain electrode DE3 can be parallel to the third source electrode SE3. The third drain electrode DE3 can be integrally formed with the second drain electrode DE2, and the third drain electrode DE3 can be the second drain electrode DE2.

[0139] As described above, the first gate-drain capacitor Cgs1 can be formed where the first drain electrode DE1 overlaps the gate line SL, and the second gate-drain capacitor Cgs2 can be formed where the second drain electrode DE2 overlaps the gate line SL.

[0140] The capacitance of the first gate-drain capacitor Cgs1 can change depending on the size of the area where the first drain electrode DE1 overlaps the gate line SL. For example, when the area where the first drain electrode DE1 overlaps the gate line SL increases, the capacitance of the first gate-drain capacitor Cgs1 can also increase. When the area where the first drain electrode DE1 overlaps the gate line SL decreases, the capacitance of the first gate-drain capacitor Cgs1 can also decrease. Similarly to the change in the capacitance of the first gate-drain capacitor Cgs1, the capacitance of the second gate-drain capacitor Cgs2 can change depending on the area where the second drain electrode DE2 overlaps the gate line SL.

[0141] In Figure 9 the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 formed of the second conductive layer can be slightly misaligned to the lower side (the lower side of the drawing) of the gate line SL. When this occurs, the area where the first drain electrode DE1 overlaps the gate line SL increases, and thus the capacitance of the first gate-drain capacitor Cgs1 can also increase. Since the area where the first vertical portion DE2_1 and the portion of the first horizontal portion DE2_2 of the second drain electrode DE2 overlap the gate line SL does not change, the capacitance value of the second gate-drain capacitor Cgs2 can not change.

[0142] On the contrary, the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 formed of the second conductive layer can be slightly misaligned to the upper side (the upper side of the drawing) of the gate line SL. When this occurs, the area where the first drain electrode DE1 overlaps the gate line SL decreases, and thus the capacitance of the first gate-drain capacitor Cgs1 can also decrease. Since the area where the first vertical portion DE2_1 and the portion of the first horizontal portion DE2_2 of the second drain electrode DE2 overlap the gate line SL does not change, the capacitance value of the second gate-drain capacitor Cgs2 can not change.

[0143] In addition, the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 formed of the second conductive layer can be slightly misaligned to the right side (the right side of the drawing) of the gate line SL. When this occurs, the area where the second drain electrode DE2 overlaps the gate line SL decreases, and thus the capacitance of the second gate-drain capacitor Cgs2 can also decrease. Although the area where the first vertical portion DE2_1 of the second drain electrode DE2 overlaps the first gate line SL does not change, the area where the first horizontal portion DE2_2 overlaps the gate line SL can decrease. Since the area where the first drain electrode DE1 overlaps the gate line SL does not change, the capacitance of the first gate-drain capacitor Cgs1 can not change.

[0144] On the contrary, as Figure 10As shown in FIG. 2, the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 formed of the second conductive layer can be slightly misaligned to the left side (left side of the drawing) of the gate line SL. When this occurs, the area in which the second drain electrode DE2 overlaps the gate line SL increases, and thus the capacitance of the second gate-drain capacitor Cgs2 can also increase. Although the area in which the first vertical portion DE2_1 of the second drain electrode DE2 overlaps the gate line SL does not change, the area in which the first horizontal portion DE2_2 overlaps the gate line SL can increase. Since the area in which the first drain electrode DE1 overlaps the gate line SL does not change, the capacitance of the first gate-drain capacitor Cgs1 can not change.

[0145] As described above, when the capacitance of the gate-drain capacitor increases, the kickback voltage increases. When the difference between the capacitance of the first gate-drain capacitor Cgs1 and the capacitance of the second gate-drain capacitor Cgs2 increases, the luminance of the first and second sub-pixel regions can change, resulting in a non-uniform defect. If the capacitance of the first gate-drain capacitor Cgs1 increases and the capacitance of the second gate-drain capacitor Cgs2 decreases, the capacitance difference between the first gate-drain capacitor Cgs1 and the second gate-drain capacitor Cgs2 further increases, resulting in a stronger non-uniform defect.

[0146] According to an exemplary embodiment of the present disclosure, as Figure 11 As shown in FIG. 2, the second drain electrode DE2 can include a first vertical portion DE2_1 extending in the second direction DR2 and a first horizontal portion DE2_2 extending from an end of the first vertical portion DE2_1 in the first direction DR1. The first vertical portion DE2_1 can overlap the gate line SL. A portion of the first horizontal portion DE2_2 can overlap the gate line SL, and another portion of the first horizontal portion DE2_2 can not overlap the gate line SL. The first vertical portion DE2_1 can be disposed in parallel with the second source electrode SE2 to face the second source electrode SE2. The first horizontal portion DE2_2 can extend from one end of the first vertical portion DE2_1, i.e., from one end adjacent to the second sub-pixel electrode 192 in a direction away from the data line DL.

[0147] In Figure 12In this embodiment, if the first drain electrode DE1 moves upward or downward (in the second direction DR2), the capacitance of the first gate-drain capacitor Cgs1 can change. If the second drain electrode DE2 moves left or right (in the first direction DR1), the capacitance of the second gate-drain capacitor Cgs2 can change. According to an exemplary embodiment of this disclosure, the second drain electrode DE2 includes a first vertical portion DE2_1 and a first horizontal portion DE2_2 overlapping the gate line SL, thereby allowing the capacitance of the first gate-drain capacitor Cgs1 and the capacitance of the second gate-drain capacitor Cgs2 to change under different conditions (different directions of movement of the drain electrodes).

[0148] In other words, because the capacitance of the first gate-drain capacitor Cgs1 changes when the drain electrode moves vertically and the capacitance of the second gate-drain capacitor Cgs2 changes when the drain electrode moves horizontally, if the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 are not aligned with the gate line SL, only one of the capacitances of the first gate-drain capacitor Cgs1 and the second gate-drain capacitor Cgs2 will change. In this way, the difference between the capacitances of the first gate-drain capacitor Cgs1 and the second gate-drain capacitor Cgs2 can be prevented from increasing, thereby reducing the range of the difference in recoil voltage between the first sub-pixel region and the second sub-pixel region. As a result, non-uniformity defects can be suppressed.

[0149] In addition, such as Figure 12 As shown, according to an exemplary embodiment of the present disclosure, the directions of the first channel region CH1 formed between the first source electrode SE1 and the first drain electrode DE1, the direction of the second channel region CH2 formed between the second source electrode SE2 and the second drain electrode DE2, and the direction of the third channel region CH3 formed between the third source electrode SE3 and the third drain electrode DE3 can all be the same.

[0150] Specifically, the length direction of the first channel region CH1 formed between the first source electrode SE1 and the first drain electrode DE1 can be a first direction DR1. The length direction of the second channel region CH2 formed between the second source electrode SE2 and the second drain electrode DE2 can be a first direction DR1. The length direction of the third channel region CH3 formed between the third source electrode SE3 and the third drain electrode DE3 can be a first direction DR1. As used herein, the length of the channel region can be the shortest distance between the source electrode and the drain electrode. The length of the first channel region CH1 can be the shortest distance between the first source electrode SE1 and the first drain electrode DE1, the length of the second channel region CH2 can be the shortest distance between the second source electrode SE2 and the second drain electrode DE2, and the length of the third channel region CH3 can be the shortest distance between the third source electrode SE3 and the third drain electrode DE3.

[0151] The length direction of each channel region can be parallel to the first direction DR1, and the width direction of each channel region can be parallel to the second direction DR2. According to an exemplary embodiment of the present disclosure, the first channel region CH1 can be formed in a U shape, and thus the channel region has different directions. Although the first channel region CH1 has a U shape, since the linear portion of the U shape is greater than the curved portion of the U shape, it can be considered that the direction of the first channel region CH1 is the first direction DR1 which is the direction of the channel region formed along the linear portion of the U shape.

[0152] When the first channel region CH1, the second channel region CH2, and the third channel region CH3 have the same direction, it is possible to prevent the length or the width of the channel region of the switching element from being different from the original design, which can occur when the channel regions have different directions. In other words, the switching element having the same channel region direction can be formed as designed, but the switching element having different channel region directions can be formed differently from the design, and thus, the variation in the electrical characteristics (e.g., the snapback voltage) can increase. In contrast, according to an exemplary embodiment of the present disclosure, it is possible to prevent the uneven defects that can occur if the difference in the snapback voltage between the switching elements increases.

[0153] Incidentally, with reference to Figure 4 , Figure 5 , Figure 6 and Figure 13 , the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 can be disposed so that they overlap with the through-holes of the color filter 112 disposed between the insulating layer 113 and the source electrode SE3.

[0154] Specifically, the first drain electrode DE1 of the first switching element T1 can be electrically connected to the first extension portion 191d of the first sub-pixel electrode through the first contact hole CNT1. The first contact hole CNT1 can overlap with the first through-hole CFH1 of the color filter 112 disposed between the first drain electrode DE1 and the first extension portion 191d. The first through-hole CFH1 can pass through the color filter 112 to expose the underlying layer, e.g., the first drain electrode DE1. The first contact hole CNT1 can expose the first drain electrode DE1 through the first through-hole CFH1. The first extension portion 191d can be electrically connected to the first drain electrode DE1 exposed through the first contact hole CNT1 and the first through-hole CFH1.

[0155] In addition, the second contact hole CNT2 and the third contact hole CNT3 can overlap the second via hole CFH2. The second via hole CFH2 can pass through the color filter 112 to expose an underlying layer, e.g., the third source electrode SE3, the gate insulating layer GI, and the third drain electrode DE3. The third contact hole CNT3 can pass through the gate insulating layer GI disposed between the third source electrode SE3 and the first storage line CSTL1 through the second via hole CFH2 to expose the first storage line CSTL1. The first electrode pattern 193 can contact the third source electrode SE3 and the first storage line CSTL1 exposed through the third contact hole CNT3 and the second via hole CFH2. The second contact hole CNT2 can pass through the insulating layer 113 to expose the third drain electrode DE3. The second extension portion 192d of the second sub-pixel electrode can contact the third drain electrode DE3 exposed through the second contact hole CNT2 and the second via hole CFH2.

[0156] The second contact hole CNT2 and the third contact hole CNT3 can overlap the second via hole CFH2. When viewed from the top, the second contact hole CNT2 and the third contact hole CNT3 can be located in the second via hole CFH2. A width W4 of the second via hole CFH2 in the second direction DR2 can be greater than a width W5 of the third contact hole CNT3 in the second direction DR2 and a width of the second contact hole CNT2 in the second direction DR2. The width W4 of the second via hole CFH2 can be greater than a sum (W5+W6) of the width W5 of the third contact hole CNT3 and the width W6 of the second contact hole CNT2. When the width W4 of the second via hole CFH2 is greater than the sum (W5+W6) of the width W5 of the third contact hole CNT3 and the width W6 of the second contact hole CNT2, the second contact hole CNT2 and the third contact hole CNT3 can be disposed in a single via hole CFH2, thereby preventing a loss of aperture ratio due to a via hole of the color filter 112.

[0157] The second via hole CFH2 can be disposed to overlap the gate line SL. The width W4 of the second via hole CFH2 can cross the gate line SL. In addition, the second contact hole CNT2 and the third contact hole CNT3 can not overlap the gate line SL. That is, the second contact hole CNT2 and the third contact hole CNT3 can be spaced apart from the gate line SL.

[0158] In addition, according to an exemplary embodiment of the disclosure, the display device can include a first conductive pattern CP1 and a second conductive pattern CP2 disposed between the gate insulating layer GI and the insulating layer 113.

[0159] Specifically, a gate insulating layer GI can be disposed on the first storage line CSTL1, the second storage line CSTL2, and the gate line SL disposed on the first substrate SUB1. The first conductive pattern CP1 and the second conductive pattern CP2 can be disposed on the gate insulating layer GI. The first conductive pattern CP1 can at least partially overlap the first storage line CSTL1 and can not overlap the gate line SL. The second conductive pattern CP2 can at least partially overlap the second storage line CSTL2 and can not overlap the gate line SL.

[0160] The first conductive pattern CP1 and the second conductive pattern CP2 can be disposed in the second through-hole CFH2. At least a portion of the first conductive pattern CP1 can be exposed through the third contact hole CNT3, and other portions of the first conductive pattern CP1 can overlap the insulating layer 113. Accordingly, the first conductive pattern CP1 can contact the first electrode pattern 193 disposed on the insulating layer 113 through the third contact hole CNT3. At least a portion of the second conductive pattern CP2 can be exposed through the second contact hole CNT2, and other portions of the second conductive pattern CP2 can overlap the insulating layer 113. Accordingly, the second conductive pattern CP2 can contact the second extension portion 192d of the second sub-pixel electrode 192 (i.e., the second electrode pattern disposed on the insulating layer 113) through the second contact hole CNT2.

[0161] Each of the first conductive pattern CP1 and the second conductive pattern CP2 can have a structure of a stacked semiconductor layer ACT and a source pattern SDP1. The source pattern SDP1 can be the same pattern as the third source electrode SE3 and can continuously extend from the third source electrode SE3. Accordingly, the source pattern SDP1 can be disposed on the same layer as the third source electrode SE3 and can include the same material.

[0162] According to an exemplary embodiment of the disclosure, the first conductive pattern CP1 and the second conductive pattern CP2 can increase adhesion to the insulating layer 113. For example, the insulating layer 113 can be formed of an organic material. The color filter 112 can be patterned under the insulating layer 113 to form the second through-hole CFH2. However, if a material for the color filter 112 remains on the gate insulating layer GI at the second through-hole CFH2, adhesion between the insulating layer 113 and the gate insulating layer GI decreases, and thus the insulating layer 113 can be peeled off. In particular, when the gate line SL is disposed in the second through-hole CFH2, a material layer for the color filter 112 is thinner where the gate line SL is disposed, and the material layer for the color filter 112 is thicker where the gate line SL is not disposed. During a process of patterning and removing the material layer for the color filter 112, the thick material layer for the color filter can not be completely removed, and thus the material can remain.

[0163] In addition, if the gate insulating layer GI is not properly formed at the edge of the gate line SL, a material for the color filter 112 remains, and thus the insulating layer 113 can be peeled off and the gate line SL can be exposed. The exposed portion of the gate line SL can be corroded during the process, and a short circuit can be generated between the gate line SL and the first electrode pattern 193 described above.

[0164] According to the exemplary embodiment of the present disclosure, the first conductive pattern CP1 and the second conductive pattern CP2 formed of metal are disposed on the gate insulating layer GI adjacent to but not overlapping the gate line SL. Then, even if a material for the color filter 112 remains, the adhesion between the insulating layer 113 and each of the first conductive pattern CP1 and the second conductive pattern CP2 is also excellent, and thus, the insulating layer 113 can be prevented from being peeled off. Then, the gate line SL can be prevented from being corroded, and thus, a short circuit between the gate line SL and the first electrode pattern 193 can be prevented.

[0165] As described above, the display device according to the exemplary embodiment of the present disclosure can prevent an increase in the difference between the capacitance of the first gate-drain capacitor Cgs1 and the capacitance of the second gate-drain capacitor Cgs2, and thus, can reduce the range of the difference in the kickback voltage between the first sub-pixel region and the second sub-pixel region. As a result, uneven defects can be suppressed. In addition, since the channel regions of the switching elements have the same direction, uneven defects that can occur when the difference in the kickback voltage between the switching elements increases can be suppressed.

[0166] Figure 14 FIG. 1B is a plan view showing one pixel according to another exemplary embodiment. Figure 15 FIG. 1C is a plan view showing a gate line, a source electrode, and a drain electrode of one pixel according to another exemplary embodiment. Figure 16 FIG. 1D is a plan view showing a second drain electrode and a third drain electrode according to another exemplary embodiment. Figure 17 FIG. 1E is a cross-sectional view taken along the line IV-IV' of FIG. 1C. Figure 14

[0167] The structure of the pixel according to another exemplary embodiment is substantially the same as that of the pixel according to the above-described exemplary embodiment, except that the second switching element and the third switching element are spaced apart. In the following description, the description will focus on the differences, and the same configuration will be briefly described. In the structure of the pixel according to another embodiment, a voltage division reference line is disposed in each of the first to third color pixels, and the structures of the first to third color pixels are similar. In the following description, the description of the first color pixel can be equally applied to the second color pixel and the third color pixel.

[0168] In the structure of the pixel according to another exemplary embodiment, the first switching element and the second switching element are disposed in the first color pixel, and the second switching element and the third switching element are disposed in the second color pixel. In the structure of the pixel according to another exemplary embodiment, the first switching element and the third switching element are disposed in the third color pixel. Figure 14 ​In the middle, the first color pixel SPX1 can include a first switching element T1, a second switching element T2, and a third switching element T3.

[0169] A first source electrode SE1 of the first switching element T1 can be connected to the data line DL, and a first drain electrode DE1 of the first switching element T1 can be connected to the first sub-pixel electrode 191 through a first contact hole CNT1. The first switching element T1 can include a first gate electrode connected to the gate line SL. According to an exemplary embodiment of the present disclosure, the first gate electrode can be the gate line SL.

[0170] A second source electrode SE2 of the second switching element T2 can be connected to the data line DL. The second source electrode SE2 can be integrally formed with the first source electrode SE1. A second drain electrode DE2 of the second switching element T2 can be connected to the second sub-pixel electrode 192 through a second contact hole CNT2. The second switching element T2 can include a second gate electrode connected to the gate line SL. According to an exemplary embodiment of the present disclosure, the second gate electrode can be the gate line SL.

[0171] A third source electrode SE3 of the third switching element T3 can be connected to the voltage division reference line RL and can be integrally formed with the voltage division reference line RL. A third drain electrode DE3 of the third switching element T3 can extend in one direction and can be connected to the second sub-pixel electrode 192 through the above-described second contact hole CNT2. The third switching element T3 can include a third gate electrode connected to the gate line SL. According to an exemplary embodiment of the present disclosure, the third gate electrode can be the gate line SL.

[0172] The first color pixel SPX1 can include the first sub-pixel electrode 191 and the second sub-pixel electrode 192.

[0173] A majority of the first sub-pixel electrode 191 can be disposed in the first sub-pixel region FSPX1, and a majority of the second sub-pixel electrode 192 can be disposed in the second sub-pixel region FSPX2. The first sub-pixel electrode 191 can include a first trunk 191a disposed in the first sub-pixel region FSPX1, first branches 191b disposed in the first sub-pixel region FSPX1, and a first extension portion 191d extending from the first sub-pixel region FSPX1 to the switching element region TA, the first branches 191b extending outward from the first trunk 191a and spaced apart from each other with a slit 191c therebetween. The second sub-pixel electrode 192 can include a second trunk 192a disposed in the second sub-pixel region FSPX2, second branches 192b disposed in the second sub-pixel region FSPX2, and a second extension portion 192d extending from the second sub-pixel region FSPX2 to the switching element region TA, the second branches 192b extending outward from the second trunk 192a and spaced apart from each other with a slit 192c therebetween.

[0174] The first color pixel SPX1 can further include a shield line EFS. The shield line EFS can be disposed on the same layer as the first and second sub-pixel electrodes 191 and 192 described above, and can include the same material. The shield line EFS can be disposed to overlap at least a portion of each of the data line DL, the gate line SL, and the first to third switching elements T1, T2, and T3, and can form a parasitic capacitor with the common electrode CE. By doing so, it is possible to prevent liquid crystals from not working properly.

[0175] It should be noted that, according to the example embodiment of the present disclosure, the second switching element T2 and the third switching element T3 are spaced apart from each other.

[0176] Referring to Figure 14 and Figure 15 Since the first source electrode SE1 of the first switching element T1 and the second source electrode SE2 of the second switching element T2 share one source pattern, the first switching element T1 and the second switching element T2 can be disposed adjacent to each other. The first channel region CH1 of the first switching element T1 can be disposed adjacent to the second channel region CH2 of the second switching element T2, with the first source electrode SE1 and the second source electrode SE2 interposed between the first channel region CH1 and the second channel region CH2.

[0177] The third switching element T3 can be spaced apart from the first switching element T1 and the second switching element T2. In the example embodiment described above, the first switching element T1 and the second switching element T2 can share a source electrode, and the second switching element T2 and the third switching element T3 can share a drain electrode. In contrast, according to the present example embodiment, the first switching element T1 and the second switching element T2 can share a source electrode, and the second switching element T2 and the third switching element T3 can not share a drain electrode. That is, each of the second switching element T2 and the third switching element T3 can have its own drain electrode, respectively.

[0178] In particular, referring to Figure 16 , the second drain electrode DE2 and the third drain electrode DE3 can be formed by a single drain pattern DEP. The drain pattern DEP can include the second drain electrode DE2, the third drain electrode DE3, and a drain junction DECP disposed between the second drain electrode DE2 and the third drain electrode DE3.

[0179] The drain junction DECP can be a portion of the drain pattern DEP that overlaps the second extension portion 192d of the second sub-pixel electrode. When viewed from the top, the drain junction DECP can have a substantially quadrangular shape, and the second contact hole CNT2 can be formed substantially at a center that can contact the second extension portion 192d.

[0180] The second drain electrode DE2 can extend from the drain connector DECP. The second drain electrode DE2 can extend from one side of the drain connector DECP toward the second source electrode SE2 adjacent to the second drain electrode DE2 in the first direction DR1. The second drain electrode DE2 may include: a first horizontal portion DE2_2 extending from one side of the drain connector DECP toward the second source electrode SE2 adjacent to the second drain electrode DE2 in the first direction DR1; and a first vertical portion DE2_1 extending from one end of the first horizontal portion DE2_2 toward the first storage line CSTL1 adjacent to the second drain electrode DE2 in the second direction DR2. The third drain electrode DE3 can extend from the other side of the drain connector DECP toward the first storage line CSTL1 adjacent to the second drain electrode DE2 in the second direction DR2. For example, when viewed from above, the second drain electrode DE2 can extend from the drain connector DECP toward the 9 o'clock position, and when viewed from above, the third drain electrode DE3 can extend from the drain connector DECP toward the 12 o'clock position.

[0181] As described above, according to an exemplary embodiment of this disclosure, the second drain electrode DE2 and the third drain electrode DE3 are spaced apart from each other by their drain junction DECP, and thus the second switching element T2 and the third switching element T3 are spaced apart from each other. Because the second switching element T2 and the third switching element T3 are spaced apart from each other, there is an advantage that the pixels can be designed with greater freedom.

[0182] exist Figure 14 and Figure 17 In the cross-sectional structure of a pixel shown, the display device according to another exemplary embodiment may include a first substrate SUB1 and a second substrate SUB2 facing the first substrate SUB1. The plurality of pixels PX may be disposed on the first substrate SUB1, and a common electrode CE may be disposed on the second substrate SUB2. A liquid crystal layer 300 including liquid crystal 310 may be disposed between the pixels PX of the first substrate SUB1 and the common electrode CE of the second substrate SUB2.

[0183] A first gate electrode GE1, a second gate electrode GE2, a third gate electrode GE3, a first memory line CSTL1, and a second memory line CSTL2 can be disposed on a first substrate SUB1. The first gate electrode GE1 can be the gate electrode of a first switching element T1, the second gate electrode GE2 can be the gate electrode of a second switching element T2, and the third gate electrode GE3 can be the gate electrode of a third switching element T3. According to an exemplary embodiment of this disclosure, the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 can be a gate line SL.

[0184] A gate insulating layer GI can be provided on the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the first storage line CSTL1, and the second storage line CSTL2 to insulate them from each other. A semiconductor layer ACT is provided on the gate insulating layer GI. The semiconductor layer ACT can include a first semiconductor region API, a second semiconductor region AP2, and a third semiconductor region AP3. The first to third semiconductor regions API, AP2, and AP3 include channel regions CH1, CH2, and CH3, respectively.

[0185] The first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 can be provided on the semiconductor layer ACT, and the color filter 112 can be provided on the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3. The insulating layer 113 can be provided on the color filter 112. The first extension portion 191d of the first sub-pixel electrode, the second extension portion 192d of the second sub-pixel electrode, and the shield line EFS can be provided on the insulating layer 113. The first drain electrode DE1 of the first switching element T1 can be electrically connected to the first extension portion 191d of the first sub-pixel electrode through the first contact hole CNT1, and the second drain electrode DE2 of the second switching element T2 can be electrically connected to the second extension portion 192d of the second sub-pixel electrode through the second contact hole CNT2.

[0186] The second substrate SUB2 facing the first substrate SUB1 can include a light-blocking member BM and a common electrode CE. The light-blocking member BM can be provided on one surface of the second substrate SUB2 facing the first substrate SUB1, and the common electrode CE can be provided on one surface of the light-blocking member BM. A liquid crystal layer 300 including the liquid crystal 310 can be provided between the first substrate SUB1 and the second substrate SUB2.

[0187] As described above, the second drain electrode DE2 and the third drain electrode DE3 are spaced apart from each other with the drain joint DECP therebetween, and thus the second switching element T2 and the third switching element T3 can be spaced apart from each other. Since the second switching element T2 and the third switching element T3 are spaced apart from each other, there is an advantage that a pixel can be designed more freely.

[0188] When the display device 100 according to Figure 14The first sub-pixel region and the second sub-pixel region, and the range of the difference in the kickback voltage between the first sub-pixel region and the second sub-pixel region were measured from a plurality of display apparatuses including pixels having the same structure. By doing so, the range of the difference in the kickback voltage between the first sub-pixel region and the second sub-pixel region was measured from a plurality of display apparatuses including pixels having the same structure.

[0189] According to an example, the kickback voltage of the first sub-pixel region was 3.32 V, and the kickback voltage of the second sub-pixel region was 2.99 V. The difference in the kickback voltage between the first sub-pixel region and the second sub-pixel region was 0.33 V, and the range of the difference in the kickback voltage between the first sub-pixel region and the second sub-pixel region was 0 to 0.7 V.

[0190] It can be seen from the above results that the range of the difference in the kickback voltage between the first sub-pixel region and the second sub-pixel region of the display apparatus according to the exemplary embodiments of the present disclosure has been improved to about 0.7 V or less.

[0191] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent to those of ordinary skill in the art from the foregoing description. The disclosure herein is intended to cover any and all modifications and equivalents within the scope of the claims. Therefore, it is not intended to be limited to the exact embodiments described above, but rather, it is intended to cover such departures from the present disclosure as come within the scope of the appended claims and various obvious modifications and equivalents thereof.

Claims

1. A display device, comprising: A gate line extending in a first direction and a data line extending in a second direction intersecting the first direction, located on the substrate; The first switching element includes a first source electrode connected to the data line, a first drain electrode spaced apart from the first source electrode, and a first gate electrode connected to the gate line; The second switching element includes a second source electrode connected to the data line, a second drain electrode spaced apart from the second source electrode, and a second gate electrode connected to the gate line; Storage lines arranged parallel to the gate lines; as well as The third switching element includes a third source electrode connected to the storage line, a third drain electrode spaced apart from the third source electrode, and a third gate electrode connected to the gate line. The region of the first drain electrode that overlaps with the first gate electrode extends in the second direction. The second source electrode extends in the second direction and is arranged parallel to the first drain electrode and the second drain electrode. Wherein, the region of the second drain electrode that overlaps with the second gate electrode includes a first region extending in the first direction and a second region extending in the second direction, and The third switching element includes a third semiconductor region, in which a third channel region is formed between the second region of the second drain electrode and the third source electrode.

2. The display device according to claim 1, wherein, The second region of the second drain electrode and the second source electrode face each other and are arranged in parallel.

3. The display device according to claim 2, wherein, The second region of the second drain electrode completely overlaps with the gate line, and a portion of the first region of the second drain electrode does not overlap with the gate line.

4. The display device according to claim 3, wherein, The first switching element includes a first semiconductor region in which a first channel region is formed between the first source electrode and the first drain electrode, and the second switching element includes a second semiconductor region in which a second channel region is formed between the second region of the second drain electrode and the second source electrode.

5. The display device according to claim 4, wherein, The length direction of each channel region in the first channel region and the second channel region is parallel to the first direction.

6. The display device according to claim 5, wherein, The length of the first channel region is the shortest distance between the first source electrode and the first drain electrode, and the length of the second channel region is the shortest distance between the second source electrode and the second drain electrode.

7. The display device according to claim 6, wherein, The first source electrode and the second source electrode are directly disposed on the same layer and formed of the same material.

8. The display device according to claim 7, wherein, The third drain electrode is connected to the second drain electrode, and the second region of the second drain electrode and the third source electrode face each other and are arranged in parallel.

9. The display device according to claim 8, wherein, The length direction of the third channel region is parallel to the first direction.

10. The display device according to claim 7, further comprising: A color filter is disposed on the first source electrode to the third source electrode and the first drain electrode to the third drain electrode; as well as An insulating layer is provided on the color filter. The color filter includes a first through-hole exposing the first drain electrode and a second through-hole exposing the third source electrode and the second drain electrode. The insulating layer includes a first contact hole exposing the first drain electrode, a second contact hole exposing the third source electrode, and a third contact hole exposing the second drain electrode.

11. The display device according to claim 10, wherein, The first contact hole overlaps with the first through hole, and the second contact hole and the third contact hole overlap with the second through hole.

12. The display device according to claim 11, wherein, The first drain electrode is connected to the adjacent first sub-pixel electrode through the first contact hole, the third source electrode is connected to the memory line through the second contact hole, and the second drain electrode is connected to the adjacent second sub-pixel electrode through the third contact hole.

13. The display device according to claim 11, further comprising: A first conductive pattern extending from the third source electrode and overlapping with the second contact hole and the second through hole; as well as The second conductive pattern extends from the second drain electrode and overlaps with the third contact hole and the second through hole. The first conductive pattern and the second conductive pattern are spaced apart from each other, the gate line is located between the first conductive pattern and the second conductive pattern, and the first conductive pattern and the second conductive pattern do not overlap with the gate line.

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