Memory-efficient filtering method for image and video coding

Abstract

A memory efficient filtering method codes images and videos. A buffer of a fixed size is allocated, the fixed size being based on the size of a processing unit for filtering a video frame. For each of the processing units, based on a write point for the video frame and an offset applied to the write point, pre-filtered pixel values ​​are copied from a corresponding region of the video frame to the buffer, filtering is performed on the pre-filtered pixel values ​​from the buffer to produce filtered pixel values, and the filtered pixel values ​​are written to the video frame based on the write point and the offset. The filtering may be performed using a loop recovery tool, such as where the pre-filtered pixel values ​​are output from a constrained directional enhancement filter (CDEF) tool. Alternatively, the filtering may be performed using the CDEF tool or another coding tool.

Description

Background Art

[0001] A digital video stream may represent a video using a sequence of frames or still images. Digital video may be used for a variety of applications, including, for example, video conferencing, high-definition video entertainment, video advertising, or sharing of user-generated videos. A digital video stream may contain a large amount of data and consume a large amount of computing or communication resources of a computing device for processing, transmitting, or storing video data. Various methods have been proposed to reduce the amount of data in a video stream, including encoding or decoding techniques. Summary of the invention

[0002] The method for filtering a video frame according to an implementation of the present disclosure includes allocating a buffer with a fixed size, and the fixed size is based on the size of the processing unit used to filter the video frame. For each processing unit in the processing unit, pre-filtered pixel values ​​are copied from the corresponding area of ​​the video frame to the buffer, and the pre-filtered pixel values ​​from the buffer are filtered to generate filtered pixel values, and these filtered pixel values ​​are written to the video frame based on the write point and based on the offset. The corresponding area of ​​the video frame is selected based on the offset applied to the write point for the video frame. The write point represents a position extending beyond the boundary of the frame. The offset specifies the distance from the write point based on the multiple processing units where filtering has been performed. After the filtered pixel values ​​are written to the video frame for each processing unit in the processing unit, the video frame is output for display or storage.

[0003] A device for filtering a video frame according to an implementation of the present disclosure includes a memory and a processor. A first portion of the memory is allocated for storing instructions. A second portion of the memory is allocated for a buffer having a fixed size, the fixed size being based on the size of the processing unit for filtering the video frame. The processor is configured to execute the instructions. The instructions include the following instructions: for a first processing unit, copying a pre-filtered pixel value from a first region of a video frame to a buffer, wherein a starting point of the first processing unit corresponds to a write point defined for the video frame; filtering the buffered pre-filtered pixel value of the first processing unit to generate a first filtered pixel value; writing the first filtered pixel value to the video frame; for a second processing unit, copying the pre-filtered pixel value from a second region of the video frame to a buffer, wherein a starting point of the second processing unit corresponds to an offset applied to the write point; filtering the buffered pre-filtered pixel value of the second processing unit to generate a second filtered pixel value; writing these second filtered pixel values ​​to the video frame; and after writing the filtered pixel values ​​for all processing units, outputting the video frame for display or storage.

[0004] An encoder according to an implementation of the present disclosure performs an operation for filtering a video frame, including identifying a write point for the video frame by shifting a starting point of the video frame by a plurality of pixels, wherein the starting point of the video frame represents an upper leftmost position of the video frame. Pre-filtered pixel values ​​for a processing unit are copied from a region of the video frame to a buffer having a fixed size, the fixed size being based on the size of the processing unit, wherein the position of the write point represents an upper leftmost position of the processing unit. Filtering is performed on the pre-filtered pixel values ​​from the buffer to generate filtered pixel values ​​for the processing unit. The filtered pixel values ​​for the processing unit are written to the video frame based on the write point.

[0005] A decoder according to an implementation of the present disclosure performs an operation for filtering a video frame, including identifying a write point for the video frame by shifting a starting point of the video frame by a number of pixels, wherein the starting point of the video frame represents the upper leftmost position of the video frame. Pre-filtered pixel values ​​for a processing unit are copied from a region of the video frame to a buffer having a fixed size, the fixed size being based on the size of the processing unit, wherein the position of the write point represents the upper leftmost position of the processing unit. Filtering is performed on the pre-filtered pixel values ​​from the buffer to generate filtered pixel values ​​for the processing unit. The filtered pixel values ​​for the processing unit are written to the video frame based on the write point.

[0006] These and other aspects of the present disclosure are disclosed in the following detailed description of implementations, the appended claims and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The description herein makes reference to the accompanying drawings described below, wherein like reference numerals refer to like components throughout the several views.

[0008] Figure 1 is a schematic diagram of an example of a video encoding and decoding system.

[0009] Figure 2 is a block diagram of an example of a computing device that may implement a transmitting station or a receiving station.

[0010] Figure 3 is a diagram of an example of a video stream that will be encoded and then decoded.

[0011] Figure 4 is a block diagram of an example of an encoder according to an implementation of the present disclosure.

[0012] Figure 5 is a block diagram of an example of a decoder according to an implementation of the present disclosure.

[0013] Figure 6 is a block diagram of an example of a video frame filtering stage according to an implementation of the present disclosure.

[0014] Figure 7is a diagram of an example of a processing unit used to filter a video frame.

[0015] Figure 8 is a flow diagram of an example of a technique for performing filtering using a processing unit for a video frame and an allocated buffer for the processing unit.

[0016] Fig. 9 is a flow diagram of an example of a technique for copying and writing pixel values ​​based on write points for a video frame. DETAILED DESCRIPTION

[0017] Video compression schemes may include decomposing the corresponding images or frames of an input video stream into smaller parts, such as blocks, and generating a bitstream using techniques that limit the information included in the corresponding blocks in the output. The compressed bitstream may be decoded to recreate the source image based on limited information. The video compression techniques performed by a typical encoder include downgrading the input video stream to reduce the data size when encoded as a bitstream. For example, lossy operations performed during the prediction, transformation, and / or quantization stages of the encoder may remove certain video data from the input video stream while retaining other video data, which is later used by a decoder to reconstruct the compressed bitstream into an output video stream. Those lossy operations may result in introducing undesirable block artifacts within the coded frame.

[0018] The encoder and decoder may also perform operations for filtering the video frames, such as after the video frames are reconstructed (e.g., within a reconstruction loop at the encoder or before output at the decoder). For example, filtering may be performed to process the reconstructed video frames for use as reference frames. The reference frames may then be used to predict subsequent video frames of the input video stream or bitstream. Depending on the particular codec used to encode and decode the video frames, filtering may be performed using one of a variety of different tools. For example, in the AV1 codec, filtering may be performed using a loop recovery tool.

[0019] Loop recovery includes dividing the video frame into processing units. A processing unit is a square fragment of a video frame of size 64x64, 128x128 or 256x256. However, affected by the ability of the codec performing loop recovery, the processing unit can alternatively have different shapes and / or different sizes. During loop recovery, filtering techniques are used to recover the video data degraded from some or all processing units. Filtering techniques that can be used for loop recovery tools can include Wiener filters (e.g., separable symmetric normalized Wiener filters), self-guided filters (e.g., dual self-guided filters), or another filter.

[0020] However, filtering techniques performed using a loop recovery tool or another tool that can be used in an encoder or decoder typically use a large amount of computing resources, such as memory. For example, in a typical loop recovery method, processing units often overlap within a video frame, resulting in the use of multiple processing units to process some pixels within a video frame. Assuming that each processing unit is used to perform filtering on pre-filtered pixel values ​​rather than already filtered pixel values, overlapping areas of video frames introduce potential processing conflicts.

[0021] Typical loop recovery methods resolve this conflict by copying the pre-filtered video frame to an additional video frame buffer. After the entire video frame has been filtered, the entire video frame is written from the additional video frame buffer, such as for display or storage. However, allocating an additional buffer for storing the entire video frame is an inefficient use of memory resources, because the encoder or decoder essentially needs to maintain two complete copies of the video data for the video frame.

[0022] The implementation of the present disclosure solves problems such as memory efficient filtering methods are used to encode images and videos. A buffer of a fixed size is allocated, the fixed size being based on the size of a processing unit used to filter a video frame. For each of the processing units, based on a write point for the video frame and an offset applied to the write point, pre-filtered pixel values ​​are copied from a corresponding area of ​​the video frame to the buffer, filtering is performed on the pre-filtered pixel values ​​from the buffer to generate filtered pixel values, and the filtered pixel values ​​are written to the video frame based on the write point and the offset.

[0023] The filtering can be performed using a loop recovery tool, such as where pre-filtered pixel values ​​are output from a constrained directional enhancement filter (CDEF) tool. Alternatively, the filtering can be performed using a CDEF tool or another coding tool. Therefore, the memory efficient filtering method disclosed herein can represent the operations performed in the filtering stage of an image or video coding process. Thus, the memory efficient filtering method disclosed herein can be used for encoding and / or decoding processes for image and / or video data.

[0024] The fixed size buffer and write point offset introduced by the implementation of the present disclosure improve the encoding and decoding performance for images and videos, and thus introduce improvements to image and video coding technology. Specifically, the use of fixed size buffers and write point offsets reduces the additional memory resource usage of filtering tools to the use of a single processing unit, rather than the use of an entire video frame. Further, the use of write point offsets to indicate the location of processing units reduces or prevents the occurrence of processing units overlapping each other in a video frame.

[0025] Further details of techniques for memory efficient filtering methods for image and video coding are described herein, with initial reference to systems in which they may be implemented. Figure 1 1 is a schematic diagram of an example of a video encoding and decoding system 100. The transmission station 102 may be, for example, an internal configuration having hardware (such as Figure 2 However, other implementations of the sending station 102 are possible. For example, the processing of the sending station 102 may be distributed among multiple devices.

[0026] The network 104 can connect the sending station 102 and the receiving station 106 for encoding and decoding of the video stream. Specifically, the video stream can be encoded in the sending station 102, and the encoded video stream can be decoded in the receiving station 106. The network 104 can be, for example, the Internet. The network 104 can also be a local area network (LAN), a wide area network (WAN), a virtual private network (VPN), a cellular phone network, or any other component that transmits the video stream from the sending station 102 to the receiving station 106 in this example.

[0027] In one example, the receiving station 106 may be an internal configuration having hardware (such as Figure 2 However, other suitable implementations of the receiving station 106 are possible. For example, the processing of the receiving station 106 may be distributed among multiple devices.

[0028] Other implementations of the video encoding and decoding system 100 are possible. For example, an implementation may omit the network 104. In another implementation, the video stream may be encoded and then stored for later transmission to a receiving station 106 or any other device with a memory. In one implementation, the receiving station 106 receives (e.g., via the network 104, a computer bus, and / or some communication path) the encoded video stream and stores the video stream for later decoding. In an example implementation, a real-time transport protocol (RTP) is used to transmit the encoded video over the network 104. In another implementation, a transport protocol other than RTP may be used, such as a video streaming protocol based on the hypertext transfer protocol (HTTP).

[0029] For example, when used in a video conferencing system, the sending station 102 and / or the receiving station 106 may include the ability to both encode and decode video streams as described below. For example, the receiving station 106 may be a video conference participant that receives an encoded video bitstream from a video conferencing server (e.g., the sending station 102) for decoding and viewing and further encodes his or her own video bitstream and sends it to the video conferencing server for decoding and viewing by other participants.

[0030] In some implementations, the video encoding and decoding system 100 may alternatively be used to encode and decode data other than video data. For example, the video encoding and decoding system 100 may be used to process image data. The image data may include data blocks from an image. In such an implementation, the sending station 102 may be used to encode the image data and the receiving station 106 may be used to decode the image data.

[0031] Alternatively, receiving station 106 may represent a computing device that stores encoded image data for later use, such as after receiving the encoded or pre-encoded image data from sending station 102. As a further alternative, sending station 102 may represent a computing device that decodes image data, such as before sending the decoded image data to receiving station 106 for display.

[0032] Figure 2 is a block diagram of an example of a computing device 200 that may implement a transmitting station or a receiving station. For example, the computing device 200 may implement Figure 1 The computing device 200 may be in the form of a computing system including a plurality of computing devices, or in the form of a computing device, such as a mobile phone, a tablet computer, a laptop computer, a notebook computer, a desktop computer, etc.

[0033] The processor 202 in the computing device 200 may be a conventional central processing unit. Alternatively, the processor 202 may be another type of device or devices capable of manipulating or processing information now existing or later developed. For example, although the disclosed implementations may be practiced with one processor (e.g., the processor 202) as shown, advantages in speed and efficiency may be realized by using more than one processor.

[0034] In an implementation, the memory 204 in the computing device 200 may be a read-only memory (ROM) device or a random access memory (RAM) device. However, other suitable types of storage devices may be used as the memory 204. The memory 204 may include code and data 206 accessed by the processor 202 using a bus 212. The memory 204 may also include an operating system 208 and application programs 210, which include at least one program that permits the processor 202 to perform the techniques described herein. For example, the application programs 210 may include applications 1 to N, which may also include a video and / or image coding application that performs the techniques described herein.

[0035] The computing device 200 may also include an auxiliary storage device 214, which may be, for example, a memory card used with a mobile computing device. Because a video communication session may contain a large amount of information, they may be stored in full or in part in the auxiliary storage device 214 and loaded into the memory 204 as needed for processing.

[0036] The computing device 200 may also include one or more output devices, such as a display 218. In one example, the display 218 may be a touch-sensitive display that combines a display with a touch-sensitive element operable to sense touch input. The display 218 may be coupled to the processor 202 via the bus 212. In addition to or in lieu of the display 218, other output devices may be provided that permit a user to program or otherwise use the computing device 200. When the output device is or includes a display, the display may be implemented in various ways, including by a liquid crystal display (LCD), a cathode ray tube (CRT) display, or a light emitting diode (LED) display, such as an organic LED (OLED) display.

[0037] The computing device 200 may also include or communicate with an image sensing device 220 (e.g., a camera) or any other image sensing device 220 now existing or later developed that can sense an image, such as an image of a user operating the computing device 200. The image sensing device 220 may be positioned so that it is pointed at the user operating the computing device 200. In an example, the orientation and optical axis of the image sensing device 220 may be configured so that the field of view includes an area directly adjacent to the display 218 and from which the display 218 is visible.

[0038] The computing device 200 may also include or communicate with a sound sensing device 222 (e.g., a microphone) or any other sound sensing device now existing or later developed that can sense sounds near the computing device 200. The sound sensing device 222 may be positioned so that it is directed toward a user operating the computing device 200, and may be configured to receive sounds, such as voice or other utterances, made by the user while the user is operating the computing device 200.

[0039] although Figure 2 The processor 202 and memory 204 of the computing device 200 are depicted as being integrated into one unit, but other configurations may be utilized. The operations of the processor 202 may be distributed across multiple machines (where individual machines may have one or more processors), which may be coupled directly or across a local area network or other network. The memory 204 may be distributed across multiple machines, such as network-based storage or storage in multiple machines that perform the operations of the computing device 200.

[0040] Although depicted here as one bus, the bus 212 of the computing device 200 may be comprised of multiple buses. Further, the secondary storage device 214 may be directly coupled to other components of the computing device 200 or may be accessible via a network and may include an integrated unit (such as a memory card) or multiple units (such as multiple memory cards). The computing device 200 may therefore be implemented in a variety of configurations.

[0041] Figure 3 is a diagram of an example of a video stream 300 to be encoded and subsequently decoded. Video stream 300 includes a video sequence 302. At the next level, video sequence 302 includes a plurality of adjacent frames 304. Although three frames are depicted as adjacent frames 304, video sequence 302 may include any number of adjacent frames 304. Adjacent frames 304 may then be further subdivided into individual frames, such as frame 306.

[0042] At the next level, frame 306 can be divided into a series of planes or fragments 308. For example, fragments 308 can be subsets of frames that allow parallel processing. Fragments 308 can also be subsets of frames that can separate video data into separate colors. For example, a frame 306 of color video data can include a luminance plane and two chrominance planes. Fragments 308 can be sampled at different resolutions.

[0043] Regardless of whether the frame 306 is divided into segments 308, the frame 306 may also be subdivided into blocks 310, which may contain data corresponding to, for example, 16x16 pixels in the frame 306. The blocks 310 may also be arranged to include data from one or more pixel data segments 308. The blocks 310 may also be any other suitable size, such as 4x4 pixels, 8x8 pixels, 16x8 pixels, 8x16 pixels, 16x16 pixels, or larger. Unless otherwise specified, the terms block and macroblock may be used interchangeably herein.

[0044] Figure 4 4 is a block diagram of an example of encoder 400. As described above, encoder 400 may be implemented in transmission station 102, such as by providing a computer software program stored in a memory (e.g., memory 204). The computer software program may include machine instructions that, when executed by a processor (such as processor 202), cause transmission station 102 to generate a signal in a manner that is consistent with the present invention. Figure 4 The video data is encoded in the manner described in . The encoder 400 may also be implemented as dedicated hardware included in the sending station 102, for example. In a particularly desirable implementation, the encoder 400 is a hardware encoder.

[0045] The encoder 400 has the following stages to perform various functions in a forward path (shown by solid connecting lines) to produce an encoded or compressed bitstream 420 using the video stream 300 as input: an intra / inter prediction stage 402, a transform stage 404, a quantization stage 406, and an entropy coding stage 408. The encoder 400 may also include a reconstruction path (shown by a dashed connecting line) to reconstruct frames for encoding future blocks. Figure 4 In FIG. 4 , the encoder 400 has the following stages to perform various functions in the reconstruction path: a dequantization stage 410 , an inverse transform stage 412 , a reconstruction stage 414 , and a loop filter stage 416 . Other structural variations of the encoder 400 may be used to encode the video stream 300 .

[0046] When the video stream 300 is presented for encoding, the corresponding adjacent frames 304, such as frame 306, may be processed in units of blocks. In the intra / inter prediction stage 402, the corresponding blocks may be encoded using intra prediction (also referred to as intra prediction) or inter prediction (also referred to as inter prediction). In either case, a prediction block may be formed. In the case of intra prediction, the prediction block may be formed from samples in the current frame that have been previously encoded and reconstructed. In the case of inter prediction, the prediction block may be formed from samples in one or more previously constructed reference frames.

[0047] Next, the prediction block can be subtracted from the current block in the intra / inter prediction stage 402 to produce a residual block (also referred to as a residual). The transform stage 404 transforms the residual into transform coefficients in, for example, the frequency domain using a block-based transform. The quantization stage 406 converts the transform coefficients into discrete quantum values, which are referred to as quantized transform coefficients, using a quantizer value or quantization level. For example, the transform coefficients can be divided by a quantizer value and truncated.

[0048] The quantized transform coefficients are then entropy encoded by an entropy encoding stage 408. The entropy encoded coefficients are then output to a compressed bitstream 420 along with other information used to decode the block (which may include, for example, syntax elements such as those used to indicate the prediction type used, the transform type, motion vectors, quantizer values, etc.). The compressed bitstream 420 may be formatted using various techniques such as variable length coding (VLC) or arithmetic coding. The compressed bitstream 420 may also be referred to as a coded video stream or a coded video bitstream, and the terms will be used interchangeably herein.

[0049] The reconstruction path (shown by the dashed connecting line) can be used to ensure that the encoder 400 and the decoder 500 (described below) Figure 5 The reconstruction path performs the same operation as in the decoding process (described below). Figure 54 and 5. The functions similar to those occurring during the quantization phase 410 and quantization phase 412 include dequantizing the quantized transform coefficients and inverse transforming the dequantized transform coefficients at the inverse transform phase 412 to produce a derivative residual block (also referred to as derivative residual).

[0050] In the reconstruction stage 414, the prediction block predicted in the intra / inter prediction stage 402 can be added to the derivative residual to create a reconstructed block. The loop filtering stage 416 can apply a loop filter or other filter to the reconstructed block to reduce distortion, such as blocking artifacts. Examples of filters that can be applied in the loop filtering stage 416 include, but are not limited to: a deblocking filter as in AVC, VP9, ​​High Efficiency Video Coding (HEVC), and AV1; a CDEF as in AV1; a super-resolution filter as in AV1; and a loop recovery filter as in AV1.

[0051] Other variations of the encoder 400 may be used to encode the compressed bitstream 420. In some implementations, a non-transform based encoder may directly quantize the residual signal without a transform stage 404 for certain blocks or frames. In some implementations, the encoder may have a quantization stage 406 and a dequantization stage 410 combined in a common stage.

[0052] Figure 5 5 is a block diagram of an example of a decoder 500. The decoder 500 may be implemented in the receiving station 106, for example, by providing a computer software program stored in the memory 204. The computer software program may include machine instructions that, when executed by a processor (such as the processor 202), cause the receiving station 106 to receive the received signal in a manner that is consistent with the received signal. Figure 5 The decoder 500 may also be implemented in hardware included in the sending station 102 or the receiving station 106, for example.

[0053] The decoder 500 (similar to the reconstruction path of the encoder 400 discussed above) includes the following stages in one example to perform various functions to produce an output video stream 516 from the compressed bitstream 420: an entropy decoding stage 502, a dequantization stage 504, an inverse transform stage 506, an intra / inter prediction stage 508, a reconstruction stage 510, a loop filtering stage 512, and a post filter stage 514. Other structural variations of the decoder 500 may be used to decode the compressed bitstream 420.

[0054] When the compressed bitstream 420 is presented for decoding, the data elements within the compressed bitstream 420 may be decoded by an entropy decoding stage 502 to produce a set of quantized transform coefficients. A dequantization stage 504 dequantizes the quantized transform coefficients (e.g., by multiplying the quantized transform coefficients by a quantizer value), and an inverse transform stage 506 inverse transforms the dequantized transform coefficients to produce derivative residuals that may be the same as the derivative residuals created by the inverse transform stage 412 in the encoder 400. Using the header information decoded from the compressed bitstream 420, the decoder 500 may use an intra / inter prediction stage 508 to create the same prediction blocks as were created in the encoder 400 (e.g., in the intra / inter prediction stage 402).

[0055] In the reconstruction stage 510, the prediction block may be added to the derivative residual to create a reconstructed block. The loop filtering stage 512 may apply an in-loop filter or other filter to the reconstructed block to reduce distortion, such as blocking artifacts. Examples of filters that may be applied in the loop filtering stage 512 include, but are not limited to: a deblocking filter as in AVC, VP9, ​​HEVC, and AV1; a CDEF as in AV1; a super-resolution filter as in AV1; and a loop restoration filter as in AV1.

[0056] Other filtering may also be applied to the reconstructed blocks. In this example, a post-filter stage 514 is applied to the reconstructed blocks to reduce block distortion, and the result is output as an output video stream 516. The output video stream 516 may also be referred to as a decoded video stream, and the terms will be used interchangeably herein.

[0057] Other variations of the decoder 500 may be used to decode the compressed bitstream 420. In some implementations, the decoder 500 may produce the output video stream 516 without the post-filter stage 514.

[0058] Figure 6 6 is a block diagram of an example of a video frame filtering stage 600 according to an implementation of the present disclosure. The video frame filtering stage 600 performs filtering on a video frame 602 to prepare the video frame 602 for display or storage. During encoding, the video frame filtering stage 600 may be Figure 4 The video frame filtering stage 600 may be a stage that performs some but not all of the operations performed in the loop filtering stage 416 of the encoder 400 shown in FIG. 6 . During decoding, the video frame filtering stage 600 may be a stage that performs some but not all of the operations performed in the loop filtering stage 416. Figure 55 or a stage that performs some but not all of the operations performed in the loop filtering stage 512 of the decoder 500 shown in FIG. 6 . Thus, the video frame filtering stage 600 may represent, for example, the functionality of a loop recovery tool of an encoder or decoder, the functionality of a CDEF tool of an encoder or decoder, or the functionality of another filtering tool of an encoder or decoder.

[0059] The video frame 602 is a video frame output from the reconstruction stage 604. For example, the reconstruction stage 604 may be the reconstruction stage 414 of the encoder 400, or the reconstruction stage 604 may be the illustrated reconstruction stage 510 of the decoder 500. After filtering at the video frame filtering stage 600, the video frame 602 is sent as an output for display or storage 606. The display or storage 606 may represent an operation for storing the filtered video frame 602 in a reference frame buffer of the encoder 400 or the decoder 500. Alternatively, the display or storage 606 may represent an operation for outputting the filtered video frame 602 within an output video stream for display at a device receiving the output video stream.

[0060] The video frame filtering stage 600 receives a video frame 602 after the video frame is output from the reconstruction stage 604 and prepares the video frame 602 for sending as output for display or storage 606. The video frame filtering stage 600 includes a pixel copy stage 608, a filtering stage 610, and a filtered pixel write stage 612. The video frame filtering stage 600 uses a buffer 614 to store the portion of the video frame 602 to be filtered.

[0061] The video frame filtering stage 600 processes individual regions of the video frame 602 one at a time using processing units. As previously described, a processing unit is a coded structure of size MxN, where M and N can be the same or different numbers. The size of the processing unit can be based on the size of the largest block within the video frame 602. For example, if the largest block within the video frame 602 is 128x128, then the size of the processing unit used by the video frame filtering stage 600 can be 128x128 or larger.

[0062] The shape of the processing unit is usually square. However, since the size of the processing unit can be MxN, the shape of the processing unit can be square or rectangular. The processing units usually have the same size and shape. However, in some cases, the processing unit can be variable-sized and / or variable-shaped. For example, a processing unit partitioning scheme of variable size and / or variable shape can be used to divide the video frame 602 into multiple processing units.

[0063] Each processing unit includes pixel values ​​from a region of the video frame 602. Each pixel value of the video frame is included in a single processing unit. In this way, the video frame filtering stage 600 filters each pixel value of the video frame 602 by processing each processing unit. The video frame filtering stage 600 processes the processing units sequentially one at a time. The order in which the processing units are processed at the video frame filtering stage 600 can depend on the scanning order or other order for encoding or decoding of the video frame 602. For example, in the case of using a raster order, the video frame filtering stage 600 first processes the processing unit including the upper leftmost pixel value of the video frame 602.

[0064] For each processing unit, the video frame filtering stage 600 performs operations, beginning at the pixel copy stage 608, and then ending at the filtering stage 610 and the filtered pixel write stage 612. First, the pixel copy stage 608 copies the pre-filtered pixel values ​​from the region of the video frame 602 corresponding to the current processing unit into the buffer 614. Next, the filtering stage 610 performs filtering on the pre-filtered pixel values ​​within the buffer 614 to produce filtered pixel values. Finally, the filtered pixel write stage 612 writes the filtered pixel values ​​back to the region of the video frame 702 from which the corresponding pre-filtered pixel values ​​were copied.

[0065] The specific technique for filtering performed on the pre-filtered pixel values ​​at filtering stage 610 is based on the one or more filtering tools used to perform the filtering. For example, where the filtering at filtering stage 610 is performed using a loop recovery tool of an encoder (e.g., encoder 400) or a decoder (e.g., decoder 500), filtering stage 610 may use one or more filtering techniques to recover video data previously degraded from video frame 602.

[0066] For example, filtering techniques that can be used to restore video data previously degraded from video frame 602 can include a Wiener filter (e.g., a separable symmetric normalized Wiener filter), a dual self-guided filter, another filter, or a combination thereof. The Wiener filter can be an MxN filter (where M and N can be the same or different numbers), the parameters of which for each horizontal and vertical filter (e.g., in the bitstream) are signaled. The dual self-guided filter can be an MxN filter (where M and N can be the same or different numbers), the noise parameters of which are signaled and the output of one or more such filters is weighted.

[0067] The filtering stage 610 is not limited to using a loop recovery tool to perform filtering. In some implementations, the filtering stage 610 can use a CDEF tool of an encoder or decoder to perform filtering. In some implementations, another filtering tool used for encoding or decoding can be used by the filtering stage 610 to perform filtering on the pre-filtered pixel values ​​for the corresponding processing unit.

[0068] Buffer 614 is allocated to have a fixed size based on the size of the processing unit used to perform filtering at filtering stage 610. Specifically, the size of buffer 614 is based on the extension area of ​​the processing unit. The extension area of ​​the processing unit refers to the processing unit and a number of pixels extending from the boundary of the processing unit on one or more sides of the processing unit. As such, the extension area and therefore the fixed size of the buffer is based on the filtering technique performed at filtering stage 610.

[0069] The extended area of ​​the processing unit is introduced for use at the filtering stage 610. Certain filtering techniques that may be performed at the filtering stage 610 may require or otherwise use a number of pixels that exceeds the size of the processing unit. Therefore, the extended area of ​​the processing unit accommodates the size requirements for the filtering technique.

[0070] In some implementations, the Wiener filter may need to be expanded by 3 pixels on each side of the processing unit. Thus, in the case where the size of the processing unit is 64x64 and the filtering stage 610 performs loop recovery using the Wiener filter, the size of the buffer 614 is fixed to store data for a 67x67 region of the video frame 602. In some implementations, the self-guided filter may need to be expanded by 1 pixel on each side of the processing unit. Thus, in the case where the size of the processing unit is 64x64 and the filtering stage 610 performs loop recovery using the self-guided filter, the size of the buffer 614 is fixed to store data for a 65x65 region of the video frame 602.

[0071] The extended frame boundary is used to enable an extended region of the processing unit. The extended frame boundary is a boundary that surrounds the video frame 602 and includes a number of pixels extended from the boundary of the video frame 602. Therefore, the extended frame boundary represents the size of the video frame 602, wherein a number of pixels are extended from each side of the boundary of the video frame 602.

[0072] The size of the extended frame boundary is based on the resolution of the video frame 602. The extended frame boundary is used to align the video frame 602 with other video frames of the input video stream or bitstream based on the resolution indicated for displaying the video frame 602 and those other video frames, as appropriate. For example, each resolution (e.g., 720p, 1080p, 2K, 4K, or other resolution) can use a specific frame size for displaying the video frame. In the case where the size of the video frame 602 during encoding or decoding is not a specific frame size for the resolution at which the video frame 602 is displayed, an extended frame boundary is introduced to change the effective size of the video frame 602 to a specific frame size for the resolution.

[0073] Video frame 602 and other video frames in the same input video stream or bitstream are aligned with half the size of those video frames. For example, if the size of those video frames corresponds to 4K resolution, the alignment is based on the size of 2K resolution. Usually, each video frame in the input video stream or bitstream has the same alignment because they are set to be displayed with the same resolution. However, in some cases, some video frames may have different alignments. For example, in the case where the user of the video streaming platform chooses to change the resolution of the video stream while the video is streaming, the video frame displayed after the resolution change may be aligned differently from the video frame displayed before the resolution change.

[0074] In at least some cases, the alignment may correspond to the maximum pixel extension required or used by the filtering technique performed at filtering stage 610. For example, if the maximum pixel extension for a filtering technique is 3 pixels, then the alignment may also be by 3 pixels to support each possible filtering technique used at filtering stage 610.

[0075] The extended frame boundary defines the location of the region corresponding to the processing unit for the video frame 602. To illustrate this point, now refer to Figure 7 . Figure 7 is a diagram of an example of a processing unit used to filter a video frame 700, which may be, for example, Figure 6 602 shown in FIG. 600. As shown, the video frame 700 is divided into 16 regions of equal size. Each of those regions includes a plurality of pixel values, and each of those regions corresponds to a processing unit. For reference, the size of such a processing unit is shown at 702. Figure 7 The example described herein refers to a processing unit size shown at 702 as 64x64; however, other processing unit sizes may be used to filter the video frame 700.

[0076] The starting point 704 of the video frame 700 indicates the location of the first pixel to be filtered (eg, using a loop recovery tool, a CDEF tool, or another filtering tool). In the case where the filtering follows a raster order, the starting point 704 is the upper leftmost pixel of the video frame 700, such as Figure 7 Alternatively, where the filtering follows an order that does not begin at the upper left corner of the video frame 700 , the starting point 704 may be located elsewhere around the video frame 700 .

[0077] Extended frame border 706 encompasses video frame 700 and extends an additional number of pixels on one or more sides of video frame 700. Figure 7As shown in FIG. 7 , the extended frame boundary 706 includes additional pixels extended on all four sides of the video frame 700. The extended frame boundary 706 also defines a write point 708 that allows for alignment of the video frame 700. The write point 708 indicates the starting position of the extended region for the first processing unit 710. Figure 7 As shown in FIG. 7 , written point 708 is positioned at the upper leftmost position of extended frame boundary 706. Thus, written point 708 represents a position extending beyond the original boundary of video frame 700.

[0078] While the size of the first processing unit is 64x64 (i.e., the size of the processing unit shown at 702), the size of the expansion area of ​​the first processing unit 710 is 64+Mx64+N, where M and N represent the expansion area of ​​the processing unit based on the resolution used to display the video frame 700, the requirements of the filtering technology to be used to filter the video frame, or both. For example, the expansion area of ​​the first processing unit 710 may be 64+3x64+3 or 67x67.

[0079] The first processing unit is used to filter a region of the video frame 700 starting at the starting point 704. For example, the pixel positions throughout the video frame 700 can be considered as a two-dimensional grid, such as having an X-axis and a Y-axis. In the case where the extended frame boundary 706 extends the size of the video frame 700 by 3 pixels on each side, the write point 708 will be located at (-3,-3). The extended region of the first processing unit 710 extends from (0-3,0-3) to (64+3,64+3) or from (-3,-3) to (67,67). The starting point 704 will be located at (0,0) so that the first region filtered for the first processing unit starts at (0,0). The size of this first region is the same as the size of the first processing unit, and therefore extends from (0,0) to (64,64).

[0080] The first region corresponding to the first processing unit is shown as a first filter block 712 after filtering. While the pixel values ​​for the first region are pre-filtered pixel values ​​before filtering, the pixel values ​​after filtering are filtered pixel values. After being filtered, the pixel values ​​of the video frame 700 are shifted toward the write point 708. For example, the pre-filtered pixel values ​​for the first region are located in the video frame 700 starting at the start point 704; however, the filtered pixel values ​​of the first filter block 712 are shifted at the write point 708 and written to the video frame 700.

[0081] The extended region of the second processing unit 714 is shown next to the extended region of the first processing unit 710. After the first filter block 712 is written to the video frame 700, the second processing unit is used to filter the next region of the video frame 700. The location of the next region of the video frame 700 corresponding to the next (e.g., second) processing unit is indicated based on the offset applied to the write point 708.

[0082] The offset specifies the distance from the write point 708 based on a number of processing units for which filtering has been performed. Here, since filtering has been performed for one processing unit, the offset applied to the write point 708 indicates where to start the second processing unit based on where the first filter block 712 ends within the video frame 700. Thus, the offset for the second processing unit indicates that the second processing unit starts at a location of 64+3 or 67 pixels from the write point 708. Referring back to the two-dimensional grid described above, the second processing unit will extend from (64,0) to (128,64), and the extension area of ​​the second processing unit 714 will extend from (64-3,0-3) to (128+3,64+3) or from (61,-3) to (131,67).

[0083] The area corresponding to the second processing unit is shown after filtering as a second filter block 716. Similar to how the filtered pixel values ​​of the first filter block 712 are shifted toward the write point 708, the filtered pixel values ​​of the second filter block 716 are shifted and written to the video frame 700 after the first filter block 712. The location where the filtered pixel values ​​of the second filter block 716 are written can be determined based on the offset applied to the write point 708. For example, the offset can indicate that the second filter block 716 will be written to the video frame 700 at a location 67-3 or 64 pixels away from the write point 708.

[0084] After the second filter block 716 is written, the offset applied to the write point 708 for the third processing unit is determined. Here, since filtering has been performed for two processing units, the offset applied to the write point 708 will indicate where to start the third processing unit based on where the second filter block 716 ends within the video frame 700.

[0085] Thus, the offset for the third processing unit will indicate that the third processing unit begins at a location of 128+3 or 131 pixels from the write point 708. Referring back to the two-dimensional grid described above, the third processing unit will extend from (128,0) to (192,64), and the extension area of ​​the third processing unit (not shown) will extend from (128-3,0-3) to (192+3,64+3) or from (125,-3) to (195,67).

[0086] Figure 7The processing unit illustrated in FIG. 7 is specifically shown by way of example as a processing unit used for loop recovery of video frame 700. However, other variations of the processing unit may be used. For example, a processing unit used for filtering by a CDEF tool may have the same Figure 7 The different forms or structures shown in .

[0087] Return to reference Figure 6 , for the first processing unit, the pixel copy stage 608 begins copying the pre-filtered pixel values ​​from the video frame 602 to the buffer 614 at the starting point of the video frame 602. The buffered pre-filtered pixel values ​​are then filtered at the filtering stage 610, for example, based on an extension area of ​​the first processing unit, the location of which is determined based on an offset applied to the write point for the video frame 602 (for example, the offset here is 0 because the processing unit has not yet been processed).

[0088] The filtered pixel values ​​output from the filtering stage 610 are then written into the video frame 602 at the filtering pixel writing stage 612. The position within the video frame 602 at which the filtered pixel values ​​for the first processing unit are written is determined based on a shift from the starting position of the processing unit (e.g., the starting position is here the starting point of the video frame 602, since the processing unit has not yet been processed) to the writing point. In particular, since this is the first processing unit, the filtering pixel writing stage 612 begins writing the filtered pixel values ​​into the video frame 602 at the writing point.

[0089] Next, for the second processing unit, the pixel copy stage 608 copies the pre-filtered pixel values ​​from the video frame 602 to the buffer 614 starting at the position defined by the offset applied to the write point. Copying the second set of pre-filtered pixel values ​​to the buffer 614 may include first clearing the buffer 614 to make room for the second set of pre-filtered pixel values. Alternatively, copying the second set of pre-filtered pixel values ​​to the buffer 614 may include overwriting previous video data stored in the buffer 614.

[0090] The offset defining the location where the pre-filtered pixel values ​​for the second processing unit are to be copied specifies the distance from the write point and is based on the number of processing units for which filtering has been performed. Here, since filtering has been performed for one processing unit, the offset is equal to the size of the first processing unit in one dimension (e.g., horizontal direction) plus the difference between the start point and the write point along the same dimension.

[0091] The newly buffered pre-filtered pixel values ​​are filtered at the filtering stage 610 and then written back to the video frame 602 at the filtered pixel writing stage 612. The location within the video frame 602 where the filtered pixel values ​​for the second processing unit are written is determined based on an offset from the starting position of the processing unit to the write point. For example, the offset to the write point can be based on the difference between the starting point and the write point in two dimensions. For example, the starting point of the reference frame is located at (0,0) and the write point is located at a two-dimensional grid of (-M,-N), and the filtered pixel values ​​for the second processing unit are written to a location in the video frame 602 with the offset (-M,-N) applied to the write point.

[0092] This process is repeated for the remaining processing units until every pixel value of the video frame 602 has been processed at the video frame filtering stage 600, regardless of whether the pixel values ​​are changed by such processing. After the last processing unit is processed, the video frame 602 is output for display or storage 606.

[0093] The same write point is typically used for each video frame of the input video stream or bitstream. However, in some cases, different video frames of the input video stream or bitstream may use different write points. In some implementations that change the resolution of the video stream while streaming, the write point for the video frame displayed after the resolution change may be different from the write point for the video frame displayed before the resolution change. In some implementations, the encoder may support using information signaled within the bitstream to change the write point between video frames to indicate how to align the video frames, such as based on different resolutions for displaying the video.

[0094] Figure 6 Other variations of the video frame 602, the video frame filtering stage 600 and / or other aspects shown in are possible. In some implementations, the video frame 602 can be a video frame buffer, such as a reference frame buffer or other buffer, and the video frame is stored in the buffer for further use in the encoding or decoding process. For example, the reconstruction stage 604 can store the video frame in the video frame buffer. The video frame filtering stage 600 can then copy the pixels of the video frame from the video frame buffer and then write the filtered pixels of the video frame back to the video frame buffer. In this implementation, display or storage 606 may include an operation for finally determining the filtered video frame as a reference frame in the video frame buffer. Alternatively, in this implementation, display or storage 606 may be omitted.

[0095] In some implementations, the video frame filtering stage 600 can process more than one region of the video frame 602 simultaneously. For example, two or more processing units can be processed simultaneously to filter two or more corresponding regions of the video frame 602. In some implementations, the buffer 614 can include two or more memory allocations for storing pre-filtered pixel values ​​from the corresponding two or more processing units. In some implementations, the buffer 614 can be one of a plurality of buffers, each of which is allocated to store one of the two or more processing units. The filtering performed at the filtering stage 610 can be performed in parallel for each of the two or more processing units, such as using multithreading.

[0096] In some implementations, the size of the processing unit used by the video frame filtering stage 600 may not be based on the size of the largest block within the video frame 602. In some implementations, the size of the processing unit may be based on the configuration of the encoder or decoder using the video frame filtering stage 600. In some implementations, the size of the processing unit may be based on the non-block partitioning of the video frame 602. In some implementations, the size of the processing unit may be smaller than the size of the largest block within the video frame 602. In some implementations, the processing units may have different sizes and / or shapes from one another.

[0097] In some implementations, the size of the extended frame boundary is based on the filtering technique performed at the filtering stage 610 rather than the resolution of the video frame 602. In some implementations where the size of the video frame is MxN and the filtering stage 610 performs loop recovery using a Wiener filter, the extended frame boundary encompasses an M+3xN+3 region around the video frame 602. In some implementations where the size of the video frame is MxN and the filtering stage 610 performs loop recovery using a self-guided filter, the extended frame boundary encompasses an M+1xN+1 region around the video frame 602.

[0098] Further details of the techniques for a memory efficient filtering method for image and video coding are now described. Figure 8 is a flow diagram of an example of a technique 800 for performing filtering using a processing unit for a video frame and an allocated buffer for the processing unit. Fig. 9 is a flow diagram of an example of a technique 900 for copying and writing pixel values ​​based on write points for a video frame.

[0099] Technique 800 and / or technique 900 may be implemented as, for example, a software program that may be executed by a computing device, such as sending station 102 or receiving station 106. For example, the software program may include machine-readable instructions that may be stored in a memory, such as memory 204 or auxiliary storage device 214, and when executed by a processor, such as processor 202, may cause a computing device to perform technique 800 and / or technique 900. Technique 800 and / or technique 900 may be implemented using dedicated hardware or firmware. For example, hardware components are configured to perform technique 800 and / or technique 900. As explained above, some computing devices may have multiple memories or processors, and the operations described in technique 800 and / or technique 900 may be distributed using multiple processors, memories, or both.

[0100] For simplicity of explanation, technology 800 and technology 900 are depicted and described herein as a series of steps or operations. However, the steps or operations according to the present disclosure may occur in various orders and / or simultaneously. Additionally, other steps or operations not presented and described herein may be used. In addition, all illustrated steps or operations may not be required to implement the technology according to the disclosed subject matter.

[0101] First reference Figure 8 , a technique 800 for filtering performed using a processing unit for a video frame and a buffer allocated for the processing unit is shown. At 802, a fixed size buffer is allocated. Allocating the buffer includes creating or identifying free space in a memory for storing video data corresponding to the fixed size. The fixed size of the buffer is based on an extension area of ​​the processing unit. The extension area of ​​the processing unit refers to the processing unit and a number of pixels extending from the boundary of the processing unit on one or more sides of the processing unit. For example, in the case where the size of the processing unit is 64x64 and a 3-pixel extension is used, the buffer has a fixed size of 67x67.

[0102] At 804, pre-filtered pixel values ​​for the Nth processing unit are copied from the region of the video frame to a buffer. Copying the pre-filtered pixel values ​​for the Nth processing unit from the region of the video frame to the buffer includes identifying the pre-filtered pixel values ​​within the video frame based on an offset applied to a write point of the video frame. The write point represents a location that extends beyond a boundary of the video frame. The offset specifies a distance from the write point based on the number of processing units for which filtering has been performed.

[0103] For example, the write point can be identified by shifting the starting point of the video frame by a certain number of pixels. The starting point of the video frame represents the position of the first pre-filtered pixel value within the video frame according to the order for performing filtering for the processing unit. The number of pixels by which the starting point of the video frame is shifted is determined based on the resolution of the video frame. Shifting the starting point of the video frame to the write point includes determining an extended frame boundary of the video frame based on the resolution of the video frame. The extended boundary of the frame is defined by the number of pixels by which the starting point of the video frame is shifted.

[0104] The offset applied to the write point changes for each processing unit. This is because the offset for a processing unit indicates the location of the top leftmost bit of the processing unit within the extended boundaries of the video frame. For example, the offset for the first processing unit is zero so that the top leftmost bit of the first processing unit is positioned at the write point, while the offset for the second processing unit is based on the size of the first processing unit along at least one axis so that the top leftmost bit of the second processing unit is positioned one pixel above the top rightmost pixel of the first processing unit.

[0105] At 806, filtering is performed on the buffered pre-filtered pixel values ​​of the Nth processing unit. Performing filtering on the buffered pre-filtered pixel values ​​includes filtering those buffered pre-filtered pixel values ​​using a filtering tool available to an encoder or decoder performing technique 800. In some implementations, filtering may be performed using a loop recovery tool of a video decoder, such as where the pre-filtered pixel values ​​from the corresponding region of the video frame are pixel values ​​output from a CDEF filtering tool of the video decoder. In some implementations, filtering may be performed using a CDEF tool of a video decoder, such as where the pre-filtered pixel values ​​from the corresponding region of the video frame are pixel values ​​output from a deblocking filtering tool of the video decoder.

[0106] At 808, the filtered pixel values ​​for the Nth processing unit are written from the buffer to the video frame. The filtered pixel values ​​are written to the video frame at a position based on the write point and based on an offset applied to the write point for the Nth processing unit. Writing the filtered pixel values ​​for the Nth processing unit to the video frame includes shifting the position of a first pixel of the region from the video frame for the processing unit based on a difference between the start point and the write point. The first pixel of the region from the video frame for the processing unit is indicated by the offset.

[0107] At 810, it is determined whether the Nth processing unit is the last processing unit. At 812, in response to determining that the Nth processing unit is not the last processing unit, the value of N is increased by 1. Technique 800 then returns to 804, where the pre-filtered pixel values ​​for the new Nth processing unit are copied to the buffer. The operations performed at 804 to 810 repeat until the current Nth processing unit is the last processing unit. At 814, in response to determining that the Nth processing unit is the last processing unit, the video frame is output for display or storage.

[0108] In some implementations, technique 800 may include clearing the buffer. In some implementations, the buffer may be cleared after the filtered pixel values ​​for the Nth processing unit are written to the video frame and before the pre-filtered pixel values ​​for the next Nth processing unit are copied to the buffer. Clearing the buffer may, for example, include deleting video data stored in the buffer to free up space for the next set of video data. In some implementations, clearing the buffer may include enabling the next set of video data to overwrite the video data then stored in the buffer.

[0109] In some implementations, the filtered pixel values ​​are written to a frame buffer, such as a reference frame buffer, rather than a video frame. For example, a video frame may simply be a source of pre-filtered pixel values ​​and may not be written. Instead, the filtered pixel values ​​may be written directly to a reference frame buffer or other frame buffer. In such implementations, outputting a video frame for display or storage may simply include verifying that the filtered pixel values ​​for the last processing unit have been written to the reference frame buffer or other frame buffer.

[0110] In some implementations, technique 800 may include changing a head pointer of a frame buffer from a starting point of a video frame to a write point. For example, a frame buffer may be a reference frame buffer that is used to store reference frames for encoding or decoding further video frames. By default, the head pointer of a frame buffer may point to the starting point of a video frame because the starting point indicates the location of the first pixel of the video frame before filtering is performed. However, because the filtering area of ​​a video frame is shifted by filtering based on the write point, the head pointer of a frame buffer is changed for a video frame to indicate that the first pixel is positioned at the write point, rather than at the starting point.

[0111] Next reference Fig. 9 , a technique 900 for copying and writing pixel values ​​based on a write point for a video frame is shown. At 902, a write point for a video frame is identified. Identifying the write point includes determining an extended frame boundary. The extended frame boundary can be determined based on an alignment for the video frame, such as based on a resolution for the video frame. The write point represents a location of a first extended pixel value of the extended frame boundary.

[0112] At 904, a value for a first processing unit is copied to a buffer based on the write point. The value for the first processing unit is a pre-filtered pixel value from a first region of the video frame, the first region starting at a start point of the video frame, which may be, for example, the upper leftmost pixel position of the video frame. The buffer is a buffer of a fixed size for storing an extended region of a processing unit of a video frame.

[0113] At 906, filtering is performed on the buffered values ​​for the first processing unit. The filtering may include using one or more filtering tools available to an encoder or decoder performing technique 900. For example, the filtering may include using a loop recovery tool or a CDEF tool to change one or more pre-filtered pixel values ​​stored in the buffer.

[0114] At 908, the filtered values ​​for the first processing unit are written to the video frame. The filtered values ​​for the first processing unit are written to the video frame at the write point.

[0115] At 910, a value for a second processing unit is copied to a buffer based on the offset applied to the write point. The value for the second processing unit is a pre-filtered pixel value from a second region of the video frame. The second region of the video frame is identified based on the offset applied to the write point.

[0116] At 912, filtering is performed on the buffered values ​​for the second processing unit.The filtering of the values ​​for the second processing unit is performed using the same filtering tools that were previously used to filter the values ​​for the first processing unit.

[0117] At 914, the filtered values ​​for the second processing unit are written to the video frame. The filtered values ​​for the second processing unit are written to the video frame at a location defined based on the offset for the second processing unit.

[0118] At 916, the video frame is output for display or storage. In some implementations, the video frame can be output for display within an output video stream. In some implementations, the video frame can be output for storage, such as in a reference frame buffer.

[0119] In some implementations, technique 900 may include clearing the buffer. In some implementations, the buffer may be cleared after copying the filtered pixel values ​​for the first processing unit to the video frame and before copying the pre-filtered pixel values ​​for the second processing unit to the buffer. Clearing the buffer may, for example, include deleting video data stored in the buffer to free up space for the next set of video data. In some implementations, clearing the buffer may include enabling the next set of video data to overwrite the video data then stored in the buffer.

[0120] In some implementations, the filtered pixel values ​​are written to a frame buffer, such as a reference frame buffer, rather than a video frame. For example, a video frame may simply be a source of pre-filtered pixel values ​​and may not be written. Instead, the filtered pixel values ​​may be written directly to a reference frame buffer or other frame buffer. In such implementations, outputting a video frame for display or storage may simply include verifying that the filtered pixel values ​​for the last processing unit have been written to the reference frame buffer or other frame buffer.

[0121] In some implementations, technique 900 may include changing a head pointer of a frame buffer from a starting point of a video frame to a write point. For example, a frame buffer may be a reference frame buffer that is used to store reference frames for encoding or decoding further video frames. By default, the head pointer of a frame buffer may point to the starting point of a video frame because the starting point indicates the location of the first pixel of the video frame before filtering is performed. However, because the filtering area of ​​a video frame is shifted by filtering based on the write point, the head pointer of a frame buffer is changed for a video frame to indicate that the first pixel is positioned at the write point, rather than at the starting point.

[0122] The aspects of encoding and decoding described above illustrate some examples of encoding and decoding techniques. However, it should be understood that encoding and decoding (as used in the claims) can mean compression, decompression, transformation or any other data processing or change.

[0123] The word "example" is used herein to mean to be used as an example, instance or diagram. Any aspect or design described as "example" herein is not necessarily understood to be preferred or advantageous over other aspects or designs. On the contrary, the use of the word "example" is intended to specifically present the concept. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or otherwise clearly indicated by context, "X includes A or B" is intended to mean any natural inclusive arrangement. That is, if X includes A, X includes B or X includes both A and B, then "X includes A or B" is satisfied under any preceding example. Additionally, unless otherwise specified or clearly indicated by context to involve a singular form, the articles "one" and "an" used in the present application and the appended claims should be generally understood to mean "one or more". In addition, unless so described, the use of the term "implementation" or the term "an implementation" throughout the present disclosure is not intended to mean the same implementation.

[0124] The implementation of the sending station 102 and / or the receiving station 106 (and being stored thereon and / or by it, including the algorithms, methods, instructions, etc. executed by the encoder 400 and the decoder 500) can be implemented in hardware, software or any combination thereof. The hardware may include, for example, a computer, an intellectual property (IP) core, an application specific integrated circuit (ASIC), a programmable logic array, an optical processor, a programmable logic controller, a microcode, a microcontroller, a server, a microprocessor, a digital signal processor, or any other suitable circuit. In the claims, the term "processor" should be understood to cover any one of the aforementioned hardware individually or in combination. The terms "signal" and "data" are used interchangeably. Further, the parts of the sending station 102 and the receiving station 106 do not necessarily have to be implemented in the same manner.

[0125] Further, in one aspect, for example, the sending station 102 or the receiving station 106 can be implemented using a general purpose computer or general purpose processor with a computer program that, when executed, performs any of the corresponding methods, algorithms and / or instructions described herein. Additionally, or alternatively, for example, a special purpose computer / processor can be utilized, which can include other hardware for performing any of the methods, algorithms or instructions described herein.

[0126] The sending station 102 and the receiving station 106 can be implemented on a computer in a video conference system, for example. Alternatively, the sending station 102 can be implemented on a server, and the receiving station 106 can be implemented on a device (such as a handheld communication device) separated from the server. In this example, the sending station 102 can use an encoder 400 to encode the content into an encoded video signal and send the encoded video signal to the communication device. Then, the communication device can then use a decoder 500 to decode the encoded video signal. Alternatively, the communication device can decode the content (such as content not sent by the sending station 102) stored locally on the communication device. Other suitable sending and receiving implementations are available. For example, the receiving station 106 can be a generally fixed personal computer instead of a portable communication device, and / or the device including the encoder 400 can also include a decoder 500.

[0127] Further, all or part of the implementation of the present disclosure may take the form of a computer program product accessible from, for example, a computer usable or computer readable medium. A computer usable or computer readable medium may be, for example, any device that can tangibly contain, store, communicate, or transport a program for use by or in conjunction with any processor. The medium may be, for example, an electronic, magnetic, optical, electromagnetic, or semiconductor device. Other suitable media are also available.

[0128] The implementation and other aspects described above have been described to facilitate easy understanding of the present disclosure and are not intended to limit the present disclosure. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, and its scope should be given the broadest interpretation permitted by law to cover all such modifications and equivalent arrangements.

Claims

1. A method for filtering a video frame, the method comprising: allocating a buffer having a fixed size based on a size of a processing unit for filtering the video frame; The following operations are sequentially performed for each of the processing units: copying pre-filtered pixel values ​​from a corresponding region of the video frame to the buffer, wherein the corresponding region of the video frame is selected based on an offset applied to a write point of the video frame, wherein the write point represents a location that extends beyond a boundary of the video frame, wherein the offset specifies a distance from the write point based on a number of processing units that have performed filtering; performing filtering on the pre-filtered pixel values ​​in the buffer to generate filtered pixel values; as well as writing the filtered pixel value from the buffer to the video frame based on the write point and based on the offset; as well as After the filtered pixel values ​​are written to the video frame of each of the processing units, the video frame is output for display or storage.

2. The method according to claim 1, further comprising: The writing point is identified by shifting the starting point of the video frame by a certain number of pixels, wherein the starting point of the video frame represents the position of the first pre-filtered pixel value within the video frame according to the order in which the filtering is performed on the processing unit, wherein the number of pixels by which the starting point of the video frame is shifted is determined based on the resolution of the video frame. 3 . The method of claim 2 , wherein the offset of a processing unit indicates a top-leftmost position of a processing unit within an extended frame boundary of the video frame.

4. A method according to claim 3, wherein the offset of the first processing unit is zero so that the upper leftmost position of the first processing unit is positioned at the write point, and wherein the offset of the second processing unit is based on the size of the first processing unit along at least one axis so that the upper leftmost position of the second processing unit is positioned at a position one pixel above the upper rightmost pixel position of the first processing unit. 5 . The method of claim 3 , wherein the extended frame boundary of the video frame is defined by the number of pixels by which a starting point of the video frame is shifted.

6. The method according to any one of claims 1 to 5, wherein the video frame is stored in a frame buffer, wherein the buffer is different from the frame buffer, wherein writing the filtered pixel values ​​of the processing unit to the video frame based on the writing point and based on the offset comprises: Writing the filtered pixel values ​​of the processing unit to the frame buffer.

7. The method of claim 1, wherein the filtering is performed using a loop restoration tool of a video decoder, wherein the pre-filtered pixel values ​​from the corresponding region of the video frame are pixel values ​​output from a restricted direction enhancement filtering tool of the video decoder.

8. The method of claim 1, wherein the write points are used to filter subsequent video frames from a video sequence including the output video frame.

9. A device for filtering a video frame, the device comprising: a memory, wherein a first portion of the memory is allocated for storing instructions, wherein a second portion of the memory is allocated for a buffer having a fixed size based on a size of a processing unit used to filter the video frame; and A processor configured to execute the instructions for: A write point defined for the video frame, the write point representing a location extending beyond a boundary of the video frame; for a first processing unit, copying pre-filtered pixel values ​​from a first region of the video frame to the buffer, wherein a starting point of the first processing unit corresponds to the writing point; performing filtering on the buffered pre-filtered pixel values ​​of the first processing unit to generate first filtered pixel values; writing the first filtered pixel value from the buffer to the write point; for a second processing unit, copying pre-filtered pixel values ​​from a second region of the video frame to the buffer, wherein a starting point of the second processing unit corresponds to the offset applied to the write point; performing filtering on the buffered pre-filtered pixel values ​​of the second processing unit to generate second filtered pixel values; writing the second filtered pixel value from the buffer to the offset applied to the write point; and After the filtered pixel values ​​are written for all processing units, the video frame is output for display or storage.

10. The apparatus of claim 9, wherein an offset of the second processing unit specifies a distance from the write point based on a size of the first processing unit.

11. The apparatus according to claim 9 or 10, wherein the instructions include instructions for: The writing point is identified by shifting a starting point of the video frame by a certain number of pixels, wherein the starting point of the video frame represents a position of a first pre-filtered pixel value within the video frame according to an order in which the filtering is performed on the processing units.

12. The apparatus of claim 11, wherein a third portion of the memory is allocated for a frame buffer, wherein the buffer is distinct from the frame buffer, and wherein the instructions for writing the first filtered pixel value to the video frame comprise instructions for: Changing the head pointer of the frame buffer from the starting point of the video frame to the writing point; and The first filtered pixel value is written to the frame buffer at the write point. 13 . The apparatus of claim 11 , wherein the number of pixels by which the starting point of the video frame is shifted is determined based on a resolution of the video frame.

14. The apparatus of claim 9, wherein new write points are defined for filtering subsequent video frames of a video sequence including the video frame.

15. The apparatus of claim 9, wherein the instructions include instructions for: After writing the first filtered pixel values ​​to the video frame and before copying the pre-filtered pixel values ​​of the second processing unit to the buffer, the buffer is cleared.

16. A decoder for performing an operation of filtering a video frame, the operation comprising: Identify a writing point of the video frame by shifting the starting point of the video frame by a certain number of pixels, wherein the starting point of the video frame represents the upper leftmost position of the video frame; For a processing unit, copying pre-filtered pixel values ​​from a region of the video frame to a buffer having a fixed size, the fixed size being based on a size of the processing unit, wherein a position of the write point represents an upper leftmost position of the processing unit; performing filtering on the pre-filtered pixel values ​​from the buffer to produce filtered pixel values ​​for the processing unit; as well as Based on the write point, the filtered pixel values ​​of the processing unit are written from the buffer to the video frame.

17. The decoder of claim 16, wherein the processing unit is a first processing unit, the operations further comprising: for a second processing unit, copying pre-filtered pixel values ​​from a next region of the video frame to the buffer, wherein an upper leftmost bit of the second processing unit is based on an offset applied to the write point; performing filtering on the pre-filtered pixel values ​​of the second processing unit from the buffer to generate filtered pixel values ​​of the second processing unit; as well as Based on the writing point and based on the offset, the filtered pixel value of the second processing unit is written into the video frame.

18. The decoder of claim 17, wherein the offset from the write point specifies a distance from the write point based on a size of the first processing unit.

19. The decoder of claim 16, wherein the number of pixels by which the starting point of the video frame is shifted is determined based on a resolution of the video frame.

20. The decoder of any one of claims 16 to 19, wherein the video frame is stored in a frame buffer, wherein the buffer is different from the frame buffer, and wherein writing the filtered pixel values ​​of the processing unit to the video frame based on the write point comprises: Changing the head pointer of the frame buffer from the starting point of the video frame to the writing point; as well as The filtered pixel values ​​of the processing unit are written to the frame buffer at the write point.

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