Semiconductor device and method of forming the same

Abstract

The method includes depositing a first passivation layer over a conductive component, wherein the first passivation layer has a first dielectric constant; forming a capacitor over the first passivation layer; depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line electrically connected to the capacitor over the capacitor; depositing a third passivation layer over the redistribution line; and forming an under bump metal (UBM) that penetrates the third passivation layer to electrically connect to the redistribution line. Embodiments of the present application also relate to semiconductor devices and methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] In the formation of integrated circuits, integrated circuit devices such as transistors are formed at the surface of a semiconductor substrate in a wafer. Then, an interconnect structure is formed over the integrated circuit devices. Metal pads are formed over the interconnect structure and are electrically coupled to the interconnect structure. A passivation layer and a first polymer layer are formed over the metal pads, and the metal pads are exposed through openings in the passivation layer and the first polymer layer.

[0003] Then, redistribution lines may be formed to connect to the top surface of the metal pads, and a second polymer layer is subsequently formed over the redistribution lines. Under-bump metal (UBM) is formed to extend into an opening in the second polymer layer, wherein the UBM is electrically connected to the redistribution lines. Solder balls may be placed over the UBM and reflowed. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, including: depositing a first passivation layer over a conductive component, wherein the first passivation layer has a first dielectric constant; forming a capacitor over the first passivation layer; depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant; forming a redistribution line over the capacitor and electrically connected to the capacitor; depositing a third passivation layer over the redistribution line; and forming an under-bump metal (UBM) that penetrates the third passivation layer to electrically connect to the redistribution line.

[0005] Some other embodiments of the present application provide a semiconductor device, including: a conductive pad; a first passivation layer located over the conductive pad, wherein the first passivation layer includes a first dielectric material and the first passivation layer has a first dielectric constant; a second passivation layer located over the first passivation layer, wherein the second passivation layer has a second dielectric constant higher than the first dielectric constant; a capacitor sandwiched between the first passivation layer and the second passivation layer; a third passivation layer located over the second passivation layer; a first redistribution line that penetrates the second passivation layer to contact the top surface of a capacitor electrode of the capacitor; and a second redistribution line that penetrates both the second passivation layer and the first passivation layer to contact the conductive pad.

[0006] Some other embodiments of the present application provide a semiconductor device, including: a conductive component; a first etch stop layer located above and in contact with the conductive component; a first passivation layer located above the first etch stop layer, wherein the first passivation layer has a first porosity value; a capacitor located above the first passivation layer; a second etch stop layer located above the capacitor; a second passivation layer located above the second etch stop layer, wherein the second passivation layer has a second porosity value lower than the first porosity value; a first redistribution line penetrating the second passivation layer and the second etch stop layer to electrically connect to the capacitor; and a second redistribution line penetrating the second passivation layer, the first passivation layer, and the first etch stop layer to electrically connect to the conductive component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 15 A cross-sectional view showing an intermediate stage of the formation of a package according to some embodiments is shown.

[0009] Figure 16 A process flow for forming a device according to some embodiments is shown. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. Except for the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0012] Devices and methods of forming the same are provided in accordance with some embodiments. The device includes a capacitor, which may be a metal-insulator-metal (MIM) capacitor. The capacitor is formed above a first passivation layer and is covered by a second passivation layer. The first passivation layer has a lower k value than the second passivation layer. When etched using the same etch gas, the first passivation layer is etched faster than the second passivation layer, thereby reducing the loading effect during the etching process. Intermediate stages in the formation of a package are shown in accordance with some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to denote like elements throughout the various views and exemplary embodiments.

[0013] Figures 1 to 15 A cross-sectional view of an intermediate stage in the formation of a device in accordance with some embodiments of the present invention is shown. The corresponding process is also schematically reflected in process flow 200 as Figure 16 shown. It will be understood that although device wafers and device dies are used as examples, embodiments of the present invention may also be applied to the formation of conductive components in other devices (packaging components), including but not limited to packaging substrates, interposers, packages, etc.

[0014] Figure 1 A cross-sectional view of an integrated circuit device 20 is shown. In accordance with some embodiments of the present invention, device 20 is or includes a device wafer that includes active devices and possibly passive devices, which are represented as integrated circuit devices 26. A plurality of chips 22 may be included in device 20, and one of the chips 22 is shown. In accordance with alternative embodiments of the present invention, device 20 is an interposer wafer that does not include active devices and may or may not include passive devices. In accordance with yet another alternative embodiment of the present invention, device 20 is or includes a package substrate strip that includes a coreless package substrate or a cored package substrate having a core therein. In the following discussion, a device wafer is used as an example of device 20, and device 20 may also be referred to as wafer 20. Embodiments of the present invention may also be applied to interposer wafers, packaging substrates, packages, etc.

[0015] According to some embodiments of the present invention, the wafer 20 includes a semiconductor substrate 24 and components formed on the top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include the following materials: crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 24 to isolate active regions in the semiconductor substrate 24. Although not shown, vias may (or may not) be formed to extend into the semiconductor substrate 24, where the vias are used to electrically interconnect components on opposite sides of the wafer 20.

[0016] According to some embodiments of the present invention, the wafer 20 includes integrated circuit devices 26 formed on the top surface of the semiconductor substrate 24. According to some embodiments, the integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit devices 26 are not shown here. According to alternative embodiments, the wafer 20 is used to form an interposer (the interposer has no active devices), and the substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0017] An interlayer dielectric (ILD) 28 is formed above the semiconductor substrate 24 and fills the spaces between the gate stacks of transistors (not shown) in the integrated circuit devices 26. According to some embodiments, the ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, etc. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present invention, the ILD 28 is formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0018] Contact plugs 30 are formed in the ILD 28 and are used to electrically connect the integrated circuit devices 26 to the upper metal lines and vias. According to some embodiments of the present invention, the contact plugs 30 are formed of or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys, and / or their multilayers. The formation of the contact plugs 30 may include: forming a contact opening in the ILD 28; filling the contact opening with the conductive material; and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of the contact plugs 30 flush with the top surface of the ILD 28.

[0019] The interconnect structure 32 is located above the ILD 28 and the contact plug 30. The interconnect structure 32 includes metal lines 34 and vias 36, which are formed in a dielectric layer 38 (also referred to as an inter-metal dielectric (IMD)). Hereinafter, metal lines of the same level are collectively referred to as metal layers. According to some embodiments of the present invention, the interconnect structure 32 includes a plurality of metal layers, and the metal layers include metal lines 34 interconnected by vias 36. The metal lines 34 and the vias 36 may be formed of copper or a copper alloy, and they may also be formed of other metals. According to some embodiments of the present invention, the dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be less than about 3.0. The dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present invention, the formation of the dielectric layer 38 includes depositing a dielectric material containing a pore former in the dielectric layer 38, and then performing a curing process to expel the pore former, so that the remaining dielectric layer 38 is porous.

[0020] The formation of the metal lines 34 and the vias 36 in the dielectric layer 38 may include a single damascene process and / or a dual damascene process. In the single damascene process for forming a metal line or a via, first, a trench or a via opening is formed in one of the dielectric layers 38, and then the trench or the via opening is filled with a conductive material. Then, a planarization process such as a CMP process is performed to remove an excessive portion of the conductive material above the top surface of the dielectric layer, leaving a metal line or a via in the corresponding trench or via opening. In the dual damascene process, a trench and a via opening are formed in the dielectric layer, and the via opening is located below the trench and connected to the trench. Then, the conductive material is filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0021] The metal line 34 includes top conductive (metal) components such as metal lines, metal pads, or vias (denoted as 34A) located in a top dielectric layer (denoted as dielectric layer 38A) that is the top layer of the dielectric layer 38. According to some embodiments, the dielectric layer 38A is formed of a low-k dielectric material similar to the material of the lower dielectric layer 38. According to other embodiments, the dielectric layer 38A is formed of a non-low-k dielectric material, which may include silicon nitride, undoped silicate glass (USG), silicon oxide, etc. The dielectric layer 38A may also have a multi-layer structure that includes, for example, two USG layers and a silicon nitride layer therebetween. The top metal component 34A may also be formed of copper or a copper alloy and may have a dual-damascene structure or a single-damascene structure. The dielectric layer 38A is sometimes referred to as the top dielectric layer. The top dielectric layer 38A and the dielectric layer 38 immediately below the top dielectric layer 38A may be formed as a single continuous dielectric layer, or may be formed as different dielectric layers using different processes, and / or formed of materials different from each other.

[0022] Reference Figure 2 , a first etch stop layer 39 is deposited over the interconnect structure 32. The corresponding process is shown as process 202 in process flow 200 as Figure 16 shown. According to some embodiments, the first etch stop layer 39 is formed of or includes silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbide, etc. The deposition process may be implemented using atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0023] A passivation layer 40 (sometimes referred to as passivation-1 or pass-1) is formed over the first etch stop layer 39. The corresponding process is shown as process 204 in process flow 200 as Figure 16 shown. According to some embodiments, the passivation layer 40 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than that of silicon oxide. The passivation layer 40 may be formed of or include an inorganic dielectric material, which may include, but is not limited to, doped silicate glass, silicon oxide (SiO2), silicon oxycarbide (SiOC x ), silicon oxynitride (SiON X ), carbon-containing low-k dielectric materials, silicon nitride, etc. The value "x" represents a relative atomic ratio. According to some embodiments, the top surface of the top dielectric layer 38a and the metal line 34A are coplanar. Thus, the etch stop layer 39 and the passivation layer 40 may be flat layers. According to alternative embodiments, the top conductive component protrudes above the top surface of the top dielectric layer 38a, and the etch stop layer 39 and the passivation layer 40 are non-flat.

[0024] The passivation layer 40 can be a low-k dielectric layer and can be porous according to some embodiments. For example, the passivation layer 40 can be formed of or include the above materials, wherein pores are formed to reduce its k value. The porosity can be between about 10% and about 30%. The formation of the passivation layer 40 can include, but is not limited to, CVD, PECVD, etc. According to some embodiments, in the formation of the passivation layer 40, a pore former is incorporated and then a curing process is performed to expel the pore former, thereby leaving the porous passivation layer 40.

[0025] Figure 3 A capacitor 52 is shown according to some embodiments. The corresponding process is shown as process 206 in process flow 200 as Figure 16 shown. The capacitor 52 can be a MIM capacitor, which includes at least two, and possibly more, capacitor plates (electrodes) and a corresponding capacitor insulator therebetween. According to alternative embodiments, other types of capacitors, such as metal-oxide-metal (MOM) capacitors, can be employed. It should be understood that the capacitor 52 can be formed using a different process than that discussed with reference to Figure 3 which is also contemplated by the present invention. Referring to Figure 3 , capacitor electrodes 42A, 42B, and 42C are formed, which are collectively and individually referred to as capacitor electrodes 42. Capacitor insulators 44A and 44B, which are collectively and individually referred to as capacitor insulators 44, are formed between the capacitor electrodes 42. The formation of each capacitor electrode 42 and each capacitor insulator 44 can include a deposition process, followed by a possible patterning process by etching to produce the desired shape and size, e.g., as Figure 3 shown. The deposition of the capacitor electrodes 42 and the capacitor insulators 44 can be implemented using methods including, but not limited to, ALD, CVD, PECVD, etc. The capacitor 52 can have a thickness in the range of about to about therebetween.

[0026] According to some embodiments of the present invention, the electrode 42 is formed of or includes a metal nitride, such as titanium nitride (TiN). The capacitor electrode 42 can have a thickness in the range of about to about therebetween. According to other embodiments, other metals, metal alloys, and metal nitrides, such as tungsten nitride (WN), etc., can be used.

[0027] According to some embodiments of the present invention, each of the capacitor insulators 44 is a single layer formed of a uniform dielectric material such as zirconia (ZrO2). According to other embodiments of the present invention, one or more of the capacitor insulators 44 may be a composite layer formed of stacked dielectric layers. For example, one of the capacitor insulators 44 may be formed of a zirconium-containing dielectric layer (such as a ZrO2 layer) and an aluminum-containing dielectric layer (such as an Al2O3 layer) located above the zirconium-containing dielectric layer. The capacitor insulator 44 may also be formed of ZrO2 / Al2O3 / ZrO2 (ZAZ), which includes a first ZrO2 layer, an Al2O3 layer located above the first ZrO2 layer, and a second ZrO2 layer located above the Al2O3 layer. ZAZ has the advantageous feature of a low equivalent oxide thickness, and thus the resulting capacitor has a high capacitance value. The thickness of the capacitor insulator 44 may be in the range between about 0.1 μm and about 0.5 μm.

[0028] Figure 4 The formation of the second etch stop layer 46 is shown. The corresponding process is shown as process 208 in process flow 200 as Figure 16 shown. In some embodiments, the second etch stop layer 46 is formed of the same material as the first etch stop layer 39. The material of the second etch stop layer 46 may also be different from but similar to the material of the etch stop layer 39 such that in subsequent etching processes, the two etch stop layers can be etched using the same etch chemistry / process gas in the same etching process. According to some embodiments, the etch stop layer 46 is formed of silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, etc. This formation may be implemented using ALD, CVD, PECVD, etc. According to some embodiments, the etch stop layer 46 is patterned in the etching process such that it covers the capacitor 52 while some other portions of the etch stop layer 46 are removed. For example, the portion of the etch stop layer 46 located directly above the metal pad 34A may be removed.

[0029] As Figure 5 shown, a passivation layer 54 (sometimes referred to as passivation-2 or pass-2) is formed over the interconnect structure 32. The corresponding process is shown as process 210 in process flow 200 as Figure 16 shown. According to some embodiments, the passivation layer 54 is formed of or includes an inorganic dielectric material, which may include materials selected from, but not limited to, undoped silicate glass, silicon oxide, silicon oxynitride, silicon carbonitride, etc. The materials of the passivation layers 40 and 54 may be the same as each other. According to alternative embodiments, the materials of the passivation layers 40 and 54 are different from each other but are also similar to each other. For example, in embodiments where the passivation layers 40 and 54 are formed of silicon carbonitride, the atomic percentages of silicon, oxygen, and carbon in the passivation layers 40 and 54 may have a difference of less than about 5%.

[0030] According to some embodiments, the passivation layers 40 and 54 are formed of the same material, while the passivation layer 40 has a higher porosity than the passivation layer 54. For example, assume that the passivation layer 40 has a porosity value PRV40 and the passivation layer 54 has a porosity value PRV54, where the porosity values are expressed as percentages. The difference (PRV40 - PRV54) can be greater than about 10%, and can be in the range between about 10% and about 30%. With the higher porosity, the k value of the passivation layer 40 is also lower than the k value of the passivation layer 54. For example, the k value of the passivation layer 40 can be in the range between about 3.0 and about 4.0, while the k value of the passivation layer 54 can be in the range between about 3.8 and about 5.0. Having the passivation layers 40 and 54 of the same or similar material, but the passivation layer 40 with a greater porosity is advantageous in subsequent etching processes, where the passivation layer 40 is etched faster than the passivation layer 54. According to alternative embodiments, the passivation layers 40 and 54 are formed of different materials.

[0031] Referring to Figure 6 , the passivation layers 54 and 40 are patterned in an etching process to form openings 56, which include 56A, 56B, 56C, and 56D. The corresponding process is shown as process 212 in process flow 200 as shown in Figure 16 . The etching process may include a dry etching process, which includes forming a patterned etch mask (not shown), such as a patterned photoresist, and then etching the passivation layers 54 and 40. In the formation of the opening 56D, if they are exposed to the opening 56, the capacitor insulator 44 is also etched through. Then the patterned etch mask is removed. An anisotropic dry etching process is used to implement the etching, where an etching gas is used as the etching chemical. The etching process stops on the etch stop layers 39 and 46. Thus, the etch stop layers 39 and 46 are formed to facilitate the selection of an etching gas that attacks the passivation layers 54 and 40 and the capacitor insulator 44, but does not attack the etch stop layers 39 and 46. It should be understood that since the opening 56D is deeper than the openings 56A, 56B, and 56C, and additional passivation layer 40 needs to be etched, making the passivation layer 40 porous (with a low k value) is advantageous so that when the passivation layer 40 is exposed, the etching rate increases, and thus the loading effect in the formation of the opening 56 is reduced. Optionally, the passivation layer 40 (formed of a low-k dielectric material) is formed of a material different from that of the passivation layer 54 and has a higher etching rate than the passivation layer 54. For example, the ratio ER40 / ER54 can be greater than about 1.5 or greater than about 2.0, and can be in the range between about 1.5 and about 5.0, where the etching rate ER54 is the etching rate of the passivation layer 54, and the etching rate ER40 is the etching rate of the passivation layer 40.

[0032] Referencing Figure 7, etch through the etch stop layers 39 and 46 such that the underlying capacitor electrodes 42A, 42B, and 42C and the metal pads 34A are exposed. The opening 56A also penetrates the capacitor insulator 44B, and the opening 56C also penetrates both the capacitor insulators 44A and 44B. The etching process is implemented using the capacitor electrodes 42A, 42B, and 42C as the etch stop layers. The etching of the etch stop layers 39 and 46 can be implemented using a wet etching process or a dry etching process, and the etching process can be isotropic or anisotropic.

[0033] Figure 8 The deposition of the metal seed layer 58 is shown. The corresponding process is shown as process 214 in the process flow 200 as shown in Figure 16 According to some embodiments, the metal seed layer 58 includes a titanium layer and a copper layer located above the titanium layer. According to alternative embodiments, the metal seed layer 58 includes a copper layer in contact with the passivation layer 40. The deposition process can be implemented using physical vapor deposition (PVD), CVD, metalorganic chemical vapor deposition (MOCVD), etc.

[0034] Figure 8 The formation of the patterned plating mask 60 is further shown. The corresponding process is shown as process 216 in the process flow 200 as shown in Figure 16 According to some embodiments, the plating mask 60 is formed of photoresist and, thus, is optionally referred to as photoresist 60. The opening 62 is formed in the patterned plating mask 60 to expose the metal seed layer 58. The opening 62 can have a width in the range between about 1 μm and about 3 μm.

[0035] Figure 9 The plating of the conductive material (component) 64 into the opening 62 and onto the metal seed layer 58 is shown. The corresponding process is shown as process 218 in the process flow 200 as shown in Figure 16 According to some embodiments of the present invention, the formation of the conductive component 64 includes a plating process, which can include an electroplating process, a chemical plating process, etc. The plating is implemented in a plating chemical solution. The conductive component 64 can include copper, aluminum, nickel, tungsten, etc. or an alloy thereof. According to some embodiments, the conductive component 64 includes copper and no aluminum.

[0036] Next, the photoresist (plating mask) 60 as shown in Figure 9 is removed. The corresponding process is shown as process 220 in the process flow 200 as shown in Figure 16 In a subsequent process, an etching process is implemented to remove the portions of the metal seed layer 58 not protected by the overlying conductive component 64. The resulting structure is also shown in Figure 10 The corresponding process is shown as process 222 in the process flow 200 as shown in Figure 16Process 222 in the process flow 200 shown. Throughout the description, the conductive component 64 and the corresponding underlying metal seed layer 58 are collectively referred to as the redistribution line (RDL) 66, which includes RDLs 66A, 66B, 66C, and 66D. Each of the RDLs 66 may include a via portion 66V extending into the passivation layer 40 and a trace / line portion 66T above the passivation layer 54. RDLs 66A, 66B, and 66C are electrically connected to the capacitor electrode 42. RDL 66D may be electrically connected to the conductive component 34A. The vias 66V in RDLs 66A, 66B, and 66D contact the capacitor electrode 42 through top contact rather than edge contact of the conventional connection scheme. Thus, the contact resistance is reduced.

[0037] Reference Figure 11 , a passivation layer 68 is deposited. The corresponding process is shown as process 224 in the process flow 200 as Figure 16 shown. The passivation layer 68 (sometimes referred to as passivation-3 or Pass-3) is formed as a blanket layer. According to some embodiments, the passivation layer 68 is formed of or includes an inorganic dielectric material, which may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbide, etc., combinations thereof, or multiple layers thereof. The deposition may be implemented by a conformal deposition process such as atomic layer deposition (ALD), CVD, etc. Thus, the vertical and horizontal portions of the passivation layer 68 have the same thickness or substantially the same thickness, e.g., varying by less than about 20% or less than about 10%. The passivation layer 68 may be formed of the same or different material as the passivation layer 54. The passivation layer 68 may be formed of the same or different material as the passivation layer 40, except that the passivation layer 68 may have a lower porosity than the passivation layer 40. Thus, the k-value and porosity of the passivation layer 68 may be similar to those of the passivation layer 54.

[0038] Reference Figure 12 , a planarization layer 70 is deposited and then patterned to form an opening 72. The corresponding process is shown as process 226 in the process flow 200 as Figure 16 shown. The planarization layer 70 may be formed of a polymer. The polymer may be photosensitive or non-photosensitive. Photosensitive polymers for forming the planarization layer 70 may include polyimide, polybenzoxazole (PBO), etc. When it is photosensitive, patterning of the planarization layer 70 may include performing an exposure process on the planarization layer 70 and then developing the planarization layer 70 to form the opening 72. According to an alternative embodiment in which the planarization layer 70 is non-photosensitive, e.g., when the planarization layer 70 includes a non-photosensitive epoxy resin / polymer, patterning of the planarization layer 70 may include applying and patterning a photoresist above the planarization layer 70 and etching the planarization layer 70 using the patterned photoresist to define the pattern of the opening.

[0039] Further refer to Figure 12 and an etching process is implemented to etch through the passivation layer 68 such that the opening 72 further penetrates the passivation layer 68. The corresponding process is shown as process 228 in the process flow 200 as shown in Figure 16 . It should be understood that the etching of the passivation layer 68 can be implemented before or after the etching of the planarization layer 70.

[0040] Figure 13 The deposition of the metal seed layer 74 is shown. The corresponding process is shown as process 230 in the process flow 200 as shown in Figure 16 . According to some embodiments, the metal seed layer 74 includes a titanium layer and a copper layer located above the titanium layer. According to alternative embodiments, the metal seed layer 74 includes a copper layer that contacts the planarization layer 70, the passivation layer 68, and the RDLs 66A, 66B, 66C, and 66D.

[0041] Next, the conductive region 75 is plated. The corresponding process is shown as process 232 in the process flow 200 as shown in Figure 16 . The process for plating the conductive region 75 may include forming a patterned plating mask (e.g., photoresist, not shown) and plating the conductive region 75 in the opening of the plating mask. The conductive region 75 may include copper, nickel, palladium, aluminum, their alloys, and / or their multi-layers. Then, the patterned plating mask is removed.

[0042] Then, the metal seed layer 74 is etched and the portions of the metal seed layer 74 that are exposed after the removal of the plating mask are removed, while leaving the portions of the metal seed layer 74 directly under the conductive region 75. The corresponding process is shown as process 234 in the process flow 200 as shown in Figure 16 . The resulting structure is as shown in Figure 14 . The remaining portion of the metal seed layer 74 is the under-bump metal (UBM) 74'. The combination of the UBMS 74' and the conductive region 75 forms the via 78 and the electrical connection 76 (also referred to as a conductive bump or a metal bump).

[0043] In a subsequent process, for example, sawing along the scribe line 79 is performed to form individual device dies 22. The corresponding process is shown as process 236 in the process flow 200 as shown in Figure 16 . The device die 22 may also be referred to as the device 22 or the package component 22 because the device 22 can be used to be bonded to other package components to form a package. As described above, the device 22 can be a device die, an interposer, a package substrate, a package, etc.

[0044] Refer to Figure 15 and the device 22 is bonded to the package component 80 to form a package 86. The corresponding process is shown as process 238 in the process flow 200 as shown in Figure 16Process 238 in the process flow 200 shown. According to some embodiments, the encapsulation component 80 is or includes an interposer, an encapsulation substrate, a printed circuit board, an encapsulation, etc. The electrical connection member 83 in the encapsulation component 80 can be joined to the encapsulation component 80 through the solder region 82. The underfill 84 is dispensed between the device 22 and the encapsulation component 80. According to some embodiments, power potentials such as VDD and VSS (ground) can be provided to the capacitor 52. For example, RDL 66A can be connected to electrical ground, RDL 66B and 66C can be connected to VDD, and thus the capacitor electrodes 42A and 42C are interconnected. RDL 66D can be used by the logic circuit and can be provided with a logic signal.

[0045] Embodiments of the present invention have some advantageous features. The vias connected to the capacitor plates contact the top surface of the capacitor electrodes, so the contact resistance is lower than that when using edge contacts. In addition, by forming the passivation layer under the capacitor with a low-k material that is lower than the passivation layer above the capacitor, the loading effect in the etching of the passivation layer is reduced. Therefore, an integrated process for forming contacts to the capacitor and the underlying metal pads is provided, where the integrated process has a reduced loading effect.

[0046] According to some embodiments of the present invention, the method includes depositing a first passivation layer above a conductive component, where the first passivation layer has a first dielectric constant; forming a capacitor above the first passivation layer; depositing a second passivation layer above the capacitor, where the second passivation layer has a second dielectric constant greater than the first dielectric constant; forming a redistribution line electrically connected to the capacitor above the capacitor; depositing a third passivation layer above the redistribution line; and forming an under-bump metal (UBM) that penetrates the third passivation layer to electrically connect to the redistribution line. In an embodiment, depositing the second passivation layer includes depositing the same material as the first passivation layer, where more porogen is incorporated into the first passivation layer compared to the second passivation layer. In an embodiment, forming the capacitor includes forming a metal-insulator-metal capacitor. In an embodiment, the method further includes, before forming the first passivation layer, depositing a first etch stop layer; after forming the capacitor and before depositing the second passivation layer, depositing a second etch stop layer; and implementing an etching process to etch through the second passivation layer to form a first opening that stops at the top surface of the first top surface of the second etch stop layer, and etching through the second passivation layer and the first passivation layer to form a second opening that stops at the top surface of the first etch stop layer. In an embodiment, the first opening and the second opening are formed in the same etching process. In an embodiment, the method further includes, in a common process, etching through the first etch stop layer and the second etch stop layer. In an embodiment, the first etch stop layer and the second etch stop layer are deposited using the same dielectric material. In an embodiment, the first passivation layer is a low-k dielectric layer, and the second passivation layer is a non-low-k dielectric layer.

[0047] According to some embodiments of the present invention, a device includes a conductive pad; a first passivation layer located above the conductive pad, wherein the first passivation layer includes a first dielectric material and has a first dielectric constant; a second passivation layer located above the first passivation layer, wherein the second passivation layer has a second dielectric constant higher than the first dielectric constant; a capacitor sandwiched between the first passivation layer and the second passivation layer; a third passivation layer located above the second passivation layer; a first redistribution line penetrating the second passivation layer to contact the top surface of the capacitor electrode of the capacitor; and a second redistribution line penetrating both the second passivation layer and the first passivation layer to contact the conductive pad. In an embodiment, the first passivation layer has a higher porosity than the second passivation layer. In an embodiment, the first passivation layer is a low-k passivation layer and the second passivation layer is a non-low-k passivation layer. In an embodiment, each of the first redistribution line and the second redistribution line includes a trace portion sandwiched between the second passivation layer and the third passivation layer; and a via portion extending into the second passivation layer. In an embodiment, the device further includes: a first etch stop layer located below the first passivation layer and contacting the first passivation layer; and a second etch stop layer located between the capacitor and the second passivation layer and contacting both the capacitor and the second passivation layer. In an embodiment, the first redistribution line penetrates the second etch stop layer, and the second redistribution line penetrates the first etch stop layer. In an embodiment, the first and second etch stop layers are formed of the same material.

[0048] According to some embodiments of the present invention, a device includes a conductive component; a first etch stop layer located above and contacting the conductive component; a first passivation layer located above the first etch stop layer, wherein the first passivation layer has a first porosity value; a capacitor located above the first passivation layer; a second etch stop layer located above the capacitor; a second passivation layer located above the second etch stop layer, wherein the second passivation layer has a second porosity value lower than the first porosity value; a first redistribution line penetrating the second passivation layer and the second etch stop layer to be electrically connected to the capacitor; and a second redistribution line penetrating the second passivation layer, the first passivation layer, and the first etch stop layer to be electrically connected to the conductive component. In an embodiment, the first redistribution line contacts the second etch stop layer and is vertically spaced apart from the first etch stop layer. In an embodiment, the second redistribution line contacts the first etch stop layer and is laterally spaced apart from the second etch stop layer. In an embodiment, the first passivation layer and the second passivation layer are formed of the same dielectric material, wherein the first passivation layer has a lower dielectric constant than the second passivation layer. In an embodiment, the second etch stop layer has a bottom surface that forms an interface with the top surface of the capacitor electrode of the capacitor.

[0049] The features of several embodiments were outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: Depositing a first passivation layer over a conductive component, wherein the first passivation layer has a first dielectric constant; Forming a capacitor over the first passivation layer; Depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant; Forming a redistribution line electrically connected to the capacitor over the capacitor; Depositing a third passivation layer over the redistribution line; and Forming an under-bump metal (UBM) that penetrates the third passivation layer to electrically connect to the redistribution line; Performing an etching process to etch through the first passivation layer and the second passivation layer; Wherein depositing the second passivation layer includes depositing the same material as the first passivation layer, and more porogen is incorporated into the first passivation layer compared to the second passivation layer.

2. The method according to claim 1, wherein The capacitor has to a thickness in the range between them.

3. The method according to claim 1, wherein, Forming the capacitor includes forming a metal-insulator-metal capacitor.

4. The method according to claim 1, further comprising: Depositing a first etch stop layer before forming the first passivation layer; Depositing a second etch stop layer after forming the capacitor and before depositing the second passivation layer; And Performing the etching process to etch through the second passivation layer to form a first opening that stops at the top surface of the first top surface of the second etch stop layer, and etching through the second passivation layer and the first passivation layer to form a second opening that stops at the top surface of the first etch stop layer.

5. The method according to claim 4, wherein, The first opening and the second opening are formed in the same etching process.

6. The method according to claim 4, further comprising: In a common process, etching through the first etch stop layer and the second etch stop layer.

7. The method according to claim 4, wherein Depositing the first etch stop layer and the second etch stop layer using the same dielectric material.

8. The method according to claim 1, wherein, The first passivation layer is a low-k dielectric layer, and the second passivation layer is a non-low-k dielectric layer.

9. A semiconductor device, comprising: A conductive pad; A first passivation layer located over the conductive pad, wherein the first passivation layer includes a first dielectric material and the first passivation layer has a first dielectric constant; A second passivation layer located over the first passivation layer, wherein the second passivation layer has a second dielectric constant higher than the first dielectric constant, wherein the first passivation layer includes the same dielectric material as the second passivation layer and the first passivation layer has a higher porosity value than the second passivation layer; A capacitor sandwiched between the first passivation layer and the second passivation layer and directly contacting the second passivation layer; A third passivation layer located over the second passivation layer; A first redistribution line that penetrates the second passivation layer to contact the top surface of the capacitor electrode of the capacitor; and A second redistribution line that penetrates both the second passivation layer and the first passivation layer to contact the conductive pad.

10. The semiconductor device according to claim 9, wherein, The first passivation layer includes silicon carbon oxide.

11. The semiconductor device according to claim 9, wherein, The first passivation layer is a low-k passivation layer, and the second passivation layer is a non-low-k passivation layer.

12. The semiconductor device according to claim 9, wherein, Each of the first redistribution line and the second redistribution line includes: A trace portion sandwiched between the second passivation layer and the third passivation layer; and A via portion extending into the second passivation layer.

13. The semiconductor device according to claim 9, further comprising: A first etch stop layer located under and in contact with the first passivation layer; And A second etch stop layer located between the capacitor and the second passivation layer and in contact with both the capacitor and the second passivation layer.

14. The semiconductor device according to claim 13, wherein, The first redistribution line penetrates the second etch stop layer, and wherein the second redistribution line penetrates the first etch stop layer.

15. The semiconductor device according to claim 13, wherein, The first etch stop layer and the second etch stop layer are formed of the same material.

16. A semiconductor device, comprising: A conductive component; A first etch stop layer located above and in contact with the conductive component; A first passivation layer located above the first etch stop layer, wherein the first passivation layer has a first porosity value; A capacitor located above the first passivation layer; A second etch stop layer located above the capacitor; A second passivation layer located above the second etch stop layer, wherein the second passivation layer directly contacts the capacitor, the second passivation layer has a second porosity value lower than the first porosity value, and wherein the first passivation layer has a lower dielectric constant than the second passivation layer; A first redistribution line penetrating the second passivation layer and the second etch stop layer to electrically connect to the capacitor; and A second redistribution line penetrating the second passivation layer, the first passivation layer, and the first etch stop layer to electrically connect to the conductive component.

17. The semiconductor device according to claim 16, wherein, The first redistribution line contacts the second etch stop layer and is vertically spaced apart from the first etch stop layer.

18. The semiconductor device according to claim 16, wherein, The second redistribution line contacts the first etch stop layer and is laterally spaced apart from the second etch stop layer.

19. The semiconductor device according to claim 16, wherein, The first passivation layer and the second passivation layer are formed of the same dielectric material.

20. The semiconductor device according to claim 16, wherein, The second etch stop layer has a bottom surface that forms an interface with the top surface of the capacitor electrode of the capacitor.

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