Pillar bumps for post-measurement qubit frequency modification

Abstract

According to one embodiment of the invention, a method of producing a quantum computer chip includes performing a frequency measurement on a qubit chip for qubits on the qubit chip at an operating temperature of the qubit chip bonded to a test interposer chip. The method also includes pulling the qubit chip to separate from the test interposer chip after performing the frequency measurement, and modifying the frequency of a subset of the qubits after pulling the qubit chip to separate from the test interposer chip. The method further includes bonding the qubit chip to a device interposer chip after modifying the frequency of the subset of qubits.

Description

Background Art

[0001] The present invention relates to a method of producing a quantum computer chip and the produced chip, and more particularly to a method of producing a quantum computer chip including performing post-measurement qubit frequency modification on the produced chip.

[0002] When fixed-frequency qubit transmons are fabricated, their actual frequencies naturally deviate slightly from the target frequency. Therefore, for a chip with multiple fixed-frequency qubits, there will be an inherent frequency spread in the population of qubits that is too high to reliably allow the operation of a cross-resonance gate between each pair of qubits. Frequency spread leads to "frequency conflict", where the undesired ZZ interaction between a pair of qubits is too large to perform a cross-resonance gate, or a slow cross-resonance gate due to a large detuning between a pair of qubits. Post-measurement annealing and lithography modifications can modify the qubit frequency by changing the Josephson junction inductance or capacitance, for example by removing a dielectric. However, post-measurement frequency modifications often require access to the qubits on the qubit chip after the qubit chip is assembled on a substrate together with the readout circuit (or part thereof). As quantum processors move toward high density, flip-chip to chip bump bonding becomes necessary. The qubit chip can be a flip-chip bonded to an interposer chip to perform measurements on the qubit chip, and a quantum computer chip can be formed. However, currently, once the qubit chip is flip-chip bonded to an interposer chip, it is no longer possible to access the qubit chip to perform frequency modification. Summary of the invention

[0003] According to one embodiment of the present invention, a method of producing a quantum computer chip includes performing a frequency measurement on a qubit chip for qubits on the qubit chip at an operating temperature of the qubit chip bonded to a test interposer chip. The method also includes pulling the qubit chip to separate from the test interposer chip after performing the frequency measurement, and modifying the frequency of a subset of the qubits after pulling the qubit chip to separate from the test interposer chip. The method further includes bonding the qubit chip to a device interposer chip after modifying the frequency of the subset of qubits.

[0004] The method supports post-measurement modification of qubit frequencies by providing access to the qubit chip after the chip has cooled and measurements have been performed at cryogenic temperatures. Cryogenic frequency measurements are more accurate than room temperature measurements of predicted frequencies and allow sequential, precise qubit frequency modification, thereby preventing frequency conflicts between qubits. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a flow chart illustrating a method of producing a quantum computer chip according to one embodiment of the present invention.

[0006] Figure 2 is a schematic diagram of a qubit chip according to one embodiment of the present invention.

[0007] Figure 3 is a schematic diagram of a test interposer chip according to an embodiment of the present invention.

[0008] Figure 4 is a schematic diagram of a combined qubit chip and test interposer chip according to an embodiment of the present invention.

[0009] Figure 5 is a schematic diagram of a device interposer chip according to an embodiment of the present invention.

[0010] Figure 6 is a schematic diagram of a combined qubit chip and device interposer chip according to an embodiment of the present invention.

[0011] Figure 7 is a schematic diagram of a qubit chip according to one embodiment of the present invention.

[0012] Figure 8 Schematic diagram of a qubit chip bonded to a test interposer.

[0013] Fig. 9 is a schematic diagram of a device interposer chip according to an embodiment of the present invention.

[0014] Fig.10 is a schematic diagram of a qubit chip bonded to a device interposer chip.

[0015] Fig.11 is a schematic diagram of a quantum bit chip according to one embodiment of the present invention.

[0016] Fig.12 is a schematic diagram of a qubit chip bonded to a test interposer chip 1202.

[0017] Fig.13 is a schematic diagram of a device interposer chip according to an embodiment of the present invention.

[0018] Fig.14 is a schematic diagram of a qubit chip bonded to a device interposer chip 1402.

[0019] Fig.15 Schematic diagram of the unbound qubit chip and interposer chip.

[0020] Fig.16 is a schematic diagram of the combined qubit chip and interposer chip.

[0021] Fig.17is an image of metal posts on a qubit chip after it has been bonded to and pulled away from a test interposer chip.

[0022] Fig.18 is a schematic diagram of a qubit chip bonded to an interposer chip.

[0023] Fig.19 A schematic diagram of a qubit chip with golden pillars and qubits.

[0024] Fig. 20 is a schematic diagram of a test interposer chip with test solder bumps.

[0025] Fig.21 is a schematic diagram of a qubit chip bonded to a test interposer chip.

[0026] Fig. 22 Schematic diagram of a qubit chip before being bonded to a device interposer chip.

[0027] Fig.23 Schematic diagram of the device interposer chip before being bonded to the qubit chip.

[0028] Fig.24 is a schematic diagram of a qubit chip bonded to a device interposer chip. DETAILED DESCRIPTION

[0029] refer to Figure 1 , a method 100 of producing a quantum computer chip includes providing a qubit chip 102, and providing a test interposer chip 104 having at least a portion of a readout circuit. The method 100 also includes bonding the qubit chip to the test interposer chip 106, and cooling the bonded qubit chip and the test interposer chip to an operating temperature of the qubit chip 108. In some embodiments, more than one qubit chip may be bonded on one test interposer chip. The method 100 also includes performing a frequency measurement 110 on the cooled bonded qubit chip and the test interposer chip for the qubits on the qubit chip using the readout circuit. The method 100 further includes, after performing the frequency measurement 110, pulling the qubit chip to separate from the test interposer chip 114. The method 100 further includes, after actuating the qubit chip to separate from the test interposer chip 114, modifying the frequency of a subset of the qubits 116, and after modifying the frequency of the subset of the qubits 116, bonding the qubit chip to a device interposer chip 118. In some embodiments, more than one qubit chip may be incorporated on a device interposer chip.

[0030] According to one embodiment of the invention, the method does not include providing a qubit chip 102, providing a test interposer chip 104, bonding the qubit chip to the test interposer chip 106, and cooling the bonded qubit chip and test interposer chip 108. For example, the qubit chip and the test interposer chip may be pre-fabricated and bonded, e.g., by a manufacturer. Thus, the method may perform a frequency measurement 110 on the qubit chip bonded to the test interposer chip.

[0031] As used herein, a qubit chip is a chip that includes a substrate and at least one quantum bit (qubit) formed on the substrate. In some embodiments, the qubit can be a superconducting qubit. The qubit can include, for example, one or more Josephson junctions. In some embodiments, the qubit can be a transmon. In some embodiments, the qubit chip includes superconducting wiring formed on the substrate. The qubit chip can include a thin under-bump metal (UBM) pad formed on the superconducting wiring that becomes superconducting due to the proximity effect. In some embodiments, the qubit chip includes a readout resonator or a portion of a readout resonator.

[0032] As used herein, an interposer chip is a chip comprising a substrate and superconducting wiring formed on the substrate. The interposer chip may include at least one thin UBM pad, which is arranged on a metal interconnect, which becomes superconducting by means of a proximity effect. In some embodiments, the interposer chip includes a readout circuit. For example, the readout circuit can be a readout resonator or a part of a readout resonator. The interposer chip can be a test interposer for testing qubits, or a device interposer chip to be incorporated into a quantum computing device. In some embodiments, the device interposer chip is a reused test interposer chip. In some embodiments, the device interposer chip is bonded to the qubit chip via cold welding.

[0033] In a quantum computing device, qubits are coupled to each other through physical connections, for example, capacitively or by coupling to a coplanar waveguide bus. As the number of coupled qubits increases, space on the qubit chip becomes a limiting factor. Moving the readout resonator or a portion of the readout resonator to the interposer chip enables more qubits to be formed on the qubit chip. As this is true for the device interposer chip, it must also be true for the test interposer chip.

[0034] Pulling the qubit chip to separate from the test interposer chip means applying a force to at least one of the qubit chip and the test interposer chip to physically separate the qubit chip from the test interposer chip. The pull will result in a break in the bond between the posts on the qubit chip and the solder bumps on the test interposer chip. However, after the pull, some solder material from the solder bumps may remain attached to the posts. The pull does not require chemical treatment or annealing of the qubit chip. Thus, the qubit chip and the interposer chip are separated while avoiding damage to the qubits on the qubit chip.

[0035] The low temperature at which a qubit can operate is defined as a temperature sufficiently below the critical temperature of the superconductor involved and the temperature corresponding to the frequency of the qubit transitions. There are two relevant temperature scales for qubits: the critical temperature (Tc) of the superconductor that makes up the qubit, and the thermal energy (k) corresponding to the temperature of the qubit. B T). Tc is relevant because metals are normal and resistive above this temperature. In addition, the quasiparticle density decreases with temperature below Tc. B T must be much less than the energy corresponding to the qubit transition frequency (hf) so that thermal fluctuations do not cause too much decoherence. According to embodiments of the invention, a sufficiently low temperature is a temperature that is a fraction of the lower of Tc and the temperature corresponding to the qubit transition frequency. The fraction may be, for example, about 1 / 10, 1 / 15, or 1 / 20. According to embodiments of the invention, if the critical temperature is 1.2K and the qubit transition frequency corresponds to a temperature of 250mK, a temperature of less than 20mK may be sufficiently low.

[0036] The frequency of a qubit corresponds to the transition energy between the two states that the qubit is used for computation. A qubit has two quantum states that are sufficiently separated in energy and / or decoupled from any additional quantum states that the qubit approximates a two-quantum-state structure under operating conditions. The transition energy between the two states is a fixed quantity that defines the frequency of the qubit. For some qubits, the transition energy can still be modified, for example, by annealing the qubit with a laser.

[0037] Method 100 realizes the potential of frequency modification feedback because the method provides access to the Josephson junction formed on the qubit chip after the frequency of the qubit has been measured. Any conventional method currently existing or developed in the future can be used to modify the qubit. Non-photolithographic modification of the qubit can be performed by laser annealing of the Josephson junction and / or laser ablation of the dielectric or conductive material, friction modification (i.e., using a nanoindenter), or dry etching through a hard mask. Photolithographic methods can also be used. In particular, photolithographic methods with thick resists and low baking temperatures can be used. Soft paraffin liquid can also be used. Negative resists with patterning greater than 100 μm can be used, such as SU-8, KMPR, and JSR for spin coating or spray coating of resists. Positive resists can also be used by spraying and exposing with a direct write laser. This will allow the use of thinner resists, which will prevent the column bumps from being covered. Moreover, positive resists can have lower baking temperatures.

[0038] Direct access to the qubit surface enables inspection, such as microscopic inspection or resistance measurement of junctions or other structures on the surface, to confirm the modification. Without access to the Josephson junction, the qubit frequency can only be modified by techniques that penetrate the interposer (above) or the qubit substrate (below) without causing undesirable damage. Such techniques would be more difficult, limited, and imprecise than if the interposer were removed and the qubit surface was directly accessible.

[0039] Performing laser annealing through an interposer chip requires the interposer chip to have a transparent substrate or processing window. A transparent substrate or processing window may require additional manufacturing steps. In addition, a transparent substrate can introduce a two-level system that reduces qubit coherence and reliability. Processing windows have stress concentrations and handling issues that reduce coherence and reliability.

[0040] Alternatively, the qubit frequency can be modified using back-symmetric qubit chip frequency modification, which requires thinning the qubit die. Thinned qubit dies are prone to stress concentration and handling issues that can negatively impact coherence and reliability.

[0041] In contrast, method 100 does not incur a coherence or reliability penalty. In addition, method 100 enables more accurate predictions of the final Josephson junction frequency than other methods. The frequency of a qubit can be modified based on cold temperature frequency radiation, for example by laser annealing or ablation. However, the broad concepts of the invention are not limited to laser-only modification of qubits. Room temperature (RT) Josephson junction resistance, as a qubit frequency predictor, is not accurate enough to guarantee that there are no frequency collisions due to inherent correlation errors and capacitor manufacturing tolerances. Table 1 shows yield predictions for qubit chips with 24, 28, 54, and 73 qubits arranged in progressively larger implementations of a common topology. These numbers indicate how many chips were tested before a functional qubit chip was achieved.

[0042] Table 1: Production forecast

[0043]

[0044]

[0045] Once the qubits are screened, chips with appropriate RT resistance patterns are combined and cooled. As a result, no qubit modification (row 3 to the last) is the same as no accessibility to the junction (row 2 to the last). This is in contrast to the case where the number of chips is screened at room temperature, because if post-measurement modification is not possible, there is a more stringent requirement for the RT resistance condition. For example, for a 54Q chip, for each chip that looks "as good as possible" at RT, only one will prove to be conflict-free once the qubits are measured. Given the strictly random qubit frequency caused by manufacturing, >10k chips (much larger than the number of attempts used to simulate the dates in Table 1) are needed in order to find a chip that looks "as good as possible" at RT. As another example, given a modest ability to tune at RT before cooling, 6k to 18k chips are needed in order to find a chip whose resistance at RT is suitable for tuning to a "as good as possible" RT configuration. In contrast, if only one chip that is "as good as possible" at RT is produced, then cooled, frequency measured, warmed, pulled, and the qubit frequency modified, the method according to an embodiment of the present invention can almost guarantee zero conflicts. Therefore, the last row of the table is "1".

[0046] As shown in the last two rows, method 100 reduces the number of test chips from 9 to 1 for a 24-qubit chip and from 1000 to 1 for a 73-qubit chip. Method 100 includes cooling the combined qubit chip and test interposer chip to a low temperature at which the qubits can operate, enabling accurate frequency measurements to be made. After the chip is heated, the frequency measurements are used to perform high-precision frequency modifications of the qubit. Tuning a qubit based on its known and measured frequency is much more accurate than tuning a qubit based on an estimate of room temperature.

[0047] Method 100 enables multiple bonding and unbonding of qubit chips from an interposer chip without chemical treatment or global annealing of the qubit chips. Method 100 is compatible with the case where the metal bumps form part of the resonator. Method 100 allows lithography or lithography result modification (i.e., laser annealing or ablation) to leave intact pillar bumps, and significantly increases the likelihood of obtaining quantum processors in excess of 50 qubits in number, with all two-qubit gates functional.

[0048] refer to Figure 2 , qubit chip 200 includes at least one metal pad 202 and a metal pillar 204 formed on at least one metal pad 202. According to one embodiment of the present invention, qubit chip 200 further includes a qubit substrate 206, and a superconducting wiring 208 formed on qubit substrate 206. Metal pad 202 may be formed on superconducting wiring 208. Although qubit chip 200 includes qubits, Figure 2 The qubits are not shown. Figure 2 The configuration shown in can be used for non-critical ground bumps.

[0049] Reference Figure 3 , the test interposer chip 300 includes at least one metal pad 302 and a test solder bump 304 formed on the at least one metal pad 302. According to an embodiment of the present invention, the test interposer chip 300 further includes an interposer substrate 306 and a superconducting wiring 308 formed on the interposer substrate 306. The metal pad 302 may be formed on the superconducting wiring 308.

[0050] According to an embodiment of the present invention, Figure 1 Bonding the qubit chips to the test interposer chip in block 106 includes bonding metal pillars formed on at least one qubit chip to test solder bumps formed on the test interposer chip. Figure 4 4 is a schematic diagram of a bonded qubit chip 400 and a test interposer chip 402 according to an embodiment of the present invention. Metal pillars 404 formed on qubit chip 400 are bonded to test solder bumps 406 formed on test interposer chip 402. Metal pads 410 are significantly larger than metal pillars 404 to enable superconducting interconnection between solder bumps 406 and metal pads 410.

[0051] refer to Figure 5, the device interposer chip 500 includes at least one metal pad 502 and a device solder bump 504 forming the metal pad 502. According to an embodiment of the present invention, the device interposer chip 500 also includes an interposer substrate 506, and a superconducting wiring 508 formed on the interposer substrate 506. The metal pad 502 may be formed on the superconducting wiring 508. The device solder bump 504 may be larger than the test solder bump so that new solder may contact the metal pad on the qubit chip, for example Figure 2 Metal pad 202 on qubit chip 200 in FIG.

[0052] According to an embodiment of the present invention, Figure 1 Bonding the qubit chip to the device interposer chip in block 118 includes bonding metal pillars formed on the qubit chip to device solder bumps formed on the device interposer chip. Figure 6 6 is a schematic diagram of a bonded qubit chip 600 and a device interposer chip 602 according to an embodiment of the present invention. Metal pillars 604 formed on qubit chip 600 are bonded to device solder bumps 606 formed on device interposer chip 602. Device solder bumps 606 may contact a larger portion of metal pads 610 than test solder bumps. Device solder bumps 606 and metal pads 610 may be designed so that the entire metal pads 610 are encapsulated with solder.

[0053] According to an embodiment of the present invention, the test solder bump contacts a first region of the metal pad having the metal pillar formed thereon, and the device solder bump contacts a second region of the metal pad having the metal pillar formed thereon. At least a portion of the second region is different from the first region. For example, Figure 4 The test solder bump 406 in FIG. 4 contacts a first region 408 of a metal pad 410 on which a metal pillar 404 is formed. Figure 6 6. The device solder bump 606 in FIG. 60 contacts a second region 608 of the metal pad 610 on which the metal pillar 604 is formed. At least a portion of the second region 608 is different from the first region. For example, the second region may be larger than the first region. Because the device solder bump 606 extends further from the metal pillar 604 than the test solder bump 406 extends from the metal pillar 404, the device solder bump 606 contacts an area of ​​the metal pad 610 that was not previously contacted by the test solder bump 406.

[0054] refer to Figure 7 , qubit chip 700, in addition to first metal pillar 702, also includes second metal pillar 704 formed on metal pad 706. This configuration can be used for critical grounding and / or signal bumps to improve reliability and yield. Metal pad 706 is significantly larger than first metal pillar 702 and second metal pillar 704 to achieve superconducting interconnection between solder and metal pad 706.

[0055] When the qubit chip is bonded to the test interposer chip, only one of the metal pillars is bonded to the test interposer chip. Figure 8 is a schematic diagram of a test interposer chip 800 bonded to a qubit chip 802. The test interposer chip 800 has a test interposer bump 804 bonded to a first metal pillar 806. A second metal pillar 808 is not bonded.

[0056] After pulling interposer chip 802 away from qubit chip 800 and modifying the frequency of the qubits on the qubit chip, a method according to an embodiment of the present invention includes bonding qubit chip 800 to a device interposer chip having two device solder bumps. Fig. 9 900 is a schematic diagram of a device interposer chip 900 according to an embodiment of the present invention. In addition to the first metal pad 902 and the first device solder bump 904, the device interposer chip 900 also includes a second metal pad 906 and a second device solder bump 908 formed on the second metal pad 906. One bump can be used to shield the metal pillar bonded to the test solder bump, while the other bump can be used as a main signal or ground interconnect. The size of the device solder bump can be larger than the size of the test solder bump so that the new solder can contact the metal pad formed on the qubit chip.

[0057] Fig.10 1 is a schematic diagram of a qubit chip 1000 bonded to a device interposer chip 1002. A first metal pillar 1004 is bonded to a first device solder bump 1006 and a second metal pillar 1008 is bonded to a second device solder bump 1010. The first device solder bump 1006 may contact Figure 8 The test solder bump 804 in FIG. 8 is not in contact with the area of ​​the metal pad 1012. The first metal pillar 1004 is bonded to the first device solder bump 1006 to prevent losses if the first metal pillar 1004 is resistive.

[0058] refer to Fig.11 , qubit chip 1100, in addition to metal pillar 1102, also includes at least one metal plating pillar 1104 formed on each metal pad 1106. This configuration can be used for critical grounding and / or signal bumps to improve reliability and yield. Metal pad 1106 is significantly larger than metal pillar 1102 and metal plating pillar 1104 to achieve superconducting interconnection between solder and metal pad 1106.

[0059] The method according to an embodiment of the present invention includes bonding the metal pillars 1102 to the test solder bumps on the test interposer chip, but does not bond the metal plated pillars 1104 to the test interposer chip. Fig.12is a schematic diagram of a qubit chip 1200 bonded to a test interposer chip 1202. Qubit chip 1200 includes metal pillars 1204 and metal plated pillars 1206 formed on metal pads 1208. A method according to an embodiment includes bonding metal pillars 1204 to test solder bumps 1210. Metal plated pillars 1206 remain unbonded.

[0060] After pulling interposer chip 1202 away from qubit chip 1200 and modifying the frequency of the qubits on qubit chip 1200 , a method according to one embodiment of the present invention includes bonding qubit chip 1200 to a device interposer chip having two device solder bumps. Fig.13 1 is a schematic diagram of a device interposer chip 1300 according to an embodiment of the present invention. In addition to a first metal pad 1302 and a first device solder bump 1304 formed on the first metal pad 1302, the device interposer chip 1300 also includes at least one second metal pad 1306 and a second device solder bump 1308 formed on the second metal pad 1306. The second device solder bump 1308 may have a larger volume than the first device solder bump 1304 so as to span the distance from the second metal pad 1306 to the metal plating column. Both the first device solder bump 1304 and the second device solder bump 1308 may be larger than the test solder bump so that new solder can contact the metal pad formed on the qubit chip.

[0061] Fig.14 is a schematic diagram of a qubit chip 1400 bonded to a device / writer chip 1402. According to an embodiment of the present invention, in addition to bonding a metal pillar 1404 to a first device solder bump 1406, a method includes bonding a metal electroplated pillar 1408 formed on the qubit chip 1400 to a second device solder bump 1410 formed on the device interposer chip 1402. Bonding the metal pillar 1404 to the first device solder bump 1406 can prevent loss.

[0062] According to an embodiment of the invention, the qubit chip includes a plurality of metal pillars, the test interposer chip includes a plurality of test solder bumps, and the device interposer chip includes a plurality of device solder bumps. Fig.15 is a schematic diagram of an unbonded qubit chip 1500 and an interposer chip 1502. The qubit chip includes a plurality of metal pillars 1504, 1506. The interposer chip 1502 includes a plurality of solder bumps 1508, 1510. Interposer 1502 may be an example of a test interposer chip or a device interposer chip.

[0063] Fig.16 is a schematic diagram of a combined qubit chip 1600 and interposer chip 1602. Fig.16, the number of solder bumps on the interposer chip 1602 is equal to the number of metal pillars on the qubit chip 1600. However, embodiments of the present invention are not limited to equal numbers of solder bumps and metal pillars. For example, according to an embodiment of the present invention, the number of test solder bumps formed on the test interposer chip is less than the number of metal pillars on the qubit chip. In this embodiment, bonding the qubit chip to the test interposer chip includes bonding a subset of the plurality of metal pillars to the plurality of test solder bumps. Reducing the number of bonds between the test interposer chip and the qubits makes it easier to separate the qubit chip from the test interposer chip during pull-out. In an embodiment of the present invention, each metal pillar is bonded to a device solder bump formed on the device interposer chip.

[0064] According to an embodiment of the present invention, a test interposer chip including a plurality of test solder bumps is reused as a device interposer chip including a plurality of device solder bumps. For example, the method may include removing the test solder bumps from the test interposer chip and forming the device solder bumps on the removed test interposer chip by reflow. Because the test interposer chip does not include a Josephson junction, it can be subjected to chemical cleaning, etching, etc. In contrast, the Josephson junctions formed on the qubit chips are sensitive to handling and may be damaged if a cleaning process is applied to them. Fig.17 is an image of the metal pillars on the qubit chip after it has been bonded to and pulled apart from the test interposer chip. Fig.17 As shown, the metal pillars are intact and can be bonded to device interposer bumps formed on the device interposer chip.

[0065] According to an embodiment of the present invention, the qubit chip further comprises a plurality of metal plated pillars. Bonding the qubit chip to the test interposer chip comprises bonding a plurality of metal layers to a plurality of test solder bumps. Bonding the qubit chip to the device interposer chip comprises bonding the plurality of metal plated pillars to a first plurality of device solder bumps among the plurality of device solder bumps, and bonding the plurality of metal plated pillars to a second plurality of device solder bumps among the plurality of device solder bumps.

[0066] According to one embodiment of the present invention, a quantum computer chip is produced according to the method described herein. According to an embodiment of the present invention, a qubit chip includes at least one metal pad and a metal pillar formed on each metal pad, a test interposer chip includes at least one metal pad and a test solder bump formed on each metal pad, and a device interposer chip includes at least one metal pad and a device solder bump formed on each metal pad. The metal pillar formed on the qubit chip is bonded to the device solder bump formed on the device interposer chip to form a quantum computer chip, such as Figure 6 shown.

[0067] According to an embodiment of the present invention, the test solder bumps are formed of a superconducting material, and the device solder bumps are formed of a superconducting material. Table 2 shows material properties according to an embodiment of the present invention.

[0068] Table 2: Material properties

[0069]

[0070]

[0071] √=superconductivity

[0072] × = No need for superconductivity

[0073] As shown in Table 2, the metal pillars on the qubit chip and the corresponding interposer solder bumps on the interposer chip can be formed of superconducting materials. However, embodiments of the present invention are not limited to pillars and bumps formed of superconducting materials, nor are they limited to the material properties shown in Table 2. The material properties shown in Table 2 are provided as examples. According to an embodiment of the present invention, the pillar bumps are gold and the solder bumps are indium. According to an embodiment of the present invention, the metal pads are Au / Pd / Ti. The broad concepts of the present invention are not limited to these embodiments.

[0074] According to an embodiment of the present invention, the quantum computer chip produced according to the method described herein further includes a qubit chip having a second metal pillar formed on each metal pad, and the device interposer chip further includes at least one second metal pad and a second device solder bump formed on each second metal pad. Fig.10 As schematically shown in , the second metal pillar is bonded to the second device solder bump.

[0075] According to an embodiment of the present invention, a quantum computer chip produced according to the method described herein further comprises a qubit chip, the qubit chip further comprising at least one metal electroplating column formed on each metal pad, and the device interposer chip further comprising at least one second metal pad and a second device solder bump formed on each second metal pad. Fig.14 As schematically shown in FIG. 1 , the metal plated pillar is bonded to a second device solder bump.

[0076] According to an embodiment of the invention, method 100 also includes performing a resistance measurement across a Josephson junction formed on the qubit chip before bonding the qubit chip to the test interposer chip. This can be performed at room temperature or colder. According to an embodiment of the invention, method 100 also includes heating the bonded qubit chip and test interposer chip to a temperature at which the modified frequency can be performed.

[0077] According to an embodiment of the present invention, a quantum computer chip produced according to the methods described herein comprises a qubit chip and a device interposer chip, wherein a portion of the qubit chip and a portion of the device interposer chip form a readout resonator. For example, a portion of the qubit chip and a portion of the device interposer chip may resonate with a lumped element having a capacitor formed on the qubit chip and an inductor formed on the device interposer ( Fig.24 ), since only one initial test is expected (Table 1), and the approach can be used with different styles of resonators, for example, testing larger distributed resonators inserted on the chip where the readout resonators can be multiplexed onto a single feed line ( Fig.21 ), can be used because space is less critical. Smaller lumped-element resonators can then be used in the final quantum computing chip, where each resonator needs to be individually connected to control and / or measurement instrumentation.

[0078] Fig.18 is a schematic diagram of qubit chip 1800 bonded to interposer chip 1802. According to an embodiment of the present invention, metal pillar 1804 is superconducting. If metal pillar 1804 is not superconducting, solder bump 1806 contacts metal plate 1808 by a distance d S-S is designed to be much larger than the coherence length of the solder bump material. According to an embodiment of the present invention, the metal plate 1808 is intrinsically superconducting. If the metal plate 1808 is not intrinsically superconducting, the thickness t of the metal plate 1808 is designed to be small enough to facilitate superconducting interconnection between the solder bump 1806 and the superconducting wiring 1810 through the proximal effect.

[0079] Fig.19 is a schematic diagram of a qubit chip 1900 having gold pillars 1902 and qubits 1904 . Fig. 20 is a schematic diagram of a test interposer chip 2000 with test solder bumps 2002. The test interposer chip 2000 also includes a λ / 4 readout resonator 2004 and a coplanar waveguide feed line 2006 for multiplexing. To test the qubit frequency, control and readout can be multiplexed through the feed line 2006, simplifying the measurement setup. Fig.21 is a schematic diagram of a qubit chip bonded to a test interposer chip. The test interposer chip has fewer bumps than the qubit chip to aid in pulling.

[0080] Fig. 22 is a schematic diagram of a qubit chip 2000 before being bonded to a device interposer chip. For the final quantum computer chip, each qubit has individual control, which is required for cross-resonance gates, rather than using multiplexed control. The qubit chip 2200 includes a capacitive portion 2202 of a readout resonator. Fig.23is a schematic diagram of a device interposer chip 2300 prior to being bonded to a qubit chip. The device interposer chip 2300 includes an inductive portion 2302 of a readout resonator. Fig.24 Schematic diagram of a qubit chip bonded to a device interposer chip. The capacitive and inductive parts of the readout resonator form the complete readout resonator in the final quantum computer chip.

[0081] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terms used herein are selected to best explain the principles of the invention, practical applications, or technical improvements found on the market, or to enable other persons of ordinary skill in the art to understand the present invention.

Claims

1. A method for producing a quantum computer chip, comprising: performing a frequency measurement of the qubit chip for qubits on the qubit chip at an operating temperature of the qubit chip bonded to the test interposer chip; After performing the frequency measurement, pulling the qubit chip to separate from the test interposer chip; modifying the frequency of a subset of qubits after pulling the qubit chip to separate from the test interposer chip; and bonding the qubit chip to a device interposer chip after modifying the frequencies of the subset of qubits; wherein the test interposer chip includes a plurality of test solder bumps, and the device interposer chip includes a plurality of device solder bumps; and The device interposer chip is a reused test interposer chip, and the method further includes removing the test solder bumps from the test interposer chip after the pulling, and forming the plurality of device solder bumps on the test interposer chip.

2. The method according to claim 1, further comprising: prior to performing the frequency measurement, bonding the qubit chip to the test interposer chip; as well as The bonded qubit chip and test interposer chip are cooled to the operating temperature of the qubit chip.

3. The method of claim 2, wherein the qubit chip comprises at least one metal pad and a metal pillar formed on each metal pad, wherein the test interposer chip comprises at least one metal pad and a test solder bump formed on each metal pad, wherein the device interposer chip comprises at least one metal pad and a device solder bump formed on each metal pad, wherein bonding the qubit chip to the test interposer chip comprises bonding the metal pillars formed on the qubit chip to the test solder bumps formed on the test interposer chip, and Wherein bonding the qubit chip to the device interposer chip includes bonding the metal pillars formed on the qubit chip to the device solder bumps formed on the device interposer chip.

4. The method according to claim 3, characterized in that The test solder bump contacts a first region of the metal pad on which the metal pillar is formed, and Wherein the device solder bump contacts a second region of the metal pad on which the metal pillar is formed, at least a portion of the second region being different from the first region.

5. The method of claim 3, wherein the qubit chip further comprises a second metal pillar formed on each metal pad, and the device interposer chip further comprises at least one second metal pad and a second device solder bump formed on each second metal pad, The method also includes bonding the second metal pillars formed on the qubit chip to the second device solder bumps formed on the device interposer chip.

6. The method of claim 3, wherein the qubit chip further comprises at least one metal plated pillar formed on each metal pad, and the device interposer chip further comprises at least one second metal pad and a second device solder bump formed on each second metal pad, The method also includes bonding the metal plated pillars formed on the qubit chip to the second device solder bumps formed on the device interposer chip.

7. The method according to claim 3, The qubit chip comprises a plurality of metal pillars.

8. The method according to claim 7, wherein the number of test solder bumps in the plurality of test solder bumps is less than the number of metal pillars in the plurality of metal pillars, wherein the number of test solder bumps in the plurality of test solder bumps is less than the number of device solder bumps in the plurality of device solder bumps, wherein bonding the qubit chip to the test interposer chip comprises bonding a subset of the plurality of metal pillars to the plurality of test solder bumps, and Wherein bonding the qubit chip to the device interposer chip comprises bonding the plurality of metal pillars to the plurality of device solder bumps. 9 . The method of claim 8 , wherein a size of each device solder bump is larger than a size of each test solder bump.

10. The method of claim 7, wherein the qubit chip further comprises a plurality of metal plated pillars, wherein bonding the qubit chip to the test interposer chip comprises bonding the plurality of metal pillars to the plurality of test solder bumps, and Wherein bonding the qubit chip to the device interposer chip comprises bonding the plurality of metal pillars to a first plurality of device solder bumps of the plurality of device solder bumps, and bonding the plurality of metal plated pillars to a second plurality of device solder bumps of the plurality of device solder bumps.

11. The method of claim 10, wherein the number and size of device solder bumps are greater than the number and size of the test solder bumps.

12. The method of claim 11, further comprising performing a resistance measurement across a Josephson junction formed on the qubit chip prior to bonding the qubit chip to the test interposer chip.

13. The method of claim 11, further comprising heating the combined qubit chip and test interposer chip to a temperature that performs the modifying of the frequency.

14. A quantum computer chip produced according to the method of claim 1.

15. The quantum computer chip of claim 14, wherein the qubit chip comprises at least one metal pad and a metal pillar formed on each metal pad, The test interposer chip includes at least one metal pad and a test solder bump formed on each metal pad. wherein the device interposer chip comprises at least one metal pad and a device solder bump formed on each metal pad, and in, The metal pillars formed on the qubit chip are bonded to the device solder bumps formed on the device interposer chip to form the quantum computer chip.

16. The quantum computer chip of claim 15, wherein the metal pillar is formed of a material that is not superconducting, and wherein the distance that the device solder bump covers the metal pillar formed on the qubit chip is greater than the coherence length of the device solder bump.

17. The quantum computer chip of claim 15, wherein the metal pillars are formed of a material that is not superconducting, and wherein the distance at which the device solder bumps contact the metal pads formed on the qubit chip is greater than the coherence length of the device solder bumps.

18. The quantum computer chip according to claim 15, wherein: The test solder bumps are formed of a material that is superconducting, and wherein the device solder bumps are formed of a material that is superconducting.

19. The quantum computer chip of claim 15, wherein the qubit chip further comprises a second metal pillar formed on each metal pad, and the device interposer chip further comprises at least one second metal pad and a second device solder bump formed on each second metal pad, Wherein the second metal pillar is bonded to the second device solder bump.

20. The quantum computer chip of claim 15, wherein the qubit chip further comprises at least one metal plating pillar formed on each metal pad, and the device interposer chip further comprises at least one second metal pad and a second device solder bump formed on each second metal pad, wherein the metal plated stud is bonded to the second device solder bump.

21. The quantum computer chip of claim 15, wherein a portion of the qubit chip and a portion of the device interposer chip form a readout resonator.

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