Three-dimensional dynamic random access memory array

Abstract

A monolithically integrated three-dimensional (3D) DRAM array structure comprising single transistor single capacitor (1T1C) cells embedded at multiple device levels of a layered substrate assembly is disclosed. In some embodiments, vertical conductive data line pillars and ground pillars extending through the substrate assembly provide transistor source and ground voltages, and horizontal conductive access lines at multiple device levels provide transistor gate voltages. A process flow for fabricating the 3D DRAM array is also described.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application Serial No. 62 / 786,985, filed on December 31, 2018, which is incorporated herein by reference in its entirety. Background Art

[0003] Dynamic random access memory (DRAM) is a type of volatile semiconductor memory commonly used as main memory in modern computers and graphics cards, as well as other electronic devices such as portable devices and video game consoles. DRAM stores each bit of data in a capacitor within an integrated circuit; DRAM is "dynamic" because it uses external memory refresh circuits to periodically rewrite the data in the capacitor, thereby preventing data loss due to charge leakage in the capacitor. Over the past few decades, DRAM bit density has experienced rapid growth, contributing to the ever-increasing memory capacity of electronic devices. However, two-dimensional DRAM scaling is expected to reach the end of the roadmap after a few generations, prompting the desire to extend DRAM structures to three dimensions. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the accompanying drawings, various fill patterns and hatching styles are used to provide visual contrast between different material layers and device components. These fill patterns and hatching styles are not intended to limit the material selection of the corresponding layers or device components (and may deviate from the convention of depicting various materials); instead, suitable materials are listed in the text description.

[0005] Figure 1 is a schematic diagram of an example DRAM device according to various embodiments.

[0006] Figure 2 is a schematic top view of a 3D RAM array according to various embodiments.

[0007] Figure 3 is a schematic cross-sectional view of a 3D DRAM array according to various embodiments.

[0008] Figure 4-19A A process for forming a 3D array of memory cells having dual-gate transistors is presented, with a series of cut-away perspective views showing intermediate structures resulting from various steps of the process, according to one embodiment.

[0009] Figure 19B-33 Demonstrated the formation and Figure 4-19A A process for electrically connecting a 3D array of memory cells, wherein a series of cutaway perspective views show intermediate structures resulting from various steps of the process.

[0010] Fig.34 In isolation, the Figure 4-33 The process creates pairs of access lines and associated contact vias for a 3D array of memory cells.

[0011] Fig.35 In isolation, the Figure 4-33 The process creates a dual-gate access transistor for the memory cell.

[0012] Fig.36 In isolation, the Figure 4-33 The process creates the storage capacitor of the memory cell.

[0013] Fig.37 A close-up view shows Fig.36 storage capacitor.

[0014] Figure 38-40 A layered substrate assembly and a 3D array of memory cells having single gate transistors formed therein are shown according to one embodiment.

[0015] Fig.41 A 3D array of memory cells is shown with peripheral circuitry located below the memory array in a substrate assembly in accordance with some embodiments. DETAILED DESCRIPTION

[0016] Three-dimensional (3D) DRAM array structures in a monolithic multilayer implementation scheme and process flows for creating such structures are described herein. According to various embodiments, the DRAM array includes a single transistor single capacitor (1T1C) cell embedded in a layered substrate assembly in a 3D lattice arrangement. The term "substrate assembly" is used herein to identify the base-level substrate itself and other structures formed on or above the substrate. In many instances, the substrate will be a semiconductor substrate such as a silicon substrate, but alternative configurations of the substrate (e.g., silicon on insulator or other configurations known to those skilled in the art) can be used to support the formation of memory structures as described herein.

[0017] The following description relates to the formation of a memory array as part of a substrate assembly, and thus the memory array will be formed on a substrate. As discussed in more detail later herein, other structures may be formed on the substrate and below the memory array. As an example, a peripheral circuit system for operating a memory device may be formed as a device having a portion formed in a semiconductor substrate and a portion formed in one or more material layers on the substrate. Such peripheral circuit systems as are well known to those skilled in the art and which may include, for example, address decoders (row and column decoders), precharge circuits, sense amplifiers, and timing and control circuit systems may be used to operate a memory array, including storing data in and reading data from the memory array. In other examples, such peripheral circuit systems may be formed side by side with the memory array. The specific form in which such peripheral circuit systems (or other structures outside the memory array) may be formed in a substrate assembly does not form part of the subject matter of this description, and therefore is not specifically set forth in this description.

[0018] The described memory array includes a plurality of device levels, each device level including a plurality of arranged memory devices, wherein connections are provided between vertically offset memory devices of the plurality of device levels. In the depicted example, the device levels are vertically separated by dielectric separation levels. In the example configuration of the depicted memory array, each device level includes a dielectric device level "sandwiched" between two conductive device levels (for dual-gate transistor embodiments) or adjacent to a single conductive device level (for single-gate transistor embodiments). The dielectric device level and the conductive device level can each be formed of a single layer of dielectric or conductive material, respectively; or alternatively, each level can include multiple materials that together form the characteristics of the corresponding level. For example, the dielectric device levels can each include multiple dielectric materials (in some examples, the multiple dielectric materials can be present in one or more layers), and / or the conductive device levels can each include multiple conductive materials present in one or more layers. Similarly, the dielectric separation levels can each be formed of a single layer of dielectric material or of a stacked plurality of layers of dielectric material. For ease of discussion, the dielectric device level and the conductive device level and the dielectric separation level will be described hereinafter simply as separate corresponding layers. It should be understood that the described "layers" are presented as basic representations of levels that contain one or more materials to form the described structures and provide the described functions. Therefore, unless otherwise explicitly stated, each discussion of a material layer represents a level formed by one or more materials.

[0019] According to various embodiments, the 3D RAM array includes vertical conductive data lines and grounding posts extending through multiple device levels to provide transistor source and ground voltages, and horizontal conductive access lines located at multiple device levels within the multilayer substrate assembly to provide transistor gate voltages. The term "grounding post" used herein when referring to the memory array to the ground potential will be a common implementation. However, each description of the post at the ground potential can be replaced by a post at a different reference potential. As used herein, the term "horizontal" means in or parallel to the plane of the substrate assembly and its layers, and the term "vertical" means generally orthogonal / perpendicular to the plane of the substrate assembly and its layers, regardless of the orientation of the substrate assembly.

[0020] The described monolithic 3D DRAM array having vertically disposed devices operably associated with vertical pillars and associated fabrication processes allow for increased bit density in a more cost-effective manner compared to a layer-by-layer implementation of a two-dimensional (2D) DRAM array stacked in the third dimension. Additionally, the disclosed 3D DRAM array allows for placement of peripheral circuitry beneath the array, further reducing overall device size.

[0021] The foregoing broad summary will be more readily understood from the following detailed description of various example embodiments, particularly when taken in conjunction with the appended drawings.

[0022] Figure 1 A schematic diagram of an example DRAM device 100 is provided according to various embodiments. The device includes memory cells 102 arranged in rows 104 and columns 106 (in Figure 1 For simplicity and to adequately explain the basic components and basic operations of the memory device 100, the array is shown in two dimensions only; Figure 1 The discussion will address how to extend the array into the third dimension according to the disclosed subject matter. Further, although only four rows 104 and four columns 106 are shown, it should be understood that a DRAM device can actually include more (e.g., tens, hundreds, or thousands) memory cells 102 per row and / or per column.

[0023] According to various embodiments, each memory cell 102 includes a single transistor 110 (e.g., a field effect transistor (FET)) and a single capacitor 112; therefore, this cell is also often referred to as a 1T1C cell. One plate of the capacitor 112 (also referred to herein as a "node plate") is connected to the drain terminal ("D") of the transistor 110, while the other plate of the capacitor 112 is connected to ground 114. Each capacitor 112 within the array of 1T1C cells 102 is used to store one bit of data, and the corresponding transistor 110 is used as an "access device" to write to or read from the storage capacitor 112.

[0024] The transistor gate terminals ("G") within each row 104 are part of a corresponding access line (alternatively referred to as a "word line") 116 (and may be formed of the same material or a different material), and the transistor source terminals ("S") within each column 106 are electrically connected to a corresponding data line (alternatively referred to as a "bit line") 118. A row decoder 120 may selectively drive individual access lines 116 in response to a row address signal 122 input to the row decoder 120. Driving a given access line 116 at a high voltage causes the access transistor 110 within the corresponding row 104 to turn on, thereby connecting the storage capacitor 112 within the row 104 to the corresponding data line 118 so that charge can be transferred between the data line 118 and the storage capacitor 112 as required for a read or write operation. Both read and write operations can be performed by sense amplifier circuitry 124, which can transfer bit values ​​between the memory cells 102 of the selected row 104 and an input / output buffer 126 (for write / read operations) or an external input / output data bus 128. A column decoder 130 responsive to a column address signal 132 can select which of the memory cells 102 within the selected row 104 is read or written. Alternatively, for a read operation, the storage capacitors 112 within the row 104 can be read and latched simultaneously, and then the column decoder 130 can select which latched bits are connected to the output data bus 128. Since the readout of the storage capacitor destroys the stored information, the read operation is accompanied by a simultaneous rewrite of the capacitor charge. Further, between read / write operations, the capacitor charge is repeatedly refreshed to prevent data loss. The details of the read / rewrite, write and refresh operations are well known to those of ordinary skill in the art.

[0025] The memory device 100 may be implemented as an integrated circuit within a package that includes pins for receiving power supply voltages (e.g., providing source and gate voltages for the transistor 110) and signals (including data, address, and control signals). In general, it should be understood that Figure 1The memory device 100 is depicted in a greatly simplified form to show the basic structural components and operating principles, omitting many details of the memory cell 102 and the associated access line 116 and data line 118 and peripheral circuit systems. For example, in addition to the row decoder 120 and column decoder 130, the sense amplifier circuit system 124 and the buffer 126, the memory device 100 may include additional peripheral circuit systems, such as a memory control unit that controls memory operations based on control signals (e.g., provided by an external processor), additional input / output circuit systems, etc. The details of such peripheral circuit systems are well known to those of ordinary skill in the art and are not further discussed herein. Instead, the subsequent description focuses on the structural details of the memory cell 102 and the layout of the memory cell array according to various embodiments.

[0026] In a conventional 2D DRAM array, rows 104 and columns 106 of memory cells 102 are arranged along a single horizontal plane (i.e., parallel to the plane of the layers) of a semiconductor substrate, for example, in a rectangular lattice with mutually perpendicular horizontal access lines 116 and data lines 118. In contrast, in the 3D DRAM array described herein, the memory cells 102 are arranged in a 3D lattice that encompasses multiple vertically stacked horizontal planes corresponding to multiple device levels of a multi-level substrate assembly, wherein each device level includes parallel rows of cells 102 whose transistor gate terminals are connected by horizontal access lines 116. (As used herein, a "device level" may include multiple material layers (or levels), but form components of a memory device of a single horizontal memory cell level.) The data lines 118 extend vertically through all or at least a vertical portion of the multi-level structure, and each data line 118 is connected to the transistor source terminals of the vertical column 106 of the associated memory cells 102 at multiple device levels. Advantageously, this 3D configuration of memory cells enables further increases in bit density compared to 2D arrays. Additionally, the disclosed 3D DRAM device allows peripheral circuitry to be placed underneath the array memory cells, further reducing overall device size.

[0027] Figure 2is a schematic top view of a 3D DRAM array 200 according to various embodiments, illustrating an example arrangement of vertical data line pillars 202 (implementing data line 118) and associated memory cells 204 (corresponding to cell 102). (For clarity, only some of the pillars 202 and cells 204 are labeled.) As shown, the data line pillars 202 can be arranged at the vertices of a parallelogram lattice spanned by lattice vectors 206, 208 that define first and second horizontal directions, respectively. The lattice vectors 206, 208 (and the corresponding horizontal directions) can include acute angles 209 (as shown, the angle between vector 206 and vector 208 is measured in the mathematically negative (clockwise) direction) or right angles (the latter causing the special case of a rectangular lattice). As described below with respect to Figure 3 Explained in more detail, the memory cells 204 can be formed at least partially around the data line pillars 202. Within a row 210 of memory cells 204 extending along a first horizontal direction (defined by the lattice vector 206), the transistor gates of the memory cells 204 are electrically coupled to each other to form a horizontal access line. In some embodiments, the electrical connection between adjacent memory cells 204 is facilitated by a conductive ring 212, which is, for example, structurally similar to the transistor gates, surrounding a vertical "dummy pillar" 214 placed in the middle of any adjacent pair of data line pillars 202 along the row 210. The DRAM array 200 also includes a "reference pillar" coupled to a reference voltage to which one plate of the storage capacitor will be coupled; in many instances, the reference voltage will be a ground potential, and therefore the reference pillar is also referred to herein as a "ground pillar" 216. The ground pillars 216 are arranged along a second set of rows 218 extending in the first direction, the second set of rows being placed between adjacent rows of data line pillars 210, such that the data line pillars 202 and the ground pillars 216 alternate in the second horizontal direction. The data line columns 202 may be individually addressable (using the column address decoder described above), allowing access to any of the memory cells at the selected device level. The horizontal access lines may likewise be individually addressable, or may be grouped by device level to select all rows of a given device level simultaneously.

[0028] Figure 32 is a schematic cross-sectional view of a 3D DRAM array 200 according to various embodiments, showing a section parallel to the vertical and second horizontal directions, through one of the data line pillars 202 and one of the adjacent ground pillars 216. The figure shows two device levels 300, 302 (generally two or more device levels), each device level including a conductive device layer 304 and an electrically insulating dielectric device layer 306. The dielectric device layer 306 can be placed above (as shown) or below the conductive device layer 304, or alternatively, the insulating dielectric device layer 306 can be sandwiched between the two conductive device layers 304. The ground pillar 216 is in electrical contact with the conductive device layer 304 (and can actually be made of the same material and form an integral structure with the conductive device layer). On the other hand, the data line pillar 202 is electrically insulated from the conductive device layer 304.

[0029] In each of the dielectric device layers 306, each data line pillar 202 is at least partially surrounded by a transistor channel 310 made of a semiconductor material (e.g., a wide bandgap material such as undoped polysilicon) and forming, for example, an inner ring around the data line pillar 202. Each transistor channel 310 is in turn at least partially surrounded by a capacitor node plate 312 made of a conductive material and forming, for example, an outer ring around the transistor channel 310. In each of the conductive device layers 304, each data line pillar 202 is at least partially surrounded by a conductive transistor gate 314 made of a conductive material and forming, for example, a ring around the data line pillar 202.

[0030] The transistor channel 310, the capacitor node plate 312, and the transistor gate 314 are all examples of structures described herein as "rings" that extend around or "surround" another structure (e.g., a data line column 202). In some instances, such a "ring" can be a continuous annular structure that extends a full 360° around the column being surrounded; in other instances, the ring can be a discontinuous structure that extends around only a portion of the column being surrounded; and in still other instances, the ring can be a discontinuous structure comprising multiple portions that together extend around at least a portion of the column being surrounded. For the purposes of this description, all of these configurations are referred to as "ring" structures. In addition, when viewed from a horizontal plane, such a "ring" structure can be conveniently formed as a vertical surface having an inner surface and / or an outer surface that define a circle; however, the ring structure is not limited to being defined by such a circular surface, and other shapes can be defined by the inner surface and / or outer surface of the "ring" described and discussed herein.

[0031] The transistor gate 314 horizontally overlaps the transistor channel 310 above it (and / or below it, depending on the positioning of the conductive layer relative to the dielectric layer), but is electrically insulated from the transistor channel and is electrically insulated from the surrounding conductive device layer 304 and the corresponding data line pillar 202, for example by one or more dielectric layers 316, the thickness of which can be, for example, between 1 nm and 50 nm. The transistor of the memory cell according to the present invention is thus formed by combining the transistor channel 310 with the transistor gate 314, wherein the data line pillar 202 and the capacitor node plate 312 serve as the source terminal and the drain terminal, respectively. The capacitor node plate 312 horizontally overlaps the conductive device layer 304 below it (and / or above it), but is electrically insulated from the conductive device layer 304, for example, by one or more dielectric layers 318, and is therefore electrically insulated from the ground pillar 202, and the thickness of which can also be between 1 nm and 50 nm. The capacitor node plate 312, the overlapping portion of the adjacent conductive device layer 304, and the insulator therebetween collectively form a storage capacitor for the memory cell.

[0032] Figure 4-19A A process for forming a 3D array of memory cells is presented, with a series of cut-away perspective views showing intermediate structures resulting from various steps of the process, in accordance with one embodiment.

[0033] Figure 4 A layered substrate assembly 400 is shown formed over a semiconductor substrate 404 (the semiconductor substrate may have multiple material levels formed thereon that are not relevant to the memory array structure and are therefore not separately depicted). In the depicted example, the semiconductor substrate 404 includes a dielectric region extending around the bottom-most structure described with reference to the figures identified (e.g., the bottom portions of pillars 202, 214, 216). The substrate assembly 400 also includes a top dielectric level 402 formed over a periodic stack of the various material levels, which may be made using standard layer deposition techniques (e.g., chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, sputtering, etc.). Each period of the stack forms a device level. In Figure 4-19A In the example of FIG. 4 , each device level includes: a dielectric device layer 306 sandwiched between two conductive device layers 304, thereby collectively forming a three-layer device level 410; and a separate dielectric level 412 disposed on top of the upper conductive device layer 304 to separate vertically adjacent device levels 410. Figure 3 As discussed, in other examples, the device hierarchy may include only two layers / levels (eg, dielectric device layer 306 and a single conductive device layer 304). Figure 4Three device levels 410 are shown, but a 3D memory array according to the present invention can be made with more device levels 410, such as dozens of device levels 410. In some embodiments, the dielectric top and bottom layers 402, 404 are made of oxides, such as silicon dioxide (SiO2). The conductive device layer 304 can be made of, for example, doped polysilicon; other material options include, for example, doped silicon germanium (SiGe), conductive metal oxides and metals, and metal nitrides. The dielectric device layer 306 can include silicon oxycarbide (SiOC), and the dielectric layer 412 separating the device levels 410 (also referred to herein as "dielectric separation layers / levels") can include silicon nitride (SiN); however, other dielectric materials can be used. The dielectric device layer 306 and the dielectric separation layer 412 are typically made of different materials that provide a high etching ratio relative to one or more etchants so that only one of the layers can be preferentially etched while exposing both layers to the etchant.

[0034] Figure 5 The structure is shown after post trenches 500 for grounding posts 216 (also referred to herein as “grounding post trenches 500 ”) have been patterned in a regular lattice arrangement (eg, photolithographically) and etched into the substrate assembly 400 and through the stack of device levels 410 .

[0035] exist Figure 6 , the ground pillar trenches 500 have been filled with polysilicon or some other conductive material (typically but not necessarily the same material as used for the conductive device layer 304) to form rows 218 of ground pillars 216. The ground pillars 216 may be closed with a cap of dielectric material 600 (e.g., a SiN cap).

[0036] Next, if Figure 7 As shown, additional column grooves 700, 702 have been formed for the data line columns 202 and the dummy columns 214; hereinafter, these column grooves may also be referred to as "data line column grooves 700 and dummy column grooves 702". (Structurally, the data line column grooves 700 and the dummy column grooves 702 are indistinguishable at this stage.) The data line column grooves 700 and the dummy column grooves 702 are arranged in a row 210 approximately midway between the rows 218 of the ground columns 216, and are spaced apart along their respective rows 210, 218 (i.e., in the first horizontal direction 206) at twice the density of the ground columns 216 (e.g., at twice the spatial frequency).

[0037] Figure 8The structure resulting from etching back the conductive device layer 304 around the data line pillar trench 700 and the dummy pillar trench 702 is shown. In this manner, an annular cavity 800 is formed (labeled only for the leftmost data line pillar trench 700). For this step, an etchant is used that etches the conductive device layer 304 but does not significantly etch the individual dielectric layers 306, 412, 402. For the doped polysilicon device layer 304, suitable etchants include various dry chemistries (e.g., based on Cl2, CF4, SF6, or combinations thereof) as well as wet chemistries such as TAMH. The cavity 800 provides a space in which the transistor gate 314 can be subsequently formed.

[0038] Fig. 9 The structure is shown after forming a thin layer 900 of high-K (also referred to as "HiK") material (i.e., a material having a higher dielectric constant than SiO2 (i.e., higher than 3.6)) covering the top surface of the substrate assembly 400 and lining the inner surface of the data line pillar trench 700 and the dummy pillar trench 702 and the surrounding annular cavity 800. Such a thin layer can be formed by an atomic layer deposition (ALD) process.

[0039] exist Fig.10 In the embodiment, a conductive material 1000 (e.g., a titanium nitride / tungsten (TiN / W) composition) has been deposited over the substrate assembly to fill the HiK-lined data line pillar trenches 700 and dummy pillar trenches 702 and the cavity 800. This material 1000 will form the access lines of the 3D RAM array.

[0040] Fig.11 The structure is shown after the access line material 1000 has been partially etched back to reopen the data line trenches 700 and the dummy pillar trenches 702. Only rings 1100 of the conductive access line material 1000 remain embedded in the conductive device layer 304 (but insulated therefrom by the HiK material 900), surrounding the pillar trenches 700, 702. These rings 1100 are electrically insulated from the surrounding device layer material, and therefore from the ground pillars 216. The rings 1100 surrounding the data line pillar trenches (not the rings surrounding the dummy pillar trenches) will form the transistor gates 314 of the memory cells.

[0041] Fig.12 Further illustrated is a horizontal cross section taken through one of the conductive device layers 304. Fig.11As can be seen in this cutaway view, the rings 1100 of storage line material are sized and spaced to be electrically connected to their respective neighbors in a first horizontal direction (indicated by vector 206), thereby forming an integral conductive structure 1200 extending along the first horizontal direction - the access line. Within each access line 1200, each other ring 1100 will form a transistor gate 314; the middle ring 1100 surrounding what will become the dummy column 214 is used only to electrically couple the transistor gates 314 within the access line 1200. Fig.12 In FIG. 1 , the inner surface of the ring 1100 forming the access line 1200 has been sealed with a thin ring 1202 of an electrically insulating material such as SiN.

[0042] Fig.13 Shows Fig.11 The structure after a dielectric trench filler 1300 is deposited on top of the substrate to close all trenches 700, 702 and form a dielectric layer. The trench filler 1300 can be, for example, aluminum nitride (AlN). (For clarity, the small circles depicted on the top surface indicate the location of the underlying pillars.)

[0043] exist Fig.14 In the embodiment, the data line pillar groove 700 has been opened (eg, by photolithographic patterning and etching), while the dummy pillar groove 702 remains sealed, thereby forming the dummy pillars 214 (alternating with portions that will become the data line pillars 202 in a first horizontal direction).

[0044] Fig.15 Another cross-sectional view is provided with a horizontal section taken through the dielectric device layer 306, which shows the structure resulting from partially etching back the dielectric device layer 306 surrounding the open data line pillar trench 700 to form a disk-shaped cavity 1500 (or an annular cavity surrounding the pillar trench 700). The etchant used for this purpose is selected to only etch the dielectric device layer 306, but not the dielectric separation layer 412 between the device levels 410. As can be seen, particularly in the top cross-sectional plane, the diameter of the cavity 1500 can be larger than the diameter of the transistor gate 314, thereby allowing the space within the cavity 1500 to form a transistor channel 310 that horizontally overlaps the transistor gate 314 in the conductive device layer 304 (i.e., in a top-down view) and a capacitor node plate 312 surrounding the transistor channel 310. In some embodiments, the dielectric device layer 306 is etched all the way to the ground pillar 216.

[0045] exist Fig.16 In FIG. 1 , another HiK layer 1600 has been deposited over the substrate assembly to line the inner surface of the data line pillar trench 700 and the surrounding cavity 1500 .

[0046] Fig.17The structure is shown in which a capacitor node plate 312 and subsequent transistor channel 310 have been formed in a HiK lined cavity 1500 of a dielectric device layer 306. The capacitor node plate 312 may be made of, for example, doped polysilicon (or such other material used for the conductive device layer 304 in the substrate assembly 400). The capacitor node plate 312 may be formed by filling the data line pillar trench 700 with a capacitor material (e.g., doped polysilicon) and then partially etching back the material to leave an outer ring of capacitor material having an inner diameter still greater than the trench diameter. The pillar trench 700 and the remaining space within the cavity 1500 may then be filled with a suitable material for the transistor channel 310, typically a wide bandgap material (e.g., undoped polysilicon). This wide bandgap material is likewise etched back to open the pillar trench 700 and form an inner ring of wide bandgap material (slightly recessed from the trench diameter) that constitutes the transistor channel 310.

[0047] Fig.18 The structure is shown when the data line pillar groove 700 is filled with a conductive material 1800 (e.g., doped silicon) to form the data line pillar 202. This step completes the creation of the memory cell, each of which contains a transistor and a capacitor. The transistor is formed by an annular transistor channel 310, which contacts the data line pillar 202 at its inner surface (corresponding to the source terminal) and contacts the surrounding annular capacitor node plate 312 at its outer surface (corresponding to the drain terminal), and the annular transistor channel is double-selected by the transistor gate 314 formed in the conductive device layer 304 above and below. The capacitor is formed by the capacitor node plate 312, the portion of the conductive device layer 304 above and below that horizontally overlaps the capacitor node plate 312, and the HiK material 1600 that separates the node plate 312 from the horizontally overlapping portion of the conductive device layer 304. It should be noted that the overlapping portion of the conductive device layer 304 is electrically connected to the ground post 216 (and, in embodiments where the same conductive material is used for the device layer 304 and the ground post 216, is integrally formed) and thus effectively forms a capacitor ground plate.

[0048] exist Fig.19A , material 1800 has been etched back at the top of the structure to again expose the dielectric top layer 402 of the substrate assembly 400, and the data line pillars 202 have been capped with a dielectric material 1900 (eg, SiOC).

[0049] Figure 19B-33 Demonstrated the formation and Figure 4-19A A process for electrically connecting a 3D array of memory cells is shown, with a series of cutaway perspective views showing intermediate structures resulting from various steps of the process. The starting point is Fig.19A The structure of Fig.19B, the structure is shown rotated approximately 90° about the vertical direction, thereby exposing the back side of the structure that was previously hidden from view. It should be noted that the regular arrangement of data line posts 202, dummy posts 214, and ground posts 216 does not extend all the way across substrate assembly 400. Instead, in a portion of the substrate assembly generally indicated at 1904, only the dummy posts 214 are formed. (It should also be noted that the dummy posts are surrounded by a conductive ring that is structurally similar to or equivalent to a transistor gate, however the conductive ring is only used to form a portion of the access line.) This area (hereinafter also referred to as the "contact area") can be used to establish an electrical connection with access line 1200. In general, making electrical connections involves creating a stepped structure in the substrate assembly to expose the various device levels.

[0050] Fig. 20 The top step 2000 is shown as being produced by etching the dielectric top layer 402 down to the uppermost dielectric separation layer 412 in the contact region 1904 while leaving the dielectric top layer 402 in position over the portion of the array containing the data line pillars 212, the dummy pillars 214, and the ground pillars 216. The etching can be limited to the contact region 1904 by covering the substrate assembly with a resist and patterning the resist by photolithography to remove only the portion of the resist in the contact region 1904.

[0051] Fig.21 A layer of resist 2100 is shown deposited over the structure and trimmed to expose only one row 2102 (in the second horizontal direction 208 ) of dummy line pillars 214 . Fig. 22 The staircase structure is shown after etching away the topmost device level 410 (encompassing the topmost dielectric device layer 306 and its adjacent conductive device layer 304 ) and the separation layer 412 thereon in the exposed row 2102 of dummy studs 214 .

[0052] Fig.23 The resist 2100 is shown trimmed back to further expose the next row 2300 of dummy line pillars 214 . Fig.24 The stepped structure is shown after etching away the topmost device level 410 and associated separation layer 412 in the second row 2300 and simultaneously etching away the next lower device level 410 and associated separation layer 412 in the first row 2102. Note that the etch rate across the exposed surface is substantially uniform, such that all previously created steps are etched down with the same material thickness.

[0053] Fig.25The staircase structure is shown after removal of the resist 2100 in the depicted example embodiment, revealing three steps 2500, 2502, 2000 corresponding to three device levels 410, each covered by its respective dielectric separation layer 412. As will be appreciated by one of ordinary skill in the art, the process of trimming the resist and etching down one device level can generally be repeated as many times as necessary to accommodate any number of device levels in any given 3D array.

[0054] Having created a staircase structure that will allow contacting of storage lines at different device levels 410, the structure is further modified in subsequent steps to facilitate contacting both access lines 1200 within each device level 410 of a dual gating embodiment with the same electrical contact.

[0055] continue Fig.26 , the stepped structure is shown with a new layer of resist 2600 disposed on top. Fig. 27 The resist 2600 is shown patterned to form gaps 2700 between every few pairs of rows of dummy line pillars 214 in the first horizontal direction 206. Fig.28 , both layers of the step (i.e., dielectric separation layer 412 and the upper conductive device layer of the two conductive device layers 304) have been etched down in the region of gap 2700. As a result, the vertical facets of the two access lines 1200 of a single device level 410 are exposed at different horizontal positions (as opposed to being in the same vertical plane as before). For example, Fig.28 Two access lines 2800, 2802 of the second device level are called out. Fig.29 The etched structure 2900 is shown after the resist 2600 is stripped.

[0056] The remaining steps are used to create vertical vias that provide electrical contact for access line 1200. Fig.30 In the embodiment, a dielectric etch stop layer 3000 such as SiN has been deposited over the entire structure 2900 . Fig.31 The area above the step filled with contact oxide 3100 is shown, which has been polished back, for example using chemical mechanical polishing (CMP), to form a planar top surface. Fig.32 In FIG. 1 , the contact oxide 3100 has been patterned and etched to open a pillar trench 3200 for a contact via above each of the dummy pillars 214 in the contact region 1904. Fig.33 In , these pillar trenches 3200 have been filled with metal or other conductive material to form contact vias 3300, one for each pair of access lines 1200 in each device level 410. With appropriate peripheral circuitry, these vias 3300, and therefore each row 210 of memory cells, can be individually addressed.

[0057] Figure 34-37 Further, the various components and combinations of components are shown in isolation to illustrate the Figure 4-33 The 3D RAM array structure is created by the process.

[0058] Fig.34 From Figure 19B-33 The same angle shows pairs of access lines 1200 and associated contact vias 3300 (one via 3300 for two access lines 1200 in each row 210 of memory cells in each device level 410). For clarity, hatching is omitted in this figure. As can be seen, the access lines 1200 are formed by integrally connected rings. In the area where the array of memory cells is formed, every other one of these rings surrounds the data line pillar 202 (not shown) and provides a gate 314 for the corresponding transistor at that location. The transistor channel 310 between each pair of access lines 1200 is also shown.

[0059] Fig.35 From Figure 4-19A The same angle shows the dual-gate access transistors of the memory cell. Each access transistor is formed by a ring-shaped transistor channel 310 and a ring-shaped transistor gate 314 above and below the channel 310. Also shown is a HiK layer 900, 1600 that lines the cavity 800, 1500 in which the transistor channel 310 and the gate 314 are formed and electrically insulates the channel 310 from the gate 314.

[0060] Fig.36 From Fig.35 The same angle shows the storage capacitors of the memory cell. Each storage capacitor includes a conductive ring forming a node plate 312, a ground plate 3600 formed in the conductive device layer 304 above and below the node plate 312, and an electrical insulator of HiK material 1600 between the node plate 312 and the ground plate 3600. Also shown is a ground post 216 from which the ground plate 3600 extends.

[0061] Fig.37 A close-up view of the storage capacitor structure is provided showing the node plate 312 (surrounding the data line pillar 202) positioned between adjacent conductive device layers 304 integrally formed with the ground pillar 216. Fig.37 The portion of the conductive device layer 304 indicated by the cross-hatching and dashed boundary in FIG. 3 that horizontally overlaps the node plate 312 forms the ground plate 3600 and determines the effective area of ​​the capacitor structure.

[0062] While the preceding discussion and accompanying drawings illustrate memory cell arrays having dual-gate transistors, the disclosed structures and associated fabrication processes can be directly modified for single-gate transistors, such as Figure 38-40 shown.

[0063] Fig.38 A layered substrate assembly 3800 is shown having three device levels 3802 separated by dielectric separation layers 412, wherein each device level 3802 includes only two (rather than three) device layers: a conductive device layer 304 and a dielectric device layer 306 disposed thereon. (Alternatively, the dielectric device layer 306 may be placed below the conductive device layer 304.)

[0064] Arrays of memory cells can be made using Figure 4-19B Essentially the same process as shown is formed in this substrate assembly 3800, namely, by forming the data line pillars 202, dummy pillars 214, and ground pillars 216, creating the annular transistor channel 310 and capacitor plate 312 in the dielectric device layer 306, and forming the transistor gates 314 in the conductive device layer 304. However, in this embodiment, each transistor will only have one gate 314 disposed below the corresponding transistor channel 310. Fig.39 The resulting device structure is shown.

[0065] After the array of memory cells is formed, electrical connections to access lines in various device levels can be established by creating a staircase structure, then depositing an oxide fill and creating metal vias therein. The staircase integration process is significantly simplified compared to the process of embodiments utilizing dual gate transistors. Fig.40 The device structure with electrical connections is shown.

[0066] As discussed previously herein, in addition to the array of memory cells, memories typically also include peripheral circuitry, which may include, for example, Figure 1 The row decoder 120 and column decoder 130 discussed, sense amplifier circuitry 124, buffer 126, memory control unit, input / output circuitry, etc. Such peripheral circuitry can be formed on the same side of the substrate as the memory cell array and adjacent to the memory cell array, or on the back side of the substrate, opposite to the memory cell array. Alternatively, as Fig.414102 and 4103. As conceptually shown in FIG. 4104, peripheral circuitry 4100 according to some embodiments may be at least partially formed in substrate 4102 and located below a 3D DRAM array. For example, various circuit components may have one or more bodies formed within a semiconductor substrate and other bodies formed in one or more materials or one or more levels above the substrate. Vias 410 and other similar connections may be connected between corresponding electrical nodes 4106 of the peripheral circuitry and electrical nodes 4108 in or adjacent to the memory array to connect data lines, access lines, and ground contacts of the 3D RAM array to the peripheral circuitry as needed.

[0067] In order to better illustrate the methods and apparatus described herein, a set of non-limiting exemplary embodiments are described below as examples of digital identification.

[0068] Example 1 is a three-dimensional DRAM array, the three-dimensional DRAM array comprising: a substrate assembly, the substrate assembly comprising a plurality of device levels vertically separated from each other by dielectric separation levels, each of the device levels comprising a dielectric device level and at least one conductive device level vertically adjacent to the dielectric device level; conductive data line posts, the conductive data line posts vertically extending through at least a portion of the device levels and the dielectric separation levels, the data line posts being spaced apart along a plurality of first rows; conductive ground posts, the conductive ground posts vertically extending through at least a portion of the device levels and the dielectric separation levels, the ground posts being spaced apart along a plurality of first rows; Two rows are spaced apart, the first row and the second row both extending in a first horizontal direction and alternating with each other in a second horizontal direction; and memory cells formed within the device level, each of the memory cells at least partially surrounding a corresponding one of the conductive data line posts and including transistors and capacitors electrically connected between the data line posts and one or more of the ground posts, wherein the memory cells include rows of memory cells extending in the first horizontal direction, and wherein the transistors of the memory cells located in each row and located in a certain level share a common access line.

[0069] In Example 2, according to the subject matter of Example 1, each of the memory cells includes a transistor channel and a capacitor node plate each formed within a cavity within the dielectric device level of the corresponding device level, and at least one transistor gate formed within at least one cavity within the at least one conductive device level of the corresponding device level.

[0070] In Example 3, according to the subject matter described in Example 2, the transistor channel of each cell includes a semiconductor ring at least partially surrounding the corresponding conductive data line pillar, and wherein the capacitor node plate of each cell includes a conductive ring at least partially surrounding the corresponding semiconductor ring, and both the semiconductor ring and the conductive ring are electrically insulated from the at least one conductive device level.

[0071] In Example 4, according to the subject matter of Example 3, each transistor gate includes a conductive ring surrounding and electrically insulated from the conductive data line post and electrically insulated from the semiconductor ring and the ground post.

[0072] In Example 5, the subject matter of any one or more of Examples 2 to 4, wherein the capacitor area of ​​each memory cell in the memory cells is defined by a horizontal overlap area between a corresponding node plate and a portion of the at least one conductive device level surrounding the at least one cavity in which the at least one transistor gate is formed.

[0073] In Example 6, the subject matter of any one or more of Examples 2-5, wherein the node plate is made of doped polysilicon.

[0074] In Example 7, the subject matter of any one or more of Examples 2 to 6, optionally wherein the cavities formed in the dielectric device level and the conductive device level are each lined with a material having a dielectric constant greater than 3.6.

[0075] In Example 8, the subject matter of any one or more of Examples 1-7, wherein each device level includes the dielectric device level sandwiched between two conductive device levels, and wherein the memory cell includes a dual gate.

[0076] In Example 9, the subject matter of any one or more of Examples 1-8, wherein each device level includes only one conductive device level adjacent to the dielectric device level, and wherein the memory cell includes a single gate.

[0077] In Example 10, the subject matter described in any one or more of Examples 1 to 9 optionally includes a plurality of vertical dummy pillars and a plurality of conductive rings, wherein the plurality of vertical dummy pillars are arranged alternately with the conductive data line pillars along the first row, and the plurality of conductive rings surround the dummy pillars to form corresponding portions of the access lines.

[0078] In Example 11, according to the subject matter of any one or more of Examples 1 to 10, the data line pillars are arranged in the form of a parallelogram lattice spanned by lattice vectors extending along the first horizontal direction and the second horizontal direction.

[0079] In Example 12, according to the subject matter of Example 11, the grounding posts are arranged at center points of edges of the lattice along the second horizontal direction.

[0080] In Example 13, the subject matter of any one or more of Examples 1-12, wherein the conductive device stage, the ground pillar, and the data line pillar comprise doped polysilicon.

[0081] In Example 14, the subject matter of any one or more of Examples 1-13, wherein the dielectric device stage comprises silicon oxycarbide and the separation stage comprises silicon nitride.

[0082] In Example 15, the subject matter of any one or more of Examples 1-14, wherein the access line comprises titanium nitride and tungsten.

[0083] Example 16 is a memory cell formed in a substrate, the substrate comprising a dielectric device level and at least one conductive device level vertically adjacent to the dielectric device level, the memory cell comprising: a transistor, the transistor comprising a semiconductor ring and at least one conductive ring, the semiconductor ring formed in the dielectric device level and electrically contacting a first conductive pillar extending vertically through the dielectric device level and the conductive device level, the first conductive pillar being connected to a source node, the at least one conductive ring forming at least one corresponding transistor gate in the at least one conductive device level and surrounding the first conductive pillar, the transistor gate being electrically insulated from the first conductive pillar and the semiconductor ring and connected to a gate voltage; and a capacitor, the capacitor comprising a conductive ring and a ground plate, the conductive ring forming a capacitor node plate in the dielectric device level, the conductive ring at least partially surrounding the semiconductor ring and electrically contacting the semiconductor ring, the capacitor node plate being electrically insulated from a second conductive pillar extending through the dielectric device level and the conductive device level, the second conductive pillar being connected to a ground node, the ground plate being formed by a portion of the conductive device level electrically connected to the second conductive pillar and horizontally overlapping the capacitor node plate.

[0084] In Example 17, according to the subject matter of Example 16, wherein the dielectric device level is disposed between two adjacent conductive device levels, and wherein the transistor is dual-gated by two corresponding conductive rings formed within the conductive device levels.

[0085] In Example 18, the subject matter of any one or more of Examples 16-17, wherein both the semiconductor ring and the capacitor node plate are formed in a first cavity surrounding the first conductive pillar; and wherein the transistor gate is formed in a second cavity surrounding the first conductive pillar, the first cavity and the second cavity being lined with a material having a dielectric constant greater than that of silicon dioxide.

[0086] In Example 19, the subject matter of any one or more of Examples 16-18, wherein the conductive device level, the first and second conductive pillars, and the capacitor node plate are made of doped polysilicon.

[0087] In Example 20, the subject matter of any one or more of Examples 16-19, wherein the at least one transistor gate is made of titanium nitride and tungsten.

[0088] Example 21 is a method of forming a DRAM array, the method comprising: forming a plurality of device levels above a substrate, the plurality of device levels being vertically separated from each other by dielectric separation levels, each of the device levels comprising a dielectric device level and at least one conductive device level; forming conductive data line posts extending vertically through the device levels and at least a portion of the dielectric separation levels, the data line posts being spaced apart along a plurality of first rows; forming conductive ground posts extending vertically through the device levels and at least a portion of the dielectric separation levels, the ground posts being spaced apart along a plurality of second rows, both of the first rows and the second rows extending in a first horizontal direction and alternating with each other in a second horizontal direction; and forming memory cells within the device levels, the memory cells at least partially surrounding a corresponding one of the conductive data line posts and comprising transistors and capacitors coupled between the data line posts and one or more of the ground posts, wherein the memory cells comprise rows of memory cells extending in the first horizontal direction, and wherein the transistors of the memory cells within each row and within the conductive device level share a common access line.

[0089] In Example 22, according to the subject matter of Example 21, forming the memory cell includes: forming a transistor channel and a capacitor node plate within a cavity within the dielectric device level of the corresponding device level; and forming at least one transistor gate, wherein the at least one transistor gate is formed within at least one cavity within the at least one conductive device level of the corresponding device level.

[0090] In Example 23, according to the subject matter of Example 22, forming the memory cell includes: forming a semiconductor ring, the semiconductor ring is formed in a dielectric device level and is electrically in contact with a first conductive pillar extending vertically through the dielectric device level and the conductive device level, the first conductive pillar is connected to a source node; and forming at least one conductive ring, the at least one conductive ring forms at least one corresponding transistor gate in the at least one conductive device level and surrounds the first conductive pillar, the transistor gate is electrically insulated from the first conductive pillar and the semiconductor ring and is connected to a gate voltage; and forming a capacitor, the forming the capacitor includes: forming a conductive ring in the dielectric device level, the conductive ring forms a capacitor node plate, the conductive ring at least partially surrounds the semiconductor ring and is electrically in contact with the semiconductor ring, the capacitor node plate is electrically insulated from a second conductive pillar extending through the dielectric device level and the conductive device level, the second conductive pillar is connected to a ground node; and forming a ground plate in a portion of the conductive device level electrically connected to the second conductive pillar and horizontally overlapping the capacitor node plate.

[0091] In Example 24, the subject matter described in any one or more of Examples 22 to 23, wherein forming the transistor channel of each cell includes: forming a semiconductor ring that at least partially surrounds the corresponding conductive data line column; and forming a capacitor node plate, the capacitor node plate includes a conductive ring that at least partially surrounds the corresponding semiconductor ring, both the semiconductor ring and the conductive ring are electrically insulated from the at least one conductive device level.

[0092] In Example 25, according to the subject matter of Example 24, each transistor gate includes a conductive ring surrounding and electrically insulated from the conductive data line post and electrically insulated from the semiconductor ring and the ground post.

[0093] In Example 26, the subject matter of any one or more of Examples 2 to 25, wherein the capacitor area of ​​each memory cell in the memory cells is defined by a horizontal overlap area between a corresponding node plate and a portion of the at least one conductive device level surrounding the at least one cavity in which the at least one transistor gate is formed.

[0094] In Example 27, the subject matter of any one or more of Examples 2-26, wherein the node plate comprises doped polysilicon.

[0095] In Example 28, the subject matter of any one or more of Examples 2-27, wherein the cavities formed in the dielectric device level and the conductive device level are each lined with a material having a dielectric constant greater than 3.6.

[0096] In Example 29, the subject matter of any one or more of Examples 1-28, wherein each device level includes the dielectric device level sandwiched between two conductive device levels, and wherein forming the memory cell includes forming a dual gate of the transistor.

[0097] In Example 30, the subject matter of any one or more of Examples 21-29, wherein each device level includes only one conductive device level adjacent to the dielectric device level, and wherein the memory cell includes a single gate.

[0098] In Example 31, the subject matter described in any one or more of Examples 21 to 30 optionally includes: forming a plurality of vertical dummy pillars, wherein the plurality of vertical dummy pillars are arranged alternately with the conductive data line pillars along the first row; and forming a plurality of conductive rings around the dummy pillars to form corresponding portions of the access lines.

[0099] In Example 32, the subject matter of any one or more of Examples 21 to 31, wherein the data line posts are arranged in a parallelogram lattice spanned by lattice vectors extending along the first horizontal direction and the second horizontal direction.

[0100] In Example 33, the subject matter of any one or more of Examples 21-32, wherein the grounding posts are arranged at center points of edges of the lattice along the second horizontal direction.

[0101] In Example 34, the subject matter of any one or more of Examples 21-33, wherein the conductive device stage, the ground pillar, and the data line pillar comprise doped polysilicon.

[0102] In Example 35, the subject matter of any one or more of Examples 1-34, wherein the dielectric device stage comprises silicon oxycarbide and the separation stage comprises silicon nitride.

[0103] In Example 36, the subject matter of any one or more of Examples 1-35, wherein the access line comprises titanium nitride and tungsten.

[0104] In Example 37, any one or more of the example 3-dimensional DRAM arrays described in Examples 1 to 15 may be constructed by the method described in any one of Examples 21 to 36.

[0105] In Example 38, any one or more of the example 3-dimensional DRAM arrays described in Examples 1-15 may include one or more memory cells described in any of Examples 16-20.

[0106] In Example 39, any one or more of the devices described in any of Examples 1 to 20 can be incorporated into a system including a processor or other structure.

[0107] In Example 40, any additional processes, sequences of operations, and materials described herein may be used with any of the methods of Examples 21 to 36.

[0108] In Example 41, any additional processes, sequences of operations, and materials described herein can be incorporated into the structure or formation of any of Examples 1 to 20.

[0109] The foregoing description of 3D memory arrays is intended to provide a general understanding of the structure of various embodiments, rather than a complete description of all of the elements and features of a device that might utilize the structure described herein.

[0110] The 3D memory array devices of various embodiments may include or be included in electronic circuit systems used in high-speed computers, communication and signal processing circuit systems, memory modules, portable memory storage devices (e.g., thumb drives), single or multiple processor modules, single or multiple embedded processors, multi-core processors, data switches, and application-specific modules including multi-layer, multi-chip modules. Such devices may be further included as subcomponents in various electronic systems such as televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0111] The above description and accompanying drawings illustrate some embodiments of the present invention to enable those skilled in the art to practice embodiments of the present invention. Other embodiments may incorporate structural, logical, electrical, process and other changes. Examples represent only possible variations. The parts and features of some embodiments may be included in those parts and features of other embodiments, or may replace those parts and features of other embodiments. After studying and understanding the above description, many other embodiments will be apparent to those skilled in the art.

[0112] The Abstract is provided to comply with 37 CFR §1.72(b)'s requirement for an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure.The Abstract of the Disclosure is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A three-dimensional DRAM array, comprising: a substrate assembly comprising a plurality of device levels vertically separated from one another by dielectric separation levels, each of the device levels comprising a dielectric device level and at least one conductive device level vertically adjacent to the dielectric device level; conductive data line posts extending vertically through the device level and at least a portion of the dielectric separation level, the data line posts being spaced apart along a first plurality of rows; conductive grounding posts extending vertically through the device level and at least a portion of the dielectric separation level, the grounding posts being spaced apart along a plurality of second rows, both the first rows and the second rows extending in a first horizontal direction and alternating with each other in a second horizontal direction; as well as memory cells formed within the device level, each of the memory cells at least partially surrounding a corresponding one of the conductive data line posts and comprising a transistor and a capacitor electrically connected between the data line post and one or more of the ground posts, The memory cells include rows of memory cells extending in the first horizontal direction, and the transistors of the memory cells in each row and in a certain level share a common access line.

2. The DRAM array of claim 1 , wherein each of the memory cells comprises a transistor channel and a capacitor node plate both formed within a cavity within the dielectric device level of the corresponding device level, and at least one transistor gate formed within at least one cavity within the at least one conductive device level of the corresponding device level.

3. A DRAM array according to claim 2, wherein the transistor channel of each cell includes a semiconductor ring at least partially surrounding the corresponding conductive data line pillar, and wherein the capacitor node plate of each cell includes a conductive ring at least partially surrounding the corresponding semiconductor ring, and both the semiconductor ring and the conductive ring are electrically insulated from the at least one conductive device level.

4. The DRAM array of claim 3, wherein each transistor gate comprises a conductive ring surrounding and electrically insulated from the conductive data line pillar and electrically insulated from the semiconductor ring and the ground pillar.

5. A DRAM array according to claim 2, wherein the capacitor area of ​​each memory cell in the memory cells is defined by the horizontal overlap area between the corresponding node plate and a portion of the at least one conductive device level surrounding the at least one cavity in which the at least one transistor gate is formed.

6. The DRAM array of claim 2, wherein the node plate is made of doped polysilicon.

7. The DRAM array of claim 2, wherein the cavities formed in the dielectric device level and the conductive device level are each lined with a material having a dielectric constant greater than 3.

6.

8. The DRAM array of claim 1, wherein each device level comprises the dielectric device level sandwiched between two conductive device levels, and wherein the memory cells comprise dual gates.

9. The DRAM array of claim 1, wherein each device level comprises only one conductive device level adjacent to the dielectric device level, and wherein the memory cells comprise a single gate.

10. The DRAM array according to claim 1, further comprising a plurality of vertical dummy pillars and a plurality of conductive rings, wherein the plurality of vertical dummy pillars are arranged alternately with the conductive data line pillars along the first row, and the plurality of conductive rings surround the dummy pillars to form corresponding portions of the access lines.

11. The DRAM array of claim 1, wherein the conductive device level, the ground pillars, and the data line pillars comprise doped polysilicon.

12. The DRAM array of claim 1 wherein the dielectric device level comprises silicon oxycarbide and the separation level comprises silicon nitride.

13. The DRAM array of claim 1 wherein the access lines comprise titanium nitride and tungsten.

14. A method of forming a DRAM array, the method comprising: forming a plurality of device levels above a substrate, the plurality of device levels being vertically separated from one another by dielectric separation levels, each of the device levels comprising a dielectric device level and at least one conductive device level; forming conductive data line posts extending vertically through the device level and at least a portion of the dielectric separation level, the data line posts being spaced apart along a first plurality of rows; forming conductive grounding posts extending vertically through the device level and at least a portion of the dielectric separation level, the grounding posts being spaced apart along a plurality of second rows, the first rows and the second rows both extending in a first horizontal direction and alternating with each other in a second horizontal direction; as well as forming a memory cell within the device level, the memory cell at least partially surrounding a corresponding one of the conductive data line posts and including a transistor and a capacitor coupled between the data line post and one or more of the ground posts, Wherein the memory cells include rows of memory cells extending in the first horizontal direction, and wherein transistors of the memory cells within each row and within a conductive device level share a common access line.

15. The method of claim 14, wherein forming the memory cell comprises: forming a transistor channel and a capacitor node plate within a cavity within the dielectric device level of a corresponding device level; as well as At least one transistor gate is formed, the at least one transistor gate being formed within at least one cavity within the at least one conductive device level of the respective device levels.

16. The method of claim 15, wherein forming the memory cell comprises: forming a semiconductor ring formed within a dielectric device level and in electrical contact with a first conductive pillar extending vertically through the dielectric device level and the conductive device level, the first conductive pillar being connected to a source node; and forming at least one conductive ring, the at least one conductive ring forming at least one corresponding transistor gate within the at least one conductive device level and surrounding the first conductive pillar, the transistor gate being electrically insulated from the first conductive pillar and the semiconductor ring and connected to a gate voltage; as well as forming a capacitor, the forming of the capacitor comprising: forming a conductive ring within the dielectric device stage, the conductive ring forming a capacitor node plate, the conductive ring at least partially surrounding the semiconductor ring and in electrical contact with the semiconductor ring, the capacitor node plate being electrically insulated from a second conductive post extending through the dielectric device stage and the conductive device stage, the second conductive post being connected to a ground node; as well as A ground plate is formed in a portion of the conductive device level electrically connected to the second conductive pillar and horizontally overlapping the capacitor node plate.

17. The method of claim 15, wherein forming the transistor channel of each cell comprises: forming a semiconductor ring at least partially surrounding a corresponding conductive data line post; as well as A capacitor node plate is formed, the capacitor node plate comprising a conductive ring at least partially surrounding a respective semiconductor ring, both the semiconductor ring and the conductive ring being electrically isolated from the at least one conductive device level.

18. The method of claim 17, wherein each transistor gate comprises a conductive ring surrounding and electrically insulated from the conductive data line post and electrically insulated from the semiconductor ring and the ground post.

19. The method of claim 15, wherein the capacitor area of ​​each of the memory cells is defined by a horizontal overlap area between a corresponding node plate and a portion of the at least one conductive device level surrounding the at least one cavity in which the at least one transistor gate is formed.

20. The method of claim 15, wherein the node plate comprises doped polysilicon.

21. The method of claim 19, wherein the cavities formed in the dielectric device level and the conductive device level are each lined with a material having a dielectric constant greater than 3.

6.

22. The method of claim 15, wherein each device level comprises the dielectric device level sandwiched between two conductive device levels, and wherein forming the memory cell comprises forming a dual gate of the transistor.

23. The method of claim 15, wherein each device level comprises only one conductive device level adjacent to the dielectric device level, and wherein the memory cell comprises a single gate.

24. The method of claim 15, further comprising: forming a plurality of vertical dummy pillars, wherein the plurality of vertical dummy pillars are arranged alternately with the conductive data line pillars along the first row; as well as A plurality of conductive rings are formed around the dummy pillars to form corresponding portions of the access lines.

Images