Configurable wideband split lna

Abstract

Methods and apparatuses are disclosed that address the design of wideband LNAs with gain modes. The disclosed teachings can be used to reconfigure RF receiver front-ends to operate in various applications that impose stringent and mutually conflicting requirements. Also disclosed are wideband and narrowband input and output matching with gain modes using the same hardware and combination of switching networks. The described methods and apparatuses also address carrier aggregation requirements and provide solutions that can be used in both single mode and split mode operations.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 242,870 and No. 16 / 242,883, filed January 8, 2019, and is a continuation of U.S. Patent Application No. 16 / 242,870 and No. 16 / 242,883, filed January 8, 2019, which are incorporated herein by reference in their entirety. This application relates to U.S. Application No. 15 / 342,016, filed November 2, 2016, entitled “Source Switched Split LNA” (now U.S. Patent No. 9,973,149, published May 15, 2018), which is incorporated herein by reference in its entirety. Background Technology (1) Technical Field

[0004] This disclosure relates to low-noise amplifiers (LNAs), and more specifically, to methods and apparatus for designing broadband LNAs with gain modes and broadband separation. (2) Background Technology

[0006] The exponential growth of mobile data and the emergence of new standards have posed significant challenges to the design and architecture of radio frequency (RF) receiver front-ends. Figure 1 Examples of frequency band specifications are shown, including the Ultra High Frequency (UHB) band defined by the 5G New Radio (NR) standard. Such bands cover a wide frequency range. More specifically, see [reference needed]. Figure 1 The frequency band n77 shown covers a 900MHz frequency range from 3.2GHz to 4.1GHz. For comparison, the relatively wide 4G LTE band B41 covers 2.5GHz to 2.69GHz, while the existing UHB LTE bands B42 and B43 cover approximately 200MHz. Based on newer wireless communication standards, RF receiver front-end designs face the challenge of meeting conflicting and demanding requirements on performance metrics such as data rate, gain, gain flatness, linearity, noise figure (NF), receiver sensitivity, and power consumption. In addition to meeting these requirements, such designs are expected to be cost-effective with a small footprint. Adding to this challenge is backward compatibility. In other words, as an example, systems designed to accommodate broadband will still need to be compatible with older narrowband requirements.

[0007] Another challenge is the ability to handle variable signal strength received at the front end of a wireless RF receiver, which typically has a wide dynamic range. This is because signal strength depends on how far or near the receiver is from the nearest base station. To accommodate such a large dynamic range, LNAs are usually designed with adjustable gain or various gain modes.

[0008] Historically, to meet the conflicting and stringent requirements described above, circuits and systems have been designed with multiple switches, filters, and LNAs. In such circuits, individual LNAs, switches, and filter banks are dedicated to different subsets of the frequency bands to be supported, for example. While such an approach may be feasible, it has significant drawbacks, such as area, component count, and cost-effectiveness. For example, designs using multiple LNAs require a large area allocation on the integrated circuits (ICs) used to manufacture the LNAs. The cost of an IC is proportional to its size (i.e., the amount of “real estate” required). Therefore, relying on multiple narrowband LNAs significantly increases the overall size and cost of the IC.

[0009] Description of concepts and terms used throughout this disclosure

[0010] The following sections define and describe some concepts employed by the methods and devices presented later in this disclosure. Some relevant performance trade-offs are also discussed, highlighting the implications of designing for demanding / conflicting requirements when designing RF receiver front-ends. Exemplary prior art architectures are also described to further illustrate the shortcomings of existing solutions to the challenges encountered in designing high-performance broadband RF receiver front-ends.

[0011] Throughout this disclosure, the term "intra-band non-contiguous" will be used to describe carrier aggregation combinations in which component carriers belong to the same operating frequency band but are separated by one or more gaps. In other words, such a carrier aggregation scheme combines channels that are not adjacent to each other in the same frequency band.

[0012] A typical RF receiver front-end includes one or more receiver chains, each comprising an LNA followed by a down-conversion block, which essentially includes a local oscillator incorporating a low-pass filter. Each such receiver chain performs a separate down-conversion, essentially consisting of a local oscillator incorporating a low-pass filter. Throughout this disclosure, the term "single-mode" will be used to describe the case where the receiver LNA is connected to only one down-conversion block. This contrasts with the term "split-mode," which will be used throughout this disclosure to describe the case where the receiver LNA is connected to two or more down-conversion blocks.

[0013] Throughout this disclosure, the term "source follower" will be used to describe one of the basic single-stage field-effect transistor (FET) amplifier topologies, which are typically used as voltage buffers. In this circuit, the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output). In such a circuit, the output impedance seen from the source of the FET is equal to... Where g m This represents the transconductance of the FET device. It is known that a source follower configuration is essentially an impedance transformer, providing improved and largely frequency-independent output matching. This is why the source follower is a suitable architecture for broadband applications.

[0014] As is known in the art, in RF systems, bandwidth is sometimes defined as percentage bandwidth, which is defined as the ratio (percentage) of the absolute bandwidth to the highest frequency at which such RF system operates. A performance metric for an RF amplifier associated with bandwidth is represented by the gain flatness over a specified bandwidth. Gain bandwidth is typically specified in dB and indicates the gain variation over the frequency range of operation. Throughout this disclosure, the terminology is as follows:

[0015] • "Narrowband" will be used to describe applications in which the frequency range in which they operate represents less than 7.5% of the bandwidth. An example of such a case is band 42 of the Long Term Evolution (LTE) standard;

[0016] • "Extended Narrowband" will be used to describe applications in which the frequency range of operation represents a percentage of bandwidth between 7.5% and 15%. An example of such a case is the NR79 band of the 5G New Radio (NR) standard; and

[0017] • "Broadband" will be used to describe applications in which the frequency range in which the bandwidth is less than 15% to 25%. An example of such a case is the NR77 band of the 5G New Radio (NR) standard.

[0018] Given the design challenges described in the previous section, input-output matching (represented by parameters S11 and S22) and gain flatness over bandwidth are key performance indicators, along with maintaining minimum NF, high gain, and linearity. Additionally, a low-gain mode requiring high linearity is highly desirable. Lower power consumption can be achieved when operating in a lower-gain mode.

[0019] Throughout this disclosure, the term "de-Qing" will be used to describe design techniques in which the quality factor (Q) of a circuit is reduced to improve some other performance metrics. For example, in a typical LNA architecture, Q-de-Qing can be performed on the load to achieve the desired gain flatness over a wider bandwidth at the cost of reduced gain. De-Qing of an LC network is typically performed by increasing the resistance of such a network (resulting in lower gain). The same concept can be applied to the input of a typical LNA architecture, thereby achieving wider input matching by reducing the quality factor of the input matching network at the expense of NF and gain.

[0020] For broadband applications, various methods can be used to design wider output matching:

[0021] • Q reduction: As mentioned above, such a technique results in lower gain;

[0022] The design will provide higher bandwidth multi-stage passive output matching. However, this approach will require high-Q inductors; and

[0023] • Source follower topologies can be used without sacrificing gain while achieving improved linearity. However, this may not be an ideal solution when lower gain and therefore lower power consumption are required.

[0024] For the receiver front-end input, resistive negative feedback networks are typically used to achieve wider input matching, which provides a better trade-off between NF, gain, and S11 bandwidth. In the following sections, to further illustrate the various techniques and associated trade-offs described above, a typical prior art LNA architecture is described.

[0025] Figure 2A A prior art RF receiver front-end (200A) is shown. The RF receiver front-end (200A) includes amplifying cascode transistors (T1, T2), an input matching circuit (201), and an output matching network (202). The input matching network (201) includes an input inductor (L1) and a degraded inductor (L2). The output matching network (202) includes an inductor (Ld), a resistor (Rd), and a capacitor (C). 匹配 As previously mentioned, a resistor (Rd) is used to reduce the Q of the output matching network (202) to address bandwidth requirements. However, this results in lower gain, thus impacting the overall system performance of the receiver implementing such a front-end architecture. At the input, Q reduction can be performed by adjusting the size of a transistor (T1), which can regulate NF and gain.

[0026] Figure 2B It shows the relationship with Figure 2AThe proposed RF receiver front-end (200A) offers better performance than the prior art RF receiver front-end (200B) in broadband applications. The RF receiver front-end (200B) includes a feedback resistor (Rf), which is turned on by closing a switch (S1) and is used to provide wider bandwidth operation. Output matching is now achieved using a source follower circuit (201) comprising a transistor (T3) and an inductor (LSF). As previously mentioned, the output impedance of the source follower is equal to... Where g m This represents the transconductance of transistor (T3). Such transconductance is virtually frequency-independent, thus providing improved output matching for broadband applications.

[0027] Figure 2C A prior art RF receiver front-end (200C) using multi-stage output matching to meet extended narrowband requirements (as defined above) is also shown. The RF receiver front-end (200C) includes a multi-stage output matching network (203) with multiple reactive elements (L1, L2, Ld, L4, C1, C2, C3). The output matching network (203) is essentially a higher-order filter with multiple poles, thus providing greater flexibility for designing wider bandwidths. However, this architecture has the disadvantage of being bulky and requiring a larger area to implement.

[0028] Figure 2D This provides a qualitative summary of its use in broadband applications. Figures 2A to 2C A comparison table (200D) of the overall performance of the architectures is shown. For comparison purposes, gain flatness, area, linearity, and current consumption requirements in typical broadband applications are shown, along with the performance of each architecture evaluated based on these requirements.

[0029] Reference Figures 2A to 2C The architectures shown do not offer multiple gain modes. Each architecture uses a specific approach to address specific requirements by trading off other system performance metrics.

[0030] In view of the foregoing, a cost-effective RF receiver front-end design is highly desirable, which uses a minimal number of electronic components and thus provides a small footprint, while meeting the aforementioned stringent and conflicting requirements related to performance metrics such as gain, gain flatness, gain mode, frequency response (NF), linearity, multi-bandwidth, wide received signal dynamic range, and power consumption. The methods and apparatus described in this disclosure address such needs and provide solutions to the aforementioned technical problems.

[0031] In RF wireless applications, it is common for transceivers, such as receivers in cellular phones, to simultaneously receive signals transmitted across multiple supported frequency ranges. Signals from each supported frequency range are combined (or “aggregated”) to be transmitted together to the receiver simultaneously. Carrier aggregation presents yet another existing challenge for the design of today's RF receiver front-ends. (Return to References) Figure 1 When designing such an RF receiver front-end, carrier aggregation can be translated into dual connectivity, which can be defined, by way of example, as enabling the device to operate simultaneously on both the 4G LTE and 5G NR bands. Further reference... Figure 1 Since channel B42 is included in both the frequency range of band n77 and the frequency range of band n78, the corresponding carrier aggregation scheme is similar to the in-band discontinuous case and can be handled in the front-end module.

[0032] In carrier aggregation, for performance optimization purposes, it is desirable to transmit each supported frequency range via a separate receiver chain optimized for that range. Each such receiver chain performs its own down-conversion, which essentially includes a local oscillator incorporating a low-pass filter. This is highly desirable, especially for discontinuous frequency bands where large gaps may exist between them.

[0033] Historically, the solution to such design challenges has been to design multiple separate RF front-ends, including antennas, filters, and LNAs to handle each chain, and similar to what has been described previously. Such solutions are not optimal and are almost daunting because they require more physical space to implement, which means more form factor constraints and higher costs.

[0034] Figure 2E A receiver front-end (200E) based on the teachings of the above-incorporated application is shown. The RF receiver front-end (200E) includes two LNAs (205, 206). Switches (S1, ..., S4) are used to select any one or both of the LNAs (205, 206). In other words, the RF receiver front-end (200E) can operate in single-mode or split-mode. Although Figure 2E The architecture shown is a solution for the aforementioned carrier aggregation, but it still cannot fully meet the stringent and conflicting requirements described in this section, such as high frequency and wide bandwidth. This is mainly due to the capacitive load at the input and the required bandwidth for input and output matching. In such a split architecture, splitting is performed at the LNA input for output isolation purposes. This can lead to a degradation in NF performance. Therefore, a new design is desired to support the wide bandwidth and higher frequencies of the NR standard while addressing the carrier aggregation requirements.

[0035] The methods and apparatus described in this disclosure address the design challenges and requirements described throughout this section and provide solutions to the problems while adapting to carrier aggregation requirements imposed, for example, by the latest standards such as 5G NR. Summary of the Invention

[0036] According to a first aspect of this disclosure, a radio frequency (RF) receiver front end is provided, comprising: a reconfigurable low-noise amplifier (LNA) block including a reconfigurable cascode amplifier and an LNA block output; an input matching network; an output matching network including a configurable passive output matching network and a source follower amplifier stage; and a switching network including switches within the input matching network, the LNA block, and the output matching network, wherein the RF receiver front end is adapted to receive an input signal at an input of the RF receiver front end and deliver a corresponding output signal at an output of the RF receiver front end capable of being connected to a load; and the switching network is structured to configure or reconfigure the input matching network, the LNA block, the LNA block output, and the output matching network to at least adjust the gain and bandwidth of the RF receiver front end.

[0037] According to a second aspect of this disclosure, a radio frequency (RF) receiver front end is provided, comprising: an input terminal and a plurality of output terminals; a reconfigurable low-noise amplifier (LNA) block having an input matching network and a plurality of output matching networks; a switching network including switches within the input matching network and the plurality of output matching networks; wherein each input matching network includes an inductor and a capacitor; the LNA block includes a cascode amplifier stage; each output matching network includes a resistor, a capacitor, an inductor, and a first source follower amplifier stage; each output matching network is connected to a corresponding output terminal among the plurality of output terminals; and the switching network is structured to configure or reconfigure the input matching network, the cascode amplifier stage, and the plurality of output matching networks.

[0038] According to a third aspect of this disclosure, a method for controlling an RF receiver front end is disclosed, comprising: providing an input matching network; providing an LNA block having an LNA block output; providing an output matching network; providing a switching network including switches within the input matching network, the LNA block, and the output matching network; and using the switches to configure or reconfigure the input matching network, the LNA block, the LNA block output, and the output matching network to at least adjust the gain and bandwidth of the RF receiver front end.

[0039] According to a fourth aspect of this disclosure, a method for controlling an RF receiver front end is disclosed, comprising: providing an input terminal and a plurality of output terminals; providing an LNA block having a cascode amplifier stage including a plurality of cascode transistors; providing a plurality of output matching networks; providing a switching network including switches within the input matching network, the LNA block, and the output matching networks; connecting each of the plurality of output matching networks to a corresponding output terminal among the plurality of output terminals; during a first operating mode: using the output matching network and the switches within the LNA block to perform the following operations: enabling a single cascode transistor among the plurality of cascode transistors and the corresponding output matching network; disabling the remaining cascode transistors among the plurality of cascode transistors and the corresponding output matching network; and receiving an input signal at the input terminal and generating a corresponding output signal at the output terminal among the plurality of output terminals; during a second operating mode: using the output matching network and the switches within the LNA block to enable two or more cascode transistors among the plurality of cascode transistors and the corresponding output matching network; and receiving an input signal at the input terminal and generating two or more corresponding output signals at two or more output terminals among the plurality of output terminals.

[0040] According to one aspect of this disclosure, a radio frequency (RF) receiver front end is provided, comprising: a reconfigurable low-noise amplifier (LNA) block having an input matching network and an LNA block output; an output matching network; and a switching network; wherein the RF receiver front end is connectable to a load; the switching network is connected to the input matching network, the LNA block, and the output matching network; the RF receiver front end is configured to receive an input signal at an input terminal of the RF receiver front end and deliver a corresponding output signal at an output terminal of the RF receiver front end connected to a load; and the switching network is configured to configure or reconfigure the RF receiver front end such that the performance characteristics of the RF receiver front end meet one or more requirements.

[0041] According to another aspect of this disclosure, a method for amplifying an input signal received at an RF receiver front end is disclosed, comprising: providing an input matching network; providing an LNA block having the input matching network and an LNA block output; providing an output matching network; and configuring the input matching network, the LNA block, and the output matching network such that the RF receiver front end meets one or more requirements.

[0042] According to another aspect of this disclosure, a radio frequency (RF) receiver front end is provided, including: an input terminal and a plurality of output terminals; a reconfigurable low noise amplifier (LNA) block having an input matching network and a plurality of electronic components, each electronic component having an electronic component output terminal; an output matching network having a plurality of output matching elements; and a switching network; wherein each of the plurality of output matching elements is connected to a corresponding output terminal of the plurality of output terminals. The switch network is connected to the input matching network, the LNA block, and the output matching network; during a first operating mode: i) in a first configuration, the switches of the switch network: enable a single electronic component among the multiple electronic components and the corresponding output matching component; disable the remaining electronic components among the multiple electronic components and the corresponding output matching components; ii) the RF receiver front end is configured to receive an input signal at the input and generate a corresponding output signal at the output of the multiple outputs; and during a second operating mode: i) in a second configuration, the switches of the multiple switches enable two or more electronic components among the multiple electronic components and the corresponding output matching component among the multiple output matching components; ii) the RF receiver front end is configured to receive an input signal at the input and generate two or more corresponding output signals at two or more outputs among the multiple outputs.

[0043] According to another aspect of this disclosure, a radio frequency (RF) receiver front end is provided, comprising: a plurality of input terminals and a plurality of output terminals; a reconfigurable low-noise amplifier (LNA) block having an input matching network and a plurality of electronic components; an output matching network having a plurality of output matching elements; and a switching network; wherein the input matching network includes a plurality of input matching elements connected to respective input terminals; each of the plurality of output matching elements is connected to a respective output terminal of the plurality of output terminals; the switching network is connected to the input matching network, the LNA block, and the output matching network; and the switching network is configured or reconfigured to: configure or reconfigure the plurality of input matching elements to receive one or more input signals from the plurality of input terminals; and configure or reconfigure the plurality of electronic components and the respective output matching elements to generate two or more output signals at two or more output terminals.

[0044] According to another aspect of this disclosure, a method for amplifying an input signal received at the front end of an RF receiver is disclosed, comprising: providing an input terminal and a plurality of output terminals; providing an LNA block having an input matching network and a plurality of electronic components; providing an output matching network having a plurality of output matching elements; connecting each of the plurality of output matching elements to a corresponding output terminal among the plurality of output terminals; providing a switch network connected to the LNA block, the input matching network, and the output matching network; configuring the switches of the switch network during a first operating mode to: enable a single electronic component among the plurality of electronic components and a corresponding output matching element; disable the remaining electronic components among the plurality of electronic components and their corresponding output matching elements; and receive an input signal at the input terminal and generate a corresponding output signal at an output terminal among the plurality of output terminals; and configuring the switches of the switch network during a second operating mode to: enable two or more electronic components among the plurality of electronic components and their corresponding output matching elements; and receive an input signal at the input terminal and generate two or more corresponding output signals at two or more output terminals among the plurality of output terminals.

[0045] Further aspects of this disclosure are provided in the specification, drawings and claims of this application. Attached Figure Description

[0046] Figure 1 Examples of frequency band specifications defined by the 5G New Radio (NR) standard are shown.

[0047] Figure 2A This demonstrates a prior art RF receiver front end that is better suited for narrowband applications.

[0048] Figure 2B Another existing RF receiver front-end architecture is shown.

[0049] Figure 2C A prior art RF receiver front end using multi-stage output matching is shown.

[0050] Figure 2D This shows a summary of usage in broadband applications. Figures 2A to 2C A comparison table of the overall performance of the architectures shown.

[0051] Figure 2E The prior art RF receiver front-end architecture is shown.

[0052] Figure 3 An electronic circuit according to an embodiment of the present disclosure is shown.

[0053] Figure 4A Another electronic circuit according to an embodiment of this disclosure is shown.

[0054] Figure 4B A switch network according to an embodiment of this disclosure is shown.

[0055] Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9 Various electronic circuits according to embodiments of this disclosure are shown.

[0056] Figure 5B , Figure 6B , Figure 7B and Figure 8B A table showing the switch states according to embodiments of this disclosure is provided.

[0057] Figure 10 A high-level flowchart illustrating the reconfigurability of an RF receiver front-end designed in accordance with the teachings of this disclosure is shown.

[0058] Figures 11 to 14 An electronic circuit according to an embodiment of the present disclosure is shown.

[0059] Figures 15 to 16 A multi-input multi-output electronic circuit according to another embodiment of the present disclosure is shown. Detailed Implementation

[0060] Throughout this disclosure, the term "node" will be used to describe any point on a circuit where two or more circuit elements are connected or adapted to be connected. Although nodes will be graphically represented as points in this disclosure, those skilled in the art will understand that a node can also represent a portion of a line or connection between elements or circuit devices, and not just a single point.

[0061] Figure 3An electronic circuit (300) according to an embodiment of the present disclosure is shown. The electronic circuit (300) includes an RF receiver front-end (310) that is connected to an input circuit (360) at an RF receiver front-end input (361) and to a load (350) at an RF receiver front-end output (351). The RF receiver front-end (310) includes an LNA block (322), an output matching network (330), and a switching network (340). The LNA block (322) includes an input matching network (321). The switching network (340) is connected to the output matching network (330), the LNA block (322), and the input matching network (321). The RF receiver front-end (310) is configured to receive an input signal (Vin) from the input circuit (360) at the RF receiver front-end input (361) and generate a corresponding output signal across the load (350) at the RF receiver front-end output (351).

[0062] Reference Figure 3 The switching network (340) includes one or more switches for configuring / reconfiguring the RF receiver front-end (310) to meet different and potentially conflicting requirements imposed by various applications. In other words, by turning on or off a subset of such switches, certain electronic components that are part of the input matching network (321), LNA block (322), and / or output matching network (330) can be accessed and removed from the signal path from the RF receiver front-end input (361) to the RF receiver front-end output (351), making the RF receiver front-end (310) suitable for meeting certain design requirements. By way of example, and not limitation, the RF receiver front-end (310) can be used in a first application where power saving is of paramount importance. In such an application, the RF receiver front-end (310) can be configured to switch to lower gains more frequently to meet overall power consumption requirements. This contrasts with a second exemplary application where a signal with the highest possible strength is highly desirable. In this case, the RF receiver front-end (310) can be configured to adapt to provide the highest data rate with the highest fidelity signal. To do this, and compared to the first application, different groups of switches can be turned on or off, thereby connecting and disconnecting different electronic components to meet the requirements imposed by the second application. Those skilled in the art will understand that the methods and apparatus designed according to the teachings of this disclosure allow for greater flexibility to accommodate applications that impose entirely different requirements using virtually the same design. Exemplary embodiments of this disclosure will be described below to further illustrate this concept.

[0063] Figure 4AAn electronic circuit (400A) according to an embodiment of this disclosure is shown. The electronic circuit (400A) includes an output matching network (430) and an LNA block (422) including an input matching network (421). An RF receiver front end (410) is... Figure 3 An exemplary implementation of the RF receiver front-end (310). In other words, the input matching network (421), the LNA block (422), and the output matching network (430) are their corresponding parts, i.e. Figure 3 An exemplary implementation of the input matching network (321), LNA block (322), and output matching network (330) is shown. The RF receiver front end (410) can be connected to a load (350). For simplicity, the connection of the switching network (440) to the rest of the circuit is not shown. Figure 4A As shown, the RF receiver front end (410) includes several connection points represented by nodes (a, a1, b, b', b”, c, c1, ..., 1, l'). Nodes whose names contain the same letter correspond to each other. For example, nodes (a, a') can be connected to each other using switches. As another example, depending on the position of the corresponding single-pole double-throw switch, node (b) can be connected to node (b') or (b”). As will be explained below, switches used for such purposes can be part of a switch network (340). The switch network can be configured in different ways to serve different applications with various and sometimes conflicting requirements.

[0064] Reference Figure 4A :

[0065] The feedback resistor (Rf) can be connected and disconnected by connecting and disconnecting nodes (a, a'), respectively. The feedback resistor (Rf) can be connected to provide a wider bandwidth of input matching. According to embodiments of this disclosure, the feedback resistor (Rf) can be part of a feedback network that includes resistors and reactive elements, such as inductors and / or capacitors.

[0066] Depending on the required output matching, larger or smaller inductors can be used by connecting node (b) to node (b') or node (b”) respectively. According to other embodiments of this disclosure, any one or combination of inductors (Ld1, Ld2) can be replaced by a variable inductor.

[0067] The transistor (T3) can be connected / disconnected by nodes (i, i'). When the transistor (T3) is connected, this combination of transistor and current source (Io) provides a source follower configuration, and this source follower can be bypassed by connecting or disconnecting nodes (i, i', j, j', and kk'), as shown below. Figure 5A (Source follower activation) and Figure 6A (Source follower bypass) is shown. As previously mentioned, this configuration is used when a wider bandwidth output matching is desired while minimizing the impact on gain and linearity. In narrower bandwidth applications where the transistor (T3) may not be needed, the gate of the transistor (T3) is connected to ground via the connection node (j, j') to minimize power consumption.

[0068] As previously mentioned, for broadband applications, the resistor (Rd) can be connected via connection nodes (c, c'). Therefore, wider bandwidth output matching is achieved at the expense of gain.

[0069] • A combination or subset of capacitors (C1, C2, C3) and inductors (L4) can be connected to achieve broadband operation using only passive components. This essentially represents a multi-stage passive output matching network.

[0070] • Nodes (l, l') can be connected / disconnected to achieve narrow / wide bandwidth input matching. When nodes (l, l') are connected, the combination of capacitor (C3) and the gate-source capacitance (Cgs) of transistor (T3) with inductors (L1, L2) and feedback resistor (Rf) forms an input matching network (421). Therefore, switching the feedback resistor (Rf) and / or capacitor (C4) provides two different mechanisms to provide wider or narrower bandwidth input matching depending on the desired requirements.

[0071] • The RF receiver front end (410) can be configured to receive voltages (Vd1, Vd2) for biasing purposes.

[0072] Figure 4B A switch network (440) according to an embodiment of the present disclosure is shown. The switch network (440) represents Figure 3 and Figure 4A An exemplary implementation of the switch network (340) includes one or more switches (S1, ..., S12). The switch network (440) also includes a plurality of nodes, shown as black dots, which are connected to corresponding nodes of the electronic circuit (400A). The connections between the nodes of the switch network (440) and the corresponding nodes of the electronic circuit (400A) are shown with dashed arrows. (Refer to...) Figures 4A to 4BAnd, as an example, switch (S1) can connect or disconnect node (a, a1), switch (S2) can connect or disconnect node (b, b') or (b'b"), switch (S3) can connect or disconnect node (c, c'), etc. As another example, as previously mentioned, the configuration of switches (S1, ..., S12) depends on the application and therefore on the desired set of requirements to be met. According to embodiments of this disclosure, the configuration of switches (S1, ..., S12) can be changed during operation of the circuit. According to embodiments of this disclosure, the switch network (440) may include control circuitry (not shown) to control the state of switches (S1, ..., S12).

[0073] According to the implementation of this disclosure, Figure 5A An electronic circuit (500A) including an RF receiver front-end (510) is shown, which is based on... Figure 5B The switch configuration table (500B) shows the contents of the configuration. Figure 4A The RF receiver front end (410). As shown in the switch configuration table (500B), the switches (S1, ..., S12) of the switch network (540) are mentioned in the top row, where the bottom row shows the state of the switch and the middle row shows the switch node ID. In other words, the input matching network (521), LNA block (522), and output matching network (530) represent Figure 4A Their respective corresponding parts (421, 422, 430), each corresponding part according to Figure 5B The table (500B) configuration. In view of what has been described throughout the disclosure, the RF receiver front end (510) is configured to use a source follower configuration that provides optimal gain flatness over broadband and to use a large inductor (a series combination of Ld1 and Ld2) to meet broadband requirements.

[0074] According to other embodiments of this disclosure Figure 6A An electronic circuit (600A) including an RF receiver front-end (610) is shown, which is based on... Figure 6B The switch configuration table (600B) shows the contents of the configuration. Figure 4A The RF receiver front end (410). As shown in the switch configuration table (600B), the switches (S1, ..., S12) of the switch network (640) are mentioned in the top row, where the bottom row shows the switch status and the middle row shows the switch node ID. In other words, the input matching network (621), LNA block (622), and output matching network (630) represent Figure 4A Their respective corresponding parts (421, 422, 430), each corresponding part according to Figure 6BThe table (600B) configuration. (and) Figure 5A Compared to the RF receiver front-end (510), in the RF front-end (610), the source follower is removed (nodes i' and k' are disconnected, while node j' is connected), and output matching is achieved using passive components. In other words, a combination of inductors (Ld1, Ld1+Ld2, L4) and capacitors (C1, C2, C3) provides a multipole filter that can be designed to adapt to output matching according to desired requirements. Furthermore, the gate of transistor (T3) is connected to ground for lower current consumption. (Return to Reference) Figure 2D Comparison table and Figures 2B to 2C As can be seen from the architecture shown, the RF receiver front end (510) can provide improved gain flatness and linearity relative to the RF receiver front end (610) when power may be increased, depending on the desired performance of other parameters with the flexibility to choose how to optimize.

[0075] According to other embodiments of this disclosure Figure 7A An electronic circuit (700A) including an RF receiver front-end (710) is shown, which is based on... Figure 7B The switch configuration table (700B) shows the contents of the configuration. Figure 4A The RF receiver front end (410). As shown in the switch configuration table (700B), the switches (S1, ..., S12) of the switch network (740) are mentioned in the top row, where the bottom row shows the switch status and the middle row shows the switch node ID. In other words, the input matching network (721), LNA block (722), and output matching network (730) represent Figure 4A Their respective corresponding parts (421, 422, 430), each corresponding part according to Figure 7B The table (700B) configuration. Based on what has been described throughout this disclosure, the RF receiver front end (710) is configured for use in narrow-band applications. In this configuration, narrow-band output matching is achieved by removing capacitors (C1, C2), inductor (L4), resistor (Rd), and transistor (T3). By using a smaller inductor (e.g., using only (Ld1 and removing Ld2)) in combination with capacitor (C3), narrow-band operation is optimized for the desired frequency band. Regarding input matching, the feedback resistor (Rf) is removed, and capacitor (C4) is connected to optimize input matching performance for narrow-band operation.

[0076] According to other embodiments of this disclosure Figure 8A An electronic circuit (800A) including an RF receiver front-end (810) is shown, which is based on... Figure 8B The switch configuration table (800B) shows the contents of the configuration. Figure 4A The RF receiver front end (410). As shown in the switch configuration table (800B), the switches (S1, ..., S12) of the switch network (840) are mentioned in the top row, where the bottom row shows the switch status and the middle row shows the switch node ID. In other words, the input matching network (821), LNA block (822), and output matching network (830) represent Figure 4A Their respective corresponding parts (421, 422, 430), each corresponding part according to Figure 8B The table (800B) configuration. Given what has been described throughout the disclosure, the RF receiver front end (810) is configured for use in a wideband application, but in a lower gain mode. In this configuration, wideband output matching is achieved by reducing Q, for example, by connecting a feedback resistor (Rd). As previously discussed, this results in lower gain. Wideband input matching is achieved by connecting a feedback resistor, following a similar mechanism as previously discussed. See reference... Figure 4A , 5A In the embodiments shown in 8A, one or more passive components (inductors or capacitors) can be variable to provide further flexibility to meet different requirements.

[0077] Further reference Figures 4A to 8B Those skilled in the art will understand that by reconfiguring the same circuit, the teachings of this disclosure can be used to meet the different requirements imposed by various applications.

[0078] Figure 9 An electronic circuit (900) including an RF receiver front-end (910) according to an embodiment of the present disclosure is shown. The RF receiver front-end (910) includes: an LNA block (922) including an input matching network (921); and an output matching network (930), wherein the input matching network (921), the LNA block (922), and the output matching network (930) are Figure 3 An exemplary implementation of the input matching network (321), LNA block (322), and output matching network (330). Regarding... Figures 4A to 8A The concepts discussed in the implementation methods also apply here. In other words, nodes represented by the same letters correspond to each other, and by connecting or disconnecting the corresponding nodes, various components of the electronic circuit (900) can be connected or removed, thereby providing flexibility to adapt to the stringent and potentially conflicting requirements imposed by different applications. Figure 9 As shown, the output matching network (930) includes variable resistors (Rd) and variable capacitors (C1, ..., C5) to provide additional flexibility when designing such a circuit for different applications. (See reference...) Figure 4A and Figure 9 It can be noted that Figure 4A The current source (Io) is now replaced by an inductor (Lsf). As an example, when nodes (n, n') and (k, k') are connected by closing the corresponding switches of nodes (n, n') and (k, k'), the inductors (Ld1, Lsf) are actually connected in parallel with each other, resulting in a smaller overall inductance. Such a configuration can be used in high-performance narrow-band applications when high-quality matching is required by using a smaller inductance. In such applications, single-stage LC matching can be achieved by connecting nodes (m, m') and (f, f') with each other by closing the corresponding switches. Continuing with the same scenario, those skilled in the art will understand that, due to the presence of variable capacitors (C1, C4), it is possible to adjust to different frequency bands to obtain high-quality output matching. Those skilled in the art will also understand that, without departing from the scope and spirit of the invention, each passive element may comprise a series and / or parallel combination of elements of the same type. As an example, the variable capacitor (C1) may comprise a series and / or parallel combination of capacitors or a combination thereof. This also applies to... Figure 9 All inductors and resistors that make up the electronic circuit (900). The different exemplary switch configurations previously described using switch configuration tables (500B, 600B, ..., 800B) also apply here. Figure 9 Electronic circuit (900).

[0079] Reference Figures 4A to 9 It is conceivable that, according to an implementation of this disclosure, the following would be present:

[0080] • A cascode configuration using transistors (T1, T2) can include one or more transistors.

[0081] Transistors (T1, T2, T3) may include field-effect transistors (FETs) or metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0082] • The switching network can be composed of field-effect transistors (FETs) or metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0083] Depending on the requirements, a switch network may include one or more switches.

[0084] The components of such an implementation can be implemented on the same chip or on separate chips.

[0085] The combination of transistor (T3) and current source (Io) or degraded inductor (Lsf) can be implemented according to common source or common gate configuration.

[0086] Figure 10 A high-level flowchart illustrating the reconfigurability of an RF receiver front-end designed according to the teachings of this disclosure and controlled by external control commands or by internal commands generated in response to internal conditions is shown. As shown, receiving an input signal, step (1001). Depending on bandwidth requirements, step (1002), the RF receiver front-end is configured as narrowband or wideband, as shown in steps (1003, 1004). Furthermore, depending on gain requirements, as shown in step (1005), the RF receiver front-end is configured for low gain or high gain, as shown in steps (1006, 1007), and then an output signal is generated. This is a flowchart based on exemplary requirements such as frequency range and gain mode, merely illustrating the design flexibility of using the same hardware that can accommodate various requirements. As detailed above, those skilled in the art will understand that the disclosed teachings can also be used to configure an RF receiver front-end to accommodate various requirements other than gain or frequency range.

[0087] Figure 11 An electronic circuit (1100) according to an embodiment of this disclosure is shown. The electronic circuit (1100) and... Figure 3 The electronic circuit (300) has some similarities and provides the same characteristics as previously detailed. Figure 3 All the benefits associated with the electronic circuit (300). In addition, the electronic circuit (1100) is designed to operate in a variety of single and split modes to address carrier aggregation requirements as previously described in examples using the 5G NR standard.

[0088] Reference Figure 11 The electronic circuit (1100) includes an RF receiver front-end (1110) connectable to an output load (1150) having multiple load elements (L1, ..., Ln). The electronic circuit (1100) is configured to receive an input signal at an input terminal (in) and provide multiple corresponding output signals at output terminals (out1, ..., outn). The RF receiver front-end (1110) includes an LNA block (1122), an output matching network (1130), and a switching network (1140). The LNA block (1122) includes an input matching network (1121) connected to multiple electronic elements (E1, ..., En). The output matching network (1130) includes multiple output matching elements (M1, ..., Mn) connected to corresponding electronic elements (E1, ..., En). Figure 11As shown, signal splitting occurs at a split point (1123), which is essentially the output of the input matching network (1121). According to embodiments of this disclosure, and depending on the operating mode, the signal at the split point (1123) is divided among multiple electronic components (E1, ..., En). A switching network (1140) is connected to the output matching network (1130), the LNA block (1122), and the input matching network (1121), and provides information regarding... Figure 3 The same functionality described in the switching network (340). According to embodiments of this disclosure, the electronic circuit (1110) can be configured to operate in various single-mode operations, connecting the input (in) to any one of the outputs (out1, ..., outn). According to other embodiments of this disclosure, the electronic circuit (1110) can also be configured to operate in various split-mode operations, connecting the input (in) to any two or more of the outputs (out1, ..., outn). Exemplary implementations of the electronic circuit (1110) according to the teachings of this disclosure will be presented below.

[0089] Figure 12 An electronic circuit (1200) according to an embodiment of this disclosure is shown. The electronic circuit (1200) is designed to be configured for both single-mode operation and split-mode operation depending on the state of the switches (S1, ..., S4). (Refer to...) Figures 11 to 12 The input matching network (1221) is Figure 11 An exemplary implementation of the input matching network (1121) is provided. The electronic circuit (1200) also includes two output matching networks (1230a, 1230b), each of which can be... Figure 11 An exemplary implementation of any one of the output matching elements (M1, ..., Mn). In other words, the combination of the two output matching networks (1230a, 1230b) is Figure 11 The corresponding part of the output matching network (1130). Similarly, each of the transistors (T2a, T2b) can be an exemplary implementation of any of the electronic components (E1, ..., En). Furthermore, each of the resistors (RL, RL') can represent... Figure 11 Any one of the load elements (L1, ..., Ln).

[0090] Further reference Figure 12 The transistors (T1, T2a) or combinations of transistors (T1, T2b) each represent a cascode configuration, wherein the splitting begins at the drain of transistor (T1), and the drain of transistor (T1) essentially represents Figure 11The corresponding part of the split point (1123). The electronic circuit (1200) is configured to receive an input signal from the input terminal (in) and generate an output signal at one or both of the output terminals (out1, out2) according to the state of the switches (S1, ..., S4). The combination of switches (S1, ..., S4) can be Figure 11 An exemplary implementation of the switching network (1140). The transistors (T3a, T3b) combined with their respective current sources (Ia, Ib) represent source followers, which provide, for example, some of the implementations described previously. Figure 4A The illustrated implementation describes a similar broadband output matching. (Refer to...) Figure 2E and Figure 12 Those skilled in the art will understand that in the electronic circuit (1200), the splitting begins at the cascode transistor (the drain of transistor (T1)), and the source follower provides the required isolation and impedance transformation. Therefore, there is no... Figure 2E The performance degradation of NF in cases such as the front-end receiver (200E) (which performs splitting at the input).

[0091] Further reference Figure 12 The electronic circuit (1200) has the following three operating modes:

[0092] • Single Mode (in to out1): In this mode, switch (S3) is closed, and therefore, transistor (T2b) is disabled because its gate is pulled to ground. Transistor (T3b) is also disabled. This can be done by opening switch (S4) to disable the current source (Ib) or by turning off the bias voltage (V2). Switch (S2) is open and switch (S1) is closed. Transistors (T1, T2a, T3a) are enabled.

[0093] • Single Mode (in to out2): In this mode, switch (S2) is closed, and therefore, transistor (T2a) is disabled because its gate is pulled to ground. Transistor (T3a) is also disabled. This can be done by opening switch (S1) to disable the current source (Ib) or by turning off the bias voltage (V2). Switch (S3) is open and switch (S4) is closed. Transistors T1, T2b, and T3b are enabled.

[0094] • Split mode: Switches (S1, S4) are closed and switches (S2, S3) are open. Therefore, transistors (T2a, T2b) and (T3a, T3b) are enabled to simultaneously amplify the input signal at the input terminal (in) to both output terminals (out1, out2).

[0095] Figure 13An electronic circuit (1300) according to other embodiments of this disclosure is shown. The operating principle of the electronic circuit (1300) is related to... Figure 12 The electronic circuit (1200) is similar to that described.

[0096] Reference Figure 11 and Figure 13 The input matching network (1321) is Figure 11 An exemplary implementation of the input matching network (1121) is provided. The electronic circuit (1300) also includes two output matching networks (1330a, 1330b), each of which can be... Figure 11 An exemplary implementation of any one of the output matching elements (M1, ..., Mn). In other words, the combination of the two output matching networks (1330a, 1330b) is Figure 11 The corresponding part of the output matching network (1130). Similarly, each of the transistors (T2a, T2b) can be an exemplary implementation of any of the electronic components (E1, ..., En). Furthermore, each of the resistors (RL, RL') can represent... Figure 11 Any one of the load elements (L1, ..., Ln). The combination of switches (S5, S6, S7) can be... Figure 11 An exemplary implementation of some of the switches included in the switch network (1140). See reference... Figures 12 to 13 Those skilled in the art will understand that the electronic circuit (1300) may also include Figure 12 A switch (S1, ..., S4) providing the same function. For clarity, such a switch is not included. Figure 13 As shown in the image.

[0097] like Figure 13As shown, the transconducting current generated by transistor (T1) is equally divided into currents (i1, i2). Assuming all other aspects are equal, this corresponds to a 6dB gain drop in split mode compared to single mode. To achieve substantially equal gain in both single and split modes, one solution is to use Q-reducing resistors (Rd, Rd') that can be switched on (in single mode operation) and off (in split mode operation) using their respective switches (S5, S6). As an example, in single-mode operation where transistors (T2a, T3a) are active, switch (S5) can be closed to engage resistor (Rd). In this scenario, the combination of inductor (Ld) and resistor (Rd) is designed to maintain substantially equal gain during single-mode and split-mode operation. According to embodiments of this disclosure, additional capacitive switching can be implemented to maintain the correct resonant frequency in all operating modes. In other words, a capacitor (not shown) can be implemented in parallel with resistors (Rd) and (Rd'). Such a capacitor can be switched on and off during different modes to maintain the same resonant frequency for both single-mode and split-mode.

[0098] Further reference Figure 13 The combination of switch (S7) and inductors (L2, L2') can also be used to maintain equal gain in various operating modes. According to embodiments of this disclosure, only inductor (L2') can be connected during split-mode, resulting in an increase in gain at the expense of input matching performance. During single-mode operation, the position of switch (S7) can be changed to include both inductors (L2, L2') and thus reduce the gain. Other embodiments according to this disclosure are conceivable, where the current sources (Ia, Ib) can be replaced by inductors. In this case, the bias point of the source follower including transistor (T3b) is set by the gate of transistor (T3b), which can be DC decoupled from the drain of transistor (T2b) by a series DC blocking capacitor (not shown). Similarly, the bias point of the source follower including transistor (T3a) is set by the gate of transistor (T3a), which can be DC decoupled from the drain of transistor (T2a) by a series DC blocking capacitor (not shown).

[0099] Figure 14 An electronic circuit (1400) according to another embodiment of this disclosure is shown. (See also...) Figure 11 and Figure 14 The input matching network (1421) is Figure 11An exemplary implementation of the input matching network (1121) is provided. The electronic circuit (1400) also includes two output matching networks (1430a, 1430b), each of which can be... Figure 11 An exemplary implementation of any one of the output matching elements (M1, ..., Mn). In other words, the combination of the two output matching networks (1430a, 1430b) is Figure 11 The corresponding part of the output matching network (1130). Similarly, each of the transistors (T2a, T2b) can be an exemplary implementation of any of the electronic components (E1, ..., En). Furthermore, each of the resistors (RL, RL') can represent... Figure 11 Any one of the load elements (L1, ..., Ln). The combination of switches (S5, S6, S7) can be... Figure 11 An exemplary implementation of some of the switches included in the switch network (1140). See reference... Figure 12 and Figure 14 Those skilled in the art will understand that the electronic circuit (1400) may also include Figure 12 A switch (S1, ..., S4) providing the same function. For clarity, such a switch is not included. Figure 14 The middle shows

[0100] Reference Figures 13 to 14 The operating principle of electronic circuit (1400) and related information Figure 13 The electronic circuit (1300) is similar to that described, except that there are two additional source followers implemented using a transistor (T4a) with a current source (Ia') and a transistor (T4b) with its associated current source (Ib'). At the cost of additional DC current generated by the current sources (Ia', Ia'), this architecture provides improved output-to-output isolation by adding an extra output buffer stage. Since transistors (T4a, T4b) drive the high-impedance gates of transistors (T3a, T3b) respectively, transistors (T4a, T4b) may not have the current requirement that transistors (T3a, T3b) might have to drive a 50-ohm load. Therefore, the DC current (Ia') may be less than the current (Ia), and the DC current (Ib') may be less than the DC current (Ib). In single-mode operation where output-to-output isolation may not be required, transistors (T4a, T4b) can be bypassed by closing switches (S8, S9) and current sources (Ia', ib') can be turned off.

[0101] Return to reference Figure 11 Those skilled in the art will understand that Figures 12 to 14 Implementation method representation Figure 11The illustrated embodiments are exemplary implementations. Without departing from the scope and spirit of the invention, other implementations as previously described can be used. Figures 4A to 9 Other embodiments are conceived based on the various designs and concepts disclosed in the embodiments. These are examples, not limitations, and reference continues to be made to... Figure 11 The implementation methods can be implemented, wherein:

[0102] • Can be used Figure 4A The input matching network (421) is used to implement the input matching network (1121).

[0103] • Can be used Figure 4A The output matching network (430) implements one or more matching elements (M1, ..., Mn) of the multiple matching elements of the output matching network (1130).

[0104] • Can be used Figure 9 The output matching network (930) implements one or more matching elements (M1, ..., Mn) of the multiple matching elements of the output matching network (1130).

[0105] • Can be used Figure 4B The switching network (440) and based on such Figures 5B to 8B The switch network (1140) can be implemented using any of the configurations shown in the table.

[0106] • Transistors can be used to implement one or more electronic elements (E1, ..., En) of the LNA block (1122), with respect to... Figures 12 to 14 The embodiments shown are similar to those described.

[0107] Further reference Figure 11 And according to various embodiments of this disclosure:

[0108] • All electronic components in a plurality of electronic components (E1, ..., En) can be identical.

[0109] • At least one of the multiple electronic components (E1, ..., En) may be different from the other electronic components (E1, ..., En).

[0110] Each electronic component in the plurality of electronic components (E1, ..., En) may be different from any other electronic component in the plurality of electronic components (E1, ..., En).

[0111] • All output matching elements in a plurality of output matching elements (M1, ..., Mn) can be the same.

[0112] • At least one of the multiple output matching elements (M1, ..., Mn) may be different from the other output matching elements in the multiple output matching elements (M1, ..., Mn).

[0113] Each of the multiple output matching elements (M1, ..., Mn) can be different from any other output matching element in the multiple output matching elements (M1, ..., Mn).

[0114] Figure 15 An electronic circuit (1500) according to an embodiment of this disclosure is shown. The electronic circuit (1500) and... Figure 11 The electronic circuit (1100) has some similarities and provides the same as previously detailed. Figure 3 All the benefits associated with the electronic circuit (300). Additionally, the electronic circuit (1500) can be configured to receive one or more input signals from the input terminals (in1, ..., ink). (Regarding...) Figure 11 Similar to the electronic circuit (1100) described above, electronic circuit (1500) can be configured to provide output signals to one or more output terminals (out1, ..., outn), where "k" and "n" are integers greater than 1. Electronic circuit (1500) is essentially a multi-input, multi-output circuit, thus providing, as described above... Figure 11 The electronic circuit (1100) offers all the benefits described herein, as well as the ability to process more than one input signal. According to embodiments of this disclosure, the electronic circuit (1500) can be configured to:

[0115] • Various single-mode operations, which involve receiving an input signal from any of the input terminals (in1, ..., ink) to provide an output signal at any of the output terminals (out1, ..., outn), and

[0116] • Various split-mode operations, which involve receiving an “i” input signal from any “i” input terminal (in1, ..., ink) to provide a “j” output signal at any “j” output terminal (out1, ..., outn), where “i” and “j” are integers, and where “i” is greater than or equal to 1 and “j” is greater than or equal to “i”.

[0117] Figure 16 An electronic circuit (1600) according to an embodiment of the present disclosure is shown, wherein a switch is not shown for ease of understanding. The electronic circuit (1600) is... Figure 15An exemplary implementation of the electronic circuit (1500) is provided. The electronic circuit (1600) is essentially a multi-input, multi-output circuit and can be configured to receive two input signals at input terminals (in1, in2) and generate two output signals at output terminals (out1, out2). Transistors (T1, T1') are configured as common-source transistors, and transistors (T2, T2') are configured as cascode transistors. Also as... Figure 15 As shown, and similar to what has been previously described, the splitting begins at the cascode transistor; in other words, the splitting begins at the drain of transistors (T1, T1'). Transistors (T3, T3') and their respective current sources (Ia, Ia') are source followers for improved output matching. According to embodiments of this disclosure, the electronic circuit (1600) can have the following operating modes:

[0118] • Single mode (in1 to out1): Transistors (T1, T2, T3) are active, and all other transistors are inactive. (Regarding...) Figures 1 to 15 Similarly, a set of switches can be implemented to allow transistors (T1, T2, T3) to be active while all other transistors are inactive.

[0119] • Single mode (in1 to out2): Transistors (T1, T2', T3') are active, and all other transistors are inactive. (Regarding...) Figures 1 to 15 Similarly, as discussed, a set of switches can be implemented to allow transistors (T1', T2', T3) to be active, while all other transistors are inactive.

[0120] • Single mode (in2 to out1): Transistors (T1', T2, T3) are active, and all other transistors are inactive. (Regarding...) Figures 1 to 15 Similarly, a set of switches can be implemented to allow transistors (T1', T2, T3) to be active while all other transistors are inactive.

[0121] • Single mode (in2 to out2): Transistors (T1', T2', T3') are active, and all other transistors are inactive. (Regarding...) Figures 1 to 15 Similarly, a set of switches can be implemented to allow transistors (T1', T2', T3') to be active while all other transistors are inactive.

[0122] • Split mode (in1 to out1 and out2): Transistors (T1, T2, T3, T2', T3') are active. Transistor (T1') is inactive. (Regarding...) Figures 1 to 15Similarly, a set of switches can be implemented to allow transistors (T1, T2, T3, T2', T3') to be active and transistor (T1') to be inactive.

[0123] • Split mode (in2 to out1 and out2): Transistors (T1', T2, T3, T2', T3') are active. Transistor (T1) is inactive. (Regarding...) Figures 1 to 15 Similar to the discussion, a set of switches can be implemented to allow transistors (T1', T2, T3, T2', T3') to be active and transistor (T1) to be inactive.

[0124] As used in this disclosure, the term "MOSFET" means any field-effect transistor (FET) having an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms "metal" or "metal-like" include at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0125] As will be apparent to those skilled in the art, various embodiments of the invention can be implemented to meet various specifications. Unless otherwise stated above, the selection of suitable component values ​​is a matter of design choice, and various embodiments of the invention can be implemented using any suitable IC technology (including, but not limited to, MOSFET structures) or in the form of hybrid or discrete circuits. Integrated circuit embodiments can be fabricated using any suitable substrate and process—including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise stated above, the invention can be implemented using other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the above-described inventive concepts are particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes with similar characteristics. CMOS fabrication based on SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high-power signals generated during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementations are particularly useful because parasitic capacitance can usually be kept low (or kept to a minimum and uniform across all cells, thus allowing for compensation of parasitic capacitance) through careful design.

[0126] Voltage levels or voltage and / or logic signal polarity inversion can be adjusted according to specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering the function of the disclosed circuit.

[0127] Several embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be independent of order and therefore may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, or parallel manner.

[0128] It should be understood that the foregoing description is intended to illustrate, rather than limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. (Note that the bracket markings used for claim elements are for ease of reference to these elements and do not in themselves indicate a particular desired order or enumeration of elements; furthermore, such markings may be repeated in dependent claims as references to additional elements and should not be considered as initiating a conflicting sequence of markings.)

Claims

1. A radio frequency (RF) receiver front end, comprising: Low-noise amplifier (LNA) block; A selectively bypassable source follower amplifier stage, comprising a combination of transistors and current sources, and Configurable output matching network, The LNA block can be selectively connected to either the selectively bypassable source follower amplifier stage or the configurable output matching network based on a selected bandwidth and / or a selected gain. The bandwidth and gain of the RF receiver front end can be adjusted based on the bypass state of the selectively bypassed source follower amplifier stage and the configuration state of the configurable output matching network. Specifically, the selectively bypassable source follower amplifier stage is bypassed by shorting its gate terminal to ground. The configuration state of the configurable output matching network and the bypass state of the selectively bypassed source follower amplifier stage are controlled by a switching network.

2. The RF receiver front end according to claim 1, wherein: In the first state: The LNA block is connected to the configurable output matching network; The LNA block is disconnected from the selectively bypassed source follower amplifier stage; and In the second state: The LNA block is disconnected from the configurable output matching network; and The LNA block is connected to the selectively bypassed source follower amplifier stage.

3. The RF receiver front end of claim 2, further comprising a configurable input matching network coupled to the LNA block, wherein, The bandwidth and gain of the RF receiver front end can be adjusted based on the configuration of the configurable input matching network.

4. The RF receiver front end according to claim 3, wherein, The configuration state of the configurable input matching network is controlled by the switch network.

5. The RF receiver front end according to claim 4, wherein, The configurable input matching network and the configurable output matching network include selectively switchable capacitors and inductors.

6. The RF receiver front end according to claim 4, wherein, The switching network configures or reconfigures the RF receiver front end to operate in one or more frequency ranges, including at least a narrowband frequency range, an extended narrowband frequency range, and a wideband frequency range.

7. The RF receiver front end according to claim 1 is implemented on a single die or chip.

8. A radio frequency (RF) receiver front end, comprising: First amplifying element; A first configurable output matching network includes a selectively bypassable first source follower amplifier stage, the selectively bypassable first source follower amplifier stage including a combination of transistors and current sources; as well as A second configurable output matching network includes a selectively bypassable second source follower amplifier stage, which comprises a combination of transistors and current sources. in: Both the first configurable output matching network and the second configurable output matching network are coupled to the drain terminal of the first amplifying element. Both the first source follower amplifier stage and the second source follower amplifier stage are configured to be selectively active or bypassed, and The configuration states of the first configurable output matching network and the second configurable output matching network, as well as the states of the first source follower amplifier stage and the second source follower amplifier stage, are controlled by a switching network.

9. The RF receiver front end according to claim 8, wherein: In the first single-mode state, the first source follower amplifier stage is active, while the second source follower amplifier stage is bypassed. In the second single-mode state, the first source follower amplifier stage is in a bypass state, while the second source follower amplifier stage is in an active state, and In split mode, both the first source follower amplifier stage and the second source follower amplifier stage are active.

10. The RF receiver front end according to claim 9 further includes a first cascode transistor and a second cascode transistor, wherein the first cascode transistor couples the first amplifying element to the first source follower amplifier stage, and the second cascode transistor couples the second source follower amplifier stage to the first amplifying element.

11. The RF receiver front end according to claim 10, wherein: In the first single-mode state, the first cascode transistor is active, while the second cascode transistor is in bypass state. In the second single-mode state, the first cascode transistor is in a bypass state, while the second cascode transistor is in an active state, and In the split mode state, both the first cascode transistor and the second cascode transistor are active.

12. The RF receiver front end according to claim 8, wherein, The bandwidth and gain of the RF receiver front end can be adjusted based on the state of the first source follower amplifier stage and the second source follower amplifier stage, as well as the configuration state of the first configurable output matching network and the second configurable output matching network.

13. The RF receiver front end of claim 12, further comprising a configurable input matching network coupled to the first amplifying element, wherein, The bandwidth and gain of the RF receiver front end can be adjusted based on the configuration of the configurable input matching network.

14. The RF receiver front end according to claim 13, wherein, The configuration state of the configurable input matching network is controlled by the switch network.

15. The RF receiver front end according to claim 13, wherein, The configurable input matching network, the first configurable output matching network, and the second configurable output matching network include selectively switchable capacitors and inductors.

16. The RF receiver front end according to claim 14, wherein, The switching network configures or reconfigures the RF receiver front end to operate in one or more frequency ranges, including at least a narrowband frequency range, an extended narrowband frequency range, and a wideband frequency range.

17. The RF receiver front end according to claim 8 further includes a third source follower amplifier stage and a fourth source follower amplifier stage, the third source follower amplifier stage being connected to the source terminal of the first source follower amplifier stage, and the fourth source follower amplifier stage being connected to the source terminal of the second source follower amplifier stage.

18. The RF receiver front end according to claim 8 further includes a second amplifying element, wherein the drain terminal of the second amplifying element is connected to the drain terminal of the first amplifying element.

19. The RF receiver front end of claim 18, configured to: receive a first RF signal at the input of the first amplifying element and receive a second RF signal at the input of the second amplifying element, the second RF signal being different from the first RF signal.

20. A method for controlling a radio frequency (RF) receiver front end, the RF receiver front end including a low-noise amplifier (LNA), the method comprising: Provides a configurable output matching network; A source follower amplifier is provided, the source follower amplifier comprising a combination of transistors and current sources, and Based on the desired gain and / or bandwidth, perform the following operations: Selectively connect or disconnect one of the configurable output matching network or the source follower amplifier from the LNA. When the output matching network is connected to the LNA, the gate terminal of the source follower amplifier is shorted to ground to bypass the source follower amplifier. The configuration state of the configurable output matching network and the bypass state of the source follower amplifier stage are controlled by a switching network.

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