A method implemented on a computer system executing instructions for semiconductor design simulation

Abstract

A method implemented by a computer system executing instructions for semiconductor design simulation is disclosed. The method includes generating a plurality of floorplan plans that differently place a plurality of circuit blocks, generating a plurality of power models from the plurality of floorplan plans, and selecting a layout corresponding to one of the plurality of floorplan plans by selecting at least one power model from among the plurality of power models that satisfies system requirements.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0023061, filed on February 25, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concepts described herein relate to semiconductor design, and more particularly, to a method implemented using a computer system executing instructions for semiconductor design simulation in which user convenience and power characteristics are improved. Background Art

[0004] The process of designing a semiconductor device includes: determining a floorplan that dictates how circuit blocks are placed; determining locations of bumps and solder balls; extracting a power model based on the bump and solder ball locations; and testing the power model to analyze whether the power model meets system requirements.

[0005] When the results of the analysis indicate that the power model does not meet the system requirements, bump and ball locations may be re-determined, the power model may be re-extracted, and the power model may be re-tested.

[0006] In the process of designing a semiconductor device, a layout plan may be determined based on experience. Therefore, the layout plan of the semiconductor device may not be optimal, and the characteristics of the semiconductor device based on the layout plan may not be optimal. Summary of the Invention

[0007] An embodiment of the inventive concept provides a method implemented using a computer system executing instructions for semiconductor design simulation, which generates various floorplans, generates power models based on the floorplans, and selects one of the power models.

[0008] According to an exemplary embodiment, a method implemented using a computer system executing instructions for semiconductor design simulation includes: generating a plurality of floorplans, each of the plurality of floorplans including a plurality of circuit blocks placed differently; generating a plurality of power models from the plurality of floorplans; and selecting a layout corresponding to one of the plurality of floorplans by selecting at least one power model from the plurality of power models that meets system requirements.

[0009] According to an exemplary embodiment, a method implemented using a computer system executing instructions for semiconductor design simulation includes: generating a plurality of floorplans, each of the plurality of floorplans including a plurality of circuit blocks positioned differently; generating a plurality of power bump and solder ball models from the plurality of floorplans; and generating a plurality of board power models from the plurality of power bump and solder ball models.

[0010] According to an example embodiment, a method implemented with a computer system executing instructions for semiconductor design simulation includes generating a plurality of floorplans, each of the plurality of floorplans including a plurality of circuit blocks placed differently, and generating a plurality of power bump models from the plurality of circuit blocks. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other objects and features of the present inventive concepts will become apparent from a detailed description of example embodiments thereof with reference to the accompanying drawings.

[0012] Figure 1 A semiconductor design system according to an example embodiment of the present inventive concepts is illustrated.

[0013] Figure 2 An example method for a semiconductor design system implemented with a computer system is illustrated. Figure 1

[0014] Figure 3 An example of the step of generating a plurality of power bump and solder ball models is illustrated.

[0015] Figure 4 An example of the step of generating a plurality of floorplans is illustrated.

[0016] Figure 5 An example of generating a plurality of floorplans based on the method of Figure 4 is illustrated.

[0017] Figure 6 An example of the step of generating a plurality of power bump maps is illustrated.

[0018] Figure 7 An example of generating an example power bump map based on the method of Figure 6 is illustrated.

[0019] Figure 8 An example of the step of generating a plurality of power connection maps of Figure 3 is illustrated.

[0020] Figure 9 An example of generating an example horizontal power model based on the method of Figure 8 is illustrated.

[0021] Figure 10 An example of a power connection map in which grids with connections and grids without connections are marked by different colors is illustrated.

[0022] Figure 11 An example of the step of generating a plurality of power solder ball maps of Figure 3 is illustrated.

[0023] ​Figure 12 An example of generating an example power bump plot based on Figure 11 .

[0024] Figure 13 An example of the steps of generating multiple horizontal power models of Figure 3 .

[0025] Figure 14 An example of generating an example horizontal power model based on Figure 13 .

[0026] Figure 15 An example of the steps of generating multiple vertical power models of Figure 3 .

[0027] Figure 16 An example of generating an example vertical power model based on Figure 15 .

[0028] Figure 17 An example of an example power bump and solder ball model generated by the steps of Figure 3 .

[0029] Figure 18 An example of the steps of generating multiple on-chip power models.

[0030] Figure 19 An example of the steps of generating multiple board power models.

[0031] Figure 20 An example of a board with semiconductor packages mounted thereon.

[0032] Figure 21 An example of an effective inductance of a board.

[0033] Figure 22 An example of the steps of generating system power analysis of Figure 2 .

[0034] Figure 23 An example of the steps of generating a power scenario of Figure 22 .

[0035] Figure 24 An example of a power scenario generated by the method of Figure 23 .

[0036] Figure 25 An example of the steps of generating what-if conditions of Figure 22 .

[0037] Figure 26 An example of the steps of generating a power scenario of Figure 2Examples of steps of a generation system power analysis.

[0038] Figure 27 Examples of a system power model generated by a semiconductor design system are shown. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numbers are used throughout the drawings to refer to the same elements.

[0040] Figure 1 A semiconductor design system 100 according to embodiments of the inventive concept is shown. Referring to Figure 1 , the semiconductor design system 100 includes a bus 110, a processor 120, a main memory 130, a storage 140, a modem 150, an attachable detachable storage 160, and a user interface 170.

[0041] The bus 110 provides a path between components of the semiconductor design system 100, allowing the components to send / receive data and instructions to / from each other. The processor 120 can control the semiconductor design system 100 and can perform simulation of a semiconductor design. For example, the processor 120 can perform a tool for simulation (see, for example, tool 300 of FIG. 1) by executing instructions 141 stored in the storage 140. Figure 5

[0042] At least a portion of the instructions 141 can include an algorithm learned based on machine learning for a semiconductor design. The semiconductor design system 100 can perform at least a portion of steps for semiconductor design simulation by executing at least some instructions corresponding to the algorithm.

[0043] The processor 120 can perform simulation for a semiconductor design with reference to data 142 stored in the storage 140. The data 142 can include libraries including various information required for a semiconductor design, information of a semiconductor design input by a user through the user interface 170, etc.

[0044] The main memory 130 can be a working memory of the processor 120. The main memory 130 can temporarily store instructions and / or data required for the processor 120 among the instructions 141 and / or the data 142 stored in the storage 140. The main memory 130 can include a high-speed random access memory such as, for example, DRAM, PRAM, MRAM, or RRAM, or storage class memory (SCM).

[0045] ​The storage 140 can function as an auxiliary memory of the semiconductor design system 100. The storage 140 can store the instructions 141 constituting the semiconductor design simulation tool and the data 142 of the semiconductor model for simulation. The storage 140 can include, for example, a hard disk drive (HDD), a solid state drive (SSD), an optical disk drive (ODD), or the like.

[0046] The modem 150 can communicate with the external device 210 wiredly or wirelessly via the network 220. For example, the instructions 141 and / or the data 142 can be stored in the storage 140 as content DLC (downloadable content) downloaded from the external device 210 through the modem 150. The instructions 141 and / or the data 142 stored in the storage 140 can be transmitted to the external device 210 through the modem 150. The modem 150 can operate based on an Ethernet protocol and technology.

[0047] The attachable and detachable storage 160 can include a portable storage. For example, the instructions 141 and / or the data 142 can be moved from the attachable and detachable storage 160 to the storage 140. The instructions 141 and / or the data 142 stored in the storage 140 can be moved to the attachable and detachable storage 160. The attachable and detachable storage 160 can be based on one of various standards such as a universal serial bus (USB) and a serial advanced technology attachment (SATA).

[0048] The user interface 170 can include various user input interface devices such as, for example, a touch sensor 171, a keyboard 172, and a mouse 173. The user interface 170 can receive execution instructions of the tool for simulation, various instructions for simulation functions of the tool, and various information required to perform simulation of the tool.

[0049] The user interface 170 can include various user output interface devices such as, for example, a display device 174. The user interface 170 can display a semiconductor model to be simulated and a process and a result of simulation of the semiconductor model on the display device 174.

[0050] In an example embodiment, the semiconductor design system 100 can be implemented with a general-purpose computer or a special-purpose computer for semiconductor simulation. The semiconductor simulation tool (see, for example, the tool 300 of FIG. 1) can be transmitted in the form of the instructions 141 through the modem 150 or can be installed on the semiconductor design system 100 through the attachable and detachable storage 160. The data 142 can be transmitted through the modem 150, can be transmitted through the attachable and detachable storage 160, or can be input through the user interface 170. Figure 5

[0051] ​The following describes various methods that can be performed by semiconductor design system 100 with respect to each step. At least one step may be omitted. Therefore, the omitted at least one step may be performed by any other external device or by a user. In an example embodiment, at least one step of the various methods that can be performed by semiconductor design system 100 may be performed using an algorithm learned through machine learning.

[0052] The terms "bump" and "solder ball" are used below. A "bump" may be manufactured when a semiconductor die is formed on a wafer and may be used to mount the semiconductor die on a board (or substrate) of a semiconductor package. A "solder ball" may be manufactured during the process of manufacturing a semiconductor package and may be used to mount the semiconductor package on any other external device. The size of a "solder ball" may be larger than that of a "bump."

[0053] The term "library" is used below. A "library" may be a collection of information that can be used to simulate the design of a semiconductor device. The "library" may be included in data 142 or may be transmitted from external device 210 to semiconductor design system 100 via network 220 and modem 150.

[0054] Below, unless explicitly mentioned otherwise, information that the semiconductor design system 100 may use (or refer to) may be input from a user through the user interface 170 , may be transmitted through the attachable and detachable storage unit 160 , and / or may be transmitted from the external device 210 through the network 220 and the modem 150 .

[0055] Figure 2 Show Figure 1 The method for semiconductor design system 100 implemented by using a computer system. Figure 1 and Figure 2 In step S110 , the semiconductor design system 100 may generate a plurality of power bump and solder ball models of a plurality of floorplans. For example, the power bump and solder ball models may be layouts corresponding to power bumps and solder balls of the semiconductor package under test.

[0056] In step S120 , the semiconductor design system 100 may generate a plurality of on-chip power models for each power bump and solder ball model. In step S130 , the semiconductor design system 100 may generate a plurality of board power models.

[0057] In step S140 , the semiconductor design system 100 may generate a system power model based on the plurality of power bump and ball models, the plurality of on-chip power models, and the plurality of board power models, and may perform system power analysis on the system power model.

[0058] In step S150 , the semiconductor design system 100 may provide (eg, display) at least one power model that meets the system requirements. For example, the semiconductor design system 100 may display the at least one power model on the display device 174 .

[0059] According to example embodiments of the present inventive concept, generation of a floorplan, generation of a power bump and ball model, generation of an on-chip power model, generation of a board power model, generation of a system power model, and system power analysis can be performed by one tool, thereby improving user convenience.

[0060] In addition, according to an exemplary embodiment of the present inventive concept, a system power model is generated according to various floorplans, and a system power analysis is performed for each of the various floorplans. Since various floorplans are considered, the at least one system power model provided in step S150 may have further improved power characteristics.

[0061] Figure 3 Shows the steps for generating multiple power bump and solder ball models ( Figure 2 Example of step S110). Figure 1 and Figure 3 In step S210, the semiconductor design system 100 may generate a plurality of floorplans. The plurality of floorplans may be configured to place circuit blocks in different parts or locations. The circuit blocks may include a given design for performing a given function. The circuit blocks may be referred to as "intellectual property (IP)". As used herein, intellectual property (IP) may also be referred to as intellectual property cores and may be used to represent self-contained discrete units that provide macro functionality to the system. Those skilled in the art will understand that the disclosed intellectual property or intellectual property cores are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, buses, communication links, etc., which may be formed using semiconductor-based manufacturing technology or other manufacturing technology.

[0062] In step S220, the semiconductor design system 100 may generate a power bump map for each floorplan. For example, in step S220, multiple power bump maps may be generated, each corresponding to a plurality of floorplans. The multiple power bump maps may be generated for the plurality of floorplans and may be considered to include the plurality of floorplans.

[0063] In step S230, the semiconductor design system 100 can generate power connection graphs of the power bumps of the power bump graphs. For example, in step S230, a plurality of power connection graphs corresponding to the plurality of layout plans, respectively, can be generated. The plurality of power connection graphs can be generated on the plurality of power bump graphs, and can be considered to include the plurality of power bump graphs (or the plurality of layout plans), respectively.

[0064] In step S240, the semiconductor design system 100 can generate a plurality of power solder ball graphs for each layout plan. For example, in step S240, a number of power solder ball graphs greater than a number of the plurality of power connection graphs can be generated from the plurality of power connection graphs. The plurality of power solder ball graphs can be generated by changing a number of the power solder balls at each power connection graph and positions of the power solder balls.

[0065] The plurality of power solder ball graphs can be generated on the plurality of power connection graphs, and each of the plurality of power solder ball graphs can be considered to include a corresponding layout plan, a corresponding power bump graph, and a corresponding power connection graph.

[0066] In step S250, the semiconductor design system 100 can generate a plurality of horizontal power models. Each of the horizontal power models can include a model of a resistance and an inductance (or a capacitance) component of a horizontal connection connecting the power bump and the power solder ball at a corresponding power solder ball graph of the plurality of power solder ball graphs.

[0067] In step S260, the semiconductor design system 100 can generate a plurality of vertical power models. Each of the vertical power models can include a model of a resistance and an inductance (or a capacitance) component of a vertical connection connecting the power bump and the power solder ball at a corresponding power solder ball graph of the plurality of power solder ball graphs.

[0068] In step S270, the semiconductor design system 100 can generate a plurality of bump and solder ball models based on the plurality of power solder ball graphs, the plurality of horizontal power models, and the plurality of vertical power models. Each of the plurality of bump and solder ball models can be based on a corresponding layout plan of the plurality of layout plans.

[0069] Each of the plurality of bump and solder ball models can be based on a corresponding horizontal power model of the plurality of horizontal power models and a corresponding vertical power model of the plurality of vertical power models. For example, when the corresponding layout plan of the plurality of layout plans is selected, each of the plurality of bump and solder ball models can include a power model (e.g., represented by a resistance, an inductance, or a capacitance component) between the power bump and the power solder ball.

[0070] Figure 4 The step of generating the plurality of layout plans is illustrated in FIG. 2A. Figure 3of step S210). Figure 5 An example of generating a plurality of layout plans based on Figure 4 the method of step S211 is shown. Referring to Figure 1 , Figure 4 and Figure 5 , in step S211, the semiconductor design system 100 can receive information IN of the circuit blocks and the associated power bump map.

[0071] For example, the user can input the information IN to the semiconductor design system 100 through the user interface 170. Alternatively, the information IN can be transmitted to the semiconductor design system 100 from the external device 210 through the modem 150, or can be transmitted to the semiconductor design system 100 by the attachable and detachable storage 160.

[0072] In an example embodiment, in order to perform simulation of the semiconductor design, the first to seventh circuit blocks CB1 to CB7 can be input as the information IN. For example, the fifth circuit block CB5 among the first to seventh circuit blocks CB1 to CB7 can have the associated bump map, and the remaining circuit blocks can not have the associated bump map. The information IN can further include various information (such as power consumption information and function information) about the first to seventh circuit blocks CB1 to CB7.

[0073] In an embodiment, the information IN can include identification information about the first to seventh circuit blocks CB1 to CB7. The semiconductor design system 100 can obtain the associated information from a library including various information (such as power information and function information) of the circuit blocks.

[0074] In step S212, the semiconductor design system 100 can receive constraints of placement of the plurality of circuit blocks in the plurality of layout plans. The constraints can be input to the semiconductor design system 100 through the user interface 170. Alternatively, the constraints can be transmitted to the semiconductor design system 100 from the external device 210 through the modem 150, or can be transmitted to the semiconductor design system 100 by the attachable and detachable storage 160.

[0075] In an example embodiment, the constraints can include a placement order according to regions of the plurality of layout plans. The constraints can define placement of the first to seventh circuit blocks CB1 to CB7 in an order from the largest to the smallest in the plurality of layout plans. Alternatively, the constraints can define placement of the first to seventh circuit blocks CB1 to CB7 such that, among the first to seventh circuit blocks CB1 to CB7 in the plurality of layout plans, a circuit block having a size greater than a threshold value is placed before a circuit block having a size equal to or less than the threshold value.

[0076] The constraint can define that the interface configured to communicate with the external device 210 is placed outside the plurality of layout plans. For example, the second circuit block CB2 can be an interface configured to connect with the external device 210. Alternatively, the constraint can define that the circuit blocks of a serializer and a deserializer are placed outside the plurality of layout plans.

[0077] The constraint can define that the circuit block consuming high power among the first circuit block CB1 to the seventh circuit block CB7 is placed in the center of the plurality of layout plans. The constraint can define that the specific circuit blocks defined by the constraint are placed at a distance shorter than the specific distance defined by the constraint from each other. For example, the constraint can define that the specific circuit blocks are placed at a distance shorter than the maximum specific distance.

[0078] In step S213, the semiconductor design system 100 can generate the plurality of layout plans of the circuit blocks. The semiconductor design system 100 can display the plurality of layout plans thus generated through the display device 174 of the user interface 170. For example, the semiconductor design system 100 can display the plurality of layout plans on the display device 174.

[0079] The constraint can further define a display priority. For example, the constraint can assign a priority to the plurality of layout plans. In detail, the constraint can define the assignment of the priority such that the priority becomes higher as the total size of each of the plurality of layout plans decreases. In addition, the constraint can define that the plurality of layout plans is displayed through the display device 174 of the user interface 170 based on the assigned priority.

[0080] For example, the semiconductor design system 100 can display the layout plan having a higher priority among the plurality of layout plans before the layout plan having a lower priority on the display device 174, or can display the layout plan having a higher priority on the left side or the top of the screen of the display device 174. The semiconductor design system 100 can display the layout plan having a lower priority among the plurality of layout plans after the layout plan having a higher priority, or can display the layout plan having a lower priority on the right side or the bottom of the screen of the display device 174.

[0081] The constraint can define a manner of discarding the layout plans. The constraint can define that the layout plans each having a total size greater than a threshold value are discarded, and the layout plans each having a total size equal to or less than the threshold value are generated and displayed as the plurality of layout plans.

[0082] In Figure 5 , the first layout plan FP1 to the n-th layout plan FPn (n is a positive integer) can be generated by the tool 300 according to the information IN. In Figure 5 , the fifth circuit block CB5 consuming high power can be placed in the center based on the constraint, and the second circuit block CB2 performing the function of the interface can be placed outside the first layout plan FP1 to the n-th layout plan FPn.

[0083] In step S214, the semiconductor design system 100 can determine whether a modification is requested. For example, when the user inputs a modification of at least one floorplan through the user interface 170, it can be determined that a modification is requested (step S214, Yes). The modification can include a modification associated with a position or an orientation of at least one of the first to seventh circuit blocks CB1 to CB7 or a modification associated with at least one constraint (e.g., adding, deleting, or changing at least one constraint).

[0084] In step S215, the semiconductor design system 100 can apply the user requested modification to at least one floorplan.

[0085] Figure 6 An example of a step of generating a plurality of power bump maps (step S220 of the method of FIG. 2) is illustrated. Figure 3 An example of generating an exemplary power bump map BMPk1 based on the method of FIG. 2 is illustrated. Figure 7 An example of generating an exemplary power bump map BMPk1 based on the method of FIG. 2 is illustrated. Figure 6 Referring to FIGS. 1 to 3,

[0086] Figure 1 , Figure 6 and Figure 7 In step S221, the semiconductor design system 100 can receive information of a power bump pitch through one of various methods described in association with the information IN.

[0087] In step S222, the semiconductor design system 100 can place a plurality of power bumps BUMP based on the power bump pitch. For example, the semiconductor design system 100 can place the power bumps BUMP in spaces other than spaces designated for signals other than power and spaces of circuit blocks having a bump map similar to that of the fifth circuit block CB5.

[0088] Information about spaces in which the power bumps are prohibited to be placed can be received as part of the information IN. Alternatively, information about spaces in which the power bumps are prohibited to be placed can be obtained from a library based on the information IN.

[0089] In step S223, the semiconductor design system 100 can determine whether there is an assignment library. When there is an assignment library (step S223, Yes), in step S224, the semiconductor design system 100 can place a plurality of ground bumps based on the assignment library. When there is no assignment library (step S223, No), in step S225, the semiconductor design system 100 can place at least one ground bump at each of the power bumps "BUMP". The semiconductor design system 100 can display the power bump map through the user interface 170. For example, the semiconductor design system 100 can display the power bump map on the display device 174.

[0090] ​In step S226 , the semiconductor design system 100 may determine whether a modification is requested. For example, when the user inputs a modification of at least one power bump map through the user interface 170 , it may be determined that a modification is requested (step S226 , Yes).

[0091] In step S227 , the semiconductor design system 100 may apply the user-requested modification to the at least one power bump map. When the modification is applied to the at least one power bump map, the semiconductor design system 100 may display the at least one modified power bump map on the display device 174 .

[0092] Figure 8 Show Figure 3 Steps for generating multiple power connection diagrams ( Figure 3 An example of step S230). Figure 9 Shown based on Figure 8 An example of generating a connection graph BMPk2 corresponding to a bump graph BMPk1 by the method.

[0093] Reference Figure 1 、 Figure 8 and Figure 9 In step S231, the semiconductor design system 100 may receive constraints on the power connection diagram. The constraints may be received by one of the various methods mentioned in reference information IN. The constraints may include information about the size and unit distance of the grid.

[0094] In step S232, the semiconductor design system 100 may generate a grid based on the constraints. The semiconductor design system 100 may connect all power bumps that are spaced at intervals equal to or less than the unit distance defined by the constraints. In addition, as defined by the constraints, the semiconductor design system 100 may connect isolated power bumps that have no adjacent power bumps within the unit distance or less to the nearest power bump.

[0095] In an example embodiment, Figure 9 As shown, the size of the grid can be set to be equal to the bump pitch, but the grid size is not limited thereto. In addition, the unit distance can be set to one grid, but the unit distance is not limited thereto. Herein, the term "grid" may refer to a single unit forming a grid structure, and the size of the grid may refer to the distance between parallel sides of a single unit. Figure 9 , the grid structure is shown by dotted lines.

[0096] In step S233, the semiconductor design system 100 may add connections CNT based on the constraints to generate a power connection diagram. The connection CNT may connect each power bump BUMP to one or more other power bump BUMPs. In step S234, the semiconductor design system 100 may display the power connection diagram based on the grid structure. For example, Figure 9As shown, the semiconductor design system 100 may display the connection CNTs on a grid through the user interface 170. For example, the semiconductor design system 100 may display the connection CNTs on the display device 174.

[0097] For example, Figure 10 As shown, the semiconductor design system 100 can display a grid with a CNT connection as a "1" and a grid without a CNT connection as a "0." The semiconductor design system 100 can display a power connection diagram BMPk3 on the grid, marking "1" and "0" with different colors.

[0098] In step S235 , the semiconductor design system 100 may determine whether a modification is requested. For example, when the user inputs a modification of at least one power connection diagram through the user interface 170 , it may be determined that a modification is requested (step S235 , Yes).

[0099] In step S236 , the semiconductor design system 100 may apply the user-requested modification to the at least one power connection diagram. When the modification is applied to the at least one power connection diagram, the semiconductor design system 100 may display the at least one modified power connection diagram on the display device 174 .

[0100] Figure 11 Show Figure 3 Steps to generate multiple power ball maps ( Figure 3 An example of step S240). Figure 12 Shown based on Figure 11 An example of generating an exemplary power ball map BMk by a method.

[0101] Reference Figure 1 、 Figure 11 and Figure 12 In step S241, the semiconductor design system 100 may receive constraints through one of the various methods described in association with the information IN. The constraints may include various information such as a power solder ball pitch, minimum and maximum values ​​of power solder balls (e.g., a minimum number of power solder balls and a maximum number of power solder balls), and information about areas where power solder balls cannot be placed.

[0102] In step S242, the semiconductor design system 100 may detect positions where a plurality of power solder balls can be placed based on the power solder ball pitch. Figure 12 In FIG, the power solder ball pitch corresponds to the two grids, and positions where power solder balls can be placed (similar to the first solder ball BALL1 ) are marked in the form of thick circles.

[0103] In step S243, the semiconductor design system 100 may assign various power ball maps to generate multiple power ball maps. For example, the semiconductor design system 100 may generate multiple power ball maps based on one power connection map by changing the number of power balls (within a range from a maximum value to a minimum value) or changing the positions of the power balls.

[0104] By changing the number of power balls and the location of the power balls, various power characteristics can be included in the power ball map. Figure 12 In FIG. 1 , a solder ball where the power solder ball is actually placed among the first solder balls BALL1 is marked by a second solder ball BALL2 filled with a slash.

[0105] In step S244 , the semiconductor design system 100 may determine whether a modification is requested. For example, when the user inputs a modification of at least one power ball map through the user interface 170 , it may be determined that a modification is requested (step S244 , Yes).

[0106] In step S245 , the semiconductor design system 100 may apply the user-requested modification to the at least one power ball map.

[0107] In example embodiments, the size of the grid may be determined based on the bump pitch of the power bumps and the ball pitch of the power solder balls. The size of the grid may correspond to the greatest common factor of the bump pitch of the power bumps and the ball pitch of the power solder balls.

[0108] Figure 13 Show Figure 3 Steps for generating multiple horizontal power models ( Figure 3 An example of step S250). Figure 14 Shown based on Figure 13 An example of a method for generating an exemplary horizontal power model. In an embodiment, Figure 13 and Figure 14 An example of generating a horizontal power model corresponding to one power ball map is shown in FIG.

[0109] Reference Figure 1 、 Figure 13 and Figure 14 In step S251, the semiconductor design system 100 may select a horizontal layer. For example, the horizontal layer may include at least one horizontal connection connecting a power bump and a power solder ball. The horizontal connection may be a connection extending in a direction parallel to the plane of the layout plan.

[0110] For example, a horizontal layer may include Figure 9 The semiconductor design system 100 can be based on the power connection diagram BMPk2. Figure 10 The grid is managed in the form of a matrix Figure 9 Information on the electrical connection diagram of the BMPk2.

[0111] As shown in Figure 10 , the semiconductor design system 100 can generate a grid-based matrix for each horizontal layer. The semiconductor design system 100 can distinguish between grids with connections and grids without connections for each horizontal layer.

[0112] In step S252, the semiconductor design system 100 can select a horizontal connection on the selected horizontal layer. For example, a grid corresponding to “1” can be selected from the information of the matrix of Figure 10 .

[0113] In step S253, the semiconductor design system 100 can assign a power model to the detected horizontal connection. In step S254, the semiconductor design system 100 can determine whether a power model has been assigned to each grid of the selected layer. If a power model has not been assigned to each grid of the selected layer (step S254, No), steps S252 and S253 can be repeated until a power model is assigned to the last grid of the selected layer (step S254, Yes).

[0114] In step S255, the semiconductor design system 100 can determine whether a power model has been assigned for each of the horizontal layers. If a power model has not been assigned for each of the horizontal layers (step S255, No), for the remaining horizontal layers, steps S251, S252, and S253 can be repeated until a power model is assigned to the last horizontal layer (step S255, Yes). For example, the remaining horizontal layers can be redistribution layers (RDLs) that include horizontal connections.

[0115] In an embodiment, as shown in Figure 14 , since the connections present in each grid that connects a power bump BUMP have the same length, the connections can be modeled identically as a first resistance R1 and a first inductance L1. At the remaining horizontal layers, the connections present in one grid can also be modeled identically as the first resistance R1 and the first inductance L1.

[0116] In an embodiment, the first resistance R1 and the first inductance L1 can be obtained with reference to a library determined by the package type, or can be obtained using known equations.

[0117] Figure 15 An example of the step of generating a plurality of vertical power models (step S260) of Figure 3 is shown. Figure 3 An example of generating an exemplary vertical power model based on Figure 15 is shown. In an embodiment, Figure 15 and Figure 16 An example of generating a vertical power model corresponding to one power solder ball map is shown in .

[0118] Referring to Figure 1 , Figure 15 and Figure 16 , in step S261, the semiconductor design system 100 can select a vertical layer. For example, the vertical layer can include at least one vertical connection (e.g., at least one of vias VIA1, VIA2, and VIA3) connecting the power bumps BUMP and the power balls BALL. The vertical connection can be a connection extending in a direction perpendicular to the plane of the floorplan.

[0119] The semiconductor design system 100 can generate a grid-based matrix for each vertical layer, as shown in Figure 10 . The semiconductor design system 100 can distinguish, for each vertical layer, the grids in which a connection exists from the grids in which a connection does not exist.

[0120] In step S262, the semiconductor design system 100 can select a vertical connection on the selected vertical layer. For example, a grid corresponding to "1" can be selected from the grid-based information similar to Figure 10 .

[0121] In step S263, the semiconductor design system 100 can assign a power model to the detected vertical connection. In step S264, the semiconductor design system 100 can determine whether a power model has been assigned to each grid of the selected vertical layer. If a power model has not been assigned to each grid of the selected vertical layer (step S264, No), steps S262 and S263 can be repeated until a power model is assigned to the last grid of the selected layer (step S264, Yes).

[0122] In step S265, the semiconductor design system 100 can determine whether a power model has been assigned to each of the vertical layers. If a power model has not been assigned to each of the vertical layers (step S265, No), steps S262 and S263 can be repeated for the remaining vertical layers until a power model is assigned to the last vertical layer (step S265, Yes).

[0123] In an embodiment, as shown in Figure 16 , the connections existing in each grid connecting the power bumps BUMP can be modeled identically as a second resistance R2 and a second inductance L2. The second resistance R2 and the second inductance L2 can be modeled differently according to a height and a thickness (or cross-sectional area) of each of the vertical connections (e.g., at least one of vias VIA1, VIA2, and VIA3).

[0124] In an example embodiment, the second resistance R2 and the second inductance L2 can be obtained with reference to a library determined by the package type, or can be obtained using known equations.

[0125] Figure 17 Shown by Figure 3 Steps for generating power bump and solder ball models ( Figure 3 Example power bump and solder ball models generated in step S270). Figure 1 and Figure 17 , by referring to Figure 13 and Figure 14 The described process models the horizontal layer between the power bump and the power ball as a horizontal power model by using a grid-based matrix.

[0126] In addition, by referring to Figure 15 and Figure 16 The described process models the vertical layer between the power bump and the power ball as a vertical power model using a grid-based matrix. The vertical power model and the horizontal power model are based on the same size matrix.

[0127] Therefore, a plurality of power bump and solder ball models connecting power bumps and power solder balls can be generated according to the vertical power model and the horizontal power model. Figure 17 As shown, multiple power bump and solder ball models can be modeled in the form of a netlist NL using SPICE.

[0128] Figure 18 The steps for generating multiple on-chip power models are shown ( Figure 2 Example of step S120). Figure 1 and Figure 18 In step S121 , the semiconductor design system 100 may select a circuit block CB from among a plurality of circuit blocks included in the floorplan.

[0129] In step S122, semiconductor design system 100 may receive on-chip capacitance and on-chip resistance of the selected circuit block. For example, semiconductor design system 100 may receive on-chip capacitance and on-chip resistance from a library or a user. For example, the on-chip capacitance and on-chip resistance may include capacitance and resistance shown at each circuit block when viewed from a power bump.

[0130] In step S123, the semiconductor design system 100 may assign on-chip capacitance and on-chip resistance to the selected circuit block CB. In step S124, the semiconductor design system 100 may determine whether on-chip capacitance and on-chip resistance have been assigned to each circuit block in the circuit block. If on-chip capacitance and on-chip resistance have not been assigned to each circuit block in the circuit block (step S124, no), the semiconductor design system 100 may repeat steps S121 to S123 until on-chip capacitance and on-chip resistance are assigned to the last circuit block (step S124, yes).

[0131] When the method of Figures 3 to 18 is executed, a package-level power model of a semiconductor device can be obtained. In an example embodiment, depending on the purpose of the semiconductor design, the semiconductor design system 100 can only execute the generation of the power bump and solder ball model of Figures 3 to 17 , or can also execute the generation of the package-level power model of Figure 18 and the generation of the power bump and solder ball model of Figures 3 to 17 .

[0132] Figure 19 An example showing the step of generating a plurality of board power models (step S130 of Figure 2 ) is shown. Figure 20 An example showing that a semiconductor package 410 is mounted on a board 400 is shown. Referring to Figure 1 , Figure 19 and Figure 20 , the power solder balls PB and the ground solder balls GB of the semiconductor package 410 can be connected with the power vias PV and the ground vias GV of the board 400.

[0133] The semiconductor package 410 can be mounted on the upper surface of the board 400. The power vias PV and the ground vias GV can be connected with the decoupling capacitors DEC on the lower surface of the board 400. The power vias PV can receive power from a power management integrated circuit (PMIC) 420 through power lines PL (shown by solid lines in Figure 20 ) and a sixth inductor L6. The voltage at a particular location of the power vias PV can be transmitted to the PMIC 420 through a feedback line FL.

[0134] The power vias PV can be modeled as a third resistance R3 and a third inductance L3. The ground vias GV can be modeled as a fourth resistance R4 and a fourth inductance L4. The decoupling capacitors DEC can be modeled as a capacitor “C”, a fifth resistance R5 and a fifth inductance L5. The third resistance R3 and the third inductance L3 can be modeled according to the height and thickness (or cross-sectional area) of the power vias PV.

[0135] The ground vias GV can receive a ground voltage from the PMIC 420 through ground lines GL marked by dashed lines. The fourth resistance R4 and the fourth inductance L4 can be modeled according to the height and thickness (or cross-sectional area) of the ground vias GV. The power models of the vias PV and GV and the decoupling capacitors DEC can be modeled, for example, with reference to a library.

[0136] Figure 21 An example showing the effective inductance of the board 400 is shown. Referring to Figure 1 , Figure 19 , Figure 20 and Figure 21The inductance of the board 400 can be modeled as: a capacitor inductance LC, which is the sum of inductances associated with the decoupling capacitors DEC; a via inductance LV, which is the sum of inductances associated with the power vias PV and connected to the power balls PB of the semiconductor package 410; and a wire inductance LL, which is the sum of inductances between the power vias PV and the PMIC 420 and connected to the PMIC 420.

[0137] In an example embodiment, the wire inductance LL can be smaller than the capacitor inductance LC and the via inductance LV, and thus can be neglected. For example, the inductance of the board 400 can be modeled as the sum of the capacitor inductance LC and the via inductance LV.

[0138] In an example embodiment, the board power model can be in the form of a third resistance R3, a third inductance L3, a capacitor C, a fifth resistance R5, and a fifth inductance L5 connected in series. The via inductance LV can correspond to the third inductance L3, and the capacitor inductance LC can correspond to the fifth inductance L5.

[0139] As described above, the power model of the board 400 is based on the vias. Thus, the semiconductor design system 100 can generate a power model for each of the power vias of the board 400.

[0140] In step S131, the semiconductor design system 100 can select one of the vias of the board 400. In step S132, the semiconductor design system 100 can generate a power model of the selected via based on information of the decoupling capacitors DEC associated with the selected via and information of the board 400 (or information of the vias of the board 400). For example, the information of the decoupling capacitors DEC and the information of the board 400 can be obtained from a library.

[0141] In step S133, the semiconductor design system 100 can determine whether the power models have been generated for all the power vias. If the power models have not been generated for each of the power vias (step S133, No), the semiconductor design system 100 can repeat step S131 and step S132 until the power models of all the power vias are generated (step S133, Yes). Step S131 and step S133 can be performed for the power model of each semiconductor package. By combining the board power models corresponding to the power models of the semiconductor packages, a power model of the board on which the semiconductor packages are mounted (i.e., a system power model) can be obtained at the board level.

[0142] Figure 22 An example of generating a system power analysis of Figure 2 is shown. Referring to Figure 2 and Figure 1 Figure 22 An example of generating a system power analysis of Figure 2 is shown. Referring to Figure 2 and Figure 1 Figure 22In step S310, the semiconductor design system 100 can generate a power scenario for the semiconductor package operation.

[0143] In step S320, the semiconductor design system 100 can set a what-if condition for each board model. In step S330, the semiconductor design system 100 can perform system power analysis based on the power scenario and the what-if condition. For example, step S330 can correspond to (or can include in or can be the same as) step S140 of Figure 2

[0144] Figure 23 An example of generating a power scenario of Figure 22 (step S310 of) is shown. Referring to Figure 22 and Figure 1 In step S311, the semiconductor design system 100 can select one of the plurality of circuit blocks CB. In step S312, the semiconductor design system 100 can receive a maximum power and an idle power of the selected circuit block CB. Figure 23 In step S313, the semiconductor design system 100 can generate a transition scenario between an active state and an idle state as the power scenario. In step S314, the semiconductor design system 100 can determine whether the transition scenario has been generated for all the circuit blocks. If the transition scenario has not been generated for each of the circuit blocks (step S314, No), the semiconductor design system 100 can repeat steps S311 to S313 until the transition scenario of all the circuit blocks is generated (step S314, Yes).

[0145] In an embodiment,

[0146] An example of generating a power scenario for each circuit block is described in Figure 23 , but one same power scenario can be generated for the entire system power model of the semiconductor package.

[0147] Figure 24 An example of a power scenario generated by the method of Figure 23 is shown. In Figure 24 , a horizontal axis represents time “T” and a vertical axis represents current “I”. Referring to Figure 1 and Figure 24 , the semiconductor design system 100 can generate a power scenario in which the semiconductor package (or circuit block) enters an idle state Idle in which a first current I1 flows from an off state Off in which no current flows.

[0148] ​Furthermore, after entering the idle state Idle, the semiconductor design system 100 may generate a power scenario in which the semiconductor package has "M" transition cycles, each transition cycle including a transition from the idle state to the active state Active in which the second current I2 flows, and a transition from the active state Active to the idle state Idle. Furthermore, the semiconductor design system 100 may generate a power scenario in which the semiconductor package transitions to the off state Off after the "M" transition cycles.

[0149] In an example embodiment, the semiconductor design system 100 may generate two or more different power scenarios for each system power model or for each circuit block. These two or more different power scenarios may be executed consecutively, and this may be treated as if one power scenario were executed. For example, a power scenario may be interpreted as including two or more cycles that transition in different modes.

[0150] Figure 25 Show Figure 22 Steps to generate what-if conditions ( Figure 22 Example of step S320). Figure 1 and Figure 25 In step S321 , the semiconductor design system 100 may set the number of clock cycles required for the transition. For example, the semiconductor design system 100 may set the number of clock cycles required to transition from the idle state to the active state.

[0151] As the number of clock cycles increases, the power integrity of the system power model may increase, and system performance may improve. As the number of clock cycles decreases, the power integrity of the system power model may decrease, and system performance may deteriorate.

[0152] In step S322, the semiconductor design system 100 may set the number of decoupling capacitors. In step S323, the semiconductor design system 100 may set the capacitance of the decoupling capacitors. Through steps S322 and S323, the parameters associated with the decoupling capacitors of the power board model of the system power model may be adjusted.

[0153] Figure 26 Show Figure 2 Steps for generating system power analysis ( Figure 2 Example of step S140). Figure 2 and Figure 26 In step S141, the semiconductor design system 100 may generate a plurality of system power models. For example, the semiconductor design system 100 may use a SPICE program simulation platform (SPICE deck) to generate the system power models.

[0154] The semiconductor design system 100 can include a reference SPICE program simulation platform in the form of a template for various packages, such as a package-on-package (POP), a 2.5D package including an interposer, and a 3D package. The semiconductor design system 100 can easily generate a system power model by selecting a package type and modifying some parameters.

[0155] Figure 27 An example of a system power model 500 generated by the semiconductor design system 100 is shown. Referring to Figure 1 、 Figure 20 and Figure 27 , the system power model 500 can include a voltage source 510, a board impedance 520, a bump and solder ball impedance 530, an on-chip impedance 540, and a current sink 550.

[0156] The voltage source 510 can be a supply voltage that is the same as the supply voltage supplied by the PMIC 420. The board impedance 520 can be an impedance of a board power model. The bump and solder ball impedance 530 can be an impedance of a power bump and solder ball model. The on-chip impedance 540 can include on-chip capacitance and on-chip resistance of a circuit block. The current sink 550 can consume current according to a power scenario. A bump node BN can correspond to a power bump. A voltage of the bump node BN can be a voltage of the power bump.

[0157] Referring to Figure 1 、 Figure 26 and Figure 27 , in step S142, the semiconductor design system 100 can select one of the plurality of system power models 500. In step S143, the semiconductor design system 100 can perform a noise analysis based on a power scenario. For example, while the current sink 550 consumes current according to the power scenario, the semiconductor design system 100 can monitor a voltage change of the bump node BN.

[0158] In step S144, the semiconductor design system 100 can determine whether the noise is less than a threshold value. When the noise is less than the threshold value (step S144, Yes), in step S145, the semiconductor design system 100 can determine that the selected system power model 500 satisfies a system requirement. When the noise is not less than the threshold value (step S144, No), in step S146, the semiconductor design system 100 can determine that the selected system power model 500 does not satisfy the system requirement.

[0159] The semiconductor design system 100 can store the determination result. In step S147, the semiconductor design system 100 can determine whether the noise analysis is completed for all the system power models. If the noise analysis is not completed for all the system power models (step S147, No), the semiconductor design system 100 can repeat steps S142 to S146 until the noise analysis is completed for all the system power models (step S147, Yes).

[0160] After that, as described in step S150 with reference to FIG. 1C, the semiconductor design system 100 can display at least one system power model satisfying the system requirement to the user on the display device 174. The user can select an appropriate one of the system power models satisfying the system requirement, and can select a semiconductor layout corresponding to the selected system power model. Figure 2

[0161] As described above, according to example embodiments of the inventive concept, a system power model to which a change in layout planning is applied is generated, and a noise analysis is performed. Thus, the system power model and the semiconductor layout can be determined considering the influence of the layout planning on the system power model.

[0162] According to example embodiments of the inventive concept, the generation of layout planning, the generation of a power bump graph, the generation of a power connection graph, the generation of a power solder ball graph, the generation of a horizontal power model, the generation of a vertical power model, the generation of a chip-on power model including a chip-on resistor and a chip-on capacitor, the generation of a board power model, the generation of a system power model, and the analysis of the system power model can be performed by one tool. Thus, the user convenience in semiconductor design can be improved.

[0163] In example embodiments, the semiconductor design system 100 can also perform an analysis in a frequency domain as well as an analysis in a time domain. The semiconductor design system 100 can perform a noise analysis together with another simulation tool (e.g., Hspice), and the semiconductor design system 100 itself can also perform a noise analysis.

[0164] In example embodiments, the semiconductor design system 100 can perform a noise analysis using FFT (Fast Fourier Transform) and IFFT (Inverse FFT). By using the FFT, the semiconductor design system 100 can generate a frequency response Z(f) of impedance of the system power model 500, and can generate a frequency response I(f) of a power scenario.

[0165] The semiconductor design system 100 can generate a frequency response V(f) of a voltage of the bump node BN by multiplying the frequency response Z(f) of impedance and the frequency response I(f) of the power scenario ((V(f) = Z(f)*I(f)). The semiconductor design system 100 can obtain a time response of the voltage of the bump node BN based on the IFFT. ​

[0166] In an example embodiment, the semiconductor design system 100 can repeat the following operations: changing what-if conditions, generating a plurality of system power models, and performing noise analysis for each of the plurality of system power models.

[0167] In the above-described example embodiment, the term "constraint" and the term "information" are used to be distinguishable from each other. However, the term "constraint" and the term "information" can not be clearly distinguishable from each other, and can be interpreted according to context. For example, the "constraint" can include information about a rule that an identity to be constrained must follow. The "information" can include a "constraint" that a specific identity must follow. The terms "information" and "constraint" can be relative, and can be used interchangeably according to context.

[0168] In the above-described example embodiment, components according to the inventive concept are described by using the terms "first", "second", "third", and the like. However, the terms "first", "second", "third", and the like can be used to distinguish the components from each other, not to limit the inventive concept. For example, the terms "first", "second", "third", and the like do not involve any form of order or numerical meaning.

[0169] According to the inventive concept, a layout plan is automatically or semi-automatically generated by a tool implemented by a computer system. Accordingly, user convenience can be improved. In addition, since at least one is selected from power models based on various layout plans, power characteristics can be improved.

[0170] Although the inventive concept has been described with reference to the example embodiments of the inventive concept, it will be apparent to those having ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the claims appended below.

Claims

1. A method implemented using a computer system executing instructions for semiconductor design simulation, the method comprising: generating a plurality of floorplans, each of the plurality of floorplans comprising a plurality of circuit blocks positioned differently; generating a plurality of power models according to the plurality of floor plans; as well as A layout corresponding to one of the plurality of floorplans is selected by selecting at least one power model satisfying system requirements from among the plurality of power models.

2. The method according to claim 1, wherein The generating of the plurality of floorplans includes: The plurality of circuit blocks are placed in order from largest to smallest within the plurality of floorplans.

3. The method according to claim 1, wherein Generating the plurality of floorplans includes: Circuit blocks having a size greater than a threshold value are placed before circuit blocks having a size equal to or smaller than a threshold value among the plurality of circuit blocks in the plurality of floor plans.

4. The method according to claim 1, wherein Generating the plurality of floorplans includes: Circuit blocks configured as interfaces for communicating with external devices are placed on outer portions of the plurality of floorplans.

5. The method according to claim 1, wherein Generating the plurality of floorplans includes: Circuit blocks of the serializer and the deserializer are placed in outer portions of the plurality of floorplans.

6. The method of claim 1, wherein: The generating of the plurality of floorplans includes: A circuit block consuming the highest power among the plurality of circuit blocks is placed in a center of the plurality of floorplans.

7. The method of claim 1, wherein: The generating of the plurality of floorplans includes: Specific circuit blocks defined by the constraints among the plurality of circuit blocks are placed to be spaced apart from each other in the plurality of floorplans by a distance shorter than a specific distance defined by the constraints.

8. The method of claim 1, wherein: Generating the plurality of floorplans includes: discarding respective first floorplans each having a total size greater than a threshold; and Respective second floorplans each having a total size equal to or smaller than the threshold are generated as the plurality of floorplans.

9. The method of claim 1 , further comprising: assigning a higher priority to each of the plurality of floorplans as a total size of each of the plurality of floorplans decreases; as well as The plurality of floorplans are displayed through a display device based on a priority of each of the plurality of floorplans.

10. The method of claim 1, further comprising: displaying the plurality of layout plans on a display device; receiving, via an input device, a modification to at least one of the plurality of floorplans; as well as The modification is applied to the at least one floorplan.

11. The method according to claim 1, in, At least a portion of the instructions includes an algorithm learned based on machine learning, and Wherein, the generating of the plurality of floorplans is performed by using the algorithm.

12. A method implemented using a computer system executing instructions for semiconductor design simulation, the method comprising: generating a plurality of floorplans, each of the plurality of floorplans comprising a plurality of circuit blocks positioned differently; generating a plurality of power bump and solder ball models based on the plurality of floorplans; as well as A plurality of board power models are generated based on the plurality of power bump and solder ball models.

13. The method of claim 12, further comprising: A plurality of on-chip power models are generated based on the plurality of circuit blocks.

14. The method of claim 13, further comprising: generating a plurality of system power models based on the plurality of power bump and solder ball models, the plurality of on-chip power models, and the plurality of board power models; generating power scenarios for the plurality of system power models; simulating driving of the plurality of system power models based on the power scenario; as well as At least one system power model having power noise less than a threshold value among the plurality of system power models is displayed.

15. A method implemented using a computer system executing instructions for semiconductor design simulation, the method comprising: generating a plurality of floorplans, each of the plurality of floorplans comprising a plurality of circuit blocks positioned differently; as well as A plurality of power bump models are generated according to the plurality of circuit blocks.

16. The method of claim 15, wherein: The generating of the plurality of floorplans includes: placing power bumps of circuit blocks having the preset bump pattern among the plurality of circuit blocks according to a preset bump pattern; and Power bumps of circuit blocks not having the preset bump pattern among the plurality of circuit blocks are placed based on a bump pitch.

17. The method of claim 15, further comprising: connecting power bumps disposed within a distance defined by the constraint among the power bumps of the plurality of power bump models to generate a power connection graph; displaying the power connection diagram through a display device based on the constraint; receiving, via an input device, a modification to at least one of the power connection diagrams; as well as The modification is applied to the at least one power connection map.

18. The method of claim 15, further comprising: A plurality of power ball models are generated according to the plurality of power bump models.

19. The method of claim 18, wherein: The generation of the plurality of power ball models includes: identifying positions where power solder balls can be placed based on the plurality of power bump models; and The plurality of power ball models are generated, in which actual positions where the power ball is placed and the number of the power ball are different among the positions where the power ball can be placed.

20. The method of claim 18, further comprising: generating a first power model of a horizontal layer, the horizontal layer including horizontal connections between power bumps of the plurality of power bump models and power solder balls of the plurality of power solder ball models; generating a second power model of a vertical layer, the vertical layer including vertical connections between power bumps of the plurality of power bump models and power solder balls of the plurality of power solder ball models; as well as A plurality of power bump and solder ball models are generated according to the first power model and the second power model.

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