Method of forming a semiconductor device

Abstract

The present invention describes a method, which includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterojunction including the first 2D layer and the second 2D layer. The method also includes separating the first 2D layer of the heterojunction from the first substrate and attaching the heterojunction to the second substrate. The method also includes removing the carrier film from the second 2D layer. Some embodiments of the present application also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. Background Art

[0002] With the advancement of semiconductor technology, people have an increasing demand for larger storage capacity, faster processing systems, higher performance and lower costs. The semiconductor industry continues to reduce the size of semiconductor devices to meet these needs. Two-dimensional (2D) material layers can be used to form the channel region of semiconductor devices to reduce the device footprint and improve device performance. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first two-dimensional (2D) layer on a first substrate; attaching a second two-dimensional layer to a carrier film; bonding the second two-dimensional layer to the first two-dimensional layer to form a heterojunction including the first two-dimensional layer and the second two-dimensional layer; separating the first two-dimensional layer of the heterojunction from the first substrate; attaching the heterojunction to a second substrate; and removing the carrier film from the second two-dimensional layer.

[0004] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first two-dimensional layer on a metal layer; depositing a hard mask layer on a second two-dimensional layer; attaching a carrier film to the hard mask layer; bonding the second two-dimensional layer to the first two-dimensional layer to form a heterojunction including the first two-dimensional layer and the second two-dimensional layer; separating the first two-dimensional layer of the heterojunction from the metal layer; attaching the heterojunction to a second substrate; and removing the carrier film and the hard mask layer from the second two-dimensional layer.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, including: forming a first two-dimensional layer on a substrate; bonding a second two-dimensional layer to the first two-dimensional layer; separating the first two-dimensional layer from the substrate; bonding the first two-dimensional layer to a third two-dimensional layer to form a heterojunction including the first two-dimensional layer, the second two-dimensional layer and the third two-dimensional layer; and forming a transistor, including: forming a first source / drain region and a second source / drain region in the heterojunction; forming a channel region using a portion of the heterojunction between the first source / drain region and the second source / drain region; and forming a gate electrode above the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flow chart of a method for transferring a layer of 2D material according to some embodiments.

[0008] Figures 2 to 5 are different views showing a 2D material layer at various stages in its manufacturing process according to some embodiments.

[0009] Figure 6 is a flow chart of a method for transferring a layer of 2D material according to some embodiments.

[0010] Figures 7 to 10 are different views showing a 2D material layer at various stages in its manufacturing process according to some embodiments.

[0011] Fig.11 is a flow chart of a method for transferring a layer of 2D material according to some embodiments.

[0012] Figures 12 to 15 are different views showing a 2D material layer at various stages in its manufacturing process according to some embodiments.

[0013] Fig.16 is a flow chart of a method for transferring a layer of 2D material according to some embodiments.

[0014] Figures 17 to 21 are different views showing a 2D material layer at various stages in its manufacturing process according to some embodiments.

[0015] Fig.22A and Fig. 22B A 2D material heterojunction is shown in a transfer process according to some embodiments.

[0016] Fig.23 A three-dimensional (3D) monolithic semiconductor device is shown in accordance with some embodiments.

[0017] The illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which other components are arranged between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0020] As used herein, the term "nominal" refers to the expected or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. Typically, slight variations in manufacturing processes or tolerances result in the formation of a range of these values.

[0021] In some embodiments, the terms "about" and "substantially" may represent a given value that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value interpreted by a person skilled in the relevant art based on the teachings herein.

[0022] The present invention provides a method for forming an exemplary complementary metal oxide semiconductor (CMOS) device. The method can also be applied to form any suitable semiconductor structure, such as a full-all-around gate (GAA) field effect transistor (FET), a fin FET (finFET), a horizontal or vertical GAA finFET, and a planar FET. An example of a FET is a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET may have, for example, (i) a planar structure built into or on the plane of a substrate (semiconductor wafer), or (ii) a vertical structure. The term "fin field effect transistor" (FinFET) refers to a FET formed above a fin oriented vertically relative to the plane of the wafer. The term "vertical" as used herein refers to a surface that is nominally perpendicular to the substrate.

[0023] Despite the implementation of various enhancement techniques, such as novel device structures for enhanced electrostatic control, enhanced transport through strained channels, increasing dopant activity and reducing parasitic resistance, the performance and scalability of silicon-based transistors have reached fundamental limits. Scaling silicon-based transistors has always been challenging as higher storage densities are achieved by shrinking device size.

[0024] 2D materials are monolayer materials that are chemically bonded together and can be used in various applications to improve performance. For example, 2D materials can be used in semiconductor devices, electrodes, water purifiers, and optoelectronic devices. Single 2D monolayers can be stacked together to form a 2D material layer stack, and the thickness of the 2D material layer stack can be changed by stacking different numbers of single monolayers. 2D material stacks can be used to form channel regions in semiconductor transistor devices to reduce device footprint and improve device performance. In semiconductor devices, 2D materials can be realized by a thin film transfer process. The thin film transfer process may include attaching a monolayer of 2D material to a carrier film, removing a monolayer of 2D material from a main wafer and placing it on a semiconductor substrate for further manufacturing operations. Since the monolayer of 2D material has an atomic thickness, keeping the monolayer of 2D material highly clean is essential for achieving high performance and high yield of the device. However, byproducts of each manufacturing process and transfer process leave undesirable residues on the monolayer of 2D material, especially on 2-inch and 3-inch wafers with larger areas. Cleaning processes to remove interfacial contamination can damage the monolayer surface of 2D materials. For example, adsorbates such as water and hydrocarbons can cover the surface of 2D materials. Cleaning processes including plasma dry etching, wet etching, and annealing can increase surface roughness or etch through the monolayer, and etching byproducts can remain on the surface after the cleaning process. In addition, solvent cleaning processes can also leave residues on the monolayer surface.

[0025] Various embodiments of the present invention describe methods for forming a semiconductor device comprising a substantially residue-free 2D material (e.g., a residue-free 2D material). The 2D material layers can be stacked together by van der Waals forces and transferred to a substrate. In some embodiments, the interface between the 2D material monolayers can be substantially residue-free (e.g., no residue). In some embodiments, the top and bottom surfaces of the layer stack can also be substantially residue-free. In some embodiments, the first monolayer formed by the 2D material is attached to the second monolayer formed by the 2D material via van der Waals forces, thereby forming a van der Waals heterojunction. The stack can be attached to a carrier layer (e.g., a polymer film) and transferred to a substrate for further processing. Other 2D material monolayers can be added to the heterojunction by performing other attachment processes and wafer-level transfer processes. Among other aspects, the use of van der Waals forces to form a 2D material heterojunction can also provide advantages such as substantially residue-free surfaces and intact layers after transfer. In addition, in a wafer-level transfer process, 2D material layers can be bonded together without an adhesive.

[0026] Figure 1 1 is a flow chart of a method 100 for forming a heterojunction including 2D materials according to some embodiments. For illustration purposes, Figure 1 The operations shown will refer to Figures 2 to 5 The method 100 is described with reference to an exemplary manufacturing process shown in FIG. Depending on the particular application, the operations may be performed in a different order or not at all. It should be noted that the method 100 may not produce a complete semiconductor device. Therefore, it should be understood that other processes may be provided before, during, and after the method 100, and only some other processes are briefly described herein. Figures 2 to 5 The transfer process described in the foregoing can be performed under vacuum in the processing chamber to prevent the structures from being exposed to the surrounding environment. This can provide the advantage of preventing surface oxidation and adsorption of contaminants, which in turn increases the van der Waals forces at the interface. In some embodiments, the vacuum level can be maintained at about 1x10 -3 Torr and about 1x10 -5 Between the support.

[0027] refer to Figure 1 In operation 102, according to some embodiments, a first monolayer of a 2D material is deposited on a substrate. Figure 2As shown, the first monolayer 206 can be deposited on the substrate 201. In some embodiments, each structure is collectively referred to as a substrate for simplicity. For example, the substrate 201 may include a bulk substrate 202 and a metal layer 204. The bulk substrate 202 may be a carrier wafer and may be formed using suitable materials, such as basic semiconductors, compound semiconductors, alloy semiconductors, and any suitable materials. For example, silicon, silicon oxide, sapphire, silicon nitride, titanium nitride, silicon germanium, any suitable material, and combinations thereof may be used to form the bulk substrate 202. The metal layer 204 may be formed using a suitable metal material (such as copper). In some embodiments, nickel, gold, copper, ruthenium, tungsten, silver, cobalt, any suitable metal, and combinations thereof may be used to form the metal layer 204. The deposition process may be performed in a deposition chamber that maintains a vacuum to prevent the substrate or the deposited film from contacting the surrounding environment. Therefore, the top surface of the first monolayer 206 may be substantially free of residue after the deposition process.

[0028] The first monolayer 206 formed of a 2D material may be deposited on the metal layer 204. In some embodiments, the first monolayer 206 may be directly deposited on the bulk substrate 202. In some embodiments, a suitable 2D material (such as hexagonal boron nitride (h-BN) material) may be used to form the first monolayer 206. The first monolayer 206 may be deposited using a suitable deposition method, such as (i) atomic layer deposition (ALD); (ii) chemical vapor deposition (CVD), such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD) and any other applicable CVD; (iii) molecular beam epitaxy (MBE); (iv) any suitable epitaxy method; and (v) combinations thereof. The thickness t of the first monolayer 206 may be the thickness of a monolayer formed of a 2D material. For example, the thickness t of the first monolayer 206 formed using the h-BN material is about 0.33 nm. In some embodiments, the thickness t may be from about 0.30 nm to about 0.36 nm. In some embodiments, the thickness t may be from about 0.2 nm to about 0.8 nm.

[0029] refer to Figure 1 In operation 104, according to some embodiments, a second monolayer of 2D material is attached to the first monolayer of 2D material. Figure 3AAs shown, the second monolayer 310 is attached to the first monolayer 206. In some embodiments, a carrier film may be attached to the second monolayer 310 before the attachment process. For example, a carrier film 312 may be attached to the top surface of the second monolayer 310. In some embodiments, the carrier film 312 may be a polymer layer and bonded to the second monolayer 310. In some embodiments, the carrier film 312 may be formed using polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polypropylene carbonate (PPC), polystyrene (PS), any suitable polymer material, and combinations thereof. In some embodiments, the carrier film 312 may be attached to the second monolayer 310 by depositing a polymer material on the second monolayer 310 and removing the second monolayer 310 from the carrier substrate.

[0030] In some embodiments, the second monolayer 310 may be formed using a transition metal dichalcogenide (TMD). A suitable TMD may be represented by MX 2 , wherein M represents a transition metal element and X represents a chalcogen element. For example, the transition metal element may be molybdenum or tungsten. In some embodiments, the chalcogen element may be one of sulfur, selenium or tellurium. In some embodiments, other suitable TMD materials may be used. The thickness of the second monolayer 310 may be the thickness of a 2D material monolayer. For example, the thickness of the second monolayer 310 formed using molybdenum disulfide may be about 0.65 nm. In some embodiments, the thickness of the second monolayer 310 may range from about 0.45 nm to about 1.2 nm.

[0031] The first monolayer 206 and the second monolayer 310 can be attached to each other by van der Waals forces. The attachment process can be performed in a vacuum environment (e.g., a vacuum chamber) to avoid impurities or water contamination on the interface, thereby reducing the van der Waals forces. After the first monolayer 206 and the second monolayer 310 are in physical contact, an optional external force 314 can be applied to the top surface of the carrier film 312 to ensure uniform contact across the interface between the two monolayers. In some embodiments, the external force can generate about 60N / in at the interface between the surfaces. 2 and about 1600N / in 2 If the pressure is greater than 1600N / in 2 , it may cause physical damage to the membrane; if the pressure is less than 60N / in 2 , it may not be sufficient to increase the van der Waals bond strength. The attachment process may be performed in a vacuum environment (such as a processing chamber that maintains a vacuum). In some embodiments, the vacuum level may be maintained at about 1x10 -3 Torr and about 1x10 -5Since the support film 312 or other structures are not in contact with the first monolayer 206, the interface between the first monolayer 206 and the second monolayer 310 may be substantially free of residue.

[0032] although Figure 3A The first monolayer 206 and the carrier film 312 are shown as not in physical contact with each other, but the first monolayer 206 and the carrier film 312 can be edge-sealed to protect the second monolayer 310 during the transfer process and prevent contamination. In addition, the edge sealing can also enhance the structural integrity of the stacked layers (composed of the carrier film and the monolayers) during the transfer process. In order to seal the edges of the films before the wafer-level transfer process, the surface area of ​​the first monolayer 206 and the carrier film 312 can be greater than the surface area of ​​the second monolayer 310. For example, the first monolayer 206 can have a circular area with a diameter of about 2 inches, and the second monolayer 310 can have a circular area with a diameter less than 2 inches, such as between about 1.7 inches and about 1.9 inches. The diameter of the carrier film 312 can be about 2.1 inches to about 2.5 inches.

[0033] Due to the difference in surface area, the first monolayer 206 and the portion of the carrier film 312 that is not in contact with the second monolayer 310 may also overlap each other. Figure 3B As shown, the peripheral portion 312A of the carrier film 312 and the peripheral portion 206A of the first monolayer 206 can be deformed under the action of force 314 and physically contact each other to seal the second monolayer 310 after physical contact. In some embodiments, the physical contact between the first monolayer 206 and the carrier film 312 can result in the formation of a chemical bond or other attachment mechanism at the above-mentioned film interface, thereby improving the structural integrity of the stacked layer. The overlapping width of the peripheral portions 312A and 206A can be greater than about 0.5 mm to ensure a secure seal that can maintain its structural integrity during the transfer process.

[0034] refer to Figure 1 In operation 106, according to some embodiments, the first monolayer is separated from the substrate. Figure 4As shown, at the interface between the first monolayer 206 and the metal layer 204, the heterojunction formed by the first monolayer 206 and the second monolayer 310 is separated from the substrate 201. In order to achieve separation only at the interface between the first monolayer 206 and the metal layer 204 while maintaining the integrity of the heterojunction, an electrochemical layering method can be used. The layer stack including the substrate 201 can be immersed in an aqueous solution of sodium hydroxide (NaOH). By using the metal layer 204 as a cathode and the platinum (Pt) foil formed on the top of the carrier film 312 as an anode, a DC voltage can be applied to the layer stack. In some embodiments, the DC voltage applied can range from about 3V to about 5V. For example, the DC voltage applied can be about 4V. In the electrochemical layering method, the first monolayer 206 can be separated from the metal layer 204 by hydrogen formed at the interface between the first monolayer 206 and the metal layer 204. The first monolayer 206 and the second monolayer 310 can be combined together by van der Waals forces in the electrochemical layering method and then transferred to a suitable substrate. In some embodiments, other suitable TMD materials may be utilized.

[0035] refer to Figure 1 In operation 108, according to some embodiments, the first monolayer is attached to another substrate. Figure 5 As shown, the heterojunction 501 formed by the first monolayer 206 and the second monolayer 310 can be attached to another substrate 502 for use in other manufacturing processes. In some embodiments, the substrate 502 can be a 4-inch wafer formed using silicon or silicon oxide. In some embodiments, the substrate 502 can be a wafer having any suitable diameter. For example, the substrate 502 can be a wafer having a diameter of about 2 inches to about 12 inches. In some embodiments, the bottom surface of the first monolayer 206 can be attached to the top surface of the substrate 502 via a suitable attachment mechanism (such as van der Waals bonding, chemical bonding, bonding, any suitable bonding method and combination thereof). In some embodiments, the carrier film 312 can be removed using a suitable method, such as dry etching, wet etching, ashing, any suitable removal method and combination thereof. In some embodiments, due to the carrier film removal process and / or subsequent processes, residues may remain on the top surface of the second monolayer 310, but the interface between the first monolayer 206 and the second monolayer 310 can be protected without being exposed and remain substantially free of residues.

[0036] Figure 6 is a flow chart of a method 600 for forming a heterojunction including 2D materials according to some embodiments. For illustration purposes, Figure 6 The operations shown will refer to Figures 7 to 10The method 200 is described with reference to the exemplary manufacturing process shown. Depending on the particular application, the operations may be performed in a different order or not at all. It should be noted that the method 200 may not produce a complete semiconductor device. Therefore, it should be understood that other processes may be provided before, during, and after the method 600, and only some of the other processes are briefly described herein. For the sake of brevity, Figures 7 to 10 and Figures 2 to 5 Similar elements in are marked with the same annotations. Figures 7 to 10 The transfer process described in the foregoing can be performed under vacuum in the processing chamber to prevent these structures from contacting the surrounding environment. This can provide the advantage of preventing surface oxidation and adsorption of contaminants, which in turn increases the van der Waals forces at the interface. In some embodiments, the vacuum can be maintained at about 1x10 -3 Torr and about 1x10 -5 Between the support.

[0037] refer to Figure 6 In operation 602, according to some embodiments, a first monolayer of a 2D material is deposited on a substrate. Figure 7 As shown, the first monolayer 206 can be deposited on the substrate 201. In some embodiments, the first monolayer 206 can be directly deposited on the metal layer 204. Figure 2 The first monolayer 206 is similarly shown. Figure 7 The first monolayer 206 shown in FIG. 1 may be formed using h-BN material. In some embodiments, the first monolayer 206 may be directly deposited on the bulk substrate 202. The first monolayer 206 may be deposited using any suitable deposition method, such as ALD and CVD.

[0038] refer to Figure 6 In operation 604, according to some embodiments, a carrier film and a hard mask layer are attached to the second monolayer of 2D material. Figure 7 As shown, the bottom surface of the hard mask layer 711 can be attached to the top surface of the second monolayer 310. In addition, the carrier film 712 can be attached to the top surface of the hard mask layer 711. In some embodiments, Figure 7 The second monolayer 310 shown and the second monolayer 310 can be formed using similar materials. For example, the second monolayer 310 can be formed using TMD. A suitable TMD can be represented by MX 2, where M represents a transition metal element, and X represents a chalcogen element. Since the second monolayer 310 is formed of a 2D material having an atomic-level thickness, the hard mask 711 can provide additional mechanical support for the second monolayer 310 to improve its structural integrity during the manufacturing process, and protect it from chemical reactions during the formation and removal process of the carrier film 712. In some embodiments, the hard mask 711 can be formed of aluminum oxide, silicon nitride, silicon oxide, any suitable dielectric material, and combinations thereof. In some embodiments, the hard mask 711 can be deposited using ALD, CVD, PVD, any suitable deposition method, and combinations thereof. In some embodiments, the carrier film 712 can be formed with Figure 3A and Figure 3B The carrier film 312 is similar to the carrier film 312 shown. For the sake of simplicity, this is not described in detail herein. In some embodiments, the surface area of ​​the carrier film 712 and the first monolayer 206 can be greater than the surface area of ​​the second monolayer 310 and the hard mask 711. Applying an external force 714 to the top surface of the carrier film can improve the bonding uniformity and the van der Waals bond strength. The force 714 can be Figure 3A The force 314 shown is similar. For the sake of brevity, this is not described in detail herein.

[0039] refer to Figure 6 In operation 606, according to some embodiments, the second monolayer of 2D material is attached to the first monolayer of 2D material, and the first monolayer is separated from the substrate. Figure 8 As shown, the bottom surface of the second monolayer 310 is attached to the top surface of the first monolayer 206. In some embodiments, the above surfaces are attached by van der Waals bonding to form a heterojunction 701 including a pair of 2D material films having the first monolayer 206 and the second monolayer 310. The first monolayer 206 can be formed by performing a process similar to Figure 4 The separation process shown is separated from the substrate 201 by an electrochemical layering method. Figure 3B Similar to the sealing process shown, the peripheral area of ​​the carrier film 712 and the first monolayer 206 can be crimped and sealed together to protect the second monolayer 310 enclosed therebetween.

[0040] refer to Figure 6 In operation 608, according to some embodiments, the first monolayer of the 2D material is attached to another substrate. Fig. 9As shown, the bottom surface of the first monolayer 206 is attached to the substrate 902 so that the heterojunction 701 can be prepared for other manufacturing processes. In some embodiments, the substrate 902 can be a substrate, a semiconductor device, or any suitable semiconductor structure. In some embodiments, the substrate 902 can be a 4-inch wafer formed using silicon or silicon oxide. In some embodiments, after the first monolayer 206 is attached to the substrate 902, the carrier film 712 can be removed using a removal process. For example, a polymer remover or wet chemical etching can be used to remove the carrier film 712, thereby exposing the lower hard mask 711. Residues may remain on the top surface of the hard mask layer 711, but the top surface of the second monolayer 310 can be protected by the hard mask 711 and remain substantially free of residue during the carrier film 712 removal process.

[0041] refer to Figure 6 In operation 610, according to some embodiments, the hard mask layer is removed from a top surface of the second monolayer formed of the 2D material. Fig.10 As shown, in order to expose the lower second monolayer 310, the hard mask 711 can be removed. The hard mask 711 can be removed using plasma dry etching, wet chemical etching, any suitable etching method, and combinations thereof. After the removal process of the hard mask 711, the top surface of the second monolayer 310 can be substantially free of residues because the second monolayer 310 can be inert to the etching process for removing the hard mask 711. For example, compared with an organic polymer carrier film, less residue can be left on the second monolayer 310 after the hard mask 711 is removed.

[0042] Fig.11 is a flow chart of a method 1100 for forming a heterojunction including 2D materials according to some embodiments. For illustration purposes, Fig.11 The operations shown will refer to Figures 12 to 15 The method 1100 is described with reference to an exemplary manufacturing process shown in FIG. 11. Depending on the particular application, the operations may be performed in a different order or not at all. It should be noted that the method 1100 may not produce a complete semiconductor device. Therefore, it should be understood that other processes may be provided before, during, and after the method 1100, and only some of the other processes are briefly described herein. For the sake of brevity, Figures 12 to 15 and Figures 2 to 5 Similar elements in are marked with the same annotations. Figures 12 to 15 The transfer process described in the foregoing can be performed under vacuum in the processing chamber to prevent these structures from being exposed to the surrounding environment. This can provide the advantage of preventing surface oxidation and adsorption of contaminants, which in turn increases the van der Waals forces at the interface. In some embodiments, the vacuum can be maintained at about 1x10 -3 Torr and about 1x10 -5 Between the support.

[0043] refer to Fig.11 In operation 1102, according to some embodiments, a first monolayer of a 2D material is deposited on a substrate. Fig.12 As shown, the first monolayer 1206 can be deposited on the substrate 1202. In some embodiments, the first monolayer 1206 can be formed using a TMD. A suitable TMD can be represented by MX 2 , where M represents a transition metal element and X represents a chalcogen element. For example, the transition metal element may be molybdenum or tungsten. In some embodiments, the chalcogen element may be one of sulfur, selenium, or tellurium. In some embodiments, other suitable TMD materials may be used. The first monolayer 1206 may be deposited using ALD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, any suitable epitaxial method, and combinations thereof. In some embodiments, the substrate 1202 may be deposited with Figure 2 The illustrated substrate 1202 is similar and will not be described in detail herein for the sake of brevity.

[0044] refer to Fig.11 According to some embodiments, in operation 1104, a second monolayer formed of a 2D material is attached to a first monolayer formed of a 2D material. The bottom surface of the second monolayer 1210 may be attached to the top surface of the first monolayer 1206. The first monolayer 1206 and the second monolayer 1210 may be attached together by van der Waals bonding to form a heterojunction. In addition, a carrier film 1212 may be attached to the top surface of the second monolayer 1210. In some embodiments, the second monolayer 1210 may be formed using a 2D material such as h-BN. In some embodiments, the second monolayer 1210 may be formed using any suitable 2D material such as a TMD material. In some embodiments, the first monolayer 1206 and the second monolayer 1210 may be formed using different 2D materials. For example, the first monolayer 1206 may be formed using molybdenum disulfide, and the second monolayer 1210 may be formed using h-BN. The first monolayer 1206 and the second monolayer 1210 may be attached together by van der Waals bonding. In some embodiments, a carrier film 1212 may be attached to the top surface of the second monolayer 1210. The carrier film 1212 may be a polymer layer formed using PMMA, PVA, PPC, PS, any suitable polymer material, and combinations thereof. In some embodiments, the carrier film 1212 may be attached to the top surface of the second monolayer 1210. Figure 3A and Figure 3B The carrier film 312 shown is similar. For the sake of brevity, this is not described in detail herein. In some embodiments, external force 1214 can be used to increase bonding uniformity and strength. External force 1214 can be similar to force 314. For the sake of brevity, this is not described in detail herein.

[0045] refer to Fig.11According to some embodiments, in operation 1106, the first monolayer may be separated from the substrate and attached to the third monolayer. Fig.13 As shown, the first monolayer 1206 can be separated from the substrate 1202. In some embodiments, the first monolayer 1206 can be removed from the substrate 1202 using a separation process, such as a thermal release process, a laser release process, an ultraviolet (UV) treatment process, a chemical stripping process, any suitable removal process, and / or a combination thereof. In some embodiments, the peripheral region of the carrier film 1212 and the first monolayer 1206 can be bonded together, and the bonding strength can be sufficient to support mechanical separation of the first monolayer 1206 from the substrate 1202. In some embodiments, the first monolayer 1206 can be formed on a metal layer of the substrate 1202, and the separation process can use an electrochemical delamination method.

[0046] The first monolayer 1206 may be attached to a third monolayer 1322 formed of a 2D material. In some embodiments, the third monolayer 1322 may be formed using h-BN. In some embodiments, the third monolayer 1322 may be formed using a suitable 2D material, such as a TMD layer. In some embodiments, the first monolayer 1206 and the third monolayer 1322 may be formed using different 2D materials. In some embodiments, the first monolayer 1206 and the third monolayer 1322 may be attached to each other using van der Waals bonding. In some embodiments, an external force 1314 may be used to improve the uniformity of bonding at the interface. For example, force 1314 may be similar to force 314. In some embodiments, the surface area of ​​the first monolayer 1206 may be greater than the surface area of ​​the second monolayer 1210, and the bonding process may include physically bonding the peripheral area of ​​the first monolayer 1206 and the carrier film 1212 to protect the enclosed second monolayer 1210. Since these interfaces are sealed during the transfer process and are not exposed to contaminants, the interface between the first monolayer 1206 and the second monolayer 1210 and the interface between the first monolayer 1206 and the third monolayer 1322 can be substantially free of residue. The heterojunction 1401 includes the first, second and third monolayers 1206, 1210 and 1322 fixed together by the van der Waals bonding process, as described above. Fig.12 and Fig.13 shown.

[0047] refer to Fig.11 In operation 1108, according to some embodiments, the third monolayer is separated from the substrate. Fig.14As shown, the third monolayer 1322 can be separated from the substrate 1302. The third monolayer 1322 can be separated from the substrate 1302 by pulling the carrier film 1212 in a direction away from the substrate 1302. In some embodiments, the process of separating the third monolayer 1322 from the substrate 1302 can be similar to the process of separating the first monolayer 1202 from the substrate 1202. For the sake of brevity, this is not described in detail herein.

[0048] refer to Fig.11 In operation 1110, a third monolayer is attached to the substrate and the carrier film is removed according to some embodiments. Fig.15 As shown, the third monolayer 1322 of the heterojunction 1401 can be attached to the top surface of the substrate 1502. In some embodiments, the substrate 1502 can be connected to the Figure 2 The substrate 1502 is similar to the substrate 202 shown. In some embodiments, the substrate 1502 may include one or more additional layers and suitable semiconductor devices. Fig.15 1502. For example, substrate 1502 may include one or more non-active devices and logic devices embedded therein. In some embodiments, substrate 1502 may be a 4-inch wafer formed using silicon or silicon oxide. After heterojunction 1401 is transferred to the top surface of substrate 1502, carrier film 1212 may be removed. Carrier film 1212 may be removed using plasma dry etching, wet chemical etching, ashing, any suitable removal method, and combinations thereof.

[0049] Fig.16 is a flow chart of a method 1600 for forming a heterojunction comprising 2D materials according to some embodiments. For illustration purposes, Fig.16 The operations shown will refer to Figures 17 to 21 The method 1600 is described with reference to an exemplary manufacturing process shown in FIG. 16. Depending on the particular application, the operations may be performed in a different order or not at all. It should be noted that the method 1600 may not produce a complete semiconductor device. Therefore, it should be understood that other processes may be provided before, during, and after the method 1600, and only some of the other processes are briefly described herein. For the sake of brevity, Figures 17 to 21 and Figures 2 to 5 Similar elements in are marked with the same annotations. Figures 17 to 21 The transfer process described in the foregoing can be performed under vacuum in the processing chamber to prevent the structures from being exposed to the surrounding environment. This can provide the advantage of preventing surface oxidation and adsorption of contaminants, which in turn increases the van der Waals forces at the interface. In some embodiments, the vacuum can be maintained at about 1x10 -3 Torr and about 1x10 -5 Between the support.

[0050] refer to Fig.16In operation 1602, according to some embodiments, a first monolayer of a 2D material is deposited on a substrate. Fig.17 As shown, a first monolayer 1706 may be deposited on a substrate 1702. In some embodiments, a TMD may be used to form the first monolayer 1706. A suitable TMD may be represented by MX 2 , where M represents a transition metal element and X represents a chalcogen element. For example, the transition metal element may be molybdenum or tungsten. In some embodiments, the chalcogen element may be one of sulfur, selenium, or tellurium. In some embodiments, other suitable TMD materials may be used. The first monolayer 1706 may be deposited using ALD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, any suitable epitaxial method, and combinations thereof. In some embodiments, the first monolayer 1706 may be deposited with Fig.12 The first monolayer 1206 is similar to that shown in FIG. 1 . In some embodiments, the substrate 1702 may be Figure 2 The illustrated substrate 202 is similar and will not be described in detail herein for the sake of brevity.

[0051] refer to Fig.16 According to some embodiments, in operation 1604, a second monolayer formed of a 2D material is attached to a first monolayer formed of a 2D material. The bottom surface of the second monolayer 1710 may be attached to the top surface of the first monolayer 1706. The first monolayer 1706 and the second monolayer 1710 may be attached together by van der Waals bonding to form a heterojunction. In some embodiments, the second monolayer 1710 may be formed using a 2D material such as h-BN. In some embodiments, the second monolayer 1710 may be formed using any suitable 2D material such as a TMD material. In some embodiments, the first monolayer 1706 and the second monolayer 1710 may be formed using different 2D materials. For example, the first monolayer 1706 may be formed using molybdenum disulfide, and the second monolayer 1710 may be formed using h-BN. In addition, a hard mask 1711 may be formed on the top surface of the second monolayer 1710. Hard mask 1711 may be formed using a material similar to hard mask 711. For example, hard mask 1711 may be formed of an aluminum oxide material and deposited using ALD. Carrier film 1712 may be attached to the top surface of hard mask 1711. Carrier film 1712 may be similar to carrier film 312 and may be formed using, for example, PMMA, PVA, PPC, PS, any suitable polymer material, and combinations thereof. In some embodiments, bonding uniformity between bonding interfaces may be improved by applying external force 1714 similar to force 314. In some embodiments, a carrier film 1712 may be formed using a carrier film 1712 similar to force 314. Figure 3BThe carrier film 1712 and the peripheral region of the first monolayer 1706 are bonded together by a process similar to the process of the carrier film 312 and the first monolayer 206. For the sake of simplicity, this is not described in detail herein.

[0052] refer to Fig.16 In operation 1606, according to some embodiments, the first monolayer may be separated from the substrate and attached to the third monolayer to form a heterojunction of the 2D material. The first monolayer 1706 may be separated from the substrate 1702 by pulling the carrier film 1712 away from the substrate 1702. The separation process may be similar to the process of separating the first monolayer 1206 from the substrate 1202. For the sake of brevity, this is not described in detail herein.

[0053] After the first monolayer 1706 is separated from the substrate 1702, the first monolayer 1706 can be attached to a third monolayer 1822 formed of a 2D material. In some embodiments, the third monolayer 1822 can be formed using h-BN. In some embodiments, the third monolayer 1822 can be formed using a suitable 2D material (such as a TMD layer). In some embodiments, different 2D materials can be used to form the first monolayer 1706 and the third monolayer 1822. In some embodiments, the first monolayer 1706 and the third monolayer 1822 can be attached to each other using van der Waals bonding. In some embodiments, an external force 1814 can be used to improve the bonding uniformity at the interface. For example, force 1814 can be similar to force 314.

[0054] In some embodiments, the surface area of ​​the first monolayer 1706 can be greater than the surface area of ​​the second monolayer 1710, and the bonding process can include physically bonding the first monolayer 1706 to the peripheral area of ​​the carrier film 1712 to protect the enclosed second monolayer 1710. Since these interfaces are enclosed and not exposed to contaminants during the transfer process, the interface between the first monolayer 1706 and the second monolayer 1710 and the interface between the first monolayer 1706 and the third monolayer 1822 can be substantially free of residue. The heterojunction 1801 includes the first, second, and third monolayers 1806, 1810, and 1822 fixed together by the van der Waals bonding process, as described above. Fig.17 and Fig.18 shown.

[0055] refer to Fig.16 , in operation 1608, according to some embodiments, the third monolayer is separated from the substrate. Fig.19As shown, the third monolayer 1822 can be separated from the substrate 1802. The third monolayer 1822 can be separated from the substrate 1802 by pulling the carrier film 1712 away from the substrate 1802. The separation process can be similar to Fig.12 and Fig.14 The separation process shown is similar. For the sake of brevity, it is not described in detail herein.

[0056] refer to Fig.16 In operation 1610, a third monolayer is attached to the substrate and the carrier film is removed according to some embodiments. Fig. 20 As shown, the third monolayer 1822 of the heterojunction 1801 can be attached to the top surface of the substrate 1902. In some embodiments, the substrate 1902 can be connected to the Figure 2 1902. In some embodiments, substrate 1902 may include one or more additional layers and suitable semiconductor devices. Fig. 20 After the heterojunction 1801 is transferred onto the top surface of the substrate 1902, the carrier film 1712 may be removed. The carrier film 1712 may be removed using plasma dry etching, wet chemical etching, ashing, any suitable removal method, and combinations thereof.

[0057] refer to Fig.16 In operation 1612, according to some embodiments, the hard mask layer is removed from the top surface of the second monolayer. Fig.21 As shown, in order to expose the lower second monolayer 1810, the hard mask 1711 can be removed. The hard mask 1711 can be removed by plasma dry etching, wet chemical etching, any suitable etching method and a combination thereof. The removal process of the hard mask 1711 can be the same as Fig.10 The removal process is similar and will not be described in detail herein for the sake of brevity.

[0058] Fig.22A , Fig. 22B and Fig.23 It shows that Figure 1-21 An exemplary additive manufacturing process after forming a heterojunction is shown. Fig.22A and Fig. 22B It shows the formation of Fig.21 The heterojunction 1801 and the carrier film 2220 on the substrate 1902 are shown in plan view and cross-sectional view, respectively. Fig.22A A-A' plane view Fig. 22B Other suitable structures may be formed, and for simplicity, Fig.22A and Fig. 22B It is not shown. The carrier film 2220 can be used to transfer the heterojunction 1801 to other substrates for further processing.

[0059] like Fig.22A and Fig. 22B As shown, a carrier film 2220 may be formed on the top surface of the heterojunction 1801. For example, the carrier film 2220 may be formed on the top surface of the second monolayer 1710. In addition, the carrier film 2220 may also be deposited in the heterojunction 1801. For example, a carrier film grid 2221 may extend vertically (e.g., in the z direction) through the first, second, and third monolayers 1706, 1710, and 1822. The term "vertical" as used herein refers to being nominally perpendicular to the surface of the substrate. The carrier film grid 2221 may be formed by etching a plurality of trenches in the heterojunction 1801 and depositing a carrier film material in the trenches until the trenches are completely filled. In some embodiments, the carrier film grid 2221 and the carrier film 2220 may be formed using the same material (e.g., a polymer material). The deposition of the carrier film material may continue until the carrier film 2220 is formed on the top surface of the second monolayer 1710. Implementing the carrier film grid 2221 may improve the structural integrity of the heterojunction 1801 during the transfer process. The carrier film 2220 and the carrier film grid 2221 may be formed using materials and processes similar to those of the carrier film 312. For the sake of brevity, this will not be described in detail herein. Fig.22A and Fig. 22B As shown, the carrier film grid 2221 can divide the heterojunction 1801 into an array of tube cores 2230, and the tube cores contain 2D material heterojunctions. In some embodiments, the array boundaries of the tube cores 2230 can also be aligned with the heterojunctions 1801 transferred to the semiconductor wafer. In some embodiments, it is also possible to Figure 5 , 7 The carrier film grid 2221 is implemented in the heterojunctions 501, 701 and 1401 described in Figures 1 and 14, respectively.

[0060] Fig.23 A three-dimensional (3D) monolithic semiconductor structure including a semiconductor device having a 2D material heterojunction according to some embodiments is shown. Figures 1 to 22B One or more transfer processes described in can transfer 2D material heterojunctions to existing semiconductor devices. Other structures can be included in Fig.23 The structure shown is not shown for the sake of simplicity.

[0061] Fig.23 The illustrated 3D monolithic semiconductor structure may include a plurality of front-end-of-line (FEOL) structures 2300 and a plurality of back-end-of-line (BEOL) structures 2320 . Fig.21 , Fig.22A and Fig. 22B The heterojunction 1801 can be used Fig.22A and Fig. 22BThe carrier film 2220 and the carrier film grid 2221 shown in FIG. 2 are transferred to the top surface of the BEOL structure 2320. After the transfer process, the carrier film 2220 and the carrier film grid 2221 can be removed by a suitable etching process.

[0062] FEOL structure 2300 may include a plurality of transistors, such as transistor 2303, formed on substrate 2302. Substrate 2302 may be Figure 2 23. The transistor 2303 may include a substrate 2301, a pair of source / drain regions 2304, a gate dielectric layer 2305, a spacer 2306, a gate electrode 2307, and a source / drain contact 2308. The source / drain region refers to the source and / or drain junctions that form the two terminals of the FET. Other structures may be formed in the transistor 2303, and for the sake of simplicity, Fig.23 It is not shown.

[0063] The BEOL structure 2320 may include a plurality of interconnect structures formed in an interlayer dielectric (ILD) layer. For example, a via 2324 formed in the ILD layer 2322 may be electrically and physically connected to the source / drain contacts 2308 of the FEOL structure 2300. A conductive line 2326 formed in the ILD layer 2322 may be connected to one or more vias 2324 to achieve lateral (e.g., x-direction) electrical connection. The via 2324 may also be connected to other structures formed above the BEOL structure 2320. In some embodiments, the via 2324 and the conductive line 2326 may be formed using copper, cobalt, aluminum, any suitable conductive material, and combinations thereof.

[0064] The semiconductor structure 2340 may be formed on the BEOL structure 2320. The semiconductor structure 2340 may include a transistor 2343 of a 2D material heterojunction. For example, Fig.22A and Fig. 22B The heterojunction 1801 can be transferred and placed on the top surface of the ILD layer 2322 of the BEOL structure 2320. The heterojunction formed by the multiple layers of 2D materials can be used as a channel region 2345 to improve the device performance of the transistor 2343. Part of the heterojunction 1801 can be used as a channel region of the transistor 2343. Although Fig.23 Heterojunction 1801 is shown, but other heterojunctions may also be implemented in transistor 2343. For example, Figure 5 , Figure 7 and Fig.14The heterojunctions 501, 701 and 1401 described in the respective embodiments may also be implemented in the transistor 2343. Other 2D material layers may be added using the wafer-level transfer process described in the present invention until the nominal thickness or electrical performance of the heterojunction is achieved. Fig.23 As shown, transistor device 2343 may include a channel region 2345 formed between source / drain regions 2348. Source / drain regions 2348 may be formed using conductive materials such as copper and doped silicon. In some embodiments, channel region 2345 may be formed using a conductive material such as copper or doped silicon. Fig.22A and Fig. 22B The carrier film grid 2221 is shown formed by a tube core 2230 formed in the heterojunction 1810. The transistor device 2343 may also include a gate dielectric layer 2345, a spacer 2346, and a gate electrode 2347. Other structures may also be included in the transistor device 2343 and are not shown for simplicity. For example, one or more work function layers may be formed between the gate dielectric layer 2345 and the gate electrode 2347. The source / drain region 2348 of the transistor 2343 can be electrically connected to the source / drain contact 2308 of the transistor 2303 through an interconnect structure formed in the BEOL structure 2320. The source / drain region 2348 can be formed by etching the ILD layer 2342 and the heterojunction 1801 and depositing a conductive material in the opening. In some embodiments, the conductive material may include copper.

[0065] Various embodiments of the present invention describe methods for forming semiconductor devices comprising substantially residue-free 2D materials. 2D material layers can be stacked together by van der Waals forces and transferred to a substrate. A 2D material monolayer is attached to another 2D material monolayer by van der Waals forces to form a van der Waals heterojunction. Other 2D material monolayers can be added to the heterojunction by performing other attachment processes and wafer-level transfer processes. The stack can be attached to a carrier layer (e.g., a polymer film) and transferred to other substrates or devices for further processing. Among other aspects, the use of van der Waals forces to form a 2D material heterojunction can also provide advantages such as substantially residue-free surfaces and intact layers after transfer. In addition, in the wafer-level transfer process, 2D material layers can be bonded together without an adhesive.

[0066] In some embodiments, a method includes forming a first 2D layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterojunction including the first 2D layer and the second 2D layer. The method further includes separating the first 2D layer of the heterojunction from the first substrate and attaching the heterojunction to the second substrate. The method further includes removing the carrier film from the second 2D layer.

[0067] In some embodiments, the bonding comprises van der Waals bonding. In some embodiments, forming the first two-dimensional layer comprises depositing a hexagonal boron nitride (h-BN) material. In some embodiments, attaching the second two-dimensional layer to the carrier film comprises: growing the second two-dimensional layer on a support structure; and crimping the carrier film to the second two-dimensional layer. In some embodiments, growing the second two-dimensional layer comprises depositing a transition metal sulfide (TMD) material. In some embodiments, the transition metal sulfide material comprises MX 2 , wherein M comprises a transition metal element and X comprises a chalcogen element. In some embodiments, the carrier film comprises a polymer film. In some embodiments, attaching the heterojunction comprises attaching the first two-dimensional layer to a metal layer formed on the second substrate. In some embodiments, the method further comprises attaching a peripheral portion of the carrier film to a peripheral portion of the first two-dimensional layer. In some embodiments, attaching the peripheral portion of the carrier film comprises overlapping the peripheral portion of the carrier film with the first two-dimensional layer so that the second two-dimensional layer does not contact the carrier film and the peripheral portion of the first two-dimensional layer.

[0068] In some embodiments, the method includes forming a first 2D layer on a metal layer and depositing a hard mask layer on a second 2D layer. The method also includes attaching a carrier film to the hard mask layer and bonding the second 2D layer to the first 2D layer to form a heterojunction including the first 2D layer and the second 2D layer. The method also includes separating the first 2D layer of the heterojunction from the metal layer and attaching the heterojunction to a second substrate. The method also includes removing the carrier film and the hard mask layer from the second 2D layer.

[0069] In some embodiments, the bonding comprises van der Waals bonding. In some embodiments, forming the first two-dimensional layer comprises depositing a hexagonal boron nitride (h-BN) material. In some embodiments, attaching the second two-dimensional layer to the carrier film comprises growing the second two-dimensional layer on a support structure and crimping the carrier film onto the second two-dimensional layer. In some embodiments, growing the second two-dimensional layer comprises depositing a transition metal sulfide (TMD) material.

[0070] In some embodiments, a method includes forming a first 2D layer on a substrate and bonding a second 2D layer to the first 2D layer. The method also includes separating the first 2D layer from the substrate and bonding the first 2D layer to a third 2D layer to form a heterojunction including the first, second, and third 2D layers. The method also includes forming a transistor including forming a first source / drain region and a second source / drain region in the heterojunction; forming a channel region using a portion of the heterojunction between the first source / drain region and the second source / drain region; and forming a gate electrode on the channel region.

[0071] In some embodiments, growing the first two-dimensional layer comprises growing a transition metal sulfide (TMD) material. In some embodiments, the method further comprises: etching a plurality of trenches in the heterojunction; and depositing a carrier film in the plurality of trenches and on a top surface of the heterojunction. In some embodiments, the second two-dimensional layer and the third two-dimensional layer comprise hexagonal boron nitride (h-BN). In some embodiments, the method further comprises: attaching the third two-dimensional layer of the heterojunction to a top surface of another transistor; and electrically connecting the first source / drain region and the second source / drain region to a first terminal and a second terminal of the other transistor, respectively.

[0072] The foregoing describes the components of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that the present invention can be easily used as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a first two-dimensional layer on a first substrate; depositing a hard mask layer on the second two-dimensional layer; attaching a carrier film to the hard mask layer, the hard mask layer being in direct contact with the carrier film and the second two-dimensional layer; bonding the second two-dimensional layer to the first two-dimensional layer to form a heterojunction including the first two-dimensional layer and the second two-dimensional layer; attaching a peripheral portion of the carrier film to a peripheral portion of the first two-dimensional layer to seal the second two-dimensional layer between the carrier film and the first two-dimensional layer; separating the first two-dimensional layer of the heterojunction from the first substrate; attaching the heterojunction to a second substrate; as well as The carrier film is removed from the second two-dimensional layer.

2. The method according to claim 1, wherein: The bonding comprises van der Waals bonding.

3. The method according to claim 1, wherein: Forming the first two-dimensional layer includes depositing a hexagonal boron nitride material.

4. The method according to claim 1, further comprising: The hard mask layer is removed from the second two-dimensional layer.

5. The method according to claim 4, wherein: Growing the second two-dimensional layer includes depositing a transition metal sulfide material.

6. The method according to claim 5, wherein: The transition metal sulfide material includes MX2, wherein M includes a transition metal element and X includes a chalcogen element.

7. The method according to claim 1, wherein: The carrier film comprises a polymer film.

8. The method according to claim 1, wherein: Attaching the heterojunction includes attaching the first two-dimensional layer to a metal layer formed on the second substrate.

9. The method according to claim 1, wherein: The material of the first two-dimensional layer is different from the material of the second two-dimensional layer.

10. The method according to claim 9, wherein: Attaching the peripheral portion of the carrier film includes overlapping the peripheral portion of the carrier film with the peripheral portion of the first two-dimensional layer such that the second two-dimensional layer does not contact the peripheral portion of the carrier film and the peripheral portion of the first two-dimensional layer.

11. A method of forming a semiconductor device, comprising: forming a first two-dimensional layer on the metal layer; depositing a hard mask layer on the second two-dimensional layer; attaching a carrier film to the hard mask layer, the hard mask layer being in direct contact with the carrier film and the second two-dimensional layer; bonding the second two-dimensional layer to the first two-dimensional layer to form a heterojunction including the first two-dimensional layer and the second two-dimensional layer; attaching a peripheral portion of the carrier film to a peripheral portion of the first two-dimensional layer to seal the second two-dimensional layer between the carrier film and the first two-dimensional layer; separating the first two-dimensional layer of the heterojunction from the metal layer; attaching the heterojunction to a second substrate; as well as The carrier film and the hard mask layer are removed from the second two-dimensional layer.

12. The method according to claim 11, wherein: The bonding comprises van der Waals bonding.

13. The method according to claim 11, wherein: Forming the first two-dimensional layer includes depositing a hexagonal boron nitride material.

14. The method according to claim 11, wherein: The carrier film comprises a polymer film.

15. The method according to claim 14, wherein: Growing the second two-dimensional layer includes depositing a transition metal sulfide material.

16. A method of forming a semiconductor device, comprising: forming a first two-dimensional layer on a substrate; depositing a hard mask layer on the second two-dimensional layer; attaching a carrier film to the hard mask layer, the hard mask layer being in direct contact with the carrier film and the second two-dimensional layer; bonding the second two-dimensional layer to the first two-dimensional layer; attaching a peripheral portion of the carrier film to a peripheral portion of the first two-dimensional layer to seal the second two-dimensional layer between the carrier film and the first two-dimensional layer; separating the first two-dimensional layer from the substrate; bonding the first two-dimensional layer to a third two-dimensional layer to form a heterojunction including the first two-dimensional layer, the second two-dimensional layer, and the third two-dimensional layer; as well as Forming a transistor, comprising: forming a first source / drain region and a second source / drain region in the heterojunction; forming a channel region using a portion of the heterojunction between the first source / drain region and the second source / drain region; and A gate electrode is formed over the channel region.

17. The method according to claim 16, wherein: Growing the first two-dimensional layer includes growing a transition metal sulfide material.

18. The method according to claim 16, further comprising: etching a plurality of trenches in the heterojunction; as well as A carrier film is deposited in the plurality of trenches and on a top surface of the heterojunction.

19. The method according to claim 16, wherein: The second two-dimensional layer and the third two-dimensional layer include hexagonal boron nitride.

20. The method according to claim 16, further comprising: attaching the third two-dimensional layer of the heterojunction to a top surface of another transistor; as well as The first source / drain region and the second source / drain region are electrically connected to a first terminal and a second terminal of the further transistor, respectively.

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