Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first package component and a second package component stacked and electrically connected to each other. The first package component includes a first conductive bump and a second conductive bump, and the second package component includes a third conductive bump and a fourth conductive bump, and the size of the first conductive bump and the second conductive bump is smaller than the size of the third conductive bump and the fourth conductive bump. The semiconductor package includes a first bonding structure partially wrapping the first conductive bump and the third conductive bump, and a second bonding structure partially wrapping the second conductive bump and the fourth conductive bump. The curvature of the first bonding structure is different from the curvature of the second bonding structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor package and a manufacturing method thereof, and more particularly to a bonding structure in a semiconductor package and a manufacturing method thereof. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density comes from the continuous reduction in the minimum feature size, which enables more components to be integrated into a given area. These smaller electronic components also require smaller packages that occupy less area than previous packages. As a result, new packaging technologies have begun to be developed. For example, some packages rely on solder bumps to provide electrical connections, and the different layers that make up the interconnection in the package have different coefficients of thermal expansion (CTE). Therefore, relatively large stresses caused by such differences are manifested in the joint area, which can lead to the risk of delamination and / or cold joints. These relatively new types of semiconductor device packaging technologies face manufacturing challenges. Summary of the invention

[0003] According to some embodiments, a semiconductor package is provided. The semiconductor package includes a first package component and a second package component, the first package component and the second package component are stacked and electrically connected to each other, the first package component includes a first conductive bump and a second conductive bump, the second package component includes a third conductive bump and a fourth conductive bump, and the size of the first conductive bump and the size of the second conductive bump are smaller than the size of the third conductive bump and the size of the fourth conductive bump. The semiconductor package includes a first bonding structure, the first bonding structure partially wraps the first conductive bump of the first package component and the third conductive bump of the second package component. The semiconductor package includes a second bonding structure, the second bonding structure partially wraps the second conductive bump of the first package component and the fourth conductive bump of the second package component, and the curvature of the first bonding structure is different from the curvature of the second bonding structure.

[0004] According to some alternative embodiments, a semiconductor package is provided. The semiconductor package includes a first semiconductor die and a second semiconductor die laterally encapsulated by an insulating encapsulant. The semiconductor package includes a packaging component, which is disposed on the first semiconductor die, the second semiconductor die, and the insulating encapsulant. The first semiconductor die is electrically coupled to the second semiconductor die through the packaging component. The packaging component includes a central conductive bump and a peripheral conductive bump, the central conductive bump is bonded to the peripheral conductive bumps of the first semiconductor die and the second semiconductor die through a first bonding structure, and the peripheral conductive bump is bonded to the central conductive bump of the first semiconductor die and the second semiconductor die through a second bonding structure, and the central conductive bump and the peripheral conductive bump of the packaging component include a size smaller than the size of the corresponding peripheral conductive bump and the corresponding central conductive bump of the first semiconductor die and the second semiconductor die.

[0005] According to some alternative embodiments, a method for manufacturing a semiconductor package includes at least the following steps: forming a stack of conductive materials on a conductive pad to form a first conductive bump of a first package component; aligning the first conductive bump of the first package component with the second conductive bump of a second package component, wherein the corresponding first conductive bump is formed to have a solder-containing layer thicker than the thickness of the solder-containing layer of the corresponding second conductive bump; and combining the solder-containing layer of the corresponding first conductive bump of the first package component with the solder-containing layer of the corresponding second conductive bump of the second package component to form a bonding structure on the corresponding first conductive bump and the corresponding second conductive bump. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1D are schematic cross-sectional views of various stages in fabricating conductive bumps of a first package assembly according to some embodiments.

[0008] Figure 2 is a schematic top view of a first package assembly including conductive bumps according to some embodiments.

[0009] Figure 3 is a schematic cross-sectional view showing a package assembly to be bonded according to some embodiments.

[0010] Figure 4is a schematic top view of a warpage distribution of a first package assembly according to some embodiments.

[0011] Figures 5 to 20 is a schematic cross-sectional view illustrating a portion of a semiconductor package according to various embodiments.

[0012] Fig.21 is a schematic cross-sectional view showing a package assembly to be combined according to some embodiments.

[0013] Figure 22 to Figure 23 is a schematic cross-sectional view illustrating a portion of a semiconductor package including a package assembly bonded together according to various embodiments.

[0014] Fig.24 is a schematic cross-sectional view of a semiconductor package including a bonding structure according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0016] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC device can be tested, probes and / or probe cards can be used, and the like. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that includes intermediate verification of known good dies to improve yield and reduce costs.

[0018] Various embodiments for bonding any two package components together are described in conjunction with certain contexts. For example, various embodiments can be used to bond a device die, a device wafer, a fan-out package, a package substrate, an interposer, a printed circuit board (PCB), a motherboard, and the like to another device die, a device wafer, a fan-out package, a package substrate, an interposer, a printed circuit board (PCB), a motherboard, and the like.

[0019] Figures 1A to 1D is a schematic cross-sectional view of various stages of manufacturing a conductive bump of a first package assembly according to some embodiments, Figure 2 is a schematic top view of a first package assembly including a conductive bump according to some embodiments. Figure 1A A plurality of first conductive pads 114 may be distributed over a main surface 112 a (eg, a top surface) of the first semiconductor substrate 112 and a first passivation layer 116 may be formed on the main surface 112 a of the first semiconductor substrate 112 to partially cover the first conductive pads 114 .

[0020] For example, the first semiconductor substrate 112 includes a bulk semiconductor that may be doped or undoped, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, or the like. In some embodiments, the first semiconductor substrate 112 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline, or amorphous structure), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), galliumarsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate has a multilayer structure or the substrate includes a multilayer compound semiconductor structure. In some embodiments, an alloy SiGe is formed on a silicon substrate. As another option, the SiGe substrate is strained. The first semiconductor substrate 112 may include a semiconductor device (not shown) formed therein or thereon, which may be or may include an active device (e.g., a transistor, a diode, etc.) and / or a passive device (e.g., a capacitor, a resistor, an inductor, etc.), or other suitable electrical components. In some embodiments, the semiconductor device is formed on one side of the first semiconductor substrate 112 close to the main surface 112a. In some embodiments, active and / or passive devices are not formed in the first semiconductor substrate 112.

[0021] In some embodiments, the first semiconductor substrate 112 includes a circuit system (not shown) formed in a front-end-of-line (FEOL) process, and an interconnect structure (not shown) disposed on a main surface 112a of the first semiconductor substrate 112 is formed in a back-end-of-line (BEOL) process. The interconnect structures can be electrically coupled to semiconductor devices formed in and / or on the first semiconductor substrate 112 and to electronic components (e.g., test pads, bonding connectors, etc.). The semiconductor devices and the metallization patterns can be interconnected to perform one or more functions, including storage structures (e.g., storage cells), processing structures, input / output (I / O) circuit systems, or similar functions. In some embodiments, the interconnect structure includes an inter-layer dielectric (ILD) layer formed on the first semiconductor substrate 112 and covering the semiconductor devices, and an inter-metallization dielectric (IMD) layer formed on the ILD layer.

[0022] The first conductive pad 114 formed on the first semiconductor substrate 112 may include an aluminum pad. For example, the material of the first conductive pad 114 includes aluminum, copper, silver, gold, nickel, tungsten, alloys thereof, and / or multiple layers thereof. In some embodiments, the first conductive pad 114 is disposed on and electrically coupled to the interconnect structure, and the semiconductor device formed in the first semiconductor substrate 112 is electrically coupled to the first conductive pad 114 through the interconnect structure. In some embodiments, the material of the first passivation layer 116 includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other non-organic materials such as un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and multiple layers thereof. For example, the first passivation layer 116 includes an opening 116o, which exposes at least a portion of the first conductive pad 114 in an accessible manner for further electrical connection. It should be understood that the number of conductive pads and the single passivation layer are shown for illustration purposes only, and other embodiments may include any number of conductive pads and / or passivation layers.

[0023] Reference Figure 1B, a patterned mask layer PR is formed on the first passivation layer 116. For example, the patterned mask layer PR includes an opening PR', which exposes a portion of the first conductive pad 114 for forming a bump. In some embodiments, the opening PR' of the patterned mask layer PR is connected to the opening 116o of the first passivation layer 116, thereby exposing the underlying first conductive pad 114 in an accessible manner. The patterned mask layer PR can define the lateral boundaries of the conductive bump to be formed subsequently. In some embodiments, the opening PR' of the patterned mask layer PR has a width W1 that is smaller than the width Wp of the corresponding first conductive pad 114. In other embodiments, the width W1 of the opening PR' is greater than or substantially equal to the width Wp of the corresponding first conductive pad 114. The patterned mask layer PR may be a dry film or a photoresist film used by a coating step, a curing step and / or the like, a subsequent photolithography technique and / or an etching process such as a dry etching process and / or a wet etching process.

[0024] Reference Figure 1C to Figure 1D , the opening PR' of the patterned mask layer PR may be filled with a conductive material layer, and then the patterned mask layer PR may be removed. The formation method of the conductive material layer (e.g., the first conductive layer 122, the second conductive layer 124, the third conductive layer 126, and the fourth conductive layer 128A) may include plating, sputtering, printing, electrochemical deposition, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. In some embodiments, the conductive material layer is sequentially plated on the first conductive pad 114. For example, the first conductive layer 122 is first formed on the portion of the first conductive pad 114 exposed by the first passivation layer 116 and the patterned mask layer PR. In some embodiments, the first conductive layer 122 is a copper-containing layer. The first conductive layer 122 may include pure elemental copper, impurity-containing copper, and / or a copper alloy containing trace amounts of elements such as indium, titanium, tantalum, chromium, tin, zinc, manganese, germanium, platinum, magnesium, and aluminum.

[0025] Next, a second conductive layer 124 is formed on the first conductive layer 122. In some embodiments, the second conductive layer 124 and the first conductive layer 122 are composed of different materials. For example, the second conductive layer 124 is a nickel-containing layer. The second conductive layer 124 may include nickel, tin, tin-lead, gold, silver, platinum, palladium, indium, nickel-palladium-gold, nickel-gold, other similar materials or alloys. Next, a third conductive layer 126 may be formed on the second conductive layer 124. The third conductive layer 126 may include the same / similar conductive material as the first conductive layer 122. For example, both the first conductive layer 122 and the third conductive layer 126 are copper-containing layers, and the second conductive layer 124 sandwiched between the first conductive layer 122 and the third conductive layer 126 may be used as a barrier layer. In some embodiments, the third conductive layer 126 is omitted. Subsequently, a fourth conductive layer 128A may be formed on the third conductive layer 126. In some embodiments, the material of the fourth conductive layer 128A is different from the underlying conductive layers (122, 124 and 126). For example, the fourth conductive layer 128A is a solder-containing layer. The fourth conductive layer 128A may include lead-free solder such as tin, SnAg solder paste, SnBi solder, copper (tin-silver-copper (SAC)) solder, and / or combinations thereof, or the like.

[0026] After sequentially forming the conductive material layer on the first conductive pad 114, the patterned mask layer PR may be removed to expose a portion of the first passivation layer 116. In some embodiments where the patterned mask layer PR is formed of a photoresist material, the photoresist may be stripped by a chemical solution or another stripping process. Other suitable removal processes (e.g., ashing, etching, combinations thereof, etc.) may be used to remove the patterned mask layer PR. Thereafter, the first conductive bump 120A is completed on the individual first conductive pads 114.

[0027] Continue to refer to Figure 1D And refer to Figure 2 , a first package component 10 including a first conductive bump 120A is provided. The first package component 10 may be a semiconductor die (or chip) that is or includes any type of integrated circuit, such as a processor, a logic circuit system, a memory, an analog circuit, a digital circuit, a mixed signal integrated circuit, and the like. In some embodiments, the first package component 10 is a bridge die for interconnecting other package components, as will be described later in other embodiments. According to some embodiments, the top view profile of the first conductive bump 120A may be circular. Although the first conductive bump 120A shown is circular in shape, the first conductive bump 120A may have any shape, such as an ellipse, a rectangle, a polygon, a combination of these shapes, and / or the like.

[0028] Still refer to Figure 2, the first package component 10 includes at least a first region R1 and a second region R2 surrounding the first region R1, and the first conductive bumps 120A are distributed in an array on the first region R1 and the second region R2. The first region R1 may be located in the central region of the first package component 10, and the second region R2 may be along the peripheral region of the first package component 10. In some embodiments, the first conductive bumps 120A are formed with the same / similar critical dimensions on different regions within the first package component 10. For example, the first conductive bumps 120A in the first region R1 and the second region R2 have a substantially uniform lateral dimension LD1 (also referred to as the diameter or width of the first conductive bump 120A). In other words, the lateral dimension LD1 of the first conductive bumps 120A on the first package component 10 may remain constant in different regions. In some embodiments, the lateral dimension LD1 is in a range from about 10 μm to about 30 μm. The bump height of the first conductive bumps 120A on the first package component 10 may also remain constant in different regions. Alternatively, the size of the first conductive bumps 120A may be non-uniform due to formation process variations. For example, the first conductive bumps 120A located at the corners of the first package component 10 may have a slightly larger size than the first conductive bumps 120A located at the center of the first package component 10. It should be noted that the first conductive bumps 120A may have any suitable lateral dimension LD1 and bump height.

[0029] The size and characteristics of the first conductive bump 120A further include a bump pitch P1, which represents the distance between two adjacent first conductive bumps 120A. In some embodiments, the bump pitch P1 is in the range of about 20 μm to about 60 μm, but in other embodiments the bump pitch P1 may be larger or smaller. It should be noted that the dimensions stated throughout this article are examples only, and if different formation techniques are used, the dimensions will change. In some embodiments, the first conductive bumps 120A are uniformly distributed on the first package component 10. In some embodiments, dummy bumps (not shown) are formed at key locations to control the distribution and / or uniformity of the bump height on the first package component 10. In some embodiments, the first conductive bumps 120A located in the first region R1 have a bump density different from the bump density of the first conductive bumps 120A distributed in the second region R2. Depending on the die configuration, the bump density in the first region R1 may be denser or sparser than the bump density in the second region R2, which is not limited in the present disclosure.

[0030] Still refer to Figure 1D, the thickness 122T of the first conductive layer 122 can be measured from the interface between the first conductive pad 114 and the first conductive layer 122 to the interface between the first conductive layer 122 and the second conductive layer 124. For example, the thickness of the first conductive layer 122 is about 2 μm to 5 μm, but the thickness 122T may be larger or smaller. In some embodiments, the thickness 122T of the first conductive layer 122 is substantially equal to the thickness 126T of the third conductive layer 126. As another option, the thickness 122T of the first conductive layer 122 may be greater or less than the thickness 126T of the third conductive layer 126, as will be discussed later in other embodiments. In some embodiments, the thickness 124T of the second conductive layer 124 is less than the thickness 122T of the first conductive layer 122 and / or the thickness 126T of the third conductive layer 126. For example, the thickness of the second conductive layer 124 is about 2 μm to 10 μm, but the thickness 124T may vary. As another option, the thickness 124T of the second conductive layer 124 is greater than the thickness 122T of the first conductive layer 122 and / or the thickness 126T of the third conductive layer 126 , as will be discussed later in other embodiments.

[0031] The combination of thickness (122T, 124T and 126T) can be regarded as the total bump height BT of the first conductive bump 120A. In some embodiments, the ratio of the thickness 124T of the second conductive layer 124 to the total bump height BT is in the range of from about 0.1 to about 0.4. In some embodiments, the ratio of the thickness 128T of the fourth conductive layer 128A to the total bump height BT is in the range of from about 0.1 to about 0.7. In some embodiments, the fourth conductive layer 128A of the corresponding first conductive bump 120A has a substantially uniform thickness 128T. The thickness 128T of the fourth conductive layer 128A may vary depending on the estimated distance between the reflow temperature and the package components. Further details will be discussed below.

[0032] Figure 3 is a schematic cross-sectional view showing a package assembly to be bonded according to some embodiments, Figure 4 is a schematic top view of a warpage distribution of a first package assembly according to some embodiments. Figure 3 and Figure 4, the first package component 10 and the second package component 20 are designed and manufactured separately, and then the first package component 10 (e.g., a semiconductor die) is attached to the second package component 20 (e.g., an interposer, an integrated fan-out wafer, a package substrate, a printed circuit board, a motherboard, and the like). In some embodiments, the size of the first package component 10 is smaller than that of the second package component 20. For example, the second package component 20 includes a second semiconductor substrate 212, a plurality of second conductive pads 214 distributed on a main surface 212a of the second semiconductor substrate 212, and a second passivation layer 216 formed on the main surface 212a of the second semiconductor substrate 212 to partially cover the second conductive pads 214. The area of ​​the main surface 112a of the first package component 10 may be smaller than the main surface 212a of the second package component 20. In some embodiments, the second package component 20 includes a plurality of through substrate vias (TSVs) 213 penetrating through the second semiconductor substrate 212 and connected to the second conductive pads 214, so as to provide vertical electrical connections between opposite sides of the second semiconductor substrate 212. As another option, TSV 213 is omitted.

[0033] The second semiconductor substrate 212 may include silicon, gallium arsenide, semiconductor on insulator, or other similar materials. In some embodiments, the material of the second semiconductor substrate 212 is similar to the material of the first semiconductor substrate 112 of the first package component 10. In some embodiments, the second semiconductor substrate 212 includes FR-4, bismaleimidetriazine (BT) resin, ceramic, glass, or other supporting materials that can carry the second conductive pad 214. The second semiconductor substrate 212 may include passive devices (such as resistors, capacitors, inductors, etc.) or active devices (such as transistors). The second semiconductor substrate 212 may include additional integrated circuits. The second conductive pad 214 of the second package component 20 may include a conductive material, such as pure copper, aluminum copper, metal alloys, and / or other metal materials. The second passivation layer 216 includes an opening 216o, which exposes at least a portion of the second conductive pad 214 in a touchable manner for further electrical connection. The second passivation layer 216 may be formed of polyimide or other suitable dielectric materials such as silicon oxide, silicon nitride, undoped silicate glass (USG), polyimide and / or multilayers thereof. In some embodiments, the second passivation layer 216 is an anti-etching film. The second conductive pad 214 may be similar to the first conductive pad 114, and the second passivation layer 216 may be similar to the first passivation layer 116. In some embodiments, the second conductive pad 214 is electrically connected to the TSV 213 through a metal line and a through hole (not shown) formed in the dielectric layer (also not shown).

[0034] Continue to refer to Figure 3, the second package component 20 may include a plurality of second conductive bumps 220A formed on the second conductive pads 214. For example, the second conductive bumps 220A are physically and electrically connected to the second conductive pads 214 via the openings 216o in the second passivation layer 216. The formation process of the second conductive bumps 220A may be similar to the formation process of the first conductive bumps 120A. For example, the corresponding second conductive bumps 220A include a first conductive layer 222 formed on the corresponding second conductive pads 214, a second conductive layer 224 formed on the first conductive layer 222, a third conductive layer 226 formed on the second conductive layer 224, and a fourth conductive layer 228A formed on the third conductive layer 226. The materials of the first conductive layer 222, the second conductive layer 224, the third conductive layer 226, and the fourth conductive layer 228A may be the same or similar to the materials of the first conductive layer 122, the second conductive layer 124, the third conductive layer 126, and the fourth conductive layer 128A, respectively.

[0035] In some embodiments, the thickness 222T of the first conductive layer 222 is substantially equal to the thickness 226T of the third conductive layer 226. Alternatively, the thickness 222T of the first conductive layer 222 may be greater than or less than the thickness 226T of the third conductive layer 226. In some embodiments, the thickness 224T of the second conductive layer 224 is less than the thickness 222T of the first conductive layer 222 and / or the thickness 226T of the third conductive layer 226. Alternatively, the thickness 224T of the second conductive layer 224 is greater than the thickness 222T of the first conductive layer 222 and / or the thickness 226T of the third conductive layer 226. In some embodiments, the fourth conductive layer 228A of the corresponding second conductive bump 220A has a substantially uniform thickness 228T. The thickness 228T of the fourth conductive layer 228A may vary depending on the reflow temperature and / or the estimated distance between the package components.

[0036] Still refer to Figure 3One of the differences between the first conductive bump 120A of the first package component 10 and the second conductive bump 220A of the second package component 20 is that the critical dimension of the corresponding first conductive bump 120A is smaller than the critical dimension of the corresponding second conductive bump 220A. For example, the lateral dimension (e.g., maximum width) LD1 of the first conductive bump 120A is smaller than the lateral dimension (e.g., maximum width) LD2 of the second conductive bump 220A. In some embodiments, the ratio of the lateral dimension LD1 of the first conductive bump 120A to the lateral dimension LD2 of the second conductive bump 220A is substantially equal to or greater than 0.3. In some embodiments, the ratio (LD1 / LD2) is approximately 0.5 to 0.7. In some embodiments, the ratio (LD1 / LD2) is substantially equal to or less than 0.9. The ratio (LD1 / LD2) may be in the range from approximately 0.3 to approximately 1 or less than 1. In some embodiments where the first conductive bump 120A and / or the second conductive bump 220A is elliptical / rectangular in a top view, the size of the major axis of the first conductive bump 120A is smaller than the size of the major axis of the second conductive bump 220A. The size of the major axis of the first conductive bump 120A may be smaller than, equal to, or greater than the size of the minor axis of the second conductive bump 220A. Alternatively, the size of the major axis of the first conductive bump 120A may be smaller than the size of the major axis of the second conductive bump 220A.

[0037] The bump pitch P2 between two adjacent second conductive bumps 220A may be greater than the bump pitch P1 of the first conductive bump 120A. In some embodiments, the thickness 128T of the fourth conductive layer 128A of the first package component 10 is substantially equal to or greater than the thickness 228T of the fourth conductive layer 228A of the second package component 20. For example, the ratio of the thickness 128T of the fourth conductive layer 128A to the thickness 228T of the fourth conductive layer 228A is greater than 1. For example, the ratio of (128T / 228T) ranges from about 1 to about 3. For example, compared to the second conductive bump 220A, the first conductive bump 120A has a reduced critical dimension and a thicker fourth conductive layer 128A (i.e., a solder-containing layer). In some embodiments, the volume of the fourth conductive layer 128A of the first conductive bump 120A is substantially equal to the volume of the fourth conductive layer 228A of the corresponding second conductive bump 220A. The required volume of the fourth conductive layer (128A and 228A) for bonding the package components (10 and 20) may be determined by the analyzed warpage characteristics of the package components (10 and 20).

[0038] Continue to refer to Figure 3, in the subsequent process steps, each of the first conductive bumps 120A of the first package component 10 may be substantially aligned with any of the second conductive bumps 220A of the second package component 20. After stacking, a reflow process may be performed to melt the fourth conductive layer 128A of the first package component 10 and the fourth conductive layer 228A of the second package component 20 together. In some embodiments, the reflow process is performed by heating the first package component 10 / the second package component 20 to a temperature suitable for melting the fourth conductive layer (128A and 228A). For example, during the reflow process, the temperature is gradually increased until the temperature reaches the melting temperature of the fourth conductive layer (128A and 228A). In some embodiments where the fourth conductive layer (128A and 228A) is a solder-containing layer, the first package component 10 / the second package component 20 may be heated to a temperature that is the melting point of the fourth conductive layer (128A and 228A) or a temperature higher than the melting point of the fourth conductive layer (128A and 228A). For example, the temperature is raised to about 20°C higher than the melting temperature of the fourth conductive layer (128A and 228A). It should be noted that the reflow temperature may vary depending on the composition content of the solder-containing layer. For example, when the fourth conductive layer 128A and / or 228A includes SAC solder, the package assembly may be heated to a higher temperature (e.g., greater than about 200°C). In some embodiments where the fourth conductive layer 128A and / or 228A includes SnBi solder, the package assembly may be heated to a lower temperature (e.g., greater than about 130°C). After reflow, the temperature may be gradually reduced, and the fourth conductive layers (128A and 228A) are bonded together and cooled and solidified.

[0039] It should be understood that the application of heat may cause warping of the package component. Such warping may be caused by differences in the coefficient of thermal expansion (CTE) between different materials. When heated, one or both package components will warp, and the distance between the two may vary, depending on the distance from the center of the package component and the temperature. For example, the distance between the two package components (10 and 20) varies in different areas due to warping. The first package component 10 may have a tendency to form a convex warp or a concave warp. Throughout the text, when the package component is placed with the conductive bump facing down and the warping causes the edge of the package component to be higher than the center of the package component, such warping is referred to as having a concave warp. In contrast, if the edge of the package component is lower than the center of the package component, such warping is referred to as having a convex warp. In some embodiments, the first package component 10 presents a complex warp, rather than a simple convex warp or a simple concave warp.

[0040] In some embodiments, the warpage characteristics of the package assembly are analyzed prior to the bonding process. Figure 4As shown, the first package component 10 has a warpage after the reflow process, and the degree of warpage on the first package component 10 can be divided into different zones (e.g., Z1 to Z5). Each zone may have a different amount of warpage. In some embodiments, the amount of warpage of the first package component 10 gradually decreases from Z1 to Z5. As another option, the amount of warpage of the first package component 10 gradually increases from Z1 to Z5. In some embodiments, the warpage distribution is substantially concentric. It should be noted that the warpage distribution divided into five zones is only an example, and the warpage distribution can be divided into fewer zones or more than five zones. It should also be understood that when the package component is heated to a higher temperature, the amount of warpage of the package component is greater than when the package component is heated to a lower temperature. For example, when the package component is subjected to the higher temperature during reflow, the amount of warpage of the package component is greater than 10μm. In some embodiments where the first package assembly 10 is to be heated to the higher temperature during the reflow process, the fourth conductive layer 128A of the first conductive bump 120A is formed to have a greater thickness 128T than when the first package assembly 10 is to be heated to a lower temperature. The amount of the fourth conductive layer 128A (i.e., the solder-containing layer) applied is increased and causes downward flow with the help of gravity. The critical dimension of the first conductive bump 120A and the thickness 128T of the fourth conductive layer 128A can be adjusted depending on the reflow temperature.

[0041] Figures 5 to 20 1 is a schematic cross-sectional view showing a portion of a semiconductor package according to various embodiments. In all the various drawings and exemplary embodiments of the present disclosure, the same reference numerals are used to represent the same elements. Figure 5 And refer to Figure 3 After the reflow process, the first package component 10 is attached to the second package component 20 to form a semiconductor package SP1, and a bonding structure JA connecting the first conductive bump 120 and the corresponding second conductive bump 220 is formed between the first package component 10 and the second package component 20. For example, after the reflow process, the fourth conductive layer 128A of the first package component 10 and the corresponding fourth conductive layer 228A of the second package component 20 are combined together to form the bonding structure JA. According to some embodiments, the bonding structure JA may be referred to as a solder joint. By reducing the critical dimension of the first conductive bump 120 of the first package component 10 while keeping the solder-containing layer (128A and 228A) at the same volume, the internal connection defects (such as cold connection and bridging) of the bonding structure JA can be eliminated.

[0042] In some embodiments, after the first package component 10 is bonded to the second package component 20, an underfill layer UF is formed in the gap G between the first package component 10 and the second package component 20. For example, the underfill layer UF is dispensed around the bonding structure JA to provide structural support and protection to the bonding structure JA. In some embodiments, the underfill layer UF climbs upward to partially cover the sidewalls of the first package component 10. The underfill layer UF may be made of a polymer such as a resin, epoxy resin, or other suitable material. In some embodiments, the underfill layer UF includes a filler such as silica to adjust the mechanical strength. As another option, the underfill layer UF is omitted.

[0043] Continue to refer to Figure 5 , the first package component 10 has a concave warpage after the reflow process. In some embodiments where the second package component 20 has a larger size than the first package component 10, the amount of warpage of the second package component 20 may be relatively small compared to the warpage of the first package component 10. For example, the first package component 10 is warped and the edge 10e is bent upward, wherein the central area of ​​the first package component 10 is lower than the peripheral area of ​​the first package component 10 relative to the main surface 212a of the second package component 20. The main surface 112a of the first package component 10 may present a concave curve in a cross-sectional view, resulting in the first conductive bump 120 in the central area (also referred to as the central bump 1201 in the present disclosure) being lower than the first conductive bump 120 in the peripheral area (also referred to as the corner bump 1202 in the present disclosure).

[0044] Still refer to Figure 5 And refer to Figure 4 , Figure 5 The first packaging component 10 shown may be along Figure 4 A cross-sectional view taken along the line II' shown. The amount of warpage of the first package component 10 can be divided into different zones and the vertical distance between the two package components (10 and 20) can vary in different zones due to the warpage. For example, a zone (such as Z1) within / near the central zone of the first package component 10 is closer to the second package component 20 than a zone (such as Z5) close to the edge 10e of the first package component 10. The vertical distance between the first package component 10 and the second package component 20 can be referred to as the standoff of the semiconductor package SP1. The standoff can vary on the semiconductor package SP1 depending on the warpage distribution. In some embodiments, the standoff SF1 in the central zone is smaller than the standoff SF2 in the peripheral zone. In other words, the semiconductor package SP1 has a higher standoff at the peripheral zone and a lower standoff at the central zone.

[0045] Still refer to Figure 5, the central axis A11 of the center bump 1201 may be substantially aligned with the central axis A21 of the center bump 2201. Due to warping, the central axis A12 of the corner bump 1202 is not aligned with the central axis A22 of the corner bump 2202. For example, the central axis A12 is offset clockwise (or counterclockwise according to some embodiments) relative to the central axis A22 by an angle α. Such an angle α may be an acute angle, which depends on the amount of warping. The angle between the central axes (A11 and A21) may be minimal or may not exist. For example, the central axes (A11 and A21) may be substantially parallel to each other due to misalignment or formation process variations. The surfaces of the conductive bumps (120 and 220) facing each other may be regarded as the main surfaces (1201a and 2201a). For example, the lateral dimension (such as width) of the main surface of the first conductive bump 120 is smaller than the lateral dimension of the main surface of the corresponding second conductive bump 220. The surface area of ​​the major surface of the first conductive bump 120 may be smaller than the surface area of ​​the major surface of the corresponding second conductive bump 220. The vertical distance may be measured from the center of the major surface of the conductive bumps (120 and 220). In some embodiments, due to the concave warping, the vertical distance VD1 between the center bumps (1201 and 2201) is smaller than the vertical distance VD2 between the corner bumps (1202 and 2202).

[0046] Continue to refer to Figure 5 , the center bump 1201 of the first package component 10 is coupled to the center bump 2201 of the second package component 20 through the bonding structure JA1. The corner bump 1202 of the first package component 10 is coupled to the corner bump 2202 of the second package component 20 through the bonding structure JA2. The bonding structure JA1 is sandwiched between the center bumps (1201 and 2201) and may at least partially cover the third conductive layer 126 of the center bump 1201 and the third conductive layer 226 of the center bump 2201. Similarly, the bonding structure JA2 is sandwiched between the corner bumps (1202 and 2202) and may at least partially cover the third conductive layer 126 of the corner bump 1202 and the third conductive layer 226 of the corner bump 2202. The bonding structure JA may extend to cover the second conductive layer (124 and 224) or further extend to cover the first conductive layer (122 and 222), as will be described later in other embodiments.

[0047] Continue to refer to Figure 5, in the cross-sectional view, the width of the bonding structure JA increases continuously from the end point of the boundary on the side wall of the conductive bump to the midpoint of the boundary. In some embodiments, the bonding structure JA2 covering the corner bumps (1202 and 2202) has a substantially elliptical cross-section extending along the first direction D1. The bonding structure JA1 covering the center bumps (1201 and 2201) may have a substantially elliptical cross-section extending along the second direction D2. The first direction D1 may be substantially parallel to the height or thickness direction, and the second direction D2 may be substantially parallel to the width direction. In some embodiments, the bonding structure JA extends along a direction D3 that is not perpendicular to the second direction D2 and / or the first direction D1. The angle between the direction D3 and the second direction D2 depends on the amount of warping and is not limited in the present disclosure.

[0048] The cross section of the bonding structure JA can be in different regions (such as Figure 4 In some embodiments, in the cross-sectional view, the curvature of the outer surface of the bonding structure JA1 covering the center bump (1201 and 2201) is greater than the curvature of the outer surface of the bonding structure JA2 covering the corner bump (1202 and 2202). For example, in the cross-sectional view, the curvature of the outer surface of the corresponding bonding structure JA on a pair of first conductive bumps / second conductive bumps gradually decreases from the bonding structure covering the center bump (1201 and 2201) to the bonding structure covering the corner bump (1202 and 2202). In some embodiments, the sidewall 120s of the first conductive bump 120 (or the sidewall 220s of the second conductive bump 220) forms an angle with a tangent at an endpoint of the boundary of the bonding structure JA. For example, the angle θ1 between the side wall (120s or 220s) of the center bump (1201 or 2201) and the tangent line TL1 at the endpoint of the boundary of the bonding structure JA1 is smaller than the angle θ2 between the side wall (120s or 220s) of the corner bump (1202 or 2202) and the tangent line TL2 at the endpoint of the boundary of the bonding structure JA2.

[0049] Still refer to Figure 5 , the maximum width MW1 of the bonding structure JA1 covering the center bumps (1201 and 2201) may be greater than the maximum width MW2 of the bonding structure JA2 covering the corner bumps (1202 and 2202). The maximum width of the corresponding bonding structure JA may be greater in different regions (such as Figure 41 to 2202). For example, the maximum width of the corresponding bonding structure JA decreases from the bonding structure covering the center bump (1201 and 2201) to the bonding structure covering the corner bump (1202 and 2202). In some embodiments, the shortest lateral distance LS1 between the bonding structure JA1 and its adjacent bonding structure is less than the shortest lateral distance LS2 between the bonding structure JA2 and its adjacent bonding structure. It should be understood that the above description provides a general description of the features of the embodiments, and many other features may exist. It should also be understood that the above description is intended only to provide the content of the embodiments discussed herein, and is not intended to limit the present disclosure.

[0050] Reference Figure 6 , showing a partial view of a semiconductor package SP2. The semiconductor package SP2 may be formed by combining a first package component 10 with a second package component 20. In some embodiments, the analyzed warpage characteristics of the first package component 10 (in some embodiments, together with the second package component 20) are used to determine the desired critical dimensions of the first conductive bump and the solder-containing layer (e.g., Figure 3 The desired volume of the fourth conductive layer 128A shown in FIG. 1 . For example, analyzing the warpage characteristics may include estimating / simulating the spacing between the two package components (10 and 20) after bonding. In some embodiments, Moiré measurement is used to analyze / predict the warpage of the package component, and other methods may also be used to analyze the warpage. During the bonding process, heating of the first package component 10 and / or the second package component 20 at a predetermined temperature and for a predetermined time is performed to form a semiconductor package SP2 having a bonding structure JB that couples the first conductive bump 120 with the corresponding second conductive bump 220. The semiconductor package SP2 can be formed by a suitable method described in the preceding paragraphs, and therefore, for simplicity, it will not be repeated herein.

[0051] Continue to refer to Figure 6 And refer to Figure 5 The semiconductor package SP2 including the first package component 10 having a concave warpage profile may be similar to Figure 5 The semiconductor package SP2 is different from the semiconductor package SP1 in that the bonding structure JB of the semiconductor package SP2 extends along the thickness direction thereof to at least partially cover the second conductive layer 124 of the first conductive bump 120 and / or the second conductive layer 224 of the second conductive bump 220. The extent to which the bonding structure JB covers the first conductive bump and the second conductive bump (120 and 220) can be determined by Figure 3 For example, when forming the fourth conductive layer 128A (shown in FIG. Figure 1CWhen the third conductive layer 126 is plated with a larger amount of solder, the surface area of ​​the first conductive bump 120 and the corresponding second conductive bump 220 wrapped by the bonding structure JB can be larger after reflow. For example, the bonding structure JB covers not only the third conductive layer (126 and 226) but also the second conductive layer (124 and 224). In some embodiments, the bonding structure further extends to cover the first conductive layer (122 and 222), as shown by the dot-dash line in the enlarged figure.

[0052] Continue to refer to Figure 6 Due to the concave warping of the first package component 10, the interval between the first package component 10 and the second package component 20 may gradually increase from the center to the edge of the semiconductor package SP2. For example, the interval SF2 corresponding to the corner bumps (1202 and 2202) is greater than the interval SF1 corresponding to the center bumps (1201 and 2201). In some embodiments, the first package component 10 is warped and the edge 10e is bent upward, resulting in the center axis A12 of the corner bump 1202 being offset relative to the center axis A22 of the corner bump 2202. The amount of warping in the center area of ​​the first package component 10 may be minimal, so that the center axis A11 of the center bump 1201 is substantially aligned with the center axis A21 of the center bump 2201. In some embodiments, due to the concave warping, the vertical distance between the main surfaces of the corresponding first conductive bumps and the second conductive bumps may gradually increase from the conductive bumps located in the center area of ​​the semiconductor package SP2 to the conductive bumps located in the peripheral area of ​​the semiconductor package SP2. For example, the vertical distance VD1 between the center bumps ( 1201 and 2201 ) is smaller than the vertical distance VD2 between the corner bumps ( 1202 and 2202 ).

[0053] Still refer to Figure 6 And refer to Figure 5, the cross-sectional view of the bonding structure JB of the semiconductor package SP2 may be similar to the cross-sectional view of the bonding structure JA of the semiconductor package SP1. Therefore, the detailed description of the bonding structure JB is simplified herein. For example, the curvature of the outer surface of the bonding structure JB2 covering the corner bumps (1202 and 2202) may be smaller than the curvature of the outer surface of the bonding structure JB1 covering the center bumps (1201 and 2201). The curvature of the outer surface of the corresponding bonding structure JB on a pair of first conductive bumps and second conductive bumps may gradually increase from the bonding structure covering the corner bumps (1202 and 2202) to the bonding structure covering the center bumps (1201 and 2201). In some embodiments, the maximum width MW2 of the bonding structure JB2 covering the corner bumps (1202 and 2202) is smaller than the maximum width MW1 of the bonding structure JB1 covering the center bumps (1201 and 2201). The maximum width of the corresponding joint structure JB may increase from the joint structure covering the corner bumps (1202 and 2202) to the joint structure covering the center bumps (1201 and 2201). The shortest lateral distance LS2 between the joint structure JB2 and its adjacent joint structure may be greater than the shortest lateral distance LS1 between the joint structure JB1 and its adjacent joint structure.

[0054] Reference Figure 7 , showing a partial view of a semiconductor package SP3. The semiconductor package SP3 may be formed by coupling a first package component 30 to a second package component 20. The first package component 30 may be similar to the above-described first package component 10, except that the first conductive bump 320 has a third conductive layer 126' thicker than the corresponding first conductive layer 122. In other words, the corresponding first conductive bump 320 of the first package component 30 includes a third conductive layer 126' having a thickness 126T' greater than the thickness 122T of the first conductive layer 122. The thickness 124T of the second conductive layer 124 may be the thinnest of the conductive layers of the first conductive bump 320. Alternatively, the third conductive layer 126' is the thickest layer of the first conductive bump 320, and the first conductive layer 122 is the thinnest layer of the first conductive bump 320. It should be noted that the semiconductor package SP3 may be formed by the above-described suitable method, and therefore will not be described in detail herein.

[0055] The semiconductor package SP3 includes a first package component 30 having a concave warpage profile similar to Figure 5. The first package component 10 of the semiconductor package SP1 described in . The bonding structure JC that couples the first conductive bump 320 to the second conductive bump 220 may be similar to the bonding structure JA of the semiconductor package SP1, so the detailed description is simplified for the sake of brevity. For example, due to the concave warping of the first package component 30, the spacing between the first package component 30 and the second package component 20 may gradually decrease from the edge to the center of the semiconductor package SP3. In some embodiments, the spacing SF2 corresponding to the corner bumps (3202 and 2202) is greater than the spacing SF1 corresponding to the center bump (3201 and 2201). For example, the first package component 30 is warped and the edge 30e is bent upward, causing the center axis A32 of the corner bump 3202 to be offset relative to the center axis A22 of the corner bump 2202. The amount of warping in the center area of ​​the first package component 30 may be minimal, so that the center axis A31 of the center bump 3201 is substantially aligned with the center axis A21 of the center bump 2201. Due to the concave warping of the first package component 30, the vertical distance between the main surfaces of the corresponding first conductive bumps and the second conductive bumps can gradually decrease from the conductive bumps located in the peripheral area of ​​the semiconductor package SP3 to the conductive bumps located in the central area of ​​the semiconductor package SP3. For example, the vertical distance VD1 between the central bumps (3201 and 2201) is smaller than the vertical distance VD2 between the corner bumps (3202 and 2202).

[0056] Continue to refer to Figure 7 The cross-sectional view of the bonding structure JC of the semiconductor package SP3 may be similar to Figure 5 A cross-sectional view of the bonding structure JA of the semiconductor package SP1 is shown. For example, the curvature of the outer surface of the bonding structure JC1 covering the center bump (3201 and 2201) is greater than the curvature of the outer surface of the bonding structure JC2 covering the corner bump (3202 and 2202). The curvature of the outer surface of the corresponding bonding structure JC on a pair of first conductive bumps and second conductive bumps may gradually decrease from the bonding structure covering the center bump (3201 and 2201) to the bonding structure covering the corner bump (3202 and 2202). In some embodiments, the maximum width MW1 of the bonding structure JC1 covering the center bump (3201 and 2201) is greater than the maximum width MW2 of the bonding structure JC2 covering the corner bump (3202 and 2202). The maximum width of the corresponding bonding structure JC may decrease from the bonding structure covering the center bump (3201 and 2201) to the bonding structure covering the corner bump (3202 and 2202). The shortest lateral distance LS1 between the engagement structure JC1 and its adjacent engagement structures may be smaller than the shortest lateral distance LS2 between the engagement structure JC2 and its adjacent engagement structures.

[0057] Reference Figure 8, showing a partial view of the semiconductor package SP4. The semiconductor package SP4 may be similar to Figure 7 . In some embodiments, the bonding structure further extends along the thickness direction to at least partially cover the first conductive layer (122 and / or 222), as shown by the dot-dash line in the enlarged view. As described above, the extent to which the bonding structure JD covers the first conductive bump and the second conductive bump (320 and 220) may be determined by the thickness (128T and 228T) of the fourth conductive layer (128A and 228A). The bonding structure JD for coupling the first conductive bump 320 and the second conductive bump 220 of the semiconductor package SP4 may be similar to Figure 7 The bonding structure JC of the semiconductor package SP3 is shown. Therefore, the detailed description of the bonding structure JD is simplified herein.

[0058] Continue to refer to Figure 8 Due to the concave warping of the first package component 30, the interval between the first package component 30 and the second package component 20 may gradually increase from the center to the edge of the semiconductor package SP4. The interval SF2 corresponding to the corner bumps (3202 and 2202) may be greater than the interval SF1 corresponding to the center bumps (3201 and 2201). Due to the concave warping of the first package component 30, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps may gradually increase from a pair of first conductive bumps and second conductive bumps located in the center area of ​​the semiconductor package SP4 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP4. For example, the vertical distance VD2 between the corner bumps (3202 and 2202) is greater than the vertical distance VD1 between the center bumps (3201 and 2201).

[0059] Still refer to Figure 8 The cross-sectional view of the bonding structure JD of the semiconductor package SP4 may be similar to Figure 5. For example, the curvature of the outer surface of the bonding structure JD2 covering the corner bumps (3202 and 2202) is smaller than the curvature of the outer surface of the bonding structure JD1 covering the center bumps (3201 and 2201). The curvature of the outer surface of the corresponding bonding structure JD on a pair of first conductive bumps and second conductive bumps (320 and 220) may gradually increase from the bonding structure covering the corner bumps (3202 and 2202) to the bonding structure covering the center bumps (3201 and 2201). In some embodiments, the maximum width MW2 of the bonding structure JD2 covering the corner bumps (3202 and 2202) is smaller than the maximum width MW1 of the bonding structure JD1 covering the center bumps (3201 and 2201). The maximum width of the corresponding bonding structures JD on a pair of first and second conductive bumps (320 and 220) may increase from the bonding structure covering the corner bumps (3202 and 2202) to the bonding structure covering the center bumps (3201 and 2201). The shortest lateral distance LS2 between the bonding structure JD2 and its adjacent bonding structure may be greater than the shortest lateral distance LS1 between the bonding structure JD1 and its adjacent bonding structure.

[0060] Reference Fig. 9 , showing a partial view of a semiconductor package SP5. The semiconductor package SP5 may be formed by coupling a first package component 40 to a second package component 20. The first package component 40 may be similar to the above-described first package component 10, except that the first conductive bump 420 has a first conductive layer 122' that is thicker than the corresponding third conductive layer 126. In other words, the corresponding first conductive bump 420 of the first package component 40 includes a first conductive layer 122' having a thickness 122T' that is greater than the thickness 126T of the third conductive layer 126. The thickness 124T of the second conductive layer 124 may be the smallest among the conductive layers of the first conductive bump 420. Alternatively, the first conductive layer 122' is the thickest layer of the first conductive bump 420, and the third conductive layer 126 is the thinnest layer of the first conductive bump 420. It should be noted that the semiconductor package SP5 may be formed by the above-described suitable method, and therefore will not be described in detail herein.

[0061] Continue to refer to Fig. 9 The semiconductor package SP5 includes a first package component 40 having a concave warpage profile, which is similar to Figure 5. The first package component 10 of the semiconductor package SP1 described in . The bonding structure JE of the semiconductor package SP5 that couples the first conductive bump 420 to the second conductive bump 220 may also be similar to the bonding structure JA of the semiconductor package SP1, so the detailed description is simplified for the sake of brevity. For example, due to the concave warping of the first package component 40, the spacing between the first package component 40 and the second package component 20 gradually increases from the center to the edge of the semiconductor package SP5. Due to the concave warping, the spacing SF2 corresponding to the corner bumps (4202 and 2202) may be greater than the spacing SF1 corresponding to the center bump (4201 and 2201). For example, the first package component 40 is warped and the edge 40e is bent upward, causing the center axis A42 of the corner bump 4202 to be offset relative to the center axis A22 of the corner bump 2202. The amount of warping in the center area of ​​the first package component 40 may be minimal, so that the center axis A41 of the center bump 1201 is substantially aligned with the center axis A21 of the center bump 2201. Due to the concave warping of the first package component 40, the vertical distance between the main surfaces of the corresponding first conductive bumps and the second conductive bumps (420 and 220) may gradually increase from the corresponding first conductive bumps and the second conductive bumps located in the central area of ​​the semiconductor package SP5 to the corresponding first conductive bumps and the second conductive bumps located in the peripheral area of ​​the semiconductor package SP5. For example, the vertical distance VD2 between the corner bumps (4202 and 2202) is greater than the vertical distance VD1 between the center bumps (4201 and 2201).

[0062] Still refer to Fig. 9 The cross-sectional view of the bonding structure JE of the semiconductor package SP5 may be similar to Figure 5 . A cross-sectional view of the bonding structure JA of the semiconductor package SP1 shown in FIG. . For example, the curvature of the outer surface of the bonding structure JE2 covering the corner bumps (4202 and 2202) is smaller than the curvature of the outer surface of the bonding structure JE1 covering the center bumps (4201 and 2201). The curvature of the outer surface of the corresponding bonding structure JE on a pair of first conductive bumps and second conductive bumps may gradually increase from the bonding structure covering the corner bumps (4202 and 2202) to the bonding structure covering the center bumps (4201 and 2201). In some embodiments, the maximum width MW2 of the bonding structure JE2 covering the corner bumps (4202 and 2202) is smaller than the maximum width MW1 of the bonding structure JE1 covering the center bumps (4201 and 2201). The maximum width of the corresponding bonding structure JE may increase from the bonding structure covering the corner bumps (4202 and 2202) to the bonding structure covering the center bumps (4201 and 2201). The shortest lateral distance LS2 between the engagement structure JE2 and its adjacent engagement structures may be greater than the shortest lateral distance LS1 between the engagement structure JE1 and its adjacent engagement structures.

[0063] Reference Fig.10 , showing a partial view of the semiconductor package SP6. The semiconductor package SP6 may be similar to Fig. 9 In some embodiments, the bonding structure further extends along the thickness direction to at least partially cover the first conductive layer (122' and / or 222), as shown by the dot-dash line in the enlarged view. Figure 6 As described in the above, the extent to which the joint structure JF covers the corresponding first conductive bump and second conductive bump (420 and 220) can be determined by the thickness (128T and 228T) of the fourth conductive layer (128A and 228A). The joint structure JF for coupling the first conductive bump 420 and the second conductive bump 220 of the semiconductor package SP6 can be similar to Fig. 9 The bonding structure JE of the semiconductor package SP5 is shown in FIG. 4 , and thus the detailed description of the bonding structure JF is simplified herein.

[0064] Continue to refer to Fig.10 Due to the concave warping of the first package component 40, the interval between the first package component 40 and the second package component 20 may gradually decrease from the edge to the center of the semiconductor package SP6. The interval SF2 corresponding to the corner bumps (4202 and 2202) may be greater than the interval SF1 corresponding to the center bumps (4201 and 2201). Due to the concave warping of the first package component 40, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps may gradually decrease from a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP6 to a pair of first conductive bumps and second conductive bumps located in the center area of ​​the semiconductor package SP6. For example, the vertical distance VD1 between the center bumps (4201 and 2201) is smaller than the vertical distance VD2 between the corner bumps (4202 and 2202).

[0065] Still refer to Fig.10 The cross-sectional view of the bonding structure JF of the semiconductor package SP6 may be similar to Figure 5. For example, the curvature of the outer surface of the bonding structure JF1 covering the center bump (4201 and 2201) is greater than the curvature of the outer surface of the bonding structure JF2 covering the corner bump (4202 and 2202). The curvature of the outer surface of the corresponding bonding structure JF on a pair of first conductive bumps and second conductive bumps may gradually decrease from the bonding structure covering the center bump (4201 and 2201) to the bonding structure covering the corner bump (4202 and 2202). In some embodiments, the maximum width MW1 of the bonding structure JF1 covering the center bump (4201 and 2201) is greater than the maximum width MW2 of the bonding structure JF2 covering the corner bump (4202 and 2202). The maximum width of the corresponding bonding structure JF may decrease from the bonding structure covering the center bump (4201 and 2201) to the bonding structure covering the corner bump (4202 and 2202). The shortest lateral distance LS1 between the joining structure JF1 and its adjacent joining structure may be smaller than the shortest lateral distance LS2 between the joining structure JF2 and its adjacent joining structure.

[0066] Reference Fig.11 , showing a partial view of a semiconductor package SP7. The semiconductor package SP7 may be formed by coupling a first package component 50 to a second package component 20. The first package component 50 may be similar to the first package component 10 described above, except that the first conductive bump 520 has a second conductive layer 124' thicker than the corresponding first conductive layer 122 and / or the corresponding third conductive layer 126. In other words, the corresponding first conductive bump 520 of the first package component 50 includes a second conductive layer 124' having a thickness 124T' greater than the thickness 122T of the first conductive layer 122 and / or the thickness 126T of the third conductive layer 126. The second conductive layer 124' may be the thickest layer among the conductive layers of the first conductive bump 520. In some embodiments, the second conductive layer 124' is thicker than the first conductive layer 122, and the first conductive layer 122 may have the same thickness as the third conductive layer 126. In some embodiments, the second conductive layer 124' is thicker than the first conductive layer 122, and the first conductive layer 122 is thicker (or thinner) than the third conductive layer 126. It should be noted that the semiconductor package SP7 can be formed by the above-mentioned suitable method, so it will not be described in detail herein.

[0067] Continue to refer to Fig.11 The semiconductor package SP7 includes a first package component 50 having a concave warpage profile, which is similar to Figure 5. The first package component 10 of the semiconductor package SP1 described in . The bonding structure JG that couples the first conductive bump 520 to the second conductive bump 220 may also be similar to the bonding structure JA of the semiconductor package SP1, so the detailed description is simplified for the sake of brevity. For example, due to the concave warping of the first package component 50, the spacing between the first package component 50 and the second package component 20 may gradually increase from the center to the edge of the semiconductor package SP7. Due to the concave warping, the spacing SF2 corresponding to the corner bumps (5202 and 2202) may be greater than the spacing SF1 corresponding to the center bump (5201 and 2201). For example, the first package component 50 is warped and the edge 50e is bent upward, causing the center axis A52 of the corner bump 5202 to be offset relative to the center axis A22 of the corner bump 2202. The amount of warping in the central area of ​​the first package component 50 may be minimal, so that the center axis A51 of the center bump 5201 is substantially aligned with the center axis A21 of the center bump 2201. Due to the concave warping of the first package component 50, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps (520 and 220) can gradually increase from a pair of first conductive bumps and second conductive bumps located in the central area of ​​the semiconductor package SP7 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP7. For example, the vertical distance VD2 between the corner bumps (5202 and 2202) is greater than the vertical distance VD1 between the center bumps (5201 and 2201).

[0068] Still refer to Fig.11 , the cross-sectional view of the bonding structure JG of the semiconductor package SP7 may be similar to the cross-sectional view of the bonding structure JA of the semiconductor package SP1. For example, the curvature of the outer surface of the bonding structure JG2 covering the corner bumps (5202 and 2202) is smaller than the curvature of the outer surface of the bonding structure JG1 covering the center bumps (5201 and 2201). The curvature of the outer surface of the corresponding bonding structure JG on a pair of first conductive bumps and second conductive bumps may gradually increase from the bonding structure covering the corner bumps (5202 and 2202) to the bonding structure covering the center bumps (5201 and 2201). In some embodiments, the maximum width MW2 of the bonding structure JG2 covering the corner bumps (5202 and 2202) is smaller than the maximum width MW1 of the bonding structure JG1 covering the center bumps (5201 and 2201). The maximum width of the corresponding joint structure JG may increase from the joint structure covering the corner bumps (5202 and 2202) to the joint structure covering the center bumps (5201 and 2201). The shortest lateral distance LS2 between the joint structure JG2 and its adjacent joint structure may be greater than the shortest lateral distance LS1 between the joint structure JG1 and its adjacent joint structure.

[0069] Reference Fig.12 , showing a partial view of the semiconductor package SP8. The semiconductor package SP8 may be similar to Fig.11 In some embodiments, the bonding structure further extends along the thickness direction to at least partially cover the first conductive layer (122 and / or 222), as shown by the dot-dash line in the enlarged view. Figure 6 As described in the foregoing, the extent to which the joint structure JH covers the pair of first conductive bumps and second conductive bumps (520 and 220) may be determined by the thickness (128T and 228T) of the fourth conductive layer (128A and 228A).

[0070] Continue to refer to Fig.12 , the bonding structure JH of the semiconductor package SP8 for coupling the first conductive bump 520 and the second conductive bump 220 may be similar to the bonding structure JG of the semiconductor package SP7. Therefore, the detailed description of the bonding structure JH is simplified herein. For example, due to the concave warping of the first package component 50, the spacing between the first package component 50 and the second package component 20 may gradually decrease from the edge to the center of the semiconductor package SP8. Due to the concave warping of the first package component 50, the vertical distance between the main surfaces of the corresponding first conductive bump and the second conductive bump may gradually decrease from a pair of first conductive bumps and second conductive bumps (520 and 220) located in the peripheral area of ​​the semiconductor package SP8 to a pair of first conductive bumps and second conductive bumps (520 and 220) located in the central area of ​​the semiconductor package SP8. For example, the vertical distance VD1 between the center bumps (5201 and 2201) is less than the vertical distance VD2 between the corner bumps (5202 and 2202).

[0071] Still refer to Fig.12 The cross-sectional view of the bonding structure JH of the semiconductor package SP8 may be similar to Figure 5. For example, the curvature of the outer surface of the bonding structure JH1 covering the center bump (5201 and 2201) is greater than the curvature of the outer surface of the bonding structure JH2 covering the corner bump (5202 and 2202). The curvature of the outer surface of the corresponding bonding structure JH on a pair of first conductive bumps and second conductive bumps may gradually decrease from the bonding structure covering the center bump (5201 and 2201) to the bonding structure covering the corner bump (5202 and 2202). In some embodiments, the maximum width MW1 of the bonding structure JH1 covering the center bump (5201 and 2201) is greater than the maximum width MW2 of the bonding structure JH2 covering the corner bump (5202 and 2202). The maximum width of the corresponding bonding structure JH may decrease from the bonding structure covering the center bump (5201 and 2201) to the bonding structure covering the corner bump (5202 and 2202). The shortest lateral distance LS1 between the engagement structure JH1 and its adjacent engagement structures may be smaller than the shortest lateral distance LS2 between the engagement structure JH2 and its adjacent engagement structures.

[0072] Reference Fig.13 , showing a partial view of a semiconductor package SP9. The semiconductor package SP9 can be formed by coupling a first package component 60 to a second package component 20. The first package component 60 can be similar to the first package component 10 described above, except that the first package component 60 has a convex warpage profile after the reflow process. For example, the first package component 60 is warped and the edge 60e is bent downward, wherein the central area of ​​the first package component 60 is higher than the peripheral area of ​​the first package component 60 relative to the main surface 212a of the second package component 20. The main surface 612a of the first package component 60 may be a convex curve in a cross-sectional view, so that the corner bump 1202 is lower than the center bump 1201. The warpage amount of the first package component 60 can be divided into various areas and the vertical distance between the two package components (60 and 20) can vary in different areas. For example, the area close to the edge 60e of the first package component 60 is closer to the second package component 20 than the area in the central area of ​​the first package component 60 / near the central area of ​​the first package component 60. The semiconductor package SP9 may have a higher spacing at the central region and a lower spacing at the peripheral region. For example, the spacing SF1' corresponding to the central bumps (1201 and 2201) is greater than the spacing SF2' corresponding to the corner bumps (1202 and 2202).

[0073] Continue to refer to Fig.13, the center axis A62 of the corner bump 1202 may be offset counterclockwise (or clockwise according to some embodiments) relative to the center axis A22 of the corresponding corner bump 2202 by an angle α'. This angle α' may be an acute angle, which depends on the amount of warping. The angle between the center axes (A61 and A21) may be minimal or may not exist. For example, the center axes (A61 and A21) may be substantially parallel to each other due to misalignment caused by warping or formation process variations. In some embodiments, due to the convex warping, the vertical distance VD1' between the center bumps (1201 and 2201) is greater than the vertical distance VD2' between the corner bumps (1202 and 2202). The first conductive bump 120 of the first package component 60 can be coupled to the corresponding second conductive bump 220 of the second package component 20 through the bonding structure JI. For example, the joint structure JI1 is sandwiched between the center bumps (1201 and 2201) and may at least partially cover the third conductive layer 126 of the center bump 1201 and the third conductive layer 226 of the center bump 2201. Similarly, the joint structure JI2 is sandwiched between the corner bumps (1202 and 2202) and may at least partially cover the third conductive layer 126 of the corner bump 1202 and the third conductive layer 226 of the corner bump 2202. If a sufficient amount of solder is applied, the joint structure JI may extend to cover the second conductive layer (124 and 224) or further extend to cover the first conductive layer (122 and 222).

[0074] Still refer to Fig.13 The cross section of the joint structure JI can be in different areas (such as Figure 4 The width of the bonding structure JI may vary from the end point of the boundary on the side wall of the conductive bump to the midpoint of the boundary as shown in the cross-sectional view. As shown in the cross-sectional view, the width of the bonding structure JI may increase continuously from the end point of the boundary on the side wall of the conductive bump to the midpoint of the boundary. In some embodiments, the bonding structure JI1 covering the center bump (1201 and 2201) may have a substantially elliptical cross-section extending along a first direction D1 (e.g., a thickness or height direction). The bonding structure JI2 covering the corner bumps (1202 and 2202) has a substantially elliptical cross-section extending along a second direction D2 (e.g., a width direction). Alternatively, the bonding structure JI extends along a direction D3 that is not perpendicular to the first direction and / or the second direction. In some embodiments, in the cross-sectional view, the curvature of the outer surface of the bonding structure JI1 covering the center bump (1201 and 2201) is less than the curvature of the outer surface of the bonding structure JI2 covering the corner bumps (1202 and 2202). For example, the curvature of the outer surface of the corresponding bonding structure JI on a pair of first conductive bumps / second conductive bumps gradually increases from the bonding structure covering the center bump (1201 and 2201) to the bonding structure covering the corner bumps (1202 and 2202).

[0075] In some embodiments, the sidewall 120s of the first conductive bump 120 (or the sidewall 220s of the second conductive bump 220) forms an angle with a tangent line at an endpoint of the boundary of the bonding structure JI. For example, the angle θ1′ between the sidewall (120s or 220s) of the center bump (1201 or 2201) and the tangent line TL1′ at an endpoint of the boundary of the bonding structure JI1 is greater than the angle θ2′ between the sidewall (120s or 220s) of the corner bump (1202 or 2202) and the tangent line TL2′ at an endpoint of the boundary of the bonding structure JI2. In some embodiments, the maximum width MW1′ of the bonding structure JI1 covering the center bump (1201 and 2201) is less than the maximum width MW2′ of the bonding structure JI2 covering the corner bump (1202 and 2202). The maximum width of the corresponding bonding structure JI may increase from the bonding structure covering the center bump (1201 and 2201) to the bonding structure covering the corner bump (1202 and 2202). In some embodiments, the shortest lateral distance LS1' between the bonding structure JI1 and its adjacent bonding structure is greater than the shortest lateral distance LS2' between the bonding structure JI2 and its adjacent bonding structure.

[0076] Reference Fig.14 , showing a partial view of a semiconductor package SP10. The semiconductor package SP10 may be formed by combining a first package component 60 with a second package component 20. In addition to the bonding structure JJ for coupling the first conductive bump 120 with the second conductive bump 220, which may extend along the thickness direction to at least partially cover the second conductive layer 124 of the first conductive bump 120 and / or the second conductive layer 224 of the second conductive bump 220, the first package component 60 may have a Fig.13 Similarly, the extent to which the joint structure JJ covers the corresponding first conductive bump and second conductive bump (120 and 220) can be determined by Figure 3 The thickness (128T and 228T) of the fourth conductive layer (128A and 228A) shown in FIG.

[0077] Continue to refer to Fig.14, the interval SF2' corresponding to the corner bumps (1202 and 2202) may be smaller than the interval SF1' corresponding to the center bumps (1201 and 2201). Due to the convex warping of the first package component 60, the interval between the first package component 60 and the second package component 20 may gradually increase from the edge to the center of the semiconductor package SP10. The first package component 60 is warped and the edge 60e is bent downward, resulting in the central axis A62 of the corner bump 1202 being offset relative to the central axis A22 of the corner bump 2202. In some embodiments, due to the convex warping, the vertical distance between the main surfaces of the corresponding first conductive bumps and the second conductive bumps (120 and 220) gradually decreases from a pair of first conductive bumps and second conductive bumps located in the central area of ​​the semiconductor package SP10 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP10. For example, the vertical distance VD2 ′ between the corner bumps ( 1202 and 2202 ) is smaller than the vertical distance VD1 ′ between the center bumps ( 1201 and 2201 ).

[0078] Still refer to Fig.14 The cross-sectional view of the bonding structure JJ of the semiconductor package SP10 may be similar to Fig.13 , so the detailed description of the bonding structure JJ is simplified herein. For example, the curvature of the outer surface of the bonding structure JJ2 covering the corner bumps (1202 and 2202) may be greater than the curvature of the outer surface of the bonding structure JJ1 covering the center bumps (1201 and 2201). The curvature of the outer surface of the corresponding bonding structure JJ on a pair of first conductive bumps and second conductive bumps (120 and 220) may gradually decrease from the bonding structure covering the corner bumps (1202 and 2202) to the bonding structure covering the center bumps (1201 and 2201). In some embodiments, the maximum width MW2' of the bonding structure JJ2 covering the corner bumps (1202 and 2202) is greater than the maximum width MW1' of the bonding structure JJ1 covering the center bumps (1201 and 2201). The maximum width of the corresponding joint structure JJ may decrease from the joint structure covering the corner bumps (1202 and 2202) to the joint structure covering the center bumps (1201 and 2201). The shortest lateral distance LS2' between the joint structure JJ2 and its adjacent joint structure may be smaller than the shortest lateral distance LS1' between the joint structure JJ1 and its adjacent joint structure.

[0079] Reference Fig.15, showing a partial view of a semiconductor package SP11. The semiconductor package SP11 may be formed by coupling a first package component 70 to a second package component 20. The first package component 70 may be similar to the above-described first package component 60, except that the first conductive bump 320 has a third conductive layer 126' thicker than the corresponding first conductive layer 122. The corresponding first conductive bump 320 of the first package component 70 includes a third conductive layer 126' having a thickness 126T' greater than the thickness 122T of the first conductive layer 122. The second conductive layer 124 may have a thickness 124T, which is the thinnest among the conductive layers of the first conductive bump 320. Alternatively, the third conductive layer 126' is the thickest layer of the first conductive bump 320, and the first conductive layer 122 is the thinnest layer of the first conductive bump 320. It should be noted that the semiconductor package SP11 may be formed by the above-described suitable method, and therefore will not be described in detail herein.

[0080] Continue to refer to Fig.15 The semiconductor package SP11 includes a first package component 70 having a convex warpage profile, which is similar to Fig.13 The first package component 60 of the semiconductor package SP9 described in FIG. The bonding structure JK that couples the first conductive bump 320 to the second conductive bump 220 may also be similar to Fig.13 The joint structure JI of the semiconductor package SP9 shown in the figure is simplified for the sake of brevity. In some embodiments, the interval SF2' corresponding to the corner bumps (3202 and 2202) is smaller than the interval SF1' corresponding to the center bumps (3201 and 2201). For example, the first package component 70 is warped and the edge 70e is bent downward, resulting in the center axis A72 of the corner bump 3202 being offset relative to the center axis A22 of the corner bump 2202. The center axis A71 of the center bump 3201 is substantially aligned with the center axis A21 of the center bump 2201. Due to the convex warping of the first package component 70, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps (320 and 220) can be gradually reduced from a pair of first conductive bumps and second conductive bumps located in the central area of ​​the semiconductor package SP11 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP11. For example, the vertical distance VD1 ′ between the center bumps ( 3201 and 2201 ) is greater than the vertical distance VD2 ′ between the corner bumps ( 3202 and 2202 ).

[0081] Still refer to Fig.15, the curvature of the outer surface of the bonding structure JK1 covering the center bump (3201 and 2201) may be smaller than the curvature of the outer surface of the bonding structure JK2 covering the corner bump (3202 and 2202). The curvature of the outer surface of the corresponding bonding structure JK on a pair of first conductive bumps and second conductive bumps (320 and 220) may gradually increase from the bonding structure covering the center bump (3201 and 2201) to the bonding structure covering the corner bump (3202 and 2202). In some embodiments, the maximum width MW1' of the bonding structure JK1 covering the center bump (3201 and 2201) is smaller than the maximum width MW2' of the bonding structure JK2 covering the corner bump (3202 and 2202). The maximum width of the corresponding bonding structure JK may increase from the bonding structure covering the center bump (3201 and 2201) to the bonding structure covering the corner bump (3202 and 2202). The shortest lateral distance LS1 ′ between the joint structure JK1 and its adjacent joint structure may be greater than the shortest lateral distance LS2 ′ between the joint structure JK2 and its adjacent joint structure.

[0082] Reference Fig.16 , showing a partial view of the semiconductor package SP12. The semiconductor package SP12 may be similar to the semiconductor package SP12 except that the bonding structure JL covers the third conductive layer (126' and 226) and further extends along the thickness direction to cover at least the second conductive layer (124 and / or 224). Fig.15 In some embodiments, the bonding structure further extends along the thickness direction to at least partially cover the first conductive layer (122 and / or 222), as shown by the dotted line in the enlarged view. Figure 6 As described above, the extent to which the joint structure JL covers the corresponding first conductive bump and second conductive bump ( 320 and 220 ) may be determined by the thickness ( 128T and 228T) of the fourth conductive layer ( 128A and 228A).

[0083] Continue to refer to Fig.16 The bonding structure JL for coupling the first conductive bump 320 and the second conductive bump 220 of the semiconductor package SP12 may be similar to Fig.15, so the detailed description of the bonding structure JL is simplified herein. For example, due to the convex warping of the first package component 70, the interval between the first package component 70 and the second package component 20 gradually decreases from the center to the edge of the semiconductor package SP12. The interval SF2' corresponding to the corner bumps (3202 and 2202) may be smaller than the interval SF1' corresponding to the center bumps (3201 and 2201). Due to the convex warping of the first package component 70, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps (320 and 220) may gradually decrease from a pair of first conductive bumps and second conductive bumps located in the center area of ​​the semiconductor package SP12 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP12. The vertical distance VD2' between the corner bumps (3202 and 2202) may be smaller than the vertical distance VD1' between the center bumps (3201 and 2201).

[0084] Still refer to Fig.16 The cross-sectional view of the bonding structure JL of the semiconductor package SP12 may be similar to Fig.15 . For example, the curvature of the outer surface of the bonding structure JL2 covering the corner bumps (3202 and 2202) is greater than the curvature of the outer surface of the bonding structure JL1 covering the center bumps (3201 and 2201). The curvature of the outer surface of the corresponding bonding structure JL on a pair of first conductive bumps and second conductive bumps (320 and 220) may gradually decrease from the bonding structure covering the corner bumps (3202 and 2202) to the bonding structure covering the center bumps (3201 and 2201). In some embodiments, the maximum width MW2' of the bonding structure JL2 covering the corner bumps (3202 and 2202) is greater than the maximum width MW1' of the bonding structure JL1 covering the center bumps (3201 and 2201). The maximum width of the corresponding joint structure JL may decrease from the joint structure covering the corner bumps (3202 and 2202) to the joint structure covering the center bumps (3201 and 2201). The shortest lateral distance LS2' between the joint structure JL2 and its adjacent joint structure may be smaller than the shortest lateral distance LS1' between the joint structure JL1 and its adjacent joint structure.

[0085] Reference Fig.17 , showing a partial view of a semiconductor package SP13. The semiconductor package SP13 may be formed by coupling the first package component 80 to the second package component 20. The first package component 80 may be similar to the first package component 80 except that the first conductive bump 420 has a first conductive layer 122' thicker than the corresponding third conductive layer 126. Fig.13. In other words, the corresponding first conductive bump 420 of the first package component 80 includes a first conductive layer 122' having a thickness 122T' greater than the thickness 126T of the third conductive layer 126. Among the conductive layers of the first conductive bump 420, the second conductive layer 124 may have a minimum thickness 124T. As another option, the first conductive layer 122' is the thickest layer of the first conductive bump 420, and the third conductive layer 126 is the thinnest layer of the first conductive bump 420. It should be noted that the semiconductor package SP13 can be formed by the above-mentioned suitable method, so it is not repeated herein.

[0086] Continue to refer to Fig.17 The bonding structure JM for coupling the first conductive bump 420 to the second conductive bump 220 may be similar to Fig.13 The bonding structure JI of the semiconductor package SP9 shown is simplified for the sake of brevity. For example, due to the convex warping of the first package component 80, the interval between the first package component 80 and the second package component 20 gradually decreases from the center to the edge of the semiconductor package SP13. Due to the convex warping, the interval SF2' corresponding to the corner bumps (4202 and 2202) may be smaller than the interval SF1' corresponding to the center bump (4201 and 2201). For example, the first package component 80 is warped and the edge 80e is bent downward, resulting in the center axis A82 of the corner bump 4202 being offset relative to the center axis A22 of the corner bump 2202. The center axis A81 of the center bump 1201 may be substantially aligned with the center axis A21 of the center bump 2201, or slightly misaligned due to warping and / or formation process variations. Due to the convex warping of the first package component 80, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps (420 and 220) may gradually decrease from a pair of first conductive bumps and second conductive bumps located in the central area of ​​the semiconductor package SP13 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP13. For example, the vertical distance VD2' between the corner bumps (4202 and 2202) is smaller than the vertical distance VD1' between the center bumps (4201 and 2201).

[0087] Still refer to Fig.17 The cross-sectional view of the bonding structure JM of the semiconductor package SP13 may be similar to Fig.13. A cross-sectional view of the bonding structure JI of the semiconductor package SP9 shown in . For example, the curvature of the outer surface of the bonding structure JM2 covering the corner bumps (4202 and 2202) is greater than the curvature of the outer surface of the bonding structure JM1 covering the center bumps (4201 and 2201). The curvature of the outer surface of the corresponding bonding structure JM on a pair of first conductive bumps and second conductive bumps may gradually decrease from the bonding structure covering the corner bumps (4202 and 2202) to the bonding structure covering the center bumps (4201 and 2201). In some embodiments, the maximum width MW2' of the bonding structure JM2 covering the corner bumps (4202 and 2202) is greater than the maximum width MW1' of the bonding structure JM1 covering the center bumps (4201 and 2201). The maximum width of the corresponding joint structure JM may decrease from the joint structure covering the corner bumps (4202 and 2202) to the joint structure covering the center bumps (4201 and 2201). The shortest lateral distance LS2' between the joint structure JM2 and its adjacent joint structure may be smaller than the shortest lateral distance LS1' between the joint structure JM1 and its adjacent joint structure.

[0088] Reference Fig.18 , showing a partial view of the semiconductor package SP14. The semiconductor package SP14 may be similar to Fig.17 In some embodiments, the bonding structure further extends along the thickness direction to at least partially cover the first conductive layer (122' and / or 222), as shown by the dot-dash line in the enlarged view. Figure 6 As described in the foregoing, the extent to which the joint structure JN covers the pair of first conductive bumps and second conductive bumps (420 and 220) may be determined by the thickness (128T and 228T) of the fourth conductive layer (128A and 228A).

[0089] Continue to refer to Fig.18 The bonding structure JN for coupling the first conductive bump 420 and the second conductive bump 220 of the semiconductor package SP14 may be similar to Fig.17The bonding structure JM of the semiconductor package SP13 shown in the figure is simplified herein, so the detailed description of the bonding structure JN is simplified herein. For example, due to the convex warping of the first package component 80, the interval between the first package component 80 and the second package component 20 gradually increases from the edge to the center of the semiconductor package SP14. The interval SF2' corresponding to the corner bumps (4202 and 2202) may be smaller than the interval SF1' corresponding to the center bumps (4201 and 2201). Due to the convex warping of the first package component 80, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps may gradually increase from a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP14 to a pair of first conductive bumps and second conductive bumps located in the center area of ​​the semiconductor package SP14. For example, the vertical distance VD1' between the center bumps (4201 and 2201) is greater than the vertical distance VD2' between the corner bumps (4202 and 2202).

[0090] Still refer to Fig.18 , the cross-sectional view of the bonding structure JN of the semiconductor package SP14 may be similar to the cross-sectional view of the bonding structure JM of the semiconductor package SP13. For example, the curvature of the outer surface of the bonding structure JN1 covering the center bump (4201 and 2201) is smaller than the curvature of the outer surface of the bonding structure JN2 covering the corner bump (4202 and 2202). The curvature of the outer surface of the corresponding bonding structure JN on a pair of first conductive bumps and second conductive bumps may gradually increase from the bonding structure covering the center bump (4201 and 2201) to the bonding structure covering the corner bump (4202 and 2202). In some embodiments, the maximum width MW1' of the bonding structure JN1 covering the center bump (4201 and 2201) is smaller than the maximum width MW2' of the bonding structure JN2 covering the corner bump (4202 and 2202). The maximum width of the corresponding joint structure JN may increase from the joint structure covering the center bump (4201 and 2201) to the joint structure covering the corner bump (4202 and 2202). The shortest lateral distance LS1' between the joint structure JN1 and its adjacent joint structure may be greater than the shortest lateral distance LS2' between the joint structure JN2 and its adjacent joint structure.

[0091] Reference Fig.19 , showing a partial view of a semiconductor package SP15. The semiconductor package SP15 may be formed by coupling the first package component 90 to the second package component 20. The first package component 90 may be similar to the first package component 90 except that the first conductive bump 520 has a second conductive layer 124' thicker than the corresponding first conductive layer 122 and / or the corresponding third conductive layer 126. Fig.13. In other words, the corresponding first conductive bump 520 of the first package component 90 includes a second conductive layer 124' having a thickness 124T' greater than the thickness 122T of the first conductive layer 122 and / or the thickness 126T of the third conductive layer 126. The second conductive layer 124' may be the thickest layer among the conductive layers of the first conductive bump 520. In some embodiments, the second conductive layer 124' is thicker than the first conductive layer 122, and the first conductive layer 122 may have the same thickness as the third conductive layer 126. In some embodiments, the second conductive layer 124' is thicker than the first conductive layer 122, and the first conductive layer 122 is thicker than the third conductive layer 126 or thinner than the third conductive layer 126. It should be noted that the semiconductor package SP15 can be formed by the above-mentioned suitable method, so it is not repeated herein.

[0092] Continue to refer to Fig.19 The semiconductor package SP15 includes a first package component 90 having a convex warpage profile, which is similar to Fig.13 The first package component 60 of the semiconductor package SP9 described in the embodiment of the present invention is a first package component 60. The bonding structure JO that couples the first conductive bump 520 to the second conductive bump 220 may also be similar to the bonding structure JI of the semiconductor package SP9, so the detailed description is simplified for the sake of brevity. For example, due to the convex warping of the first package component 90, the interval between the first package component 90 and the second package component 20 may gradually decrease from the center to the edge of the semiconductor package SP15. Due to the convex warping, the interval SF2' corresponding to the corner bumps (5202 and 2202) may be smaller than the interval SF1' corresponding to the center bump (5201 and 2201).

[0093] For example, the first package component 90 is warped and the edge 90e is bent downward, resulting in the center axis A92 of the corner bump 5202 being offset relative to the center axis A22 of the corner bump 2202. The center axis A91 of the center bump 5201 may be substantially aligned with the center axis A21 of the center bump 2201, or may be misaligned due to the warping and / or formation process variations. Due to the convex warping of the first package component 90, the vertical distance between the main surfaces of the corresponding first conductive bumps and second conductive bumps may gradually decrease from a pair of first conductive bumps and second conductive bumps located in the center area of ​​the semiconductor package SP15 to a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP15. For example, the vertical distance VD2' between the corner bumps (5202 and 2202) is less than the vertical distance VD1' between the center bumps (5201 and 2201).

[0094] Still refer to Fig.19, the cross-sectional view of the bonding structure JO of the semiconductor package SP15 may be similar to the cross-sectional view of the bonding structure JI of the semiconductor package SP9. For example, the curvature of the outer surface of the bonding structure JO2 covering the corner bumps (5202 and 2202) is greater than the curvature of the outer surface of the bonding structure JO1 covering the center bumps (5201 and 2201). The curvature of the outer surface of the corresponding bonding structure JO on a pair of first conductive bumps and second conductive bumps may gradually decrease from the bonding structure covering the corner bumps (5202 and 2202) to the bonding structure covering the center bumps (5201 and 2201). In some embodiments, the maximum width MW2' of the bonding structure JO2 covering the corner bumps (5202 and 2202) is greater than the maximum width MW1' of the bonding structure JO1 covering the center bumps (5201 and 2201). The maximum width of the corresponding joint structure JO may decrease from the joint structure covering the corner bumps (5202 and 2202) to the joint structure covering the center bumps (5201 and 2201). The shortest lateral distance LS2' between the joint structure JO2 and its adjacent joint structure may be smaller than the shortest lateral distance LS1' between the joint structure JO1 and its adjacent joint structure.

[0095] Reference Fig. 20 , showing a partial view of the semiconductor package SP16. The semiconductor package SP16 may be similar to the semiconductor package SP16 except that the bonding structure JP covers the third conductive layer (126 and 226) and further extends along the thickness direction to cover at least the second conductive layer (124' and / or 224). Fig.19 In some embodiments, the bonding structure further extends along the thickness direction to at least partially cover the first conductive layer (122 and / or 222), as shown by the dot-dash line in the enlarged view. Figure 6 As described above, the extent to which the joint structure JP covers the pair of first conductive bumps and the second conductive bumps ( 520 and 220 ) may be determined by the thickness ( 128T and 228T) of the fourth conductive layer ( 128A and 228A).

[0096] Continue to refer to Fig. 20, the bonding structure JP for coupling the first conductive bump 520 and the second conductive bump 220 of the semiconductor package SP16 may be similar to the bonding structure JO of the semiconductor package SP15, so the detailed description of the bonding structure JP is simplified herein. For example, due to the convex warping of the first package component 90, the spacing between the first package component 90 and the second package component 20 gradually increases from the edge to the center of the semiconductor package SP16. Due to the convex warping of the first package component 90, the vertical distance between the main surfaces of the corresponding first conductive bump and the second conductive bump may gradually increase from a pair of first conductive bumps and second conductive bumps located in the peripheral area of ​​the semiconductor package SP16 to a pair of first conductive bumps and second conductive bumps located in the central area of ​​the semiconductor package SP16. For example, the vertical distance VD1' between the center bumps (5201 and 2201) is greater than the vertical distance VD2' between the corner bumps (5202 and 2202).

[0097] Still refer to Fig. 20 , the cross-sectional view of the joint structure JP of the semiconductor package SP16 may be similar to the cross-sectional view of the joint structure JI of the semiconductor package SP13. For example, the curvature of the outer surface of the joint structure JP1 covering the center bump (5201 and 2201) is smaller than the curvature of the outer surface of the joint structure JP2 covering the corner bump (5202 and 2202). The curvature of the outer surface of the corresponding joint structure JP on a pair of first conductive bumps and second conductive bumps (520 and 220) may gradually increase from the joint structure covering the center bump (5201 and 2201) to the joint structure covering the corner bump (5202 and 2202). In some embodiments, the maximum width MW1' of the joint structure JP1 covering the center bump (5201 and 2201) is smaller than the maximum width MW2' of the joint structure JP2 covering the corner bump (5202 and 2202). The maximum width of the corresponding joint structure JP may increase from the joint structure covering the center bump (5201 and 2201) to the joint structure covering the corner bump (5202 and 2202). The shortest lateral distance LS1' between the joint structure JP1 and its adjacent joint structure may be greater than the shortest lateral distance LS2' between the joint structure JP2 and its adjacent joint structure.

[0098] Fig.21 is a schematic cross-sectional view showing a package assembly to be combined according to some embodiments, Figure 22 to Figure 23 1 is a schematic cross-sectional view showing a portion of a semiconductor package including a package assembly bonded together according to various embodiments. In all the various drawings and exemplary embodiments of the present disclosure, the same reference numerals are used to denote the same elements. Fig.21, the first package component 15 and the second package component 25 are designed and manufactured separately and the first package component 15 is to be bonded to the second package component 25. The first package component 15 may be similar to the first package component 15 except that the first package component 15 includes a plurality of through substrate vias (TSVs) 113 penetrating through the first semiconductor substrate 112 and connected to the first conductive pads 114 for providing vertical electrical connections between opposite sides of the first semiconductor substrate 112. Figure 3 The first packaging component 10 described in .

[0099] The second package assembly 25 may include a semiconductor die (300 and 400) laterally covered by an insulating encapsulant 520. The semiconductor die (300 and 400) may include integrated circuits that perform the same or different functions (e.g., storage structures, processing structures, sensors, amplifiers, power distribution, input / output circuit systems, or similar functions). For example, the semiconductor die (300 and 400) is a packaged die that may be or may include any type of integrated circuit device, such as a logic device, a memory device (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), a high-bandwidth memory stack, etc.), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, combinations thereof, and other suitable types of devices. The semiconductor die 300 and / or 400 may include a second conductive pad 214 distributed over the main surface 212a of the second semiconductor substrate 212, a second passivation layer 216 formed on the main surface 212a of the second semiconductor substrate 212 to partially cover the second conductive pad 214, and a second conductive bump 220A including stacked conductive layers (such as 222, 224, 226, and 228A) formed on the second conductive pad 214. For example, the insulating encapsulant 520 extends along the sidewalls (300s and 400s) of the semiconductor die (300 and 400). The insulating encapsulant 520 may include a molding compound, an epoxy resin, the like, or other suitable electrically insulating materials, and may be applied by compression molding, transfer molding, or a similar process.

[0100] Continue to refer to Fig.21, the first package component 15 can be picked up and placed on the second package component 25, wherein each of the first conductive bumps 120A is substantially aligned with one of the second conductive bumps 220A of the semiconductor die (300 and 400). The first conductive bumps 120A of the first package component 15 can have a smaller critical dimension than the critical dimension of the second conductive bumps 220A of the semiconductor die (300 and / or 400). The fourth conductive layer 128A (i.e., the solder-containing layer) of the corresponding first conductive bump 120A can be thicker than the fourth conductive layer 228A of the corresponding second conductive bump 220A. The first conductive bumps 120A and the second conductive bumps 220A can be similar to Figure 3 The first conductive bump 120A and the second conductive bump 220A described in the embodiment of the present invention are not described in detail for the sake of brevity. In some embodiments, the second conductive bumps of the semiconductor die (300 and / or 400) have different critical dimensions. In this case, the first conductive bumps of the first package assembly may have variable critical dimensions depending on the corresponding critical dimensions of the second conductive bumps of the semiconductor die (300 and 400).

[0101] Reference Fig. 22 After the first package component 15 is placed on the second package component 25, a reflow process may be performed to couple the first package component 15 to the second package component 25. The reflow process may be similar to the reflow process described in the previous paragraph, so for the sake of brevity, it will not be repeated. In some embodiments, after the reflow, the first package component 15 is bonded to the second package component 25 to form the semiconductor package SP17 and the semiconductor dies (300 and 400) may be electrically coupled to each other through the first package component 15. The first package component 15 may be regarded as a bridge die in the semiconductor package SP17 for internally connecting the semiconductor dies (300 and 400).

[0102] In some embodiments, after reflow, the first package component 15 has a concave warpage. For example, the first package component 15 is warped and the edge 15e is bent upward, wherein the peripheral area of ​​the first package component 15 is higher than the central area of ​​the first package component 15 relative to the main surface 25a of the second package component 25. The main surface 15a of the first package component 15 may be a concave curve in a cross-sectional view, resulting in the first conductive bump 120 in the central area of ​​the first package component 15 / near the central area of ​​the first package component 15 (referred to as the central bump 1201) being lower than the first conductive bump 120 in the peripheral area of ​​the first package component 15 / near the peripheral area of ​​the first package component 15 (referred to as the corner bump 1202). In some embodiments, the interval SF1 in the central area is smaller than the interval SF2 in the peripheral area. For example, the interval SF2 corresponding to the corner bumps (1202 and 2202) is greater than the interval SF1 corresponding to the central bumps (1201 and 2201). The vertical distance VD1 between the center bumps ( 1201 and 2201 ) may be smaller than the vertical distance VD2 between the corner bumps ( 1202 and 2202 ).

[0103] In some embodiments, after reflow, the corresponding fourth conductive layers (128A and 228A) are bonded together to form a bonding structure JQ coupling the first conductive bump 120 to the corresponding second conductive bump 220. A cross-sectional view of the bonding structure JQ of the semiconductor package SP17 may be similar to Figure 5 , and thus the detailed description of the bonding structure JQ is simplified herein. For example, the curvature of the outer surface of the bonding structure JQ2 covering the corner bumps (1202 and 2202) is smaller than the curvature of the outer surface of the bonding structure JQ1 covering the center bumps (1201 and 2201). In some embodiments, the maximum width MW2 of the bonding structure JQ2 covering the corner bumps (1202 and 2202) is smaller than the maximum width MW1 of the bonding structure JQ1 covering the center bumps (1201 and 2201). The maximum width of the corresponding bonding structure JQ may increase from the bonding structure covering the corner bumps (1202 and 2202) to the bonding structure covering the center bumps (1201 and 2201).

[0104] In some embodiments, the bonding structure JQ on a pair of first conductive bumps and second conductive bumps (120 and 220) at least covers the third conductive layer (126 and 226) of the pair of first conductive bumps and second conductive bumps (120 and 220). In some embodiments, the bonding structure JQ' further extends along the thickness direction to at least partially cover the second conductive layer (124 and / or 224), as shown by the dotted line. In some embodiments, the bonding structure JQ" extends beyond the second conductive layer (124 and 224) along the thickness direction to cover the first conductive layer (122 and / or 222), as shown by the dotted line. As described in the preceding paragraphs, the extent to which the bonding structure JQ covers the corresponding first conductive bumps and second conductive bumps (120 and 220) may be determined by the thickness of the fourth conductive layer (128A and 228A). The first conductive bump 120 of the first package component 15 may utilize other types of first conductive bumps (such as those shown in the variations of the embodiments discussed elsewhere in the present disclosure) Figure 7 320 of them Fig. 9 420 Fig.11 520) in the above code.

[0105] Reference Fig.23 , showing a partial cross-sectional view of the semiconductor package SP18. The semiconductor package SP18 formed by bonding the first package component 15 to the second package component 25 may be similar to Fig. 22 . For example, the first package component 15 is warped and the edge 15e' is bent downward, wherein the central area of ​​the first package component 15 is higher than the peripheral area of ​​the first package component 15 relative to the main surface 25a of the second package component 25. The main surface 15a' of the first package component 15 may be a convex curve in a cross-sectional view, resulting in the corner bump 1202 being lower than the center bump 1201. Due to the convex warping of the first package component 15, the vertical distance VD1' between the center bumps (1201 and 2201) is greater than the vertical distance VD2' between the corner bumps (1202 and 2202). The semiconductor package SP18 may have a higher spacing at the central area and a lower spacing at the peripheral area. For example, the spacing SF1' corresponding to the center bumps (1201 and 2201) is greater than the spacing SF2' corresponding to the corner bumps (1202 and 2202).

[0106] Continue to refer to Fig.23 , the first conductive bump 120 of the first package component 15 may be coupled to the corresponding second conductive bump 220 of the second package component 25 through the bonding structure JR. The cross-sectional view of the bonding structure JR of the semiconductor package SP18 may be similar to Fig.13, and therefore the detailed description of the bonding structure JR is simplified herein. For example, in the cross-sectional view, the curvature of the outer surface of the bonding structure JR1 covering the center bump (1201 and 2201) is smaller than the curvature of the outer surface of the bonding structure JR2 covering the corner bump (1202 and 2202). In some embodiments, the maximum width MW1' of the bonding structure JR1 covering the center bump (1201 and 2201) is smaller than the maximum width MW2' of the bonding structure JR2 covering the corner bump (1202 and 2202).

[0107] For example, the joint structure JR1 is sandwiched between the center bumps (1201 and 2201) and may at least partially cover the third conductive layer 126 of the center bump 1201 and the third conductive layer 226 of the center bump 2201. The joint structure JR2 is sandwiched between the corner bumps (1202 and 2202) and may at least partially cover the third conductive layer 126 of the corner bump 1202 and the third conductive layer 226 of the corner bump 2202. In some embodiments, the joint structure JR' may extend to cover the second conductive layer (124 and 224), as shown by the dotted line. In other embodiments, if a sufficient amount of solder is applied, the joint structure JR" extends beyond the second conductive layer (124 and 224) to cover the first conductive layer (122 and 222), as shown by the dot-dash line. Similarly, the extent to which the joint structure JR covers the corresponding first conductive bumps and second conductive bumps (120 and 220) can be determined by the thickness of the fourth conductive layer (128A and 228A). The first conductive bump 120 of the first package component 15 can utilize other types of first conductive bumps (such as Figure 7 320 of them Fig. 9 420 Fig.11 520) in the above code.

[0108] Fig.24 is a schematic cross-sectional view of a semiconductor package including a bonding structure according to some embodiments. Fig.24 And refer to Fig. 22 and Fig.23 , a semiconductor package SP19 is provided. The semiconductor package SP19 includes a plurality of first package components 15 bonded to second package components 25. Fig.24 The enlarged cross-sectional view of the dotted line area A may be similar to Fig. 22 The structure shown or Fig.23In some embodiments, the semiconductor package SP19 includes an insulating layer 540 formed on the second package component 25 to laterally encapsulate the first package component 15. The insulating layer 540 may include any suitable material, such as epoxy resin, molding underfill, and / or other suitable electrical insulating materials, and may be formed by molding or other suitable deposition methods.

[0109] In some embodiments, the semiconductor package SP19 includes a redistribution structure 600 formed on the first package component 15 and the insulating layer 540 opposite to the second package component 25. The redistribution structure 600 including at least one patterned dielectric layer 610 and at least one patterned conductive layer 620 embedded in the patterned dielectric layer 610 can be electrically coupled to the semiconductor die (300 and 400) of the second package component 25 through the first package component 15. For example, the patterned conductive layer 620 is in physical and electrical contact with the first package component 15. The patterned conductive layer 620 may be referred to as a redistribution layer (RDL) or a redistribution line. Fig.24 Two patterned dielectric layers 610 and three patterned conductive layers 620 are shown, but there may be more or fewer patterned dielectric layers and patterned conductive layers.

[0110] In some embodiments, the semiconductor package SP19 includes a plurality of through insulating vias (TIVs) 545 penetrating through the insulating layer 540 to provide vertical electrical connections for connecting the second package component 25 with the redistribution structure 600. In some embodiments, the semiconductor package SP19 includes a third package component 35 and the redistribution structure 600 is electrically coupled to the third package component 35 through a plurality of conductive connectors 700. The conductive connectors 700 may be or may include controlled collapse chip connection (C4) bumps, metal pillars, solder balls, ball grid array (BGA) connectors, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), or the like. The third package component 35 may be or may include a package substrate, a board (such as a printed circuit board (PCB), a system board, a motherboard, etc.), a wafer, a chip, an interposer substrate, or other suitable circuit substrates. For example, the third package component 35 includes a plurality of contact pads 314 distributed on the substrate 312 and a polymer layer 316 partially exposing the contact pads 314. The polymer layer 316 may be a solder mask layer for preventing solder from bridging between conductors and generating a short circuit. After performing the reflow process, the contact pads 314 may be coupled to the patterned conductive layer 620 of the redistribution structure 600 through the conductive connector 700.

[0111] The semiconductor package SP19 optionally includes a bottom filling layer 800 formed in the space between the redistribution structure 600 and the third package component 35 to surround the conductive connector 700 for protection. The bottom filling layer 800 may cover the sidewalls of the redistribution structure 600 or further extend to cover the insulating layer 540 and / or the second package component 25. The bottom filling layer 800 may be made of a polymer such as a resin, an epoxy resin or other suitable materials. In some embodiments, the bottom filling layer 800 includes a filler (such as silicon dioxide) to adjust the mechanical strength. It should be noted that the semiconductor package SP19 is shown only for illustrative purposes, and in other embodiments, more components or fewer components may be included in the semiconductor package.

[0112] For example, the semiconductor package SP19 is formed using wafer level packaging (WLP), chip-on-wafer-on-substrate (CoWoS) process, chip-on-chip-on-substrate (CoCoS) process, etc. Other packaging technologies can be used to form the semiconductor package SP19, which are not limited in the present disclosure. The semiconductor package SP19 can be part of an electronic system for, for example, a computer (such as a high-performance computer), a computing device used in conjunction with an artificial intelligence system, a wireless communication device, a computer-related peripheral device, an entertainment device, etc. The semiconductor package SP19 including the bonding structure discussed herein can provide reliable electrical contacts between packaged components. It should be noted that other electronic applications are also possible.

[0113] According to some embodiments, a semiconductor package is provided. The semiconductor package includes a first package component and a second package component, the first package component and the second package component are stacked and electrically connected to each other, the first package component includes a first conductive bump and a second conductive bump, the second package component includes a third conductive bump and a fourth conductive bump, and the size of the first conductive bump and the size of the second conductive bump are smaller than the size of the third conductive bump and the size of the fourth conductive bump. The semiconductor package includes a first bonding structure, the first bonding structure partially wraps the first conductive bump of the first package component and the third conductive bump of the second package component. The semiconductor package includes a second bonding structure, the second bonding structure partially wraps the second conductive bump of the first package component and the fourth conductive bump of the second package component, and the curvature of the first bonding structure is different from the curvature of the second bonding structure.

[0114] In some embodiments, each of the first conductive bump, the second conductive bump, the third conductive bump, and the fourth conductive bump includes a first copper-containing layer, a nickel-containing layer overlying the first copper-containing layer, and a second copper-containing layer overlying the nickel-containing layer. In some embodiments, the first bonding structure and the second bonding structure include solder, the first bonding structure covers at least the second copper-containing layer of the first conductive bump and the second copper-containing layer of the third conductive bump, and the second bonding structure covers at least the second copper-containing layer of the second conductive bump and the second copper-containing layer of the fourth conductive bump. In some embodiments, the bump pitch of the third conductive bump and the fourth conductive bump is greater than the bump pitch of the first conductive bump and the second conductive bump. In some embodiments, the first package component is warped in a way that the edge is bent upward and the curvature of the first bonding structure is greater than the curvature of the second bonding structure. In some embodiments, the first package component is warped in a way that the edge is bent downward and the curvature of the first bonding structure is less than the curvature of the second bonding structure. In some embodiments, the first package component includes a concave warping profile and the maximum width of the first bonding structure is greater than the maximum width of the second bonding structure. In some embodiments, the first package component includes a convex warpage profile and the maximum width of the first bonding structure is less than the maximum width of the second bonding structure. In some embodiments, the ratio of the size of the first conductive bump of the first package component to the size of the third conductive bump of the second package component is less than 1.

[0115] According to some alternative embodiments, a semiconductor package is provided. The semiconductor package includes a first semiconductor die and a second semiconductor die laterally encapsulated by an insulating encapsulant. The semiconductor package includes a packaging component, which is disposed on the first semiconductor die, the second semiconductor die, and the insulating encapsulant. The first semiconductor die is electrically coupled to the second semiconductor die through the packaging component. The packaging component includes a central conductive bump and a peripheral conductive bump, the central conductive bump is bonded to the peripheral conductive bumps of the first semiconductor die and the second semiconductor die through a first bonding structure, and the peripheral conductive bump is bonded to the central conductive bump of the first semiconductor die and the second semiconductor die through a second bonding structure, and the central conductive bump and the peripheral conductive bump of the packaging component include a size smaller than the size of the corresponding peripheral conductive bump and the corresponding central conductive bump of the first semiconductor die and the second semiconductor die.

[0116] In some embodiments, each of the central conductive bump and the peripheral conductive bump of the package assembly includes a first copper-containing layer, a nickel-containing layer overlying the first copper-containing layer, and a second copper-containing layer overlying the nickel-containing layer and close to the first semiconductor die and the second semiconductor die, wherein the first bonding structure and the second bonding structure at least wrap the second copper-containing layer of the central conductive bump and the peripheral conductive bump of the package assembly. In some embodiments, the first bonding structure and the second bonding structure include solder, the corresponding first bonding structure includes a substantially elliptical cross-section with a first curvature, and the corresponding second bonding structure includes a substantially elliptical cross-section with a second curvature different from the first curvature. In some embodiments, the vertical distance between the central conductive bump of the package assembly and the peripheral conductive bumps of the first semiconductor die and the second semiconductor die is less than the vertical distance between the peripheral conductive bump of the package assembly and the central conductive bump of the first semiconductor die and the second semiconductor die, and the maximum width of the first bonding structure is greater than the maximum width of the second bonding structure. In some embodiments, the vertical distance between the central conductive bump of the packaging component and the peripheral conductive bumps of the first semiconductor die and the second semiconductor die is greater than the vertical distance between the peripheral conductive bumps of the packaging component and the central conductive bumps of the first semiconductor die and the second semiconductor die, and the maximum width of the first bonding structure is less than the maximum width of the second bonding structure.

[0117] According to some alternative embodiments, a method for manufacturing a semiconductor package includes at least the following steps: forming a stack of conductive materials on a conductive pad to form a first conductive bump of a first package component; aligning the first conductive bump of the first package component with the second conductive bump of a second package component, wherein the corresponding first conductive bump is formed to have a solder-containing layer thicker than the thickness of the solder-containing layer of the corresponding second conductive bump; and combining the solder-containing layer of the corresponding first conductive bump of the first package component with the solder-containing layer of the corresponding second conductive bump of the second package component to form a bonding structure on the corresponding first conductive bump and the corresponding second conductive bump.

[0118] In some embodiments, the manufacturing method further includes analyzing the warpage characteristics of the first package component and forming the solder-containing layer of the first conductive bump with a predetermined thickness based on the warpage characteristics before forming the first conductive bump of the first package component. In some embodiments, when forming the first conductive bump of the first package component, the volume of the solder-containing layer of the corresponding first conductive bump of the first package component is formed to be substantially equal to the volume of the solder-containing layer of the corresponding second conductive bump of the second package component. In some embodiments, forming the first conductive bump of the first package component includes sequentially plating a first copper-containing layer, a nickel-containing layer, a second copper-containing layer, and a solder-containing layer on the conductive pad. In some embodiments, forming the bonding structure includes heating the first package component at a predetermined temperature, wherein the first package component forms a concave warpage profile, and cooling the first package component, wherein the solder-containing layer of the corresponding first conductive bump of the first package component is combined with the solder-containing layer of the corresponding second conductive bump to form the bonding structure, and the curvature of the cross-section of the bonding structure decreases from one of the bonding structures located in the central area of ​​the first package component to the other of the bonding structures located in the peripheral area of ​​the first package component. In some embodiments, forming the bonding structure includes heating the first packaging component at a predetermined temperature, wherein the first packaging component forms a convex warping profile, and cooling the first packaging component, wherein the solder-containing layer of the corresponding first conductive bump of the first packaging component is combined with the solder-containing layer of the corresponding second conductive bump to form the bonding structure, and the curvature of the cross-section of the bonding structure increases from one of the bonding structures located in the central area of ​​the first packaging component to another of the bonding structures located in the peripheral area of ​​the first packaging component.

[0119] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0120] [Explanation of Symbols]

[0121] 10, 60: Packaging component / first packaging component

[0122] 10e, 15e, 15e', 30e, 40e, 50e, 60e, 70e, 80e, 90e: Edge

[0123] 15, 30, 40, 50, 70, 80, 90: First packaging component

[0124] 15a, 15a', 25a, 112a, 212a, 612a: Main surface

[0125] 20: Packaging component / second packaging component

[0126] 25: Second packaging component

[0127] 35: The third packaging component

[0128] 112: First semiconductor substrate

[0129] 113, 213: Through substrate via (TSV)

[0130] 114: First conductive pad

[0131] 116: First passivation layer

[0132] 116o, 216o, PR': Open

[0133] 120: conductive bump / first conductive bump

[0134] 120A, 320, 420: first conductive bump

[0135] 120s, 220s, 300s, 400s: Sidewall

[0136] 122, 222: Conductive layer / first conductive layer

[0137] 122': first conductive layer

[0138] 122T, 122T', 124T, 124T', 126T, 126T', 128T, 222T, 224T, 226T, 228T: thickness

[0139] 124, 224: Conductive layer / second conductive layer

[0140] 124': Second conductive layer

[0141] 126, 226: Conductive layer / third conductive layer

[0142] 126': The third conductive layer

[0143] 128A: Fourth conductive layer / solder-containing layer

[0144] 212: Second semiconductor substrate

[0145] 214: Second conductive pad

[0146] 216: Second passivation layer

[0147] 220: Conductive bump / second conductive bump

[0148] 220A: Second conductive bump

[0149] 228A: Conductive layer / fourth conductive layer / solder-containing layer

[0150] 300, 400: semiconductor die

[0151] 312: Substrate

[0152] 314: Contact pad

[0153] 316: Polymer layer

[0154] 520: first conductive bump / insulating package

[0155] 540: Insulation layer

[0156] 545: Insulation penetration (TIV)

[0157] 600: Rewiring Structure

[0158] 610: Patterned dielectric layer

[0159] 620: Patterned conductive layer

[0160] 700: Conductive connector

[0161] 800, UF: bottom filling layer

[0162] 1201, 2201, 3201, 4201, 5201: Center bump

[0163] 1202, 2202, 3202, 4202, 5202: corner bumps

[0164] A: Dashed area

[0165] A11, A12, A21, A22, A31, A32, A41, A42, A51, A52, A61, A62, A71, A72, A81, A82, A91, A92: Center axis

[0166] BT: Total bump height

[0167] D1: First direction

[0168] D2: Second direction

[0169] D3: direction

[0170] G: Gap

[0171] I-I': line

[0172] JA, JA1, JA2, JB, JB1, JB2, JC, JC1, JC2, JD, JD1, JD2, JE, JE1, JE2, JF, JF1, JF2, JG, JG1, JG2, JH, JH1, JH2, JI, JI1, JI2, JJ, JJ1, JJ2, JK, JK1, JK2, JL, JL1, JL2, JM, JM1, JM2, JN, JN1, JN2, JO, JO1, JO2, JP, JP1, JP2, JQ, JQ', JQ", JQ1, JQ2, JR, JR', JR", JR1, JR2: Joint structure

[0173] LD1, LD2: lateral dimensions

[0174] LS1, LS1', LS2, LS2': Shortest lateral distance

[0175] MW1, MW1', MW2, MW2': Maximum width

[0176] P1, P2: bump pitch

[0177] PR: Patterned mask layer

[0178] R1: Zone 1

[0179] R2: Second Zone

[0180] SF1, SF1', SF2, SF2': Interval

[0181] SP1, SP2, SP3, SP4, SP5, SP6, SP7, SP8, SP9, SP10, SP11, SP12, SP13, SP14, SP15, SP16, SP17, SP18, SP19: Semiconductor packaging

[0182] TL1, TL1', TL2, TL2': Tangent

[0183] VD1, VD1', VD2, VD2': vertical distance

[0184] W1, Wp: Width

[0185] Z1, Z2, Z3, Z4, Z5: Zone

[0186] α, α', θ1, θ1', θ2, θ2': angle

Claims

1. A semiconductor package, comprising: A first package component and a second package component are stacked and electrically connected to each other, the first package component includes a first conductive bump and a second conductive bump, the first package component is warped and the second conductive bump is higher than the first conductive bump, the second package component includes a third conductive bump and a fourth conductive bump, and the size of the first conductive bump and the size of the second conductive bump are smaller than the size of the third conductive bump and the size of the fourth conductive bump; a first bonding structure, wrapping a portion of a side wall of the first conductive bump of the first package component and a portion of a side wall of the third conductive bump of the second package component; as well as A second bonding structure wraps a portion of the side wall of the second conductive bump of the first packaging component and a portion of the side wall of the fourth conductive bump of the second packaging component, wherein the curvature of the first bonding structure is different from the curvature of the second bonding structure, wherein a first angle between another portion of the side wall of the first conductive bump not wrapped by the first bonding structure and a first tangent of the first bonding structure at an endpoint of a boundary of the other portion on the side wall of the first conductive bump is smaller than a second angle between another portion of the side wall of the second conductive bump not wrapped by the second bonding structure and a second tangent of the second bonding structure at an endpoint of a boundary of the other portion on the side wall of the second conductive bump.

2. The semiconductor package according to claim 1, wherein each of the first conductive bump, the second conductive bump, the third conductive bump, and the fourth conductive bump comprises: a first copper-containing layer; a nickel-containing layer overlying the first copper-containing layer; as well as A second copper-containing layer covers the nickel-containing layer.

3. The semiconductor package according to claim 2, wherein the first bonding structure and the second bonding structure comprise solder, the first bonding structure at least covers the second copper-containing layer of the first conductive bump and the second copper-containing layer of the third conductive bump, and the second bonding structure at least covers the second copper-containing layer of the second conductive bump and the second copper-containing layer of the fourth conductive bump. 4 . The semiconductor package according to claim 1 , wherein a bump pitch between the third conductive bump and the fourth conductive bump is greater than a bump pitch between the first conductive bump and the second conductive bump. 5 . The semiconductor package according to claim 1 , wherein the first package component is warped in such a manner that an edge thereof is bent upward and the curvature of the first bonding structure is greater than the curvature of the second bonding structure. 6 . The semiconductor package according to claim 1 , wherein the first package component is warped in such a manner that an edge thereof is bent downward. 7 . The semiconductor package of claim 1 , wherein the first package component comprises a concave warpage profile and a maximum width of the first bonding structure is greater than a maximum width of the second bonding structure. 8 . The semiconductor package of claim 1 , wherein the first package component comprises a convex warpage profile. 9 . The semiconductor package of claim 1 , wherein a ratio of the size of the first conductive bump of the first package component to the size of the third conductive bump of the second package component is less than 1. 10 .

10. A semiconductor package, comprising: The first semiconductor die and the second semiconductor die are laterally encapsulated by an insulating encapsulation body; A packaging component is disposed on the first semiconductor die, the second semiconductor die and the insulating package, the first semiconductor die is electrically coupled to the second semiconductor die through the packaging component, and the packaging component includes: a central conductive bump bonded to the peripheral conductive bumps of the first semiconductor die and the second semiconductor die by a first bonding structure and the first bonding structure covers a portion of a sidewall of the central conductive bump; and a peripheral conductive bump bonded to the central conductive bumps of the first semiconductor die and the second semiconductor die by a second bonding structure and the second bonding structure covers a portion of a sidewall of the peripheral conductive bump, the central conductive bump and the peripheral conductive bump of the package assembly include a size smaller than the size of the corresponding peripheral conductive bump and the corresponding central conductive bump of the first semiconductor die and the second semiconductor die, the package assembly is warped and the peripheral conductive bump of the package assembly is higher than the central conductive bump of the package assembly, wherein; A first angle between another portion of the side wall of the central conductive bump of the package component that is not covered by the first joining structure and a first tangent line of the first joining structure at an endpoint of a boundary of the other portion on the side wall of the central conductive bump of the package component is smaller than a second angle between another portion of the side wall of the peripheral conductive bump of the package component that is not covered by the second joining structure and a second tangent line of the second joining structure at an endpoint of a boundary of the other portion on the side wall of the peripheral conductive bump of the package component.

11. The semiconductor package of claim 10, wherein each of the central conductive bump and the peripheral conductive bump of the package component comprises: a first copper-containing layer; a nickel-containing layer overlying the first copper-containing layer; as well as A second copper-containing layer is overlaid on the nickel-containing layer and is close to the first semiconductor die and the second semiconductor die, wherein the first bonding structure and the second bonding structure at least wrap the second copper-containing layer of the central conductive bump and the peripheral conductive bump of the package component.

12. The semiconductor package according to claim 10, wherein the first bonding structure and the second bonding structure comprise solder, the corresponding first bonding structure comprises a substantially elliptical cross-section having a first curvature, and the corresponding second bonding structure comprises a substantially elliptical cross-section having a second curvature different from the first curvature.

13. The semiconductor package according to claim 10, wherein: A vertical distance between the central conductive bump of the package assembly and the peripheral conductive bumps of the first semiconductor die and the second semiconductor die is smaller than a vertical distance between the peripheral conductive bumps of the package assembly and the central conductive bumps of the first semiconductor die and the second semiconductor die, and The maximum width of the first bonding structure is greater than the maximum width of the second bonding structure.

14. The semiconductor package according to claim 10, wherein: A vertical distance between the central conductive bump of the package assembly and the peripheral conductive bumps of the first semiconductor die and the second semiconductor die is greater than a vertical distance between the peripheral conductive bumps of the package assembly and the central conductive bumps of the first semiconductor die and the second semiconductor die, and The maximum width of the first engagement structure is smaller than the maximum width of the second engagement structure.

15. A method for manufacturing a semiconductor package, comprising: forming a stack of conductive materials on the conductive pad to form a first conductive bump and a second conductive bump of a first package component, wherein the first package component is warped and the second conductive bump is higher than the first conductive bump; aligning the first conductive bump of the first package component with the third conductive bump of the second package component and aligning the second conductive bump with the fourth conductive bump of the second package component, wherein the corresponding first conductive bump is formed to have a solder-containing layer thicker than a thickness of a solder-containing layer of the corresponding third conductive bump; as well as The solder-containing layer of the first conductive bump of the first package component is combined with the solder-containing layer of the third conductive bump of the second package component to form a first bonding structure on the first conductive bump and the third conductive bump, and the second conductive bump and the fourth conductive bump are combined to form a second bonding structure, wherein: The first bonding structure wraps a portion of the sidewall of the first conductive bump and a portion of the sidewall of the third conductive bump. The second bonding structure wraps a portion of the sidewall of the second conductive bump and a portion of the sidewall of the fourth conductive bump, and A first angle between another portion of the side wall of the first conductive bump not wrapped by the first bonding structure and a first tangent line of the first bonding structure at an endpoint of a boundary of the other portion on the side wall of the first conductive bump is smaller than a second angle between another portion of the side wall of the second conductive bump not wrapped by the second bonding structure and a second tangent line of the second bonding structure at an endpoint of a boundary of the other portion on the side wall of the second conductive bump.

16. The method for manufacturing a semiconductor package according to claim 15, further comprising: Before forming the first conductive bump of the first package component, analyzing a warpage characteristic of the first package component; as well as The solder containing layer of the first conductive bump is formed to have a predetermined thickness based on the warpage characteristic.

17. A method for manufacturing a semiconductor package according to claim 15, wherein when forming the first conductive bump of the first package component, the volume of the solder-containing layer of the corresponding first conductive bump of the first package component is formed to be substantially equal to the volume of the solder-containing layer of the corresponding third conductive bump of the second package component.

18. The method for manufacturing a semiconductor package according to claim 15, wherein forming the first conductive bump of the first package component comprises: A first copper-containing layer, a nickel-containing layer, a second copper-containing layer and a solder-containing layer are plated on the conductive pad in sequence.

19. The method for manufacturing a semiconductor package according to claim 15, wherein forming the first bonding structure comprises: heating the first package component at a predetermined temperature, wherein the first package component forms a concave warpage profile; as well as Cooling the first package component, wherein the solder-containing layer of the corresponding first conductive bump of the first package component is combined with the solder-containing layer of the corresponding third conductive bump to form the first bonding structure, and the curvature of the cross-section of the first bonding structure decreases from one of the first bonding structures located in the central area of ​​the first package component to another of the first bonding structures located in the peripheral area of ​​the first package component.

20. The method for manufacturing a semiconductor package according to claim 15, wherein forming the first bonding structure comprises: heating the first package component at a predetermined temperature, wherein the first package component forms a convex warpage profile; as well as The first package component is cooled, wherein the solder-containing layer of the corresponding first conductive bump of the first package component is bonded together with the solder-containing layer of the corresponding third conductive bump to form the first bonding structure.

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