Substrate structure containing embedded semiconductor device and its manufacturing method

Abstract

This invention provides a substrate structure. The substrate structure includes an interconnect structure, a dielectric layer on the interconnect structure, an electronic component embedded in the dielectric layer, and a first via disposed through the dielectric layer and adjacent to the electronic component. The interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. At least one of the first conductive layer and the second conductive layer, and the first via, define a first shielding structure surrounding the electronic component. A method for manufacturing the substrate structure is also disclosed.

Description

Technical Field

[0001] The present invention generally relates to a substrate, and more particularly to a substrate in which electronic components are embedded. Background Technology

[0002] Embedded substrate technology incorporates at least one active or passive electronic component within a conductive layer of a substrate. This conductive layer facilitates electrical interconnection or signal transmission for the embedded electronic component. Embedded substrates are becoming increasingly popular due to their potential to reduce package size, increase power density, and improve device performance. Summary of the Invention

[0003] In one or more embodiments, the present invention provides a substrate structure. The substrate structure includes an interconnect structure, a dielectric layer on the interconnect structure, an electronic component embedded in the dielectric layer, and a first via disposed through the dielectric layer and adjacent to the electronic component. The interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. At least one of the first conductive layer and the second conductive layer, and the first via, define a first shielding structure surrounding the electronic component.

[0004] In one or more embodiments, the present invention provides a semiconductor device package. The semiconductor device package includes an interconnect structure, a dielectric layer on the interconnect structure, a first electronic component embedded in the dielectric layer, and a first via disposed through the dielectric layer and adjacent to the first electronic component. The interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The semiconductor device package further includes an encapsulation layer disposed on the second conductive layer, and a second electronic component embedded in the encapsulation layer and electrically connected to the second conductive layer. The first conductive layer and the first via define a first shielding structure surrounding the first electronic component.

[0005] In one or more embodiments, the present invention provides a method for manufacturing a substrate structure. The method includes providing an interconnect structure. The interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The method further includes attaching an electronic component to the interconnect structure, and forming a first via adjacent to the electronic component. The first via is electrically connected to at least one of the first conductive layer and the second conductive layer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of the invention will be readily understood from the following embodiments. It should be noted that various features may not be drawn to scale. For clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a cross-sectional view of the substrate structure according to an embodiment of the present invention.

[0008] Figure 2A This is a schematic perspective view of an electromagnetic interference (EMI) shielding mechanism according to an embodiment of the present invention.

[0009] Figure 2B This is a schematic perspective view of an EMI shielding mechanism according to another embodiment of the present invention.

[0010] Figure 3 This is a cross-sectional view of a substrate structure according to another embodiment of the present invention.

[0011] Figure 4 This is a cross-sectional view of a substrate structure according to another embodiment of the present invention.

[0012] Figure 5A This is a cross-sectional view of a semiconductor device package according to another embodiment of the present invention.

[0013] Figure 5B This is a cross-sectional view of a semiconductor device package according to another embodiment of the present invention.

[0014] Figure 6A One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0015] Figure 6B One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0016] Figure 6C One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0017] Figure 6D One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0018] Figure 6E One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0019] Figure 6F One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0020] Figure 6G One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0021] Figure 6HOne or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0022] Figure 6I One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0023] Figure 6J One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present invention are shown.

[0024] Common reference numerals are used throughout the drawings and embodiments to indicate the same or similar elements. The invention will become more apparent from the following embodiments in conjunction with the accompanying drawings. Detailed Implementation

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these components and arrangements are merely examples and are not intended to be limiting. In this invention, references to a first feature being formed above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this invention. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0026] Embodiments of the invention are described in detail below. However, it should be understood that the invention provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative and do not limit the scope of the invention.

[0027] Figure 1 This is a cross-sectional view of a substrate structure 1 according to an embodiment of the present invention. The substrate structure 1 includes an interconnect structure 10, dielectric layers 11 and 12, electronic components 13 and 14, a conductive layer 15, a protective layer 16, and electrical contacts 17 and 18.

[0028] The interconnect structure 10 includes a carrier 10d having a surface 10d1 and a surface 10d2 opposite to the surface 10d1. The interconnect structure 10 further includes a conductive layer 10c1 disposed on the surface 10d1 and a conductive layer 10c2 disposed on the surface 10d2. A via 10v passes through the carrier 10d and connects between the conductive layers 10c1 and 10c2. The via 10v gradually narrows towards the conductive layer 10c1. For example, the width of the via 10v closer to the conductive layer 10c1 is substantially smaller than the width of the via 10v closer to the conductive layer 10c2.

[0029] In some embodiments, the interconnect structure 10 may include a copper-clad laminate (CCL) substrate. In some embodiments, the carrier 10d may include a molding compound, a prepreg composite fiber (e.g., a prepreg), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass (USG), any combination of two or more thereof, or similar materials. In some embodiments, the carrier 10d may include an organic material. In some embodiments, the carrier 10d may include an organic material that further includes a filler such as a glass optical fiber. In some embodiments, the carrier 10d may have a thickness ranging from about 35 micrometers (μm) to about 400 μm.

[0030] In some embodiments, conductive layers 10c1 and 10c2 may each comprise copper (Cu) or other conductive materials, such as aluminum (Al), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, another metal, or a mixture, alloy, or other combination thereof. In some embodiments, conductive layers 10c1 and 10c2 may each have a thickness ranging from about 5 μm to about 18 μm.

[0031] A protective layer 18 is disposed over the conductive layer 10c2 to encapsulate or cover the conductive layer 10c2. In some embodiments, the protective layer 18 may fully expose or expose at least a portion of the via 10v and / or the conductive layer 10c2 for electrical connection. In some embodiments, the protective layer 18 may contain solder resist or solder mask.

[0032] Electronic components 13 and 14 are disposed above conductive layer 10c1. Electronic component 13 has a surface (or may be referred to as an active surface) 131, a surface (or may be referred to as a back surface) 132 opposite to surface 131, and a lateral surface (or may be referred to as a lateral surface) 133 extending between surface 131 and surface 132.

[0033] In some embodiments, electronic component 13 may be a chip or die, comprising a semiconductor substrate, one or more integrated circuit devices, and one or more overlay interconnect structures thereon. The integrated circuit device may comprise active devices such as transistors, and / or passive devices such as resistors, capacitors, inductors, or combinations thereof.

[0034] Electronic component 13 is attached to interconnect structure 10 via dielectric layer 11. For example, dielectric layer 11 may be or may include adhesive or bonding layer and is attached to surface 132 of electronic component 13 on conductive layer 10c1. Electronic component 13 includes conductive pads 13p and vias 13v on surface 131 to provide electrical interconnection or signal transmission for substrate structure 1. Electronic component 14 may have a similar structure and arrangement to electronic component 13, and similar descriptions are omitted below for simplicity and clarity.

[0035] Dielectric layer 12 is disposed on dielectric layer 11 and surrounds electronic component 13 and electronic component 14. Electronic component 13 and electronic component 14 are embedded, encapsulated or covered in dielectric layers 11 and 12.

[0036] In some embodiments, each of dielectric layer 11 and dielectric layer 12 may comprise a laminate or a film. In some embodiments, dielectric layer 12 may comprise, for example, one or more organic materials (e.g., molding compounds, bismaleimide triazine (BT), polyimide (PI), polybenzoxazole (PBO), solder resist, Ajinomoto accumulator (ABF), polypropylene (PP), epoxy-based materials, or combinations thereof), inorganic materials (e.g., silicon, glass, ceramics, quartz, or combinations thereof), liquid film materials, or dry film materials, or combinations thereof. In some embodiments, the interface between dielectric layer 11 and dielectric layer 12 may be observed via scanning electron microscopy (SEM) or other suitable techniques. In some embodiments, the thickness of the first dielectric layer 11 may be approximately 35 μm.

[0037] The conductive layer 15 is disposed on the dielectric layer 12 and electrically connected to the via 13v on the surface 131 of the electronic component 13. In some embodiments, the conductive layer 15 may include the materials listed above for the conductive layers 10c1 and 10c2.

[0038] A protective layer 16 is disposed on the conductive layer 15 to fully expose or expose at least a portion of the via 13v and / or the conductive layer 15 for electrical connection.

[0039] Electrical contacts 17 (e.g., solder balls) are disposed on vias 13v and / or conductive layers 15 and provide electrical connections between the substrate structure 1 and external components (e.g., external circuitry or circuit boards). In some embodiments, electrical contacts 17 include controllable collapse chip connection (C4) bumps, ball grid arrays (BGAs), or platform grid arrays (LGAs).

[0040] Via 11v is disposed within dielectric layers 11 and 12. Via 11v passes through dielectric layers 11 and 12. Via 11v is connected between conductive layers 10c1 and 15. Via 11v is connected to via conductive layer 10c1.

[0041] like Figure 1As shown, a shielding structure (labeled "SD1") is formed in the substrate structure 1 and surrounds electronic components 13 and 14. The shielding structure SD1 provides electromagnetic interference (EMI) protection to prevent electronic components 13 and 14 from being interfered with by other electronic components, and vice versa. For example, the shielding structure SD1 may be defined by a conductive layer 10c2, vias 10v and 11v, and a conductive layer 15. In some embodiments, the shielding structure SD1 may include two shielding structures, one surrounding electronic component 13 and the other surrounding electronic component 14. This further prevents electronic components 13 and 14 from interfering with each other.

[0042] In some embodiments, conductive layer 10c2 may be a conductive thin film. In some embodiments, conductive layer 10c2 may be grounded. In some embodiments, conductive layer 10c2 may be unpatterned. For example, the percentage (or density) of copper coverage in conductive layer 10c2 may be higher than the percentage (or density) of copper coverage in conductive layer 10c1.

[0043] In some embodiments, conductive layer 10c1 may be part of a shielding structure, and conductive layer 10c2 may be patterned. As a result, the shielding structure is closer to electronic components 13 and 14, which inevitably introduces parasitic capacitance.

[0044] The via 11v gradually narrows towards the conductive layer 10c1. For example, the width of the via 11v closer to the conductive layer 10c1 is substantially smaller than the width of the via 11v closer to the conductive layer 15. The vias 11v and 10v gradually narrow in opposite directions. The vias 11v and 10v gradually narrow towards each other.

[0045] In some existing practices, unlike the substrate structure 1 of the present invention which has an embedded electronic component (i.e., electronic component 13) and an embedded shielding structure (i.e., shielding structure SD1), the substrate structure 1 can be encapsulated in a package body, and the shielding layer or frame can be provided on the outer surface of the package body, for example, by molding and sputtering operations. Such practices are costly and time-consuming.

[0046] In comparison, in this invention, the shielding structure SD1 is built into the substrate structure 1, thus reducing the package size. The shielding structure SD1 is manufactured by forming vias in the dielectric layer 12 to connect to the conductive layer 10c2 and the vias 10v of the interconnect structure 10. The cost of forming the shielding structure SD1 is lower than the cost of forming a shielding layer or frame on the outer surface of the package body.

[0047] In some other existing practices, electronic components (e.g., electronic component 13) may be housed within a carrier 10d. Vias 10v and conductive layer 10c2 provide EMI protection. However, to form these vias, drilling is performed on different materials during the drilling process, which may result in a significant amount of glass fiber remaining in the carrier 10d. Such residual glass fiber may cause the later-formed vias to disconnect electrical connections. In contrast, the problems of the existing practices are solved when the electronic component 13 according to the invention is housed above the interconnect structure 10.

[0048] In substrate structure 1, conductive layer 10c2 is part of shielding structure SD1 and can be grounded, while conductive layer 10c1 is patterned and can provide signal transmission. For example, conductive layer 10c1 is patterned and may include conductive trace portions 10t for signal transmission. Conductive layer 10c2 may include a ground layer or shielding portion 10s to provide EMI protection.

[0049] Figure 2A This is a schematic perspective view of an EMI shielding mechanism according to an embodiment of the present invention. In some embodiments, Figure 2A The structure in can be Figure 1 A portion of the substrate structure 1 is shown. For simplicity and clarity, only the via 11v, electronic component 13, and conductive layer 10c2 are shown.

[0050] like Figure 2A As shown, multiple vias (or conductive pillars) 11v surround the electronic component 13. The conductive pillars 11v are connected vias in the interconnect structure 10 (such as...). Figure 1 (As shown in the figure) It is electrically connected to the conductive layer 10c2 and provides EMI protection for the electronic component 13.

[0051] The conductive post 11v is spaced apart from the electronic component 13. The conductive post 11v is disposed adjacent to the electronic component 13. The conductive post 11v is laterally spaced apart from the electronic component 13. For example, the surface 133 of the electronic component 13 faces the via 11v.

[0052] In some embodiments, the via 10v in the interconnect structure 10 (such as...) Figure 1 The number of associated conductive posts 11v (as shown in the diagram), their structure, and their deployment pattern may vary depending on the application.

[0053] Figure 2B This is a schematic perspective view of an EMI shielding mechanism according to another embodiment of the present invention. In some embodiments, Figure 2B The structure in can be Figure 1 A portion of the substrate structure 1 is shown. For simplicity and clarity, only the conductive wall 11w, electronic component 13, and conductive layer 10c2 are shown.

[0054] like Figure 2B As shown, a conductive wall 11w surrounds the electronic component 13. The surface 133 of the electronic component 13 faces the conductive wall 11w. The conductive wall 11w is connected via a via 10v in the interconnect structure 10 (e.g., ...). Figure 1 (As shown in the figure) It is electrically connected to the conductive layer 10c2 and provides EMI protection for the electronic component 13.

[0055] Figure 3 This is a cross-sectional view of substrate structure 3 according to another embodiment of the present invention. In some embodiments, Figure 3 The substrate structure 3 in the middle is similar to Figure 1 The substrate structure 1 is described below, and the differences between them are described in detail below.

[0056] Interconnect structure 30 includes conductive layers 30c1 and 30c2. Conductive layer 30c1 is partially patterned. For example, the portion of conductive layer 30c1 located directly below electronic component 14 (labeled "30t") is patterned. In some embodiments, conductive layer 30c1 includes a shielding portion 30s and a conductive trace portion 30t. The shielding portion 30s and via 11v of conductive layer 30c1 define a shielding structure (labeled "SD2") for providing EMI protection for electronic component 13. The conductive trace portion 30t of conductive layer 30c1 is at the same level or layer as the shielding portion 30s.

[0057] Similar to conductive layer 30c1, conductive layer 30c2 is partially patterned. For example, the portion of conductive layer 30c2 located directly below electronic component 13 (labeled "30t") is patterned. In some embodiments, conductive layer 30c2 includes a shielding portion 30s and a conductive trace portion 30t. The shielding portion 30s, vias 10v and 11v of conductive layer 30c2 define a shielding structure (labeled "SD3") for providing EMI protection for electronic component 14. The conductive trace portion 30t of conductive layer 30c2 is at the same level or layer as the shielding portion 30s.

[0058] The shielding structures SD3 and SD4 further prevent electronic components 13 and 14 from interfering with each other.

[0059] Figure 4 This is a cross-sectional view of substrate structure 4 according to another embodiment of the present invention. In some embodiments, Figure 4 The substrate structure 4 in the middle is similar to Figure 1 The substrate structure 1 is described below, and the differences between them are described in detail below.

[0060] Interconnect structure 40 includes conductive layer 40c1 and conductive layer 40c2. Conductive layer 40c2, via 10V, and via 11V define a shielding structure (labeled "SD1") for providing EMI protection for electronic components 13 and 14. Conductive layer 40c1 and via 11V define a shielding structure (labeled "SD5") for providing EMI protection for electronic components 13 and 14. Shielding structure SD5 is formed within shielding structure SD1. Shielding structures SD1 and SD5 together form a two-layer shielding structure for electronic components 13 and 14.

[0061] Figure 5A This is a cross-sectional view of the substrate structure 5 according to another embodiment of the present invention. In some embodiments, Figure 5A The substrate structure 5 in the middle is similar to Figure 1 The substrate structure 1 is described below, and the differences between them are described in detail below.

[0062] The substrate structure 5 includes an electronic component 51 disposed on an interconnect structure 50. The electronic component 51 is disposed on the opposite side of the interconnect structure 50 relative to the electronic component 13. The electronic component 51 is electrically connected to the conductive layer 50c2 via an electrical contact 51c. An encapsulation layer 52 is disposed on the top surface of the protective layer 18 to cover or encapsulate the electronic component 51. In some embodiments, the encapsulation layer 52 comprises an epoxy resin having a filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material wherein silicone is dispersed, or a combination thereof.

[0063] Figure 5B This is a cross-sectional view of a substrate structure 6 according to another embodiment of the present invention. The substrate structure 6 includes a plurality of units (e.g., substrate structure 5), which are separated from each other by cleavage.

[0064] Figure 6A-6J This is a cross-sectional view of a substrate structure 6 according to another embodiment of the present invention. The interconnect structure 50 includes a CCL substrate, which contains a plurality of cells that can be separated from each other by dicing channels.

[0065] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6J These are cross-sectional views of the wiring structure at various manufacturing stages according to some embodiments of the present invention. At least some of these figures have been simplified for a better understanding of aspects of the invention.

[0066] refer to Figure 6AAn interconnect structure 10 is provided. The interconnect structure 10 includes a carrier 10d having a surface 10d1 and a surface 10d2 opposite to the surface 10d1. The interconnect structure 10 includes a conductive layer 10c1 on the surface 10d1 and a conductive layer 10c2 on the surface 10d2. The carrier 10d may include a dielectric layer and may include a filler such as glass fiber.

[0067] In an embodiment of the invention, the interconnect structure 10 includes a CCL substrate containing a plurality of cells that can be separated from each other by dicing channels. Because each of the cells undergoes similar or identical processes in the manufacturing method, for convenience, only exemplary cells are shown and described below.

[0068] refer to Figure 6B For example, in a photolithography process, the conductive layer 10c1 is subsequently patterned in an etching process to create a patterned conductive layer. See also... Figure 1 The patterned conductive layer may include conductive pads or conductive traces 10t, or both, to facilitate electrical interconnection or signal transmission. Next, a dielectric layer 11 is formed on the surface 10d1 of the carrier 10d, covering the conductive traces 10t. Suitable materials for the first dielectric layer 11 may be selected from materials having the desired adhesiveness to facilitate attachment, for example, of semiconductor devices or electronic components. In some embodiments, the dielectric layer 11 comprises a resin. Furthermore, the dielectric layer 11 may not contain fillers such as glass fibers.

[0069] Then, refer to Figure 6C Electronic components 13 and 14 are attached to dielectric layer 11. Electronic components 13 and 14 are oriented "face up", with their conductive pads 13p and 14p facing away from dielectric layer 11. Electronic components 13 and 14 may each contain active or passive devices.

[0070] refer to Figure 6D A dielectric layer 12 is formed on the dielectric layer 11, covering electronic components 13 and 14. Suitable materials for the dielectric layer 12 are similar to or equivalent to those used for the dielectric layer 11. Specifically, similar to the dielectric layer 11, the dielectric layer 12 may comprise a glass fiber-free resin.

[0071] refer to Figure 6E For example, in a lamination process, a conductive layer 15 is formed on the surface of the dielectric layer 12. Suitable materials for the conductive layer 15 may include Cu.

[0072] Subsequently, reference Figure 6F The conductive layer 15 is patterned to create a patterned conductive layer 15. The patterned conductive layer 15 exposes a first portion (unnumbered) of the dielectric layer 12, the location of which corresponds to a via (e.g., Figure 1The via 11v shown in the figure. In addition, the patterned conductive layer 15 exposes a second portion (unnumbered) of the dielectric layer 12, the position of which corresponds to the conductive pads 13p and 14p.

[0073] Subsequently, the first opening 11h is formed as an exposed first portion, for example, in a laser drilling process using a carbon dioxide (CO2) laser, thereby exposing the conductive trace 10t in the patterned conductive layer 10c1. The first opening 12h extends toward the conductive trace 10t through the dielectric layer 12 and the dielectric layer 11. In addition, the second opening 12h is formed as an exposed second portion by, for example, a sandblasting process, thereby exposing the conductive pads 13p and 14p.

[0074] Furthermore, the conductive layer 10c2 is patterned to create a patterned conductive layer 10c2 that exposes several portions of the carrier 10d. Subsequently, an opening 10h is formed from its exposed portion as the carrier 10d by, for example, laser drilling, thereby exposing several portions of the conductive trace 10t.

[0075] In some embodiments, openings 10h and 11h are formed by laser drilling. During the formation of opening 11h extending through a glass fiber-free dielectric layer, a laser is applied with a first pulse energy. In contrast, during the formation of opening 10h extending through a glass fiber-filled dielectric layer, a laser is applied with a second pulse energy. The second pulse energy is higher than the first pulse energy.

[0076] Next, refer to Figure 6G For example, in an electroplating process, conductive material is formed on a patterned conductive layer 15. The conductive material fills openings 11h and 12h, thereby creating vias 11v, 13v, and 14v. In this embodiment of the invention, via 11v gradually narrows toward the conductive layer 10c1. A first conductive layer is also disposed on a patterned first conductive foil p23.

[0077] Similarly, for example in an electroplating process, conductive material is formed on a patterned conductive layer 10c2. The conductive material fills the opening 10h, thereby creating a via 10v.

[0078] The conductive layer 10c2, the via 10v, the via 10v and the conductive layer 15 define the shielding structure surrounding the electronic component 13 and the electronic component 14.

[0079] In some embodiments, the seed layer (not shown) may be conformally disposed on the sidewalls of openings 10h, 11h, and 12h. In some embodiments, the seed layer may be formed by sputtering titanium and copper (Ti / Cu) or titanium-tungsten alloy (TiW). In some embodiments, the seed layer may be formed by electrodeless electroplating of Ni or Cu.

[0080] Next, refer to Figure 6H The patterned conductive layer 15 undergoes a patterning process to form holes 15h, which are electrically isolated from some of the vias 11v, 13v and 14v and define conductive traces for electrical interconnection.

[0081] Next, refer to Figure 6I A protective layer 16, such as solder resist, is applied to the patterned conductive layer 15, thereby exposing vias 13v and 14v. The protective layer 16 helps control the movement of solder balls that will form on the exposed vias 13v and 14v during soldering.

[0082] Subsequently, reference Figure 6J Electrical contact 17 is provided on the exposed vias 13V and 14V.

[0083] In some embodiments, electronic components (e.g. Figure 5A The electronic component 51) can be provided on the interconnect structure 10 and electrically connected to the conductive layer 10c2.

[0084] Encapsulation layer (e.g.) Figure 5A Encapsulation layer 52 may be formed on interconnect structure 10 to cover or encapsulate electronic components. In some embodiments, the encapsulation layer may be formed by molding techniques such as transfer molding or compression molding. In some embodiments, monomerization may be performed to isolate individual substrate structures or semiconductor device package devices. Monomerization may be performed, for example, by using a dicing machine, laser, or other suitable dicing techniques.

[0085] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” “right,” and similar terms are used herein to describe the relationship between one element or feature and another, as illustrated in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intervening elements.

[0086] As used herein, the terms “approximately,” “substantially,” “generally,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the term may refer to an instance in which the event or situation clearly occurred or an instance in which the event or situation is very close to occurring. As used herein, with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may refer to two surfaces that differ by no more than a few micrometers (μm) along the same plane, for example, by no more than 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When referring to a value or characteristic as “substantially” the same, the term may mean that the value is within ±10%, ±5%, ±1%, or ±0.5% of the average of the values.

[0087] The foregoing summary outlines several embodiments and detailed features of the present invention. The embodiments described herein can be readily used as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the embodiments introduced herein. These equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A substrate structure comprising: An interconnect structure, wherein the interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier; A first dielectric layer is located on the interconnect structure; The second dielectric layer is located on the first dielectric layer; Electronic components are embedded in the second dielectric layer; and A first via is disposed through the first dielectric layer and the second dielectric layer and adjacent to the electronic component; The first conductive layer and at least one of the second conductive layer, and the first via define a first shielding structure surrounding the electronic component.

2. The substrate structure of claim 1, wherein the electronic component has an active surface facing away from the interconnect structure, a back surface opposite to the active surface, and a lateral surface extending between the active surface and the back surface; wherein the lateral surface of the electronic component faces the first via; and wherein the back surface of the electronic component is substantially coplanar with the lower surface of the second dielectric layer.

3. The substrate structure according to claim 2, wherein the first conductive layer includes conductive traces for signal transmission, and wherein the first dielectric layer is formed on the carrier and covers the conductive traces.

4. The substrate structure of claim 2, wherein the first via extends beyond the back surface of the electronic component.

5. The substrate structure according to claim 2, wherein the back surface of the electronic component is in direct contact with the first dielectric layer.

6. The substrate structure according to claim 1, wherein the first dielectric layer is formed on the carrier and covers the first conductive layer, and the substrate structure further comprises: A second via is connected between the first conductive layer and the second conductive layer, wherein the second via gradually narrows toward the first conductive layer.

7. The substrate structure of claim 6, wherein the first via and the first conductive layer define a first shielding structure surrounding the electronic component, and the second conductive layer and the second via define a second shielding structure surrounding the electronic component.

8. The substrate structure of claim 1, wherein the first via includes a conductive wall surrounding one side of the electronic component.

9. The substrate structure according to claim 1, further comprising: A conductive layer disposed on the second dielectric layer and electrically connected to the first via, wherein the first via passes through the conductive layer; and A third via disposed on the electronic component and electrically connected to the conductive layer and the electronic component, wherein the third via passes through a portion of the second dielectric layer.

10. A semiconductor device package comprising: An interconnect structure, wherein the interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier; The first dielectric layer is located on the first conductive layer; The second dielectric layer is located on the first dielectric layer; The first electronic component is embedded in the second dielectric layer; A capsule sealing layer is disposed on the second conductive layer; The second electronic component is embedded in the encapsulation layer and electrically connected to the second conductive layer; and The first via is disposed through the first dielectric layer and the second dielectric layer and adjacent to the first electronic component; The first conductive layer and the first via define a first shielding structure surrounding the first electronic component.

11. The semiconductor device package of claim 10, wherein the first electronic component has an active surface facing away from the interconnect structure, a back surface opposite to the active surface, and a lateral surface extending between the active surface and the back surface; wherein the lateral surface of the first electronic component faces the first via; and wherein the back surface of the electronic component is substantially coplanar with the lower surface of the second dielectric layer.

12. The semiconductor device package of claim 11, wherein the first conductive layer includes conductive traces for signal transmission, wherein the first dielectric layer is formed on the carrier and covers the conductive traces.

13. The semiconductor device package of claim 11, wherein the first via extends beyond the back surface of the electronic component.

14. The semiconductor device package of claim 11, wherein the back surface of the electronic component is in direct contact with the first dielectric layer.

15. The semiconductor device package of claim 10, wherein the first dielectric layer is formed on the carrier and covers the first conductive layer, and the semiconductor device package further comprises: A second via is connected between the first conductive layer and the second conductive layer, wherein the second via gradually narrows toward the first conductive layer.

16. The semiconductor device package of claim 15, wherein the first via and the first conductive layer define a first shielding structure surrounding the first electronic component, and the second conductive layer and the second via define a second shielding structure surrounding the first electronic component.

17. The semiconductor device package of claim 10, further comprising: A protective layer is disposed between the second conductive layer and the encapsulation layer; The second electronic component is electrically connected to the second conductive layer via an electrical contact passing through the protective layer; and The second electronic component is located outside the first shielding structure.

18. A method for manufacturing a substrate structure, comprising: An interconnect structure is provided, wherein the interconnect structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier; A first dielectric layer is formed on the interconnect structure; Attach the electronic components to the first dielectric layer; A second dielectric layer is formed on the first dielectric layer to cover the electronic component; and A first via is formed through the first dielectric layer and the second dielectric layer and adjacent to the electronic component, wherein the first via is electrically connected to at least one of the first conductive layer and the second conductive layer.

19. The method of claim 18, further comprising: A conductive layer is formed on the second dielectric layer; The first dielectric layer, the second dielectric layer, and the conductive layer are patterned to create a first opening that exposes a portion of the first conductive layer.

20. The method of claim 19, further comprising: The carrier and the second conductive layer are patterned to create the second opening; The first opening is filled with a conductive material to create a first via.

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