Semiconductor device and method of forming the same

Abstract

The gate cut technique disclosed herein forms a gate isolation fin to isolate metal gates of a multi-gate device from one another prior to forming the multi-gate device, particularly prior to forming the metal gates of the multi-gate device. An exemplary device includes a first multi-gate device having first source / drain components and a first metal gate surrounding a first channel layer, and a second multi-gate device having second source / drain components and a second metal gate surrounding a second channel layer. A gate isolation fin separating the first metal gate and the second metal gate includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed above the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap can be disposed on the gate isolation fin to provide additional isolation. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Multi-gate devices have been introduced to improve gate control. They have been observed to increase gate-channel coupling, reduce off-state current, and / or reduce short-channel effect (SCE). One such multi-gate device is the gate all-around (GAA) device, which includes a gate structure that can extend partially or entirely around the channel region to provide access to the channel region at least on both sides. GAA devices are able to aggressively scale down IC technology, maintain gate control, and reduce SCE while seamlessly integrating with conventional IC manufacturing processes. However, as GAA devices continue to scale, non-self-aligned gate dicing techniques, typically used to isolate the gates of different GAA devices from each other (such as isolating the first gate of a first GAA transistor from the second gate of a second GAA transistor), are hindering the dense packaging of IC components required for advanced IC technology nodes. Therefore, while existing GAA devices and the methods used to manufacture them are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device, including: a first multi-gate device having: a first channel layer disposed between first source / drain components, and a first metal gate surrounding the first channel layer; a second multi-gate device having: a second channel layer disposed between second source / drain components, and a second metal gate surrounding the second channel layer; and a gate isolation fin disposed between the first metal gate and the second metal gate and separating the first metal gate and the second metal gate, wherein the gate isolation fin includes: a first dielectric layer having a first dielectric constant, and a second dielectric layer disposed above the first dielectric layer, wherein the second dielectric layer has a second dielectric constant smaller than the first dielectric constant.

[0004] Some other embodiments of this application provide a semiconductor device, including: an isolation member disposed above a substrate, wherein the isolation member is disposed between a first fin portion and a second fin portion extending from the substrate; a gate isolation fin disposed above the isolation member, wherein the gate isolation fin includes a low-k dielectric layer disposed above a high-k dielectric layer; a first multi-gate device having a first channel layer disposed above the first fin portion, a first metal gate enclosing the first channel layer, and a first source / drain member, wherein the first metal gate is disposed between the first channel layer and the first fin portion; and a second multi-gate device having a second channel layer disposed above the second fin portion, a second metal gate enclosing the second channel layer, and a second source / drain member, wherein the second metal gate is disposed between the second channel layer and the second fin portion, and wherein the gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device.

[0005] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming an isolation component in the lower portion of a trench; forming a gate isolation fin above the isolation component, wherein the gate isolation fin is formed in the upper portion of the trench by the following steps: depositing a first dielectric layer having a first dielectric constant along the bottom and sidewalls of the upper portion of the trench; depositing a second dielectric layer in the upper portion of the trench above the first dielectric layer, wherein the second dielectric layer has a second dielectric constant less than the first dielectric constant; and performing a planarization process on the first dielectric layer and the second dielectric layer; and after forming the gate isolation fin, forming a first multi-gate device and a second multi-gate device, wherein: the first multi-gate device... The first multi-gate device has a first channel layer, a first metal gate, and a first source / drain component, wherein the first channel layer is disposed between the first source / drain component and the first metal gate surrounds the first channel layer; the second multi-gate device has a second channel layer, a second metal gate, and a second source / drain component, wherein the second channel layer is disposed between the second source / drain component and the second metal gate surrounds the second channel layer; and the gate isolation fin is disposed between the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device and separates the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device. Attached Figure Description

[0006] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a flowchart of a method for manufacturing a gate-cut isolation structure for a multi-gate device according to various aspects of the present invention.

[0008] Figures 2 to 9 , Figures 10A to 10D , Figures 11A to 11D , Figures 12A to 12D , Figures 13A to 13D , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18D , Figures 19A to 19D , Figures 20A to 20E , Figures 21A to 21D , Figures 22A to 22D , Figures 23A to 23D , Figures 24A to 24D , Figures 25A to 25D and Figures 26A to 26D It is according to various aspects of the invention at various manufacturing stages (such as with) Figure 1 A partial or overall three-dimensional view of a multi-gate device (related to the methods in the text).

[0009] Figures 27A to 27D and Figures 28A to 28D It is according to various aspects of the invention at various manufacturing stages (such as with) Figure 1 A partial or overall three-dimensional view of another multi-gate device (related to the methods in the text).

[0010] Figures 29 to 35 It is according to various aspects of the invention at various manufacturing stages (such as with) Figure 1 A partial or overall three-dimensional view of a multi-gate device (related to the methods in the text). Detailed Implementation

[0011] This invention relates generally to integrated circuit devices, and more specifically to gate isolation techniques for multi-gate devices.

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the invention. Spatially relative terms are intended to include different orientations of the components. Furthermore, when numerical values ​​or ranges are described using terms such as “about,” “approximately,” etc., the term is intended to cover values ​​included within a reasonable range, taking into account variations inherent during manufacturing as understood by those skilled in the art. For example, a numerical value or range of values ​​encompasses a reasonable range including the described value, such as within + / -10% of the described value, based on known manufacturing tolerances associated with manufacturing parts having the characteristics related to the value. For example, a material layer with a thickness of “about 5 nm” can cover a size range from 4.5 nm to 5.5 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -10%. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] An exemplary non-self-aligned gate dicing technique may include forming a mask layer over a gate stack, wherein the mask layer covers a first portion and a second portion of the gate stack, and exposes a third portion of the gate stack via an opening formed in the mask layer. The third portion of the gate stack is disposed between the first portion and the second portion of the gate stack. An etching process is then performed to remove the exposed third portion of the gate stack (including, for example, at least one gate electrode layer and at least one gate dielectric layer) to form a gate opening separating the first portion and the second portion of the gate stack. A gate isolation component, such as a dielectric layer (e.g., a silicon nitride layer), is then formed in the gate opening to provide electrical isolation between the first portion of the gate stack (which may be disposed over a first channel layer (i.e., a first active device region) of a first GAA device) and the second portion of the gate stack (which may be disposed over a second channel layer (i.e., a second active device region) of a second GAA device).

[0014] The spacing between active device regions (such as the first and second channel layers) is intentionally designed to be larger than the spacing necessary to compensate for process variations that occur during non-self-aligned gate dicing techniques. For example, etch load effects and / or other load effects can reduce critical dimensional uniformity (CDU) across the wafer, causing the width of openings in the mask layer and / or the width of gate openings to exceed target widths at some locations. This can lead to unintentional exposure and / or damage to the first channel layer, the second channel layer, the first portion of the gate stack, and / or the second portion of the gate stack. In another example, overlap offsets caused by photolithography processes can cause openings in the mask layer to shift to the left or right of their intended locations, which can also lead to unintentional exposure and / or damage to the first channel layer, the second channel layer, the first portion of the gate stack, and / or the second portion of the gate stack. The increased spacing between active device regions required to adequately compensate for such process variations prevents compact packaging of the active device regions and thus prevents the compact cell height required for scaled memory devices.

[0015] This invention proposes a self-aligned gate dicing (isolation) technique for multi-gate devices that allows for smaller spacing (and therefore smaller cell height) between active device regions compared to the spacing required by non-self-aligned gate dicing techniques. The proposed self-aligned gate dicing technique forms a metal gate isolation structure (e.g., gate isolation fin) in the first stage of multi-gate device fabrication, which typically involves defining the active regions of the multi-gate device. For example, the gate isolation fin is formed after forming isolation components (e.g., shallow trench isolation structures) defining the active regions of the multi-gate device and before forming the metal gate of the multi-gate device. In some embodiments, the gate isolation fin is formed after the fin active regions defining the multi-gate device and / or after forming n-wells and / or p-wells in the active regions of the multi-gate device. In some embodiments, the gate isolation fin is formed before forming the gate structure (e.g., dummy gate stacks, metal gate stacks, and / or gate spacers) and source / drain components. Because the gate isolation fins are formed in the first stage of multi-gate device fabrication, the disclosed metal gate dicing technique does not need to consider photolithography variations (e.g., overlap errors), thus allowing for smaller spacing between the active regions of the transistor and therefore smaller cell height. Therefore, multi-gate devices fabricated using this technique can increase transistor packaging density and IC patterning density. The proposed metal gate dicing technique also provides for trimming the gate isolation fins to enlarge the metal gate fill window during gate replacement (e.g., when replacing dummy gate stacks with metal gates), thereby improving processing. The proposed self-aligned gate dicing technique for multi-gate devices and the details of the resulting multi-gate devices will be described in the following pages.

[0016] Figure 1This is a flowchart of a method 100 for manufacturing a multi-gate device according to various aspects of the present invention. In some embodiments, method 100 manufactures p-type multi-gate transistors and / or n-type multi-gate transistors. In block 110, method 100 includes forming an isolation component, such as a shallow trench isolation structure, a deep trench isolation structure, other isolation structures, or combinations thereof, in a substrate. In block 115, method 100 includes forming a gate isolation fin over the isolation component. The gate isolation fin physically contacts the isolation component. The gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. In some embodiments, the gate isolation fin further includes a third dielectric layer disposed over the second dielectric layer. In some embodiments, the first dielectric constant is less than about seven, and the second dielectric constant is greater than about seven. In some embodiments, the gate isolation fin further includes an oxide layer disposed over the second dielectric layer. In some embodiments, the gate isolation fin further includes a third dielectric layer having a third dielectric constant disposed over the oxide layer, wherein the third dielectric constant is less than the first dielectric constant. In block 120, method 100 includes forming a first multi-gate device and a second multi-gate device after forming a gate isolation fin. The first multi-gate device has a first channel layer, a first metal gate, and a first source / drain component. The first channel layer is disposed between the first source / drain component, and the first metal gate surrounds the first channel layer. The second multi-gate device has a second channel layer, a second metal gate, and a second source / drain component. The second channel layer is disposed between the second source / drain component, and the second metal gate surrounds the second channel layer. A gate isolation fin is disposed between the first metal gate and the second metal gate and separates the first metal gate and the second metal gate. In some embodiments, the first metal gate is disposed between the first channel layer and the gate isolation fin and physically contacts the first channel layer and the gate isolation fin, and the second metal gate is disposed between the second channel layer and the gate isolation fin and physically contacts the second channel layer and the gate isolation fin. Additional steps may be provided before, during, and after method 100, and for additional embodiments of method 100, some described steps may be moved, substituted, or omitted. The following discussion illustrates various embodiments of multi-gate based integrated circuit devices that can be manufactured according to method 100.

[0017] Figures 2 to 9 , Figures 10A to 10D , Figures 11A to 11D , Figures 12A to 12D , Figures 13A to 13D , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18D , Figures 19A to 19D , Figures 20A to 20E , Figures 21A to 21D , Figures 22A to 22D , Figures 23A to 23D , Figures 24A to 24D , Figures 25A to 25D and Figures 26A to 26D It is according to various aspects of the invention at various manufacturing stages (such as with) Figure 1 This is a partial perspective view of a portion or the entire multi-gate device 200 (as described in Method 100). As described herein, processing the multi-gate device 200 to form a multi-gate transistor generally refers to a transistor having gates that are joined to a channel on at least two sides. In some embodiments, the multi-gate transistor has gates surrounding the channel, and these multi-gate transistors may be referred to as GAA transistors. In some embodiments, the multi-gate device 200 may be part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The multi-gate device 200 may be included in a microprocessor, memory, and / or other IC devices. For clarity, simplified diagrams have been provided. Figures 2 to 9 , Figures 10A to 10D , Figures 11A to 11D , Figures 12A to 12D , Figures 13A to 13D , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18D , Figures 19A to 19D , Figures 20A to 20E , Figures 21A to 21D , Figures 22A to 22D , Figures 23A to 23D , Figures 24A to 24D , Figures 25A to 25D and Figures 26A to 26D To better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200.

[0018] Transfer to Figure 2The multi-gate device 200 includes a substrate (wafer) 202. In the depicted embodiment, the substrate 202 includes silicon. Optionally or additionally, the substrate 202 includes another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Optionally, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using oxygen-implantation isolation (SIMOX), wafer bonding, and / or other suitable methods. The substrate 202 includes various doped regions, such as p-type doped regions (referred to as p-wells) and / or n-type doped regions (referred to as n-wells). For example, the portion of substrate 202 corresponding to the n-type transistor may include a p-well, and the portion of substrate 202 corresponding to the p-type transistor may include an n-well. The n-well is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. The p-well is doped with a p-type dopant, such as boron, indium, other p-type dopant, or combinations thereof. In some embodiments, substrate 202 includes a doped region formed with a combination of p-type and n-type dopants. The doped region can be formed directly on and / or in substrate 202, for example, by providing a p-well structure, an n-well structure, a double-well structure, a bump structure, or a combination thereof. Ion implantation, diffusion, and / or other suitable doping processes can be implemented to form the doped region.

[0019] A semiconductor layer stack 210 is formed over a substrate 202, comprising semiconductor layers 215 and 220 stacked vertically (e.g., along the z-direction) from the top surface of the substrate 202 in an alternating or staggered configuration. In some embodiments, semiconductor layers 215 and 220 are epitaxially grown in the depicted alternating and staggered configuration. For example, a first semiconductor layer 215 is epitaxially grown on the substrate 202, a first semiconductor layer 220 is epitaxially grown on the first semiconductor layer 215, a second semiconductor layer 215 is epitaxially grown on the first semiconductor layer 220, and so on, until the semiconductor layer stack 210 has a desired number of semiconductor layers 215 and 220. In such embodiments, semiconductor layers 215 and 220 may be referred to as epitaxial layers. In some embodiments, the epitaxial growth of semiconductor layers 215 and 220 is achieved via molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), other suitable epitaxial growth processes, or combinations thereof. The composition of semiconductor layer 215 differs from that of semiconductor layer 220 to achieve etch selectivity and / or different oxidation rates during subsequent processing. In some embodiments, semiconductor layer 215 has a first etch rate to an etchant, and semiconductor layer 220 has a second etch rate to an etchant, wherein the second etch rate differs from the first etch rate. In some embodiments, semiconductor layer 215 has a first oxidation rate, and semiconductor layer 220 has a second oxidation rate, wherein the second oxidation rate differs from the first oxidation rate. In the depicted embodiments, semiconductor layers 215 and 220 include different materials, component atomic percentages, component weight percentages, thicknesses, and / or properties to achieve desired etch selectivity during etching processes, such as etching processes implemented to form a floating channel layer in the channel region of a multi-gate device 200. For example, in the case where semiconductor layer 215 comprises silicon-germanium and semiconductor layer 220 comprises silicon, the silicon etch rate of semiconductor layer 220 is less than the silicon-germanium etch rate of semiconductor layer 215. In some embodiments, semiconductor layer 215 and semiconductor layer 220 comprise the same material but have different component atomic percentages to achieve etch selectivity and / or different oxidation rates. For example, semiconductor layer 215 and semiconductor layer 220 may comprise silicon-germanium, wherein semiconductor layer 215 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 220 has a second, different silicon atomic percentage and / or a second, different germanium atomic percentage. The present invention contemplates that semiconductor layer 215 and semiconductor layer 220 comprise any combination of semiconductor materials that provide desired etch selectivity, desired oxidation rate differences, and / or desired performance characteristics (e.g., materials that maximize current), including any semiconductor materials disclosed herein.

[0020] As further described below, semiconductor layer 220 or a portion thereof will form the channel region of multi-gate device 200. In the depicted embodiment, semiconductor layer stack 210 includes three semiconductor layers 215 and three semiconductor layers 220 configured to form three pairs of semiconductor layers disposed over substrate 202, each pair having a respective semiconductor layer 215 and a respective semiconductor layer 220. After subsequent processing, such a configuration will produce a multi-gate device 200 with three channels. However, the present invention contemplates embodiments of semiconductor layer stack 210 including more or fewer semiconductor layers, for example, depending on the desired number of channels of multi-gate device 200 and / or the design requirements of multi-gate device 200. For example, semiconductor layer stack 210 may include two to ten semiconductor layers 215 and two to ten semiconductor layers 220. In a further depicted embodiment, semiconductor layer 215 has a thickness t1, and semiconductor layer 220 has a thickness t2, wherein thickness t1 and thickness t2 are selected based on fabrication and / or device performance considerations of multi-gate device 200. For example, thickness t1 can be configured to define a desired distance (or gap) between adjacent channels of the multi-gate device 200 (e.g., between semiconductor layers 220 when levitated), thickness t2 can be configured to achieve a desired channel thickness of the multi-gate device 200, and thicknesses t1 and t2 can be configured to achieve desired performance of the multi-gate device 200. In some embodiments, thicknesses t1 and t2 are each about 1 nm to about 10 nm. In some embodiments, semiconductor layers 220 include n-type and / or p-type dopants, depending on their corresponding transistors. For example, semiconductor layers 220 in the n-type transistor region of the multi-gate device 200 may include p-type dopants, and semiconductor layers 220 in the p-type transistor region of the multi-gate device 200 may include n-type dopants.

[0021] Transfer to Figure 3A fin manufacturing process is performed to form fins extending from substrate 202. For example, fins 222A, fin 222B, fin 222C, fin 222D, and fin 222E (also referred to as fin structures, fin elements, active fin regions, etc.) extend from substrate 202 after the fin manufacturing process. Each of fins 222A-222E includes a substrate portion (i.e., the fin portion 202' of substrate 202 (also referred to as a substrate extension portion, substrate fin portion, etched substrate portion, etc.)), a semiconductor layer stack portion disposed above the substrate portion (i.e., a portion of semiconductor layer stack 210 including semiconductor layer 215 and semiconductor layer 220), and a patterned layer portion disposed above the semiconductor layer stack portion (i.e., patterned layer 225). Each of fins 222A-222E extends substantially parallel to each other in the x-direction, having a length defined in the x-direction, a width defined in the y-direction, and a height defined in the z-direction. Various trenches, such as those between fin active regions, are defined between fins 222A-222E. For example, a trench 230A is defined between fins 222A and fin 222B, a trench 230B is defined between fins 222B and fin 222C, a trench 230C is defined between fins 222C and fin 222D, and a trench 230D is defined between fins 222D and fin 222E. Trenches 230A-230D may have the same or different widths, creating the same or different spacings (distances) between the fin active regions. In the depicted embodiment, the multi-gate device 200 is configured to have different spacings (distances) between the fin active regions, such as spacing D1 and spacing D2. For example, fins 222A and fin 222B are separated by spacing D1, while fins 222B and fin 222C, fin 222C and fin 222D, and fin 222D and fin 222E are separated by spacing D2, where spacing D1 is greater than spacing D2. Different intervals (e.g., D1 > D2) result in different trench filling effects, and thus different configurations of the materials filling trenches 230A and 230B-230D, as further described below. In some embodiments, a ratio of interval D1 to interval D2 (i.e., D1 / D2) greater than or equal to about 1.2 results in different trench filling effects. In some embodiments, interval D1 is greater than about 40 nm, and interval D2 is from about 30 nm to about 50 nm, wherein interval D1 is greater than interval D2.

[0022] In some embodiments, photolithography and / or etching processes are performed to pattern the semiconductor layer stack to form fins 222A-222E. The photolithography process may include: forming a resist layer over the semiconductor layer stack 210 (e.g., by spin coating); performing a pre-exposure baking process; performing an exposure process using a mask; performing a post-exposure baking process; and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet (UV), deep UV (DUV), or extreme UV (EUV) light), wherein the mask blocks, transmits, and / or reflects radiation to the resist layer, depending on the mask pattern and / or mask type (e.g., a binary mask, a phase-shift mask, or an EUV mask), such that an image is projected onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiant energy, the exposed portions of the resist layer undergo chemical changes, and the exposed (or unexposed) portions of the resist layer dissolve during the development process, depending on the properties of the resist layer and the properties of the developer used in the development process. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. An etching process uses the patterned resist layer as an etching mask to remove portions of the semiconductor layer stack 210. In some embodiments, a patterned resist layer is formed over a mask layer disposed above the semiconductor layer stack 210, a first etching process removes portions of the mask layer to form a patterned layer 225 (i.e., a patterned hard mask layer), and a second etching process uses the patterned layer 225 as an etching mask to remove portions of the semiconductor layer stack 210. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. After the etching process, the patterned resist layer is removed, for example, by a resist stripping process or other suitable process. Optionally, fins 222A-222E are formed using multiple patterning processes, such as dual patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric (SID) SADP process, other dual patterning processes, or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process), or combinations thereof. Such processes can also provide fins 222A-222E with a patterned layer 225, a semiconductor layer stack 210, and a fin portion 202', such as... Figure 3As depicted. In some embodiments, directional self-assembly (DSA) technology is performed while patterning the semiconductor layer stack 210. Furthermore, in some embodiments, the exposure process may perform maskless lithography, electron beam writing, and / or ion beam writing for patterning the resist layer.

[0023] Transfer to Figure 4Isolation members 235 are formed in trenches 230A-230D, causing fins 222A-222E to extend (protrude) between the isolation members 235. For example, the isolation members 235 surround the bottom of fins 222A-222E, thereby defining an upper fin active region 238U of fins 222A-222E (generally referring to the portion of fins 222A-222E extending from the top surface of the isolation member 235) and a lower fin active region 238L of fins 222A-222E (generally referring to the portion of fins 222A-222E surrounded by the isolation member 235 and extending from the top surface of the substrate 202 to the top surface of the isolation member 235). The isolation members 235 electrically isolate the active device regions (such as fin active regions) and / or passive device regions of the multi-gate device 200. For example, the isolation members 235 separate and electrically isolate fins 222A-222E from each other. The isolation component 235 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components) or combinations thereof. Various dimensions and / or characteristics of the isolation component 235 can be configured during processing to achieve a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a localized oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof. In the depicted embodiment, the isolation component 235 is STI. The isolation component 235 can be formed by depositing an insulating material (e.g., an oxide material) over the substrate 202 after forming the fins 222A-222E, such that the thickness of the insulating material is greater than the height of the fins 222A-222E (i.e., the insulating material overfills the trenches 230A-230D); planarizing (e.g., by chemical mechanical polishing (CMP) process) the insulating material, thereby reducing the thickness of the insulating material, for example, until it is equal to the height of the fins 222A-222E; and etching back (recessing) the insulating material to form the isolation component 235. The deposition process can be a flowable CVD (FCVD) process, a high aspect ratio deposition (HARP) process, a high density plasma CVD (HDPCVD) process, other suitable deposition processes, or combinations thereof. In some embodiments, the patterned layer 225 of the fins 222A-222E serves as a planarization (e.g., CMP) stop layer, such that the planarization process is performed until the patterned layer 225 is reached and exposed. In some embodiments, the isolation member 235 includes a multilayer structure filling trenches 230A-230D, such as a silicon nitride body layer disposed above an oxide pad layer. In some embodiments, the isolation member 235 includes a dielectric layer (including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG)) disposed above a doped pad layer. In some embodiments, the isolation member 235 includes a dielectric layer disposed above a dielectric pad layer, wherein the dielectric layer and the dielectric pad layer comprise materials depending on design requirements.In some embodiments, the etching process recesses the insulating material until the desired (target) height of the upper fin active region 238U is achieved. In the depicted embodiments, the etching process continues until the semiconductor layer stack 210 is fully exposed and the fin portions 202' of fins 222A-222E are partially exposed, such that the top surface of the fin portions 202' is higher than the top surface of the isolation member 235 relative to the top surface of the substrate 202. In some embodiments, the etching process continues until the semiconductor layer stack 210 is fully exposed and reaches the fin portions 202', such that the top surface of the fin portions 202' is substantially coplanar with the top surface of the isolation member 235. In some embodiments, the semiconductor layer stack 210 is partially exposed rather than fully exposed by the etching process, such that the top surface of the fin portions 202' is lower than the top surface of the isolation member 235 relative to the top surface of the substrate 202.

[0024] Transfer to Figure 5 A silicon-germanium sacrificial layer 240 with a thickness t3 is formed over fins 222A-222E. In the depicted embodiment, the silicon-germanium sacrificial layer 240 is formed on the top surface and sidewalls of the upper fin active region 238U of fins 222A-222E, such that the silicon-germanium sacrificial layer encloses the upper fin active region 238U. In a further depicted embodiment, the upper portion of trenches 230A-230D is filled with the silicon-germanium sacrificial layer 240. In some embodiments, the thickness t3 is about 4 nm to about 12 nm. The thickness t3 can be selected according to the desired internal spacer thickness of the multi-gate device 200. In some embodiments, the silicon-germanium sacrificial layer 240 is formed by depositing a silicon-germanium layer over fins 222A-222E and etching the silicon-germanium layer to have a thickness t3 and / or a desired profile. In some embodiments, the silicon-germanium layer is selectively deposited over fins 222A-222E. In some embodiments, the silicon-germanium layer is blanket-deposited over fins 222A-222E and isolation member 235. In such an embodiment, the etching process is configured to remove the silicon-germanium layer from above the isolation member 235, thereby leaving the silicon-germanium layer on the fins 222A-222E. The silicon-germanium sacrificial layer 240 may also be referred to as a silicon-germanium cladding layer, a silicon-germanium cap, and / or a silicon-germanium protective layer.

[0025] Transfer to Figure 6A dielectric pad 260 with a thickness t4 is deposited over the multi-gate device 200, a dielectric pad 262 with a thickness t5 is deposited over the dielectric pad 260, and an oxide layer 264 is deposited over the dielectric pad 262. Because the width of trench 230A is greater than the width of trenches 230B-230D, the remaining portion of the upper part of trench 230A is filled with oxide layer 264, dielectric pad 262, and dielectric pad 264, while the remaining portion of the upper part of trenches 230B-230D is filled with dielectric pad 262 and dielectric pad 264. In some embodiments, the thickness t4 is about 2 nm to about 10 nm. In some embodiments, the thickness t5 is about 3 nm to about 10 nm. Dielectric pads 260, 262, and / or oxide layer 264 are deposited using any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), HDPCVD, FCVD, HARP, metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), subatmospheric pressure chemical vapor deposition (SACVD), other suitable deposition processes, or combinations thereof. In some embodiments, an ALD process is performed to form dielectric pads 260 and / or 262, and a CVD process is performed to form oxide layer 264. In some embodiments, thicknesses t4 and / or t5 are substantially uniform above the respective surfaces of the multi-gate device 200. For example, the thickness t4 is substantially the same along the top surface of the silicon-germanium sacrificial layer 240, the sidewall surface of the silicon-germanium sacrificial layer 240 (which defines the remaining upper portion of trenches 230A-230D), and the top surface of the isolation member 235 (which defines the bottom of the remaining upper portion of trenches 230A-230D). In another example, the thickness t5 is substantially the same along the top surface of the silicon-germanium sacrificial layer 240, the sidewall surface of the silicon-germanium sacrificial layer 240 in trench 230A (which defines the remaining upper portion of trench 230A), and the top surface of the isolation member 235 in trench 230A (which defines the bottom of the remaining upper portion of trench 230A).

[0026] Dielectric pad 260 comprises a dielectric material having a dielectric constant greater than that of the dielectric material of dielectric pad 262. In the depicted embodiment, dielectric pad 260 comprises a dielectric material having a dielectric constant greater than about 7.0 (k ≥ 7.0), and dielectric pad 262 comprises a dielectric material having a dielectric constant less than about 7.0 (k ≤ 7.0). For the purposes of this invention, dielectric materials having a dielectric constant greater than about 7.0 are referred to as high-k dielectric materials, and dielectric materials having a dielectric constant less than about 7.0 are referred to as low-k dielectric materials. Therefore, dielectric pad 260 and dielectric pad 262 may be referred to as a high-k dielectric pad and a low-k dielectric pad, respectively. In some embodiments, dielectric pad 260 comprises a dielectric material having a dielectric constant of about 7.0 to about 30.0, and dielectric pad 262 comprises a dielectric material having a dielectric constant of about 1.0 to about 7.0. In some embodiments, the dielectric pad 260 comprises a metal- and oxygen-containing dielectric material having a dielectric constant of, for example, from about 7.0 to about 30.0, such as a dielectric material comprising oxygen bonded to hafnium, aluminum, and / or zirconium. In such embodiments, the dielectric pad 260 may also be referred to as a metal oxide layer. For example, the dielectric pad 260 comprises hafnium oxide (e.g., HfO). x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ( ) or combinations thereof, where x is the number of oxygen atoms in the dielectric material of dielectric pad 260. In some embodiments, dielectric pad 260 includes n-type dopant and / or p-type dopant. In some embodiments, dielectric pad 260 includes HfO2, HfSiO x (e.g., HfSiO or HfSiO4), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3, HfO2-Al2O3, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, dielectric pad 262 comprises a nitrogen-containing dielectric material, such as a dielectric material comprising nitrogen bonded to silicon, carbon, and / or oxygen. In such embodiments, dielectric pad 262 may be referred to as a nitride pad. For example, dielectric pad 262 comprises silicon nitride, silicon carbonitride, silicon carbonitride, or combinations thereof. In some embodiments, dielectric pad 262 comprises an n-type dopant and / or a p-type dopant. For example, dielectric pad 262 may be a boron-doped nitride pad. In some embodiments, the dielectric pad 262 comprises a dielectric material having a dielectric constant smaller than that of silicon dioxide (SiO2) (k≈3.9), such as fluorine-doped silicon dioxide (e.g., fluorosilicate glass (FSG)) or carbon-doped silicon dioxide (e.g., carbon-doped FSG). (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorocarbon, parylene, benzocyclobutene (BCB)-based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, dielectric pad 262 comprises BSG, PSG, and / or boron-doped PSG (BPSG).

[0027] In a further depicted embodiment, oxide layer 264 comprises an oxide material (i.e., a material comprising oxygen and another chemical element (e.g., silicon)). For example, oxide layer 264 comprises silicon and oxygen and may be referred to as a silicon oxide layer. The oxide material of oxide layer 264 and the low-k dielectric material of dielectric pad 262 are selected to ensure etch selectivity during subsequent etching processes, as further described below. In other words, oxide layer 264 and dielectric pad 262 comprise materials with different etch sensitivities to a given etchant. For example, oxide layer 264 comprises an oxide material whose etch rate to the etchant is greater than that of the low-k dielectric material of dielectric pad 262. In some embodiments, the composition of oxide layer 264 is tailored to achieve an etch selectivity greater than or equal to about 50:1 (i.e., the ratio of the etch rate of oxide layer 264 to the etch rate of dielectric pad 262). In some embodiments, oxide layer 264 includes a low-k dielectric material, wherein the low-k dielectric material is different from the low-k dielectric material of dielectric pad 262, thereby enabling desired etch selectivity between oxide layer 264 and dielectric pad 262.

[0028] Transfer to Figure 7CMP and / or other planarization processes are performed on oxide layer 264 and dielectric pad 262. After the CMP process, the remaining portions of oxide layer 264 and dielectric pad 262 form dielectric pad 262A and oxide layer 264A in the upper portion of trench 230A, dielectric pad 262B in the upper portion of trench 230B, dielectric pad 262C in the upper portion of trench 230C, and dielectric pad 262D in the upper portion of trench 230D. Dielectric pad 260 serves as a CMP stop layer, thereby allowing the CMP process to be performed until dielectric pad 260 is reached and exposed. The CMP process removes the portion of oxide layer 264 disposed above the top surface of dielectric pad 260 and the portion of dielectric pad 262 disposed above the top surface of dielectric pad 260. The CMP process can planarize the top surface of oxide layer 264A, the top surfaces of dielectric pads 262A-262D, and the top surface of dielectric pad 260, so that such surfaces are substantially coplanar after the CMP process.

[0029] Transfer to Figure 8 The process is implemented to replace a portion of the oxide layer 264A with a dielectric capping layer 266. The dielectric capping layer 266 is similar to dielectric pads 262A-262D. For example, the dielectric capping layer 266 comprises a dielectric material having a dielectric constant less than about 7.0 (e.g., a dielectric material having a dielectric constant from about 1.0 to about 7.0). Therefore, the dielectric capping layer 266 is a low-k dielectric material and may comprise the same material described above with reference to dielectric pad 262. In some embodiments, the dielectric capping layer 266 comprises a nitrogen-containing dielectric material, such as a dielectric material comprising nitrogen bonded to silicon, carbon, and / or oxygen. For example, the dielectric capping layer 266 comprises silicon nitride, silicon carbonitride, silicon carbonitride oxide, or combinations thereof. In such embodiments, the dielectric capping layer 266 may be referred to as a nitride capping layer. In some embodiments, the dielectric capping layer 266 and dielectric pads 262A-262D comprise the same low-k dielectric material. In some embodiments, the dielectric capping layer 266 and the dielectric pads 262A-262D comprise different low-k dielectric materials.

[0030] The process of replacing a portion of the oxide layer 264A with the dielectric capping layer 266 may include: etching back (recessing) the oxide layer 264 to form a recess having sidewalls defined by the dielectric pad 262A and a bottom defined by the recessed top surface of the oxide layer 264A; depositing a dielectric capping material over the multi-gate device 200, wherein the dielectric capping material is disposed over the oxide layer 264A and fills the recess; and performing a planarization process such as a CMP process to remove any dielectric capping material disposed over the top surfaces of the fins 222A-222E. The remaining portion of the dielectric capping material forms the dielectric capping layer 266 having a thickness t6. In some embodiments, the thickness t6 is from about 15 nm to about 50 nm. In some embodiments, the oxide layer 264 is etched back until the distance defined between the top surface of the patterned layer 225 and the oxide layer 264A satisfies the target thickness of the dielectric capping layer 266. The recessing of oxide layer 264 can be achieved by an etching process configured to selectively remove oxide layer 264 relative to dielectric pads 262A-262D, and in some embodiments relative to dielectric pad 260. In other words, the etching process substantially removes oxide layer 264, but does not remove or substantially does not remove dielectric pads 262A-262D and / or dielectric pad 260. For example, an etchant is selected for the etching process that etches the silicon- and oxygen-containing dielectric material (i.e., oxide layer 264) at a higher rate than that of the silicon- and nitrogen-containing dielectric material (i.e., dielectric pads 262A-262D) (i.e., the etchant has high etch selectivity relative to the silicon-containing dielectric material). In the depicted embodiments, patterned layer 225 of fins 222A-222E serves as a planarization stop layer, thereby enabling a planarization process to be performed until the patterned layer 225 is reached and exposed. In this embodiment, the CMP process also removes the portions of dielectric pads 262A-262D disposed above the top surface of patterned layer 225, the portion of dielectric pad 260 disposed above the top surface of patterned layer 225, and the portion of silicon-germanium layer 240 disposed above the top surface of patterned layer 225, thereby forming dielectric pads 260A, 260B, 260C, 260D, and silicon-germanium spacer 240'. The CMP process can planarize the top surface of dielectric capping layer 266, the topmost surface of dielectric pads 262A-262D, the topmost surface of dielectric pads 260A-260D, the top surface of silicon-germanium spacer 240', and the top surface of patterned layer 225, thereby making these surfaces substantially coplanar after the CMP process. In some embodiments, the dielectric coating material is formed by ALD, CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, APCVD, SAVCD, other suitable deposition processes, or combinations thereof.

[0031] After forming the dielectric capping layer 266, gate isolation fins 270A and silicon-germanium spacers 240' are combined to fill the upper portion of trench 230A, gate isolation fins 270B and silicon-germanium spacers 240' are combined to fill the upper portion of trench 230B, gate isolation fins 270C and silicon-germanium spacers 240' are combined to fill the upper portion of trench 230C, and gate isolation fins 270D and silicon-germanium spacers 240' are combined to fill the upper portion of trench 230D. Because the width of trench 230A (i.e., the spacing D1 between fins 222A and fins 222B) is greater than the width of trenches 230B-230D (i.e., the spacing D2 between fins 222B-222E), gate isolation fins 270A are different from gate isolation fins 270B-270D. For example, gate isolation fin 270A includes four dielectric layers (i.e., dielectric pad 260A, dielectric pad 262A, oxide layer 264A and dielectric capping layer 266), while each of gate isolation fins 270B-270D includes two dielectric layers (i.e., dielectric pads 260B-260D and dielectric pads 262B-262D, respectively, but excluding oxide layers or dielectric capping layers).

[0032] Transfer to Figure 9 An etching process is performed to remove the patterned layer 225 from the portion of the fins 222A-222E and the silicon-germanium sacrificial spacer 240' that is disposed along the sidewall of the patterned layer 225, thereby forming an opening 275 in the semiconductor layer stack 210 exposing the fins 222A-222E between the gate isolation fins 270A-270D. Figure 9In this process, the top surfaces of the gate isolation fins 270A-270D are higher than the top surfaces of the fins 222A-222E relative to the top surface of the substrate 202. The etching process is configured to selectively remove the patterned layer 225 and the silicon-germanium sacrificial spacer 240' relative to the semiconductor layer 220 of the gate isolation fins 270A-270D and fins 222A-222E. In other words, the etching process substantially removes the portion of the patterned layer 225 and the silicon-germanium sacrificial spacer 240' disposed along the sidewall of the patterned layer 225, but does not remove or substantially does not remove the gate isolation fins 270A-270D and the semiconductor layer 220. For example, an etchant is selected for the etching process that etches at a higher rate than materials containing metals and oxygen (i.e., dielectric pads 260A-260D, such as high-k dielectric layers), dielectric materials containing silicon and carbon (which may also include nitrogen and / or oxygen) (i.e., dielectric pads 262A-262D and / or dielectric capping layer 266), and silicon (i.e., semiconductor layer 220) etch materials containing silicon and nitrogen (i.e., patterned layer 225, such as silicon nitride layer) and silicon-germanium (i.e., silicon-germanium sacrificial spacer 240') (i.e., the etchant has high etch selectivity relative to silicon nitride and silicon-germanium). The etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the patterned layer 225 and a second etching step selectively etching the silicon-germanium sacrificial spacer 240' (e.g., the first and second etching steps use different etchants).

[0033] Transfer to Figures 10A to 10D A dummy gate stack 280 is formed above portions of fins 222A-222E and dielectric fins 270A-270D. For ease of description and understanding, Figure 10D It was after the interaction with Figures 2 to 9 and Figures 10A to 10D A top view of the multi-gate device 200 after relevant processing; Figure 10A It is along Figure 10D The cross-sectional view of line GG in the diagram (which can also be called the cross-sectional view of metal gate cutting); Figure 10B It is along Figure 10D The cross-sectional view of the line SD-SD (which can also be called the source / drain cut cross-sectional view); and Figure 10C It is along Figure 10D A cross-sectional view of the FF line (which can also be called a fin-cut cross-sectional view). In Figures 10A to 10DIn the multi-gate device 200, the dummy gate stack 280 fills the opening 275. The dummy gate stack 280 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fins 222A-222E. For example, the dummy gate stack 280 extends substantially parallel to each other in the y-direction, having a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. The dummy gate stack 280 is disposed above the channel region (C) of the multi-gate device 200 and between the source / drain regions (S / D) of the multi-gate device 200. In the XZ plane, the dummy gate stack 280 is disposed on the top surface of the fins 222A-222E (particularly the top surface of the semiconductor layer stack 210), the top of the gate isolation fins 270A-270D, and the sidewalls of the gate isolation fins 270A-270D, such that the dummy gate stack 280 wraps around the top of the gate isolation fins 270A-270D in the channel region of the multi-gate device 200. In the YZ plane, dummy gate stacks 280 are disposed above the top surfaces of the corresponding channel regions of fins 222A-222E, such that the dummy gate stacks 280 are positioned between the corresponding source / drain regions of fins 222A-222E. Each dummy gate stack 280 includes a dummy gate dielectric 282, a dummy gate electrode 284, and a hard mask 286 (including, for example, a first mask layer 287 and a second mask layer 288). The dummy gate dielectric 282 includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the dummy gate dielectric 282 includes an interface layer (including, for example, silicon oxide) and a high-k dielectric layer disposed above the interface layer. The dummy gate electrode 284 includes a suitable dummy gate material, such as polysilicon, and the hard mask 286 (including the first mask layer 287 and the second mask layer 288) includes any suitable hard mask material. In some embodiments, the dummy gate stack 280 includes a plurality of other layers, such as capping layers, interface layers, diffusion layers, barrier layers, or combinations thereof. The dummy gate stack 280 is formed by deposition processes, photolithography processes, etching processes, other suitable processes, or combinations thereof. For example, a first deposition process is performed to form a dummy gate dielectric layer over the multi-gate device 200, a second deposition process is performed to form a dummy gate electrode layer over the dummy gate dielectric layer, and a third deposition process is performed to form a hard mask layer over the dummy gate electrode layer. Deposition processes include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. Photolithographic patterning and etching processes are then performed to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer to form the dummy gate stack 280, which includes a dummy gate dielectric 282, a dummy gate electrode 284, and a hard mask 286, as shown below. Figures 10A to 10DThe process described includes photolithography patterning processes such as resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, resist development, rinsing, drying (e.g., hard baking), other suitable photolithography processes, or combinations thereof. Etching processes include dry etching, wet etching, other etching processes, or combinations thereof.

[0034] Transfer to Figures 11A to 11D Gate spacers 289 are formed along the sidewalls of the dummy gate stack 280, thereby forming a gate structure 290 (collectively referred to as the dummy gate stack 280 and the gate spacers 289). At least partially, portions of the fins 222A-222E in the source / drain regions of the multi-gate device 200 (i.e., the source / drain regions of fins 222A-222E not covered by the gate structure 290) are also removed to form source / drain recesses (trenches) 295. For ease of description and understanding, Figure 11D It was after the interaction with Figures 2 to 9 , Figures 10A to 10D and Figures 11A to 11D A top view of the multi-gate device 200 after relevant processing; Figure 11A It is along Figure 11D GG cross-sectional diagram in the middle; Figure 11B It is along Figure 11D Source / drain cut cross-sectional view of the line SD-SD; and Figure 11C It is along Figure 11D The fin section of line FF is shown. Furthermore, for the purposes of the following discussion and for ease of description and understanding, Figures 12A to 26A It is along Figure 11D A cross-sectional view of the metal gate cut of the multi-gate device 200 during the processing of line GG cut (e.g., through a cut in gate structure 290); Figures 12B to 26B It is along Figure 11D A source / drain cut cross-sectional view of the multi-gate device 200 during the processing of line SD-SD (e.g., by cutting through the source / drain regions disposed between gate structures 290); Figures 12C to 26C It is along Figure 11D A fin-cut cross-sectional view of the multi-gate device 200 during the processing of the line FF (e.g., truncated by fin 222A); Figure 12D , Figure 13D and Figures 18D to 26D It is along Figure 11D A cross-sectional view of the gate spacer cut in the multi-gate device 200 during the processing of the line SS (e.g., cut by gate spacer 289 in one of the gate structures 290); and Figure 20E Is with Figures 20A to 20E A top view of the multi-gate device 200 during the relevant processing.

[0035] exist Figures 11A to 11DIn this process, relative to the unexposed portions of the gate isolation fins 270A-270D (e.g., the portions of the gate isolation fins 270A-270D in the channel region of the multi-gate device 200), the processing associated with forming the gate spacer 289 and / or the source / drain recess 295 reduces the height of the exposed portions of the gate isolation fins 270A-270D (e.g., the portions of the gate isolation fins 270A-270D in the source / drain region of the multi-gate device 200). For example, the gate isolation fins 270A-270D have a height h1 ( Figure 11A ), and the etching process performed to form the gate spacer 289 and / or the source / drain recess 295 intentionally or unintentionally reduces the height of the exposed portion of the gate isolation fins 270A-270D from height h1 to height h2. Figure 11B In some embodiments, height h1 is about 40 nm to about 80 nm, and height h2 is about 25 nm to about 75 nm. In some embodiments, the ratio of height h1 to height h2 is about 1.06:1 to about 1.6:1. Therefore, the portion of the gate isolation fins 270A-270D disposed in the channel region of the multi-gate device 200 below the gate structure 290 has height h1, while the portion of the gate isolation fins 270A-270D disposed in the source / drain region of the multi-gate device 200 but not disposed below the gate structure 290 has height h2. In such embodiments, the thickness of the dielectric capping layer 266 of the gate isolation fin 270A can be reduced from thickness t6 to a thickness t7 less than thickness t6 by an etching process. In some embodiments, thickness t7 is about 5 nm to about 30 nm. In some embodiments, where the multi-gate device 200 has multiple gate isolation fins with dielectric capping layers, the etching process may consume varying amounts of dielectric capping layers and produce dielectric capping layers of different thicknesses across the multi-gate device 200.

[0036] Gate spacers 289 are configured to be adjacent to (i.e., along) the sidewalls of a corresponding dummy gate stack 280. Gate spacers 289 are formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, and / or silicon carbonoxynitride). For example, a dielectric layer comprising silicon and nitrogen (such as a silicon nitride layer) is deposited and etched (e.g., anisotropic etching) over the multi-gate device 200 to form the gate spacer 289. In some embodiments, gate spacers 289 include a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one group of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the dummy gate stack 280. In such embodiments, the respective groups of spacers may include materials with different etch rates. For example, a first dielectric layer comprising silicon and oxygen (e.g., silicon oxide) is deposited and etched to form a first spacer group adjacent to the sidewalls of the dummy gate stack 280, and a second dielectric layer comprising silicon and nitrogen (e.g., silicon nitride) is deposited and etched to form a second spacer group adjacent to the first spacer group.

[0037] In the depicted embodiment, the etching process completely removes the semiconductor layer stack 210 in the source / drain region of the multi-gate device 200, thereby exposing the fin portion 202' in the source / drain region of the multi-gate device 200. The etching process also completely removes the portion of the silicon-germanium sacrificial layer 240 disposed along the sidewalls of the semiconductor layer stack 210 in the source / drain region of the multi-gate device 200. Thus, each source / drain recess 295 has a first sidewall defined by one of the gate isolation fins 270A-270D (or other gate isolation fins), a second sidewall defined by one of the gate isolation fins 270A-270D (or other gate isolation fins), and a third sidewall defined by the remaining portion of the semiconductor layer stack 210 disposed under the gate structure 290 and the remaining portion of the silicon-germanium sacrificial layer 240 disposed under the gate structure 290. Each source / drain recess 295 also has a bottom defined by the corresponding fin portion 202' and the corresponding isolation member 235. In some embodiments, the etching process removes some, but not all, of the semiconductor layer stack 210, such that the source / drain recess 295 has a bottom defined by the respective semiconductor layer 215 or semiconductor layer 220. In some embodiments, the etching process also removes some, but not all, of the fin portions 202', such that the source / drain recess 295 extends below the top surface of the isolation member 235. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may use etchants alternately to remove semiconductor layer 215, semiconductor layer 220, and / or silicon-germanium layer 240, respectively and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor layer stack 210 while minimally (or not at all) etching the gate structure 290 (i.e., the dummy gate stack 280 and gate spacer 289), gate isolation fins 270A-270D, and / or isolation member 235. In some embodiments, photolithography processes (such as those described herein) are performed to form a patterned mask layer covering the gate structure 290 and / or the gate isolation fins 270A-270D, and an etching process uses the patterned mask layer as an etching mask. In such embodiments, the height of the gate isolation fins 270A-270D is not reduced in the source / drain region of the multi-gate device 200, such that after the formation of the gate spacer 289 and the source / drain recess 295, the gate isolation fins 270A-270D have a height h1 in both the channel region and the source / drain region of the multi-gate device 200.

[0038] Transfer to Figures 12A to 12D and Figures 13A to 13DInternal spacers 300A and 300B are formed below the gate structure 290 along the sidewalls of semiconductor layers 220 and 215 beneath the dummy gate stack 280. Below the gate spacer 289, internal spacer 300A separates the semiconductor layers 220 from each other and separates the bottommost semiconductor layer 220 from the fin portion 202', while internal spacer 300B separates the sidewalls of semiconductor layers 220 and 215 from the gate isolation fins 270A-270D. Figures 12A to 12D In this process, a first etching process is performed, which selectively etches the semiconductor layer 215 exposed by the source / drain trench 295, while at least (or not at all) etching the semiconductor layer 220, fin portions 202', isolation members 235, gate isolation fins 270A-270D, and gate structure 290, thereby forming gaps 300A' between the semiconductor layers 220 and between the fin portions 202' and the semiconductor layers 220. The first etching process also selectively etches the silicon-germanium sacrificial spacer 240' exposed by the source / drain trench 295, thereby forming gaps 300B' between the semiconductor layers 220 and the gate isolation fins 270A-270D. Gap 300A' and gap 300B' are disposed below the gate spacer 289. Thus, the semiconductor layers 220 are suspended below the gate spacer 289, separated from each other by gap 300A', and separated from the gate isolation fins 270A-270D by gap 300B'. In some embodiments, gaps 300A' and / or gaps 300B' extend at least partially beneath the dummy gate stack 280. A first etching process is configured to laterally etch the semiconductor layer 215 and the silicon-germanium spacer 240' (e.g., along the x-direction and / or y-direction). In the depicted embodiment, the first etching process reduces the length of the semiconductor layer 215 and the silicon-germanium spacer 240' along the x-direction. The first etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof.

[0039] exist Figures 13A to 13DIn the process, a deposition process is then performed to form a spacer layer over the gate structure 290 and over the components defining the source / drain recess 295 (e.g., semiconductor layer 215, semiconductor layer 220, fin portion 202', gate isolation fins 270A-270D, isolation component 235, and / or silicon-germanium spacer 240'), such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. The spacer layer partially (and in some embodiments, completely) fills the source / drain recess 295. The deposition process is configured to ensure that the spacer layer at least partially fills gaps 300A' and 300B'. A second etching process is then performed, which selectively etches the spacer layer to form the inner spacer 300A filling gap 300A' and the inner spacer 300B filling gap 300B', as shown below. Figures 13A to 13D The semiconductor layer 220, fin portion 202', isolation member 235, gate isolation fins 270A-270D, and gate structure 290 are depicted, but are etched at least (or not at all). The spacer layer (and therefore the inner spacers 300A and 300B) comprises a material different from the material of the semiconductor layer 220 and fin portion 202', the material of the isolation member 235, the material of the gate isolation fins 270A-270D, and / or the material of the gate structure 290, to achieve desired etch selectivity during the second etch process. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and / or silicon carbonitride). In some embodiments, the spacer layer comprises a low-k dielectric material, such as those described herein. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dielectric material, such that the spacer layer comprises a doped dielectric material.

[0040] Transfer to Figures 14A to 14CAn epitaxial source / drain component is formed in the source / drain recess 295. For example, semiconductor material is epitaxially grown from the fin portion 202' exposed by the source / drain recess 295 and the semiconductor layer 220 to form the epitaxial source / drain component 310. In some embodiments, because the semiconductor material does not grow from the dielectric surface during the epitaxial growth process used to form the epitaxial source / drain component 310, an air gap 312 can be formed between the epitaxial source / drain component 310, the gate isolation fins 270A-270D, and the isolation component 235. In some embodiments, as depicted, the epitaxial source / drain component 310 does not completely fill the source / drain recess 295 in the YZ plane, such that the top surface of the epitaxial source / drain component 310 is lower than the top surface of the gate isolation fins 270A-270D relative to the top surface of the substrate 202. In some embodiments, the epitaxial source / drain component 310 completely fills the source / drain recess 295 in the YZ plane, such that the top surface of the epitaxial source / drain component 310 is substantially coplanar with the top surface of the gate isolation fins 270A-270D, or is higher than the top surface of the gate isolation fins 270A-270D relative to the top surface of the substrate 202. The epitaxial process can use CVD deposition techniques (e.g., LPCVD, VPE, and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process can use gaseous and / or liquid precursors that interact with the composition of the fin portion 202' and / or the semiconductor layer 220. The epitaxial source / drain component 310 is doped with n-type dopant and / or p-type dopant. In some embodiments, for an n-type transistor, the epitaxial source / drain component 310 comprises silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for a p-type transistor, the epitaxial source / drain component 310 comprises silicon germanium or germanium, which may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component). In some embodiments, the epitaxial source / drain component 310 comprises more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may comprise the same or different materials and / or dopant concentrations. In some embodiments, the epitaxial source / drain component 310 includes materials and / or dopants that achieve desired tensile and / or compressive stresses in the respective channel regions of the n-type transistor and / or p-type transistor. In some embodiments, during deposition, the epitaxial source / drain component 310 is doped by adding impurities to the source material of the epitaxial process (i.e., in situ). In some embodiments, after the deposition process, the epitaxial source / drain component 310 is doped by an ion implantation process.In some embodiments, an annealing process (e.g., rapid thermal annealing and / or laser annealing) is performed to activate the dopants in the epitaxial source / drain components 310 and / or other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain (LDD) regions). The present invention considers each of the epitaxial source / drain components 310 to be configured according to the transistor region of the multi-gate device 200 corresponding to the respective epitaxial component 310, such that the epitaxial source / drain components can have the same material and / or different materials. For example, the epitaxial source / drain component 310 corresponding to an n-type transistor region may include silicon and an n-type dopant (e.g., phosphorus and / or carbon), while the epitaxial source / drain component corresponding to a p-type transistor region may include silicon, germanium, and a p-type dopant (e.g., boron).

[0041] Transfer to Figures 15A to 15CA contact etch stop layer (CESL) 320 is formed over the multi-gate device 200, an interlayer dielectric (ILD) layer 322 is formed over the CESL 320, and an ILD guard layer 324 is formed over the ILD layer 322. CMP and / or other planarization processes are then performed until the top (or top surface) of the dummy gate stack 280 is reached (exposed). The CESL 320 and ILD layer 322 are disposed over the epitaxial source / drain components 310 and gate isolation fins 270A-270D in the source / drain regions of the multi-gate device 200, and in the depicted embodiment, the CESL 320 and ILD layer 322 fill the remaining portion of the source / drain recess 295. The CESL 320, ILD layer 322, and ILD guard layer 324 are disposed between adjacent gate structures 290. In some embodiments, the CESL 320 and / or ILD layer 322 are disposed on and physically contact the facets of the epitaxial source / drain component 310, which extend from the gate isolation fins 270A-270D to the top surface (facet) of the epitaxial source / drain component 310, while the facets of the epitaxial source / drain component 310 extending from the gate isolation fins 270A-270D to the bottom surface (facet) of the epitaxial source / drain component 310 (i.e., the surface disposed on the fin portion 202') do not physically contact any dielectric material due to the air gap 312. The CESL 320, ILD layer 322, and ILD protective layer 324 are formed by CVD, PVD, ALD, HDPCVD, HARP, FCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In some embodiments, the ILD layer 322 is formed by FCVD, HARP, HDPCVD, or a combination thereof. In some embodiments, a planarization process removes the hard mask 286 of the dummy gate stack 280 to expose the underlying dummy gate electrode 284, such as a polysilicon gate electrode. The ILD layer 322 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, etc. (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 322 comprises a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, ILD layer 322 comprises a dielectric material having a dielectric constant less than about 2.5 (i.e., very low k (ELK) dielectric material), such as SiO2 (e.g., porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxides (e.g., SiCOH-based materials (having, for example, Si-CH3 bonds)), each of which is tuned / configured to exhibit a dielectric constant less than 2.5. ILD layer 322 may comprise a multilayer structure having a variety of dielectric materials. CESL 320 includes a material different from that of ILD layer 322, such as a dielectric material different from that of ILD layer 322. For example, where ILD layer 322 includes a dielectric material comprising silicon and oxygen and having a dielectric constant less than that of silicon dioxide, CESL 320 may include silicon and nitrogen, such as silicon nitride or silicon oxynitride. ILD guard layer 324 includes a material different from that of ILD layer 322, and this material provides the etch selectivity and / or planarization selectivity required for fabricating the multi-gate device 200 as described herein. In the depicted embodiments, ILD guard layer 324 includes a silicon and nitrogen-containing material, such as silicon nitride or silicon carbonitride. In some embodiments, ILD guard layer 324 includes silicon, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonate, other suitable materials, or combinations thereof.

[0042] Then, a gate replacement process is performed to replace the dummy gate stack 280 with a metal gate stack. During the gate replacement process, a channel release process is performed to form a floating channel layer in the channel region of the multi-gate device 200, wherein the metal gate stack at least partially surrounds the floating channel layer. For example, turn to Figures 16A to 16CBy removing the dummy gate stack 280 to form a gate opening 330 in the gate structure 290, the semiconductor layer stack 210 of the fins 222A-222E in the channel region of the multi-gate device 200 and the silicon-germanium spacer 240' disposed along the sidewalls of the semiconductor layer stack 210 of the fins 222A-222E in the channel region of the multi-gate device 200 are exposed. For example, an etching process is performed to remove the hard mask 286, the dummy gate electrode 284, and the dummy gate dielectric 282. The etching process is configured to selectively remove the hard mask 286, the dummy gate electrode 284, and / or the dummy gate dielectric 282 relative to the ILD protective layer 324, the gate spacer 289, the silicon-germanium spacer 240', and / or the semiconductor layer 220. In other words, the etching process substantially removes the hard mask 286, the dummy gate electrode 284, and the dummy gate dielectric 282, but does not remove or substantially does not remove the ILD protective layer 324, the gate spacer 289, the silicon-germanium spacer 240', and / or the semiconductor layer 220. The etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the hard mask 286, a second etching step selectively etching the dummy gate electrode 284, and a third etching step selectively etching the dummy gate dielectric 282 (e.g., the first, second, and third etching steps employ different etchants). In some embodiments, the etching process uses a patterned mask layer as the etching mask, wherein the patterned mask layer covers the ILD protective layer 324 and / or the gate spacer 289, but has openings therein exposing the dummy gate stack 280.

[0043] After removing the dummy gate stack 280, the semiconductor layer 215 exposed by the gate opening 330 of the semiconductor layer stack 210 is selectively removed from the channel region of the multi-gate device 200, thereby forming suspended semiconductor layers 220' and / or fin portions 202' spaced apart from each other by gaps 335A. The silicon-germanium sacrificial spacer 240' is also selectively removed from the channel region of the multi-gate device 200, thereby forming a gap 335B between the suspended semiconductor layers 220' and the gate isolation fins 270A-270D. Therefore, each transistor region of the multi-gate device 200 has at least one suspended semiconductor layer 220'. For example, each transistor region of the multi-gate device 200 includes three suspended semiconductor layers 220' stacked vertically along the z-direction to provide three channels through which current can flow between the corresponding epitaxial source / drain portions 310 during operation of the transistor corresponding to the transistor region. Therefore, the suspended semiconductor layer 220' is hereinafter referred to as channel layer 220', and the process used to form channel layer 220' can be referred to as channel release process. In the depicted embodiment, the top surface of the topmost channel layer 220' is lower than the top surface of the gate isolation fins 270A-270D relative to the top surface of the substrate 202 (i.e., the channel height of the transistor of the multi-gate device 200 is less than the height of the gate isolation fins 270A-270D). For example, the height difference Δh between the top surface of the topmost channel layer 220' and the top surface of the gate isolation fins 270A-270D is about 5 nm to about 25 nm. A spacing s1 is defined between the channel layers 220' along the z-direction, and a spacing s2 is defined between the channel layers 220' and the gate isolation fins 270A-270D along the y-direction. Spacing s1 and spacing s2 correspond to the widths of gaps 335A and 335B, respectively. In some embodiments, the spacing s1 is approximately equal to the thickness t1 of the semiconductor layer 215, and the spacing s2 is approximately equal to the thickness of the silicon-germanium sacrificial spacer 240'. However, embodiments in which the spacing s1 is greater than or less than the thickness t1 and the spacing s2 is greater than or less than the thickness of the silicon-germanium spacer 240' are considered. In some embodiments, the spacing s1 is approximately 8 nm to approximately 15 nm. In some embodiments, the spacing s2 is approximately 8 nm to approximately 15 nm. In some embodiments, each channel layer 220' has nanoscale dimensions and may be individually or collectively referred to as a "nanostructure". For example, each channel layer 220' may have a width of approximately 8 nm to approximately 100 nm along the x-direction, a length of approximately 8 nm to approximately 100 nm along the y-direction, and a thickness of approximately 3 nm to approximately 10 nm along the z-direction. In some embodiments, the channel layer 220' has subnanometer dimensions.The channel layer 220' may have a profile with a cylindrical profile (e.g., nanowires), a rectangular profile (e.g., nanorods), a sheet profile (e.g., nanosheets (e.g., dimensions in the XY plane are larger than dimensions in the XZ and YZ planes to form a sheet-like structure)) or any other suitable shape.

[0044] In some embodiments, an etching process is performed to selectively etch semiconductor layer 215 and silicon-germanium sacrificial spacer 240', while at least (or not at all) etching semiconductor layer 220, fin portion 202', isolation member 235, gate isolation fins 270A-270D, gate spacer 289, internal spacer 300A, internal spacer 300B, and / or ILD protective layer 324. In some embodiments, an etchant is selected for the etching process that etches silicon-germanium (i.e., semiconductor layer 215 and silicon-germanium sacrificial spacer 240') at a higher rate than silicon (i.e., semiconductor layer 220 and fin portion 202') and dielectric material (i.e., isolation member 235, gate isolation fins 270A-270D, gate spacer 289, internal spacer 300A, internal spacer 300B, and / or ILD protective layer 324) (i.e., the etchant has high etch selectivity relative to silicon-germanium). The etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process partially, but at least partially, etches the semiconductor layer 220 and the fin portion 202'. For example, in Figures 16A to 16C In this embodiment, the etching process reduces the length of the semiconductor layer 220 along the y-direction, thereby making the length of the channel layer 220' smaller than the length of the semiconductor layer 220 before the etching process. In such an embodiment, the etching process may also reduce the width of the portion of the fin portion 202' extending above the top surface of the isolation member 235 along the y-direction, thereby making the width of a portion of the fin portion 202' (which may be referred to as the fin extension) smaller than the width of the fin portion 202'. In some embodiments, the etching process is configured to intentionally etch the semiconductor layer 220 along the y-direction to achieve a target length for the channel layer 220'. In some embodiments, an oxidation process may be performed prior to the etching process to convert the semiconductor layer 215 and / or the silicon-germanium sacrificial spacer 240' into a silicon-germanium oxide component, wherein the etching process then removes the silicon-germanium oxide component. In some embodiments, the etching process includes multiple steps, such as a first etching step configured to remove the silicon-germanium spacer 240' and a second etching step configured to remove the semiconductor layer 215. In some embodiments, after removing the semiconductor layer 215 and the silicon-germanium sacrificial spacer 240', an etching process is performed to modify the contour of the channel layer 220' to achieve the target size and / or target shape of the channel layer 220'.

[0045] exist Figures 16A to 16CIn this process, a trimming process is performed on the dielectric pads 260A-260D of the gate isolation fins 270A-270D to increase the spacing s2 between the channel layer 220' and the gate isolation fins 270A-270D. Increasing the spacing s2 between the channel layer 220' and the gate isolation fins 270A-270D will enlarge the metal gate fill window for forming a metal gate stack in the gate opening 330, as further described below. The trimming process increases the spacing s2 by reducing the thickness t4 of the dielectric pads 260A-260D along the sidewalls of the gate isolation fins 270A-270D to a thickness t8. In some embodiments, the thickness t8 is about 1 nm to about 7 nm. Therefore, the dielectric pads 260A-260D have different thicknesses along the sidewalls (e.g., thickness t8, less than thickness t4) and the bottom (e.g., thickness t4) of the gate isolation fins 270A-270D in the channel region of the multi-gate device 200, but have substantially the same thickness (e.g., thickness t4) along the sidewalls and bottom of the gate isolation fins 270A-270D. Furthermore, after the trimming process, the gate isolation fins 270A-270D in the channel region are smaller than the width of the gate isolation fins 270A-270D in the source / drain region. For example, gate isolation fin 270A separates the active region by a spacing (width) D3 in the source / drain region and a spacing (width) D4 in the channel region, and gate isolation fins 270B to 270D separate the active region by a spacing (width) D5 in the source / drain region and a spacing (width) D6 in the channel region. Spacing D4 is smaller than spacing D3, spacing D6 is smaller than spacing D5, spacing D3 is smaller than spacing D1, and spacing D5 is smaller than spacing D2. In some embodiments, spacing (width) D5 is greater than about 15 nm. In some embodiments, spacing (width) D6 is from about 5 nm to about 20 nm. In some embodiments, the ratio of spacing (width) D5 to spacing (width) D6 (D5 / D6) is from about 3 to about 20.

[0046] The trimming process is an etching process that selectively etches dielectric pads 260A-260D, while at least (or not at all) etching dielectric pads 262A-262D, dielectric capping layer 266, channel layer 220', fin portion 202', isolation structure 235, gate spacer 289, internal spacer 300A, internal spacer 300B, and / or ILD protective layer 324. In other words, the trimming process substantially removes dielectric pads 260A-260D, but does not remove or substantially does not remove dielectric pads 262A-262D, dielectric capping layer 266, channel layer 220', fin portion 202', isolation component 235, gate spacer 289, internal spacer 300A, internal spacer 300B, and / or ILD protective layer 324. For example, an etchant is selected for the trimming process that etches a high-k dielectric material (i.e., dielectric pads 260A-260D) at a higher rate than silicon (i.e., channel layer 220' and fin portion 202') and other dielectric materials (i.e., dielectric pads 262A-262D, dielectric capping layer 266, isolation member 235, gate spacer 289, internal spacer 300A, internal spacer 300B, and / or ILD protective layer 324) (i.e., the etchant has high etch selectivity relative to the high-k dielectric material). The etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process is configured to etch substantially along the y-direction to reduce the thickness of dielectric pads 260A-260D along the y-direction. In some embodiments, the etching process is a plasma etching process.

[0047] Transfer to Figures 17A to 17CA metal gate stack 340 (also referred to as a metal gate and / or a high-k metal gate) filling the gate opening 330 is formed over the multi-gate device 200. The metal gate stack 340 includes a gate dielectric 342 (e.g., a gate dielectric layer) and a gate electrode 344 (e.g., a power function layer and a bulk metal layer). The metal gate stack 340 may include a number of other layers. In some embodiments, forming the metal gate stack 340 includes: depositing a gate dielectric layer partially filling the gate opening 330 over the multi-gate device 200; depositing a gate electrode layer filling the remaining portion of the gate opening 330 over the gate dielectric layer; and performing a planarization process on the gate electrode layer to form the metal gate stack 340 having the gate dielectric 342 and the gate electrode 344. The gate dielectric 342 and the gate electrode 344 extend uninterruptedly along the y-direction. The metal gate stack 340 is configured to achieve the desired functionality according to the design requirements of the multi-gate device 200. Because the metal gate stack 340 can span different transistor regions of the multi-gate device 200, the metal gate stack 340 can have different layers in different transistor regions. For example, the number, configuration, and / or material of the gate dielectric 342 and / or gate electrode 344 layers corresponding to the first transistor region (e.g., an n-type transistor region) of the multi-gate device 200 can differ from the number, configuration, and / or material of the gate dielectric 342 and / or gate electrode 344 layers corresponding to the second transistor region (e.g., a p-type transistor region) of the multi-gate device 200.

[0048] Gate dielectric 342 partially fills gate opening 330 and wraps around the corresponding channel layer 220', thereby partially filling gaps 335A and 335B. In the depicted embodiment, gate dielectric 342 covers the exposed surface of channel layer 220', thereby distributing gate dielectric 342 along the top, bottom, and sidewalls of channel layer 220'. For example, gate dielectric 342 surrounds channel layer 220', such that each channel layer 220' is wrapped and / or surrounded by a corresponding gate dielectric (i.e., a portion of gate dielectric 342). In some embodiments, gate dielectric 342 is also disposed over fin portions 202', isolation members 235, and gate isolation fins 270A-270D in the channel region. In the depicted embodiment, gate dielectric 342 extends uninterruptedly between transistor regions of multi-gate device 200. The gate dielectric 342 includes a high-k dielectric layer comprising a high-k dielectric material. For the purposes of the metal gate stack 340, the high-k dielectric layer refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k≈3.9). For example, the high-k dielectric layer includes HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials for metal gate stacks, or combinations thereof. The high-k dielectric layer is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. For example, an ALD process deposits the high-k dielectric layer. In some embodiments, the ALD process is a conformal deposition process, such that the thickness of the high-k dielectric layer is substantially uniform (conformal) above the respective surfaces of the multi-gate device 200. In some embodiments, the gate dielectric 342 includes an interface layer disposed between the high-k dielectric layer and the channel layer 220'. The interface layer comprises a dielectric material, such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The interface layer is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. For example, the interface layer is formed by a chemical oxidation process that exposes the exposed surface of the channel layer 220' to hydrofluoric acid. In some embodiments, the interface layer is formed by a thermal oxidation process that exposes the exposed surface of the channel layer 220' to an oxygen and / or air environment. In some embodiments, the interface layer is formed after the formation of a high-k dielectric layer. For example, in some embodiments, after the formation of the high-k dielectric layer, the multi-gate device 200 may be annealed in an oxygen and / or nitrogen environment (e.g., nitrous oxide).

[0049] A gate electrode 344 is formed above the gate dielectric 342, filling the remaining portion of the gate opening 330 and enclosing the corresponding channel layer 220', thereby filling the remaining portions of gaps 335A and 335B. Because the trimming process increases the spacing S2 (and thus the lateral spacing between the channel layer 220' and the gate isolation fins 270A-270D), the gate electrode 344 can better fill the gap 335B from top to bottom. For example, when the spacing S2 is too small, the gate electrode 344 may fill the portion of the gap 335B between the channel layer 220' and the gate isolation fins 270A-270D before filling the portion between the gap 335A and the gate isolation fins 270A-270D. This can create voids in the gate electrode 344 and / or some layers of the gate electrode 344 that do not surround the channel layer 220', both of which degrade transistor performance. By increasing the spacing S2 using a trimming process, the filling of gap 335B is more uniform from top to bottom, thereby preventing voids from forming within the gate electrode 344 and ensuring that the various layers of the gate electrode 344 properly wrap around and / or surround the channel layer 220' as needed. In the depicted embodiment, the gate electrode 344 is disposed along the top, bottom, and sidewalls of the channel layer 220', such that the gate electrode 344 surrounds the channel layer 220'. The gate electrode 344 is also disposed above the fin portion 202', the isolation member 235, and the gate isolation fins 270A-270D in the channel region. The gate electrode 344 comprises a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the gate electrode 344 comprises a work function layer and a bulk conductive layer. The work function layer is a conductive layer tuned to have a desired work function (e.g., n-type or p-type work function), and the bulk conductive layer is a conductive layer formed on top of the work function layer. In some embodiments, the work function layer comprises an n-type work function material, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer comprises a p-type work function material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or filled) conductive layer comprises a suitable conductive material, such as Al, W, Ti, Ta, polycrystalline silicon, Cu, metal alloys, other suitable materials, or combinations thereof. The gate electrode 344 is formed by any of the processes described herein, such as ALD, CVD, PVD, plating, other suitable processes, or combinations thereof.

[0050] Transfer to Figures 18A to 18DA self-aligned metal gate dicing process is implemented to remove a portion of the metal gate stack 340 to form the metal gates of the multi-gate device 200, such as metal gates 340A, 340B, 340C, 340D, 340E, and 340F. The metal gate dicing process is called "self-aligned" because the gate isolation fins 270A-270D are aligned between the metal gates 340A-340E without requiring a photolithography process after the metal gate stack 340 is formed. For example, an etch-back (recessed) process removes the portion of the gate electrode 344 disposed above the top surface of the gate isolation fins 270A-270D, thereby forming gate electrodes 344A, 344B, 344C, 344D, 344E, and 344F. The etch-back process also removes the portion of the gate dielectric 342 disposed above the ILD protective layer 324, but does not remove the portion of the gate dielectric 342 from above the top surface of the gate isolation fins 270A-270D. Therefore, after the etch-back process, the gate electrode 344 no longer extends continuously along the y-direction, while the gate dielectric 342 continues to extend continuously along the y-direction, and the metal gates 340A-340F include corresponding portions of the gate dielectric 342 and corresponding one of the gate electrodes 344A-344F. (In the metal gate cut view...) Figure 18A In the fin cut view, gate isolation fins 270A-270D separate adjacent metal gates of the multi-gate device 200. For example, gate isolation fin 270A separates and isolates metal gate 340A from metal gate 340B, gate isolation fin 270B separates and isolates metal gate 340B from metal gate 340C, gate isolation fin 270C separates and isolates metal gate 340C from metal gate 340D, and gate isolation fin 270D separates and isolates metal gate 340D from metal gate 340E. (In the fin cut view...) Figure 18CILD layers 322 and CESL 322 separate adjacent metal gates of the multi-gate device 200. For example, ILD layers 322 and CESL 320 separate and isolate metal gate 340A from metal gate 340F. In some embodiments, an etch-back process may slightly etch the gate dielectric 342 over the top surface of the gate isolation fins 270A-270D. In such embodiments, the thickness of the gate dielectric 342 over the top surface of the gate isolation fins 270A-270D is less than the thickness of the gate dielectric 342 enclosing the channel layer 220' and / or the thickness of the gate dielectric 342 along the sidewalls of the gate isolation fins 270A-270D. The etch-back process also removes a portion of the gate spacer 289 (e.g., reducing the height of the gate spacer 289 along the z-direction) and forms an opening 345 having a bottom defined by the metal gates 340A-340F and a sidewall defined by the remaining portion of the CESL 320 and the gate spacer 289. In the depicted embodiment, the etch-back process removes the gate electrode 344 and the gate dielectric 342 at a rate faster than the gate spacer 289, thereby creating a top surface of the metal gates 340A-340F that is lower than the top surface of the gate spacer 289 relative to the top surface of the substrate 202. The etch-back process is configured to selectively remove the gate electrode 344 relative to the ILD protective layer 324 and CESL 320. In other words, the etch-back process substantially removes the gate electrode 344, but does not remove or substantially does not remove the ILD protective layer 324 and CESL 320. For example, an etchant is selected for the etching process that etches the metal material (e.g., the gate electrode 344) at a rate higher than that of the nitrogen-containing material (e.g., the ILD protective layer 324 and CESL 320) (i.e., the etchant has high etch selectivity relative to the metal and oxide materials). In the depicted embodiments, the etch-back process also exhibits low etch selectivity relative to the dielectric materials (e.g., gate dielectric 342 (including a high-k dielectric) and gate spacer 289 (including silicon, oxygen, and / or carbon)), resulting in some etching of the gate dielectric 342 and gate spacer 289 by the etch-back process. The etch-back process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof.

[0051] Transfer to Figures 19A to 19D , Figures 20A to 20E , Figures 21A to 21D and Figures 22A to 22D Manufacturing can continue by forming gate isolation caps over one or more of the gate isolation fins 270A-270D, depending on the design requirements of the multi-gate device 200. Figures 19A to 19DFabricating a gate isolation cap includes: depositing a hard mask layer 350 over a multi-gate device 200 to fill an opening 345; planarizing (e.g., by CMP) the hard mask layer 350; and depositing a hard mask layer 355 over the hard mask layer 350. An ILD protector layer 324 serves as a planarization (e.g., CMP) stop layer, thereby enabling planarization processes to be performed until the ILD protector layer 324 is reached and exposed. The hard mask layer 350 comprises a material different from the materials of the hard mask layer 355 and the ILD protector layer 324 to achieve etch selectivity and / or planarization (polishing) selectivity. In the depicted embodiments, the hard mask layer 350 is an amorphous silicon layer or a spin-coated carbon (SOC) layer, and the hard mask layer 355 is a silicon nitride layer. The present invention contemplates hard mask layers 350 and 355 comprising any other materials that can provide the etch selectivity and / or planarization selectivity required to form a gate isolation cap as described herein. Hard mask layer 350 and / or hard mask layer 355 can be formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods (e.g., spin coating) or combinations thereof.

[0052] exist Figures 20A to 20E In the process, a patterning process is implemented to form gate isolation cap openings, such as gate isolation cap opening 360A and gate isolation cap opening 360B, in hard mask layers 355 and 350 (hereinafter referred to as patterned hard mask layer 355' and patterned hard mask layer 350'). (See metal gate cut view.) Figure 20A In the gate isolation cap opening 360A and gate isolation cap opening 360B, the gate isolation cap openings 360A and 360B further extend through the gate dielectric 342 to expose the gate isolation fins 270A and 270C in the channel region of the multi-gate device 200, respectively, so that the gate dielectric 342 no longer extends uninterruptedly along the y-direction. For example, the gate isolation cap openings (e.g., gate isolation cap openings 360A, 360B) divide the gate dielectric 342 into gate dielectrics 342A, 342B, 342C, and 342D. In the gate spacer cut view ( Figure 20DIn the multi-gate device 200, gate isolation cap openings 360A and 360B extend through the gate spacer 289 to expose gate isolation fins 270A and 270C, respectively. Gate isolation cap openings 360A and 360B define the location and size of the gate isolation caps to be formed for the multi-gate device 200, such as the metal gates of the multi-gate device 200, which will electrically separate and isolate regions from each other, such as the metal gates of different transistors. In some embodiments, patterned hard mask layers 355' and 350' define self-aligned contact (SAC) regions of the multi-gate device 200, where metal overlays and / or dielectric overlays may be formed, as described below. In some embodiments, patterned hard mask layers 355' and 350' define metal gate connection regions of the multi-gate device 200, such as metal connection regions 362A and 362B. As further described below, in metal connection regions 362A and 362B, metal overlays are formed to physically and electrically connect adjacent metal gates, such as the gate electrode 344B of metal gate 340B to the gate electrode 344C of metal gate 340C in metal connection region 362A, and the gate electrode 344D of metal gate 340D to the gate electrode 344E of metal gate 340E in metal connection region 362B.

[0053] Patterning processes include photolithography and / or etching processes. Photolithography may include: forming a resist layer over a hard mask layer 355 (e.g., by spin coating); performing a pre-exposure baking process; performing an exposure process using a mask; performing a post-exposure baking process; and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as UV, DUV, or EUV light), where the mask blocks, transmits, and / or reflects radiation to the resist layer, depending on the mask pattern and / or mask type (e.g., a binary mask, phase-shift mask, or EUV mask), thereby projecting an image onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiant energy, the exposed portions of the resist layer undergo chemical changes, and the exposed (or unexposed) portions of the resist layer dissolve during the development process, depending on the properties of the resist layer and the properties of the developer used in the development process. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses a patterned resist layer as an etching mask to remove exposed portions of the underlying layers (here, hard mask layer 355 and / or hard mask layer 350). In some embodiments, a first etching process uses a patterned resist layer as an etching mask to remove exposed portions of hard mask layer 355 to form a patterned hard mask layer 355', and a second etching process uses a patterned hard mask layer 355' and / or a patterned resist layer as an etching mask to remove exposed portions of hard mask layer 350 to form a patterned hard mask layer 350'. In some embodiments, the second etching process also removes portions of the gate dielectric 342 and / or the gate spacer 289 located beneath the exposed portions of hard mask layer 350. In some embodiments, a third etching process uses patterned hard mask layer 350', patterned hard mask layer 355', and / or a patterned resist layer as etching masks to remove exposed portions of the gate dielectric 342 and / or the gate spacer 289. Etching processes may include dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, a patterned resist layer is removed by a first etching process, a second etching process, and / or a third etching process. In some embodiments, the patterned resist layer is removed, for example, by a resist stripping process, after the first etching process, the second etching process, and / or the third etching process.

[0054] exist Figures 21A to 21DIn this process, deposition and planarization processes are performed to form gate isolation caps 365A and 365B, which may also be referred to as gate isolation plugs or gate isolation layers. Gate isolation cap 365A is disposed on and physically contacts gate isolation fin 270A, and gate isolation cap 365B is disposed on and physically contacts gate isolation fin 270B. Gate isolation cap 365A separates the metal gate region (and / or SAC region) by a gap (width) D7. In the depicted embodiment, because the gap D7 is smaller than the gap (width) D4 of gate isolation fin 270A, gate isolation cap 365A is disposed between a portion of gate dielectric 342A and a portion of gate dielectric 342B, with the portions of gate dielectric 342A and 342B disposed above the top surface of gate isolation fin 270A. In some embodiments, the gap (width) D7 is approximately 5 nm to approximately 20 nm. A gate isolation cap 365B separates the metal gate region (and / or SAC region) by a gap (width) D8. In the depicted embodiment, because the gap D8 is substantially the same as the gap (width) D6 of the gate isolation fin 270C, the gate isolation cap 365B is disposed between a portion of the gate dielectric 342B disposed along the first sidewall of the gate isolation fin 270C and a portion of the gate dielectric 342C disposed along the second sidewall of the gate isolation fin 270C. In some embodiments, the gap (width) D8 is from about 5 nm to about 20 nm. In some embodiments, the gap D8 is smaller than the gap D6, such that the gate isolation cap 365B is disposed between a portion of the gate dielectric 342B and a portion of the gate dielectric 342C, which are disposed above the top surface of the gate isolation fin 270C. In some embodiments, the gap D7 is substantially the same as the gap D4. In some embodiments, a gate isolation cap material filling the gate isolation cap openings 360A, 360B is deposited over the multi-gate device 200, and a planarization process (e.g., CMP) is performed on the gate isolation cap material and the patterned hard mask layer 355' until the patterned hard mask layer 350', which serves as a planarization stop layer, is reached. In such embodiments, the planarization process completely removes the patterned hard mask layer 355'. The gate isolation cap material differs from the material of the patterned hard mask layer 350' to achieve etch selectivity during subsequent processing. In some embodiments, the gate isolation cap material comprises the same material as the patterned hard mask layer 355', such as silicon nitride. The present invention contemplates that the gate isolation cap material also differs from the material of the patterned hard mask layer 355', as long as the gate isolation cap material can provide the etch selectivity required for subsequent removal of the patterned hard mask layer 350'.For example, the gate isolation cap material can be silicon nitride, silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon carbon oxynitride (SiOC), silicon carbide, or other suitable materials. The gate isolation cap material can be formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods (e.g., spin coating), or combinations thereof.

[0055] exist Figures 22A to 22D In this process, for example, a patterned hard mask layer 350' is removed from the multi-gate device 200 via an etching process. The etching process is configured to selectively remove the patterned hard mask layer 350' relative to the gate isolation caps 365A, 365B, ILD protection layer 324, CESL 320, and / or gate structure 290 (i.e., gate spacers 289 and metal gate stacks 340A-340F). In other words, the etching process substantially removes the patterned hard mask layer 350', but does not remove or substantially does not remove the gate isolation caps 365A, 365B, ILD protection layer 324, CESL 320, and / or gate structure 290. For example, an etchant is selected for the etching process that etches amorphous silicon or spin-coated carbon (i.e., the gate isolation caps 365A, 365B, ILD protection layer 324 and / or CESL 320) at a higher rate than silicon and nitrogen-containing materials (i.e., gate electrodes 344A-344F) and other dielectric materials (i.e., gate dielectrics 342A-342C, gate dielectric 342 and / or gate spacer 289) (i.e., the etchant has high etch selectivity relative to amorphous silicon or spin-coated carbon). The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In the depicted embodiment, removing the patterned hard mask layer 350' defines an opening for forming a SAC capping layer that can protect the metal gates 340A-340F from damage during subsequent processing, such as implementing a self-aligned contact etching process to form gate contacts and / or source / drain contacts. For example, openings 370A, 370B, 370C, and 370D are defined for forming a SAC capping layer. Openings 370A-370D have sidewalls defined by gate isolation caps (e.g., gate isolation caps 365A and / or gate isolation caps 365B), CESL 320, and / or gate spacers 289, and a bottom defined by gate spacers 289 and / or metal gates 340A-340F. In some embodiments, as described below, one or more of the SAC capping layers may be electrically connected to the metal gates 340A-340F.

[0056] Transfer to Figures 23A to 23D , Figures 24A to 24D , Figures 25A to 25D and Figures 26A to 26D A SAC capping layer is formed in openings 370A-370D. Figures 23A to 23D In this process, fabrication continues by depositing a metal cap seed layer 375 over the multi-gate device 200, for example, by PVD. The metal cap seed layer 375 comprises a metal-containing material that facilitates the growth and / or deposition of the metal cap layer in the openings 370A-370D and promotes adhesion between the metal cap layer and the metal gates 340A-340F. The metal-containing material may include titanium, titanium alloys, tantalum, tantalum alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, molybdenum, molybdenum alloys, palladium, palladium alloys, other suitable components, or combinations thereof. For example, the metal cap seed layer 375 comprises tantalum, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, tantalum carbide, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In the depicted embodiment, the metal cap seed layer 375 is a titanium nitride layer. The metal cap seed layer 375 has a thickness less than the depth of the openings 370A-370D, such that the metal cap seed layer 375 partially fills the openings 370A-370D. In the depicted embodiment, the thickness of the metal cap seed layer 375 varies above the multi-gate device 200, such that the metal cap seed layer 375 has a thickness t9 along the bottom of the openings 370A-370D and a thickness t10 along the sidewalls of the openings 370A-370D. For example, a portion of the metal cap seed layer 375 disposed on the top surface of the metal gates 340A-340D and the top surface of the gate spacer 289 (both defining the bottom of the openings 370A-370D), the top surface of the gate isolation caps 365A and 365B, and the top surface of the ILD protective layer 324 has a thickness t9, while a portion of the metal cap seed layer 375 disposed on the sidewalls of the gate isolation caps 365A and 365B, the sidewall of the CESL 320, and the sidewall of the gate spacer 289 (all of which define the sidewalls of the openings 370A-370D) has a thickness t10. In some embodiments, the thickness t9 is from about 1 nm to about 5 nm. In some embodiments, the thickness t10 is less than or equal to about 1 nm. In some embodiments, the thickness t10 is tapered along the sidewalls of the openings 370A-370D. For example, in Figure 23CIn this process, the thickness t10 decreases along the sidewalls of the openings 370A and 370D defined by CESL 320, and also decreases along the sidewalls of the openings 370A and 370D defined by the gate spacer 289. In some embodiments, the thickness of the metal cap seed layer 375 is substantially uniform above each surface of the multi-gate device 200. In some embodiments, the metal cap seed layer 375 is formed above the multi-gate device 200 by CVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods (e.g., spin coating) or combinations thereof.

[0057] exist Figures 24A to 24D In this process, a patterning process is performed on the metal cap seed layer 375 to form metal cap seed layers 375A, 375B, 375C, and 375D in openings 370A-370D, respectively. The metal cap seed layer 375A is disposed on and physically contacts the metal gate 340A, such as the gate electrode 344A and the gate dielectric 342A. The metal cap seed layer 375B is disposed on and physically contacts the metal gates 340B and 340C, such as the gate electrode 344B, the gate electrode 344C, and the gate dielectric 342B. A metal cap seed layer 375C is disposed on and physically contacts metal gates 340D and 340E, such as gate electrode 344D, metal gate electrode 344E, and gate dielectric 342C. Metal cap seed layers 375B and 375C span metal connection regions 362A and 362B, respectively. A metal cap seed layer 375D is disposed on and physically contacts metal gate 340F, such as gate electrode 344F. The patterning process essentially removes the portion of the metal cap seed layer 375 disposed on the dielectric surface, such as gate isolation caps 365A and 365B, ILD protection layer 324, CESL 320, and gate spacer 289. The patterning process may leave a small amount of the metal cap seed layer 375 remaining along the sidewall of the gate spacer 289, thereby making the fin cut view ( Figure 24CIn this embodiment, the metal cap seed layers 375A-375D may have a U-shaped profile formed by a sidewall portion along the gate spacer 289 and a bottom portion along the metal gates 340A-340F. In some embodiments, the thickness of the sidewall portion of the metal cap seed layers 375A-375D is less than 1 nm. In some embodiments, the patterning process includes: depositing a patterned layer over the multi-gate device 200; etching back the patterned layer to expose a portion of the metal cap seed layer 375 (i.e., the thickness of the patterned layer is less than the height of the gate isolation caps 365A, 365B); etching back the exposed portion of the metal cap seed layer 375 (thus forming the metal cap seed layers 375A-375D); and removing the patterned layer. In some embodiments, the patterned layer is a bottom anti-reflective coating (BARC), such as a silicon oxide layer.

[0058] exist Figures 25A to 25D In this process, a metal cap layer is formed in the openings 370A-370D above the metal cap seed layers 375A-375D. For example, metal cap layers 380A, 380B, 380C, and 380D are deposited above the metal cap seed layers 375A-375D, respectively. The metal cap layers 380A-380D have a thickness t11 that is less than the depth of the openings 370A-370D, such that the metal cap layers 380A-380D partially fill the openings 370A-370D. In some embodiments, the thickness t11 is about 3 nm to about 10 nm. The metal cap layers 380A-380D include tungsten, tungsten alloys, ruthenium, ruthenium alloys, cobalt, cobalt alloys, copper, copper alloys, aluminum, aluminum alloys, iridium, iridium alloys, palladium, palladium alloys, platinum, platinum alloys, nickel, nickel alloys, other low resistivity metal components and / or alloys thereof or combinations thereof. A metal cap layer 380A-380D is formed in openings 370A-370D using a bottom-up deposition process. This bottom-up deposition process typically refers to a deposition process that fills the openings from bottom to top (it can also be called a bottom-up opening-filling process). In some embodiments, the bottom-up deposition process is selective CVD, wherein the parameters of the selective CVD are adjusted to selectively grow tungsten, ruthenium, cobalt, or alloys thereof from the metal cap seed layers 375A-375D, while limiting (or preventing) the growth of tungsten, ruthenium, cobalt, or alloys thereof from the gate isolation caps 365A, 365B, CESL 320, and / or ILD protective layer 324. The parameters include deposition precursors (e.g., metal precursors and / or reactants), deposition precursor flow rates, deposition temperature, deposition time, deposition pressure, other suitable deposition parameters, or combinations thereof. In the depicted embodiments, the metal cap layers 380A-380D comprise tungsten, and the various parameters of the selective CVD can be adjusted to selectively grow polycrystalline tungsten on the metal cap layers 375A-375D. In some embodiments, the selective CVD includes processing a tungsten-containing precursor (e.g., WF) x(where x represents the number of F atoms, and x≥1), WCl y (where y represents the number of Cl atoms and y≥1), other suitable tungsten-containing gases or combinations thereof, and reactant precursors (e.g., H2, other suitable reactive gases or combinations thereof) flow into the process chamber to form metal cap layers 380A-380D. In the depicted embodiments, metal cap layers 380A-380F comprise fluorine-free tungsten. In such embodiments, the tungsten-containing precursor may be tungsten pentachloride (e.g., WCl5). In some embodiments, metal cap layers 380A-380D are deposited by another suitable selective deposition process. In some embodiments, metal cap layers 380A-380D are formed by blanket deposition of a metal cap material over the multi-gate device 200 and patterning the metal cap material.

[0059] exist Figures 26A to 26D In this process, dielectric cap layers are formed in openings 370A-370D above metal cap layers 380A-380D. For example, dielectric cap layers 385A, 385B, 385C, and 385D are formed above metal cap layers 380A-380D, respectively. Dielectric cap layers 385A-385D fill the remaining portion of openings 370A-370D and can improve the photolithography process window associated with forming the source / drain contacts to the epitaxial source / drain components 310 (e.g., increase coverage margin). In the gate dicing view ( Figure 26A ) and gate spacer cut view ( Figure 26B In the fin cut view, dielectric cap layers 385A-385D are disposed between and physically contact the gate isolation caps, such as gate isolation cap 365A and gate isolation cap 365B. Figure 26CIn this configuration, dielectric cap layers 385A-385D are disposed between and physically contact the CESL 320 and the gate spacer 289. In some embodiments, as depicted, the width of the dielectric cap layers 385A-385D between the CESL 320s is greater than the width of the dielectric cap layers 385A-385B between the gate spacers 289s. The dielectric cap layers 385A-385D comprise a material different from that of the ILD layer 322 to achieve etch selectivity and / or planarization selectivity during subsequent processing. For example, if the ILD layer 322 comprises a silicon- and oxygen-containing material, the dielectric cap layers 385A-385D may comprise a silicon- and nitrogen-containing material, such as silicon nitride or silicon carbonitride. In some embodiments, the dielectric cap layers 385A-385D comprise silicon, silicon carbide, silicon carbonitride, silicon carbonoxide, or other suitable materials or combinations thereof. In some embodiments, the dielectric cap layers 385A-385D comprise a metal and oxygen-containing material, such as aluminum oxide (e.g., Al2O3), zirconium oxide (ZrO2), other metal oxides, or combinations thereof. In some embodiments, a deposition process and a planarization process are performed to form dielectric cap layers 385A-385D over the metal cap layers 380A-380D. For example, a dielectric cap material is fabricated to continue depositing over the multi-gate device 200 to fill the remaining portions of the openings 370A-370D, and a planarization process (e.g., CMP) is performed on the dielectric cap material until the ILD layer 322, which serves as a planarization stop layer, is reached and exposed. Thus, the planarization process removes the ILD protective layer 324 from over the multi-gate device 200. The dielectric cap material can be formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods (e.g., spin coating), or combinations thereof.

[0060] exist Figures 26A to 26DIn the multi-gate device 200, there are various transistors, such as a first transistor having a metal gate 340A (which includes a gate dielectric 342A and a gate electrode 344A), a second transistor having a metal gate 340B (which includes a corresponding portion of the gate dielectric 342B and the gate electrode 344B), a third transistor having a metal gate 340C (which includes a corresponding portion of the gate dielectric 342B and the gate electrode 344C), a fourth transistor having a metal gate 340D (which includes a corresponding portion of the gate dielectric 342C and the gate electrode 344D), a fifth transistor having a metal gate 340E (which includes a corresponding portion of the gate dielectric 342C and the gate electrode 344E), and a sixth transistor having a metal gate 340F (which includes a gate dielectric 342D and the gate electrode 344F). The first, second, third, fourth, fifth, and sixth transistors each have a corresponding epitaxial source / drain component 310, wherein the metal gates 340A-340F of the first, second, third, fourth, fifth, and sixth transistors are encapsulated in the corresponding channel layer 220' disposed between the corresponding epitaxial source / drain components 310. Because the metal gates 340A-340F are in... Figures 26A to 26D The metal gates 340A-340F completely surround their respective channel layers 220', so the first, second, third, fourth, fifth, and sixth transistors can be referred to as GAA transistors. In the depicted embodiment, the metal gates 340A-340F cover all four sides of their respective channel layers 220'. The invention contemplates embodiments in which the metal gates 340A-340F cover more or fewer four sides of their respective channel layers 220' depending on the configuration of the multi-gate device 200. Depending on the design considerations of the multi-gate device 200, the first, second, third, fourth, fifth, and sixth transistors can be any combination of n-type and p-type transistors.

[0061] Gate isolation fins 270A-270D and / or gate isolation caps 365A, 365B separate and isolate the metal gates 340A-340F of the multi-gate device 200. For example, gate isolation fin 270A and gate isolation cap 365A separate and isolate the metal gate 340A of the first transistor from the metal gate 340B of the second transistor, gate isolation fin 270B separates and isolates the metal gate 340B of the second transistor from the metal gate 340C of the third transistor, gate isolation fin 270C and gate isolation cap 365B separate and isolate the metal gate 340C of the third transistor from the metal gate 340D of the fourth transistor, and gate isolation fin 270D separates and isolates the metal gate 340D of the fourth transistor from the metal gate 340E of the fifth transistor. As described above, the gate isolation fins 270A-270D have a height greater than that of the channel layer 220'. The gate isolation fins 270A-270D have different configurations depending on the spacing between the active regions, and each gate isolation fin 270A-270D includes at least a first dielectric layer (e.g., dielectric pads 260A-260D) and a second dielectric layer (e.g., dielectric pads 262A-262D) disposed above the first dielectric layer, wherein the dielectric constant of the first dielectric layer is greater than that of the second dielectric layer. The gate isolation fins 270A-270D formed in the regions of the multi-gate device 200 with large spacing between the active regions also include a third dielectric layer disposed above the second dielectric layer (e.g., oxide layer 264A) and a fourth dielectric layer disposed above the third dielectric layer (e.g., dielectric capping layer 266). Because the thickness of the first dielectric layer along the sidewalls of the gate isolation fins 270A-270D is reduced to enlarge the metal gate fill window during gate replacement (i.e., when the dummy gate stack 280 is replaced with metal gates 340A-340F), the gate isolation fins 270A-270D are configured differently in the channel region and the source / drain region of the multi-gate device. For example, the thickness of the first dielectric layer of the gate isolation fins 270A-270D in the channel region is less than the thickness of the first dielectric layer of the gate isolation fins 270A-270D in the source / drain region.

[0062] In a further example, gate isolation cap 365A prevents the metal gate 340A of the first transistor from being electrically connected to the metal gate 340B of the second transistor, and gate isolation cap 365B prevents the metal gate 340C of the third transistor from being electrically connected to the metal gate 340D of the fourth transistor. In the depicted embodiment, the metal gate 340B of the second transistor and the metal gate 340C of the third transistor share a gate dielectric 342B, the metal gate 340B of the second transistor is electrically connected to the metal gate 340C of the third transistor through a metal capping layer (i.e., a metal cap seed layer 375B and a metal cap layer 380B), the metal gate 340D of the fourth transistor and the metal gate 340E of the fifth transistor share a gate dielectric 342C, and the metal gate 340D of the fourth transistor is electrically connected to the metal gate 340E of the fifth transistor through a metal capping layer (i.e., a metal cap seed layer 375C and a metal cap layer 380C). In some embodiments, the second and third transistors can form a CMOS transistor, wherein the second transistor is an n-type transistor and the third transistor is a p-type transistor, or vice versa. In some embodiments, the fourth and fifth transistors can form a CMOS transistor, wherein the fourth transistor is an n-type transistor and the fifth transistor is a p-type transistor, or vice versa.

[0063] In some embodiments, instead of implementing as referenced Figures 18A to 18D The described self-aligned metal gate dicing process uses photolithography to define metal gates 340A-340F and metal connection regions 362A, 362B. In such embodiments, the processes associated with forming gate isolation caps 365A, 365B and metal capping layers (i.e., metal cap seed layers 375A-375D and metal cap layers 380A-380D) are omitted because the metal gates 340A-340F are electrically connected via gate electrodes 344A-344F as needed, rather than via the metal capping layers. For example... Figures 27A to 27D and Figures 28A to 28D This is a partial perspective view of a multi-gate device 400 at various manufacturing stages according to such an embodiment. For clarity and simplicity, identical components of the multi-gate device 400 and multi-gate device 200 described above are identified by the same reference numerals. For clarity, simplified figures have been provided. Figures 27A to 27D and Figures 28A to 28D To better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 400, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 400.

[0064] The multi-gate device 400 undergoes a process similar to that of the multi-gate device 200, such as a reference. Figures 2 to 9 , Figures 10A to 10D , Figures 11A to 11D , Figures 12A to 12D , Figures 13A to 13D , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C and Figures 17A to 17C The described process. Compared to the fabrication of the multi-gate device 200, in Figures 27A to 27D In the process, the metal gate dicing process (as described herein) is performed to form a patterned mask layer 410 over the gate electrode 344, and an etch-back process is performed using the patterned mask layer 410 as an etch mask to form the gate electrodes 344A-344F. The etch-back process can be similar to that described above. Figures 18A to 18D The described etch-back process, in addition to the patterned mask layer 410 covering the portion of the gate electrode 344 disposed above the gate isolation fins in the metal connection region (i.e., the region where the metal gates will be electrically connected to each other) during the etch-back process, includes gate isolation fins 270B in the metal connection region 362A and gate isolation fins 270D in the metal gate connection region 362B. Figures 27A to 27D In the etching process, the portion of gate electrode 344 disposed above the top surfaces of gate isolation fins 270A and 270C is removed, but the portion of gate electrode 344 disposed above the top surfaces of gate isolation fins 270B and 270D is not removed. Therefore, after the etching process, gate electrode 344 continues to extend uninterruptedly within the metal connection regions 362A and 362B. For example, gate electrode 344B of metal gate 340B is physically connected to gate electrode 344C of metal gate 340C, and gate electrode 344D of metal gate 340D is physically connected to gate electrode 344E of metal gate 340E. Although metal gate 340B is connected to metal gate 340C, the number, configuration, and / or material of the layers of gate electrode 344B corresponding to metal gate 340B may differ from the number, configuration, and / or material of the layers of gate electrode 344C corresponding to metal gate 340C, such as when metal gate 340B and metal gate 340C belong to different types of transistors. Furthermore, although the metal gate 340D is connected to the metal gate 340E, the number, configuration and / or material of the layers of the gate electrode 344D corresponding to the metal gate 340D may differ from the number, configuration and / or material of the layers of the gate electrode 344E corresponding to the metal gate 340E, such as in which the metal gate 340D and the metal gate 340E belong to different types of transistors.

[0065] The etch-back process also recesses the exposed portion of the gate electrode 344 below the top surface of the gate isolation fins 270A-270D, thereby causing the metal gate in the metal connection region (e.g., metal gates 340B-340E) to have a first portion and a second portion, the first portion having a top surface higher than the top surface of the gate isolation fins 270A-270D, and the second portion having a top surface lower than the top surface of the gate isolation fins 270A-270D. In some embodiments, a first height difference may be defined between the first portion of the metal gates 340B-340E and the top surface of the gate isolation fins 270A-270D, and a second height difference may be defined between the second portion of the metal gates 340B-340E and the top surface of the gate isolation fins 270A-270D. The first height difference and the second height difference may be the same or different. In some embodiments, as depicted, the gate isolation fins 270B and 270D have a top enveloped by the gate electrode 344. The etch-back process also removes the portions of the gate electrode 344 and gate dielectric 342 disposed above the ILD protective layer 324, but does not remove the portion of the gate dielectric 342 disposed above the top surfaces of the gate isolation fins 270A and 270C. In such an embodiment, the gate dielectric 342 extends uninterruptedly from the metal gate 340A to the metal gate 340E in the multi-gate device 400, and the metal gates 340A-340E share a common gate dielectric. In some embodiments, the etch-back process removes the portion of the gate dielectric 342 disposed above the gate isolation fins 270A and 270C, thereby forming gate dielectrics such as gate dielectrics 342A, 342B, 342C, and 342D separating the metal gates 340A-340E, as described above.

[0066] Then, in Figures 28A to 28D In this process, the patterned mask layer 410 can be further removed, and a dielectric cap layer 485 is formed over the multi-gate device 400. Compared to the multi-gate device 200, the multi-gate device 400 has a single dielectric cap layer, namely the dielectric cap layer 485, which extends over and physically contacts the metal gates 340A-340D and the gate isolation fins 270A-270D. The dielectric cap layer 485 also extends below the top surface of the gate isolation fins 270A-270D and the top surface of the first portion of the metal gates 240B-340E. The dielectric cap layer 485 includes features similar to those referenced above. Figures 26A to 26D The dielectric cap layer 385A-385D is described and manufactured in a manner similar to that of dielectric cap layer 385A-385D.

[0067] In some embodiments, the process of manufacturing the multi-gate device 200 and the multi-gate device 400 omits the element related to... Figure 8 The relevant processing does not utilize the dielectric capping layer 266 to replace a portion of the oxide layer 264A. For example, Figure 29 and Figure 30 These are partial perspective views of multi-gate device 200 and multi-gate device 400 according to such embodiments, respectively. Figure 29 and Figure 30 In this configuration, the gate isolation fin 270 comprises only dielectric pads 260A, 262A, and an oxide layer 264A. Figure 29 In the middle, the gate isolation cap 365A physically contacts the oxide layer 264A. In Figure 30 In the middle, the gate dielectric 342 physically contacts the oxide layer 264A. For clarity, this has been simplified. Figure 29 and Figure 30 To better understand the inventive concept of this invention.

[0068] In some embodiments, the multi-gate device 200 and the multi-gate device 400 are omitted in their fabrication, as referenced. Figure 6 The described process relates to the deposition and planarization of the oxide layer 264. Conversely, in Figure 6 In this process, dielectric pad 262 is deposited above dielectric pad 260 to fill the remaining portion of the upper part of trench 230A and the remaining portion of the upper part of trenches 230B-230D. For example, Figure 31 and Figure 32 These are partial perspective views of multi-gate device 200 and multi-gate device 400 according to such embodiments, respectively. Figure 31 and Figure 32 In the diagram, gate isolation fins 270A-270D have the same layer (i.e., gate isolation fins 270A-270D each include only dielectric pads 260A-260D, and each includes dielectric pads 262A-262D) but different configurations (i.e., gate isolation fin 270A is wider than gate isolation fins 270B-270D). For clarity, the diagram has been simplified. Figure 31 and Figure 32 To better understand the inventive concept of this invention.

[0069] In some embodiments, in conjunction with Figures 16A to 16CDuring the relevant processing, the dielectric pads 260A-260D are completely removed from the sidewalls of the gate isolation fins 270A-270D by a trimming process. In such an embodiment, in the channel regions of the multi-gate devices 200 and 400, the gate isolation fins 270A-270D have dielectric pads 260A-260D that separate the top surface of the isolation member 235 from the dielectric pads 262A-262D, while in the source / drain regions of the multi-gate devices 200 and 400, the dielectric pads 260A-260D are retained along the sidewalls and bottom of the gate isolation fins 270A-270D. Figure 33 and Figure 34 These are partial perspective views of multi-gate device 200 and multi-gate device 400 according to such embodiments, respectively. For example, in Figure 33 and Figure 34 In the channel region, the gate dielectrics 342A-342D physically contact the dielectric pads 262A-262D of the gate isolation fins 270A-270D. For clarity, this has been simplified. Figure 33 and Figure 34 To better understand the inventive concept of this invention.

[0070] In some embodiments, the etching process associated with forming the gate spacer 289 and / or the source / drain recess 295 completely consumes the dielectric capping layer 266 of the gate isolation fin 270A. In such embodiments, the gate isolation fin 270A does not include the dielectric capping layer 266 in the source / drain regions of the multi-gate device 200 and the multi-gate device 400. Figure 35 This is a partial perspective view of a multi-gate device 200 or a multi-gate device 400 according to such an embodiment. For example, in Figure 35 In the CESL 320, the dielectric pads 260A, 262A, and oxide layer 264A of the gate isolation fin 270A are physically contacted in the source / drain region. In some embodiments, the top surface of the oxide layer 264A is substantially coplanar with the top surfaces of the dielectric pads 262A-262D and the top surfaces of the dielectric pads 260A-260D in the source / drain region. For clarity, the following has been simplified. Figure 35 To better understand the inventive concept of this invention.

[0071] Fabrication may also include forming gate contacts, forming source / drain contacts, and / or forming multilayer interconnect (MLI) components, all of which can facilitate the operation of the transistors of the multi-gate device 200 and / or multi-gate device 400. In some embodiments, ILD layers 320 and CESL 322 form the bottom layer of the MLI component (e.g., ILD0). The MLI component electrically couples the respective devices (e.g., p-type and / or n-type transistors of the multi-gate device 200 and / or multi-gate device 400, resistors, capacitors, and / or inductors) and / or components (e.g., gate electrodes of the p-type and / or n-type transistors of the multi-gate device 200 and / or multi-gate device 400 and epitaxial source / drain components) so that the respective devices and / or components can operate in a manner specified by the design requirements of the multi-gate device 200 and / or multi-gate device 400. The MLI component includes a combination of dielectric and conductive layers (e.g., metal layers) configured to form the respective interconnect structures. The conductive layer is configured to form vertical interconnect components (such as device-level contacts and / or vias) and / or horizontal interconnect components (such as wires). Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the MLI component. During operation, the interconnect components are configured to route signals between devices and / or components of the multi-gate device 200 and / or multi-gate device 400 and to distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to devices and / or components of the multi-gate device 200 and / or multi-gate device 400.

[0072] The various etching processes described herein include dry etching processes, wet etching processes, or combinations thereof. Dry etching processes can be performed using hydrogen-containing etching gases (e.g., H2 and / or CH4), nitrogen-containing etching gases (e.g., N2 and / or NH3), chlorine-containing etching gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), oxygen-containing etching gases (e.g., O2), fluorine-containing etching gases (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6, SF6, and / or NF3), bromine-containing etching gases (e.g., Br, HBr, CH3Br, CH2Br2, and / or CHBr3), iodine-containing etching gases, other suitable etching gases, or combinations thereof. Dry etching processes can use a carrier gas to deliver the etching gas. The carrier gas can include nitrogen, argon, helium, xenon, other suitable carrier gas components, or combinations thereof. Wet etching processes can be implemented using wet etchant solutions comprising H2SO4, H2O2, NH4OH, HCl, HF, DHF, KOH, NH3, CH3COOH, HNO3, H3PO4, H2O (which may be DIW or DIWO3), O3, other suitable chemicals, or combinations thereof. During each etching process, various etching parameters can be adjusted to achieve desired selective etching, such as the flow rate of the etching gas, the concentration of the etching gas, the concentration of the carrier gas, the ratio of the concentration of the first etching gas to the concentration of the second etching gas, the ratio of the concentration of the carrier gas to the concentration of the etching gas, the concentration of the wet etching solution, the ratio of the concentration of the first wet etching component to the concentration of the second wet etching component, the power of the RF source, the bias voltage, the pressure, the duration of the etching process, the temperature maintained in the process chamber during the etching process, the temperature of the wafer during the etching process, the temperature of the wet etching solution, other suitable etching parameters, or combinations thereof. Furthermore, the various etching processes described herein may include multiple steps.

[0073] The gate dicing technique disclosed herein forms gate isolation fins to isolate the metal gates of a multi-gate device from each other before the multi-gate device is formed, particularly before the metal gates of the multi-gate device are formed. As can be seen from the above description, the multi-gate device described herein offers advantages over conventional multi-gate devices. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, and not all embodiments require a specific advantage. The present invention provides many different embodiments. Exemplary devices include: a first multi-gate device having first source / drain components and a first metal gate surrounding a first channel layer; and a second multi-gate device having second source / drain components and a second metal gate surrounding a second channel layer. The first channel layer is disposed between the first source / drain components, and the second channel layer is disposed between the second source / drain components. The gate isolation fin separating the first metal gate and the second metal gate includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed above the first dielectric layer. The second dielectric constant is less than the first dielectric constant. In some embodiments, the first dielectric constant is greater than or equal to about seven, and the second dielectric constant is less than or equal to about seven.

[0074] A gate isolation cap may be disposed on the gate isolation fin to provide additional isolation. In some embodiments, the device further includes a first metal cap layer disposed over a first metal gate, a second metal cap layer disposed over a second metal gate, and a gate isolation cap disposed over the gate isolation fin. The gate isolation cap is disposed between and separates the first and second metal cap layers. In some embodiments, the first width of the gate isolation cap is smaller than the second width of the gate isolation fin. In some embodiments, the gate isolation fin further includes a third dielectric layer disposed over a second dielectric layer. The third dielectric layer has a third dielectric constant less than a first dielectric constant. In some embodiments, the gate isolation fin further includes a fourth dielectric layer disposed over the third dielectric layer. In such an embodiment, the second dielectric layer is disposed along a first sidewall of the fourth dielectric layer and a second sidewall of the third dielectric layer, and the fourth dielectric layer has a fourth dielectric constant less than the first dielectric constant. In some embodiments, the first dielectric layer has a bottom portion having a first thickness and a sidewall portion having a second thickness, wherein the second thickness is less than the first thickness. In some embodiments, a first dielectric layer separates a first metal gate from a first sidewall portion of a second dielectric layer and separates a second metal gate from a second sidewall portion of the second dielectric layer. In some embodiments, the first dielectric layer physically contacts the bottom of the second dielectric layer, the first metal gate physically contacts the first sidewall portion of the second dielectric layer, and the second metal gate physically contacts the second sidewall portion of the second dielectric layer. In some embodiments, a first height is defined between the top surface of the gate isolation fin and the top surface of the substrate, and a second height is defined between the top surface of the first channel layer and the top surface of the substrate, wherein the first height is greater than the second height.

[0075] Another exemplary device includes an isolation member disposed above a substrate and a gate isolation fin disposed above the isolation member. The isolation member is disposed between a first fin portion and a second fin portion extending from the substrate. The gate isolation fin includes a low-k dielectric layer disposed above a high-k dielectric layer. The device further includes: a first multi-gate device having a first channel layer disposed above the first fin portion, a first metal gate enclosing the first channel layer, and a first source / drain member. The first metal gate is disposed between the first channel layer and the first fin portion. The device further includes: a second multi-gate device having a second channel layer disposed above the second fin portion, a second metal gate enclosing the second channel layer, and a second source / drain member. The second metal gate is disposed between the second channel layer and the second fin portion. The gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device. In some embodiments, a first width of the isolation member is greater than a second width of the gate isolation fin. In some embodiments, the low-k dielectric layer is U-shaped, and the high-k dielectric layer is U-shaped.

[0076] In some embodiments, the isolation member is a first isolation member, the gate isolation fin is a first gate isolation fin, the low-k dielectric layer is a first low-k dielectric layer, and the high-k dielectric layer is a first high-k dielectric layer. In such embodiments, the device may further include: a second isolation member disposed above a substrate and located between a second fin portion and a third fin portion extending from the substrate; and a second gate isolation fin disposed above the isolation member. The second gate isolation fin includes a second low-k dielectric layer disposed above the second high-k dielectric layer and an oxide layer disposed above the second low-k dielectric layer. In such embodiments, the device may further include: a third multi-gate device having a third channel layer disposed above the third fin portion, a third metal gate enclosing the third channel layer, and a third source / drain member. The third metal gate is disposed between the third channel layer and the third fin portion. The second gate isolation fin separates the second metal gate of the second multi-gate device from the third metal gate of the third multi-gate device. In some embodiments, a first gap is located between the first fin portion and the second fin portion, a second gap is located between the second fin portion and the third fin portion, and the second gap is larger than the first gap.

[0077] In some embodiments, the device further includes a first metal cap layer and a second metal cap layer. The first metal cap layer is disposed above the first metal gate, the first gate isolation fin, and the second metal gate. The second metal cap layer is disposed above the third metal gate. In some embodiments, a first dielectric cap layer is disposed above the first metal cap layer, and a second dielectric cap layer is disposed above the second metal cap layer. In some embodiments, a gate isolation cap is disposed between the first metal cap layer and the second metal cap layer, and between the first dielectric cap layer and the second dielectric cap layer. The gate isolation cap physically contacts the second gate isolation fin.

[0078] An exemplary method includes: forming an isolation member in the lower portion of a trench; and forming a gate isolation fin above the isolation member. The gate isolation fin is formed in the upper portion of the trench by depositing a first dielectric layer having a first dielectric constant along the bottom and sidewalls of the upper portion of the trench; depositing a second dielectric layer in the upper portion of the trench above the first dielectric layer; and performing a planarization process on the first and second dielectric layers. The second dielectric layer has a second dielectric constant smaller than the first dielectric constant. The method further includes forming a first multi-gate device and a second multi-gate device after forming the gate isolation fin. The first multi-gate device has a first channel layer, a first metal gate, and a first source / drain member, wherein the first channel layer is disposed between the first source / drain member, and the first metal gate surrounds the first channel layer. The second multi-gate device has a second channel layer, a second metal gate, and a second source / drain member, wherein the second channel layer is disposed between the second source / drain member, and the second metal gate surrounds the second channel layer. A gate isolation fin is disposed between a first metal gate of a first multi-gate device and a second metal gate of a second multi-gate device, separating the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device. In some embodiments, forming a first multi-gate device having a first channel layer and a second multi-gate device having a second channel layer includes performing a channel release process. In some embodiments, the method further includes trimming a first dielectric layer of the gate isolation fin after performing the channel release process. In some embodiments, the first dielectric layer and the second dielectric layer partially fill the upper portion of the trench. In such embodiments, forming the gate isolation fin may further include: depositing a third dielectric layer having a third dielectric constant over the second dielectric layer; and performing a planarization process on the third dielectric layer. The third dielectric layer fills the remaining portion of the upper portion of the trench. The third dielectric constant is less than the first dielectric constant. In some embodiments, forming the gate isolation fin may further include: etching back the third dielectric layer; and forming a fourth dielectric layer over the third dielectric layer, wherein the fourth dielectric layer has a fourth dielectric constant less than the first dielectric constant.

[0079] Another exemplary device includes a first multi-gate device and a second multi-gate device. The first multi-gate device has a first channel layer disposed between first source / drain components and a first metal gate surrounding the first channel layer. The second multi-gate device has a second channel layer disposed between second source / drain components and a second metal gate surrounding the second channel layer. The device further includes a dielectric gate isolation fin disposed between the first metal gate and the second metal gate and separating the first metal gate and the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant, a second dielectric layer disposed above the first dielectric layer, and a third dielectric layer disposed above the second dielectric layer. The second dielectric layer has a second dielectric constant less than the first dielectric constant. The third dielectric layer has a third dielectric constant less than the first dielectric constant. In some embodiments, the third dielectric constant is greater than the second dielectric constant. In some embodiments, along the length of the fin, the top surface of the dielectric gate isolation fin is higher than the top surface of the first metal gate and the top surface of the second metal gate relative to the top surface of the substrate.

[0080] In some embodiments, a second dielectric layer is disposed above the bottom surface and sidewalls of a third dielectric layer. In some embodiments, the second dielectric layer is also disposed above the top surface of the third dielectric layer. In some embodiments, a first dielectric constant is greater than or equal to about seven, and a second dielectric constant is less than or equal to about seven. In some embodiments, the first dielectric layer comprises a high-k dielectric material, the second dielectric layer comprises a low-k dielectric material, and the third dielectric layer comprises an oxide material. In some embodiments, the thickness of the first dielectric layer is from about 1 nm to about 7 nm. In some embodiments, a first height is defined between the top surface of the dielectric gate isolation fin and the top surface of the substrate, and a second height is defined between the top surface of the first channel layer and the top surface of the second channel layer relative to the top surface of the substrate, and the first height is about 5 nm to about 25 nm greater than the second height. In some embodiments, the dielectric gate isolation fin is a first dielectric gate isolation fin, and a first metal gate also surrounds the third channel layer. In such embodiments, the device may further include a second dielectric gate isolation fin disposed between the first channel layer and the third channel layer. The second dielectric gate isolation fin may not have a third dielectric layer. The second dielectric gate isolation fin may include a first dielectric layer having a first dielectric constant and a second dielectric layer disposed above the first dielectric layer, wherein the second dielectric layer has a second dielectric constant smaller than the first dielectric constant. In such an embodiment, a first metal gate may extend above the top surface of the second dielectric gate isolation fin. In such an embodiment, the top surface of the first dielectric gate isolation fin may be higher than a first portion of the top surface of the first metal gate disposed above the first channel layer and the third channel layer, and lower than a second portion of the top surface of the first metal gate disposed above the second dielectric gate isolation fin.

[0081] In some embodiments, the dielectric gate isolation fin is a first dielectric gate isolation fin. In such embodiments, the device may further include a third multi-gate device having a third channel layer disposed between a third source / drain component and a third metal gate surrounding a third channel layer. In such embodiments, the device may further include a second dielectric gate isolation fin disposed between and separating the first and third metal gates. The second dielectric gate isolation fin may not have a third dielectric layer. The second dielectric gate isolation fin may include a first dielectric layer having a first dielectric constant and a second dielectric layer disposed above the first dielectric layer, wherein the second dielectric layer has a second dielectric constant smaller than the first dielectric constant. In some embodiments, a first width of the first dielectric gate isolation fin is greater than a second width of the second dielectric gate isolation fin. In some embodiments, a metal layer extends continuously and uninterruptedly over the first metal gate, the second dielectric gate isolation fin, and the third metal gate along the gate length direction. In some embodiments, the metal layer also extends over the first dielectric gate isolation fin and the second metal gate along the gate length direction. The dielectric layer may extend through the metal layer to the first dielectric gate isolation fin. In some embodiments, the metal layer includes a tungsten layer. In some embodiments, the metal layer includes a titanium nitride layer. In some embodiments, the metal layer is disposed between first spacers disposed along a first sidewall of a first metal gate and between second spacers disposed along a second sidewall of a third metal gate.

[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device comprising: a first multi-gate device having: a first channel layer of a channel region disposed between first source / drain components of a source / drain region, and a first metal gate surrounding the first channel layer; a second multi-gate device having: a second channel layer of the channel region disposed between second source / drain components of the source / drain region, and a second metal gate surrounding the second channel layer; and a gate isolation fin disposed between and separating the first metal gate and the second metal gate, wherein the gate isolation fin comprises: a first dielectric layer having a first dielectric constant, wherein the first dielectric layer has a first thickness of a bottom portion and a second thickness of a sidewall portion, wherein the second thickness is less than the first thickness, and a second dielectric layer disposed above the first dielectric layer, wherein the second dielectric layer has a second dielectric constant less than the first dielectric constant, wherein a width of the gate isolation fin in the channel region is different than a width of the gate isolation fin in the source / drain region. the sidewall portion is a first sidewall portion disposed between the second dielectric layer and the first metal gate and the second metal gate, the gate isolation fin is further disposed between the first source / drain components and the second source / drain components, and the first dielectric layer further has a second sidewall portion disposed between the second dielectric layer and the first source / drain components and the second source / drain components, wherein the second sidewall portion has the first thickness.

2. The semiconductor device of claim 1, wherein, the first dielectric layer separates the first metal gate from a first sidewall portion of the second dielectric layer and separates the second metal gate from a second sidewall portion of the second dielectric layer, 3. The semiconductor device of claim 1, wherein, wherein the first dielectric constant is greater than or equal to 7 ± 10% and the second dielectric constant is less than or equal to 7 ± 10%. the first dielectric layer physically contacts a bottom portion of the second dielectric layer, the first metal gate physically contacts a first sidewall portion of the second dielectric layer, and the second metal gate physically contacts a second sidewall portion of the second dielectric layer.

4. The semiconductor device of claim 1, wherein, a first height is defined between a top surface of the gate isolation fin and a top surface of a substrate, a second height is defined between a top surface of the first channel layer and the top surface of the substrate, and the first height is greater than the second height.

5. The semiconductor device of claim 1, wherein, the gate isolation fin further comprises a third dielectric layer disposed above the second dielectric layer, wherein the third dielectric layer has a third dielectric constant less than the first dielectric constant.

6. The semiconductor device of claim 1, wherein, the gate isolation fin further comprises a fourth dielectric layer disposed above the third dielectric layer, wherein the second dielectric layer is disposed along a first sidewall of the fourth dielectric layer and a second sidewall of the third dielectric layer, and wherein the fourth dielectric layer has a fourth dielectric constant less than the first dielectric constant.

7. The semiconductor device of claim 6, wherein, ​ 8. The semiconductor device of claim 1, further comprising a first metal cap layer disposed above the first metal gate, a second metal cap layer disposed above the second metal gate, and a gate isolation end cap disposed above the gate isolation fin, wherein, The gate isolation end cap is disposed between and separates the first metal cap layer and the second metal cap layer.

9. The semiconductor device of claim 8, wherein, A first width of the gate isolation end cap is less than a second width of the gate isolation fin.

10. The semiconductor device of claim 1, wherein, A width of the gate isolation fin in the channel region is less than a width of the gate isolation fin in the source / drain region.

11. A semiconductor device, comprising: an isolation component disposed above a substrate, wherein the isolation component is disposed between a first fin portion and a second fin portion extending from the substrate; a gate isolation fin disposed above the isolation component, wherein the gate isolation fin includes a low-k dielectric layer disposed above a high-k dielectric layer having a first thickness for a bottom portion and a second thickness for a sidewall portion, wherein the second thickness is less than the first thickness; a first multi-gate device having a first channel layer disposed at a channel region above the first fin portion, a first metal gate wrapping the first channel layer, and a first source / drain component at a source / drain region, wherein the first metal gate is disposed between the first channel layer and the first fin portion; and a second multi-gate device having a second channel layer disposed at the channel region above the second fin portion, a second metal gate wrapping the second channel layer, and a second source / drain component at the source / drain region, wherein the second metal gate is disposed between the second channel layer and the second fin portion, and wherein the gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device, wherein a width of the gate isolation fin in the channel region is different than a width of the gate isolation fin in the source / drain region.

12. The semiconductor device of claim 11, wherein, A width of the gate isolation fin in the channel region is less than a width of the gate isolation fin in the source / drain region.

13. The semiconductor device of claim 11, wherein, A first width of the isolation component is greater than a second width of the gate isolation fin, and wherein the low-k dielectric layer is u-shaped and the high-k dielectric layer is u-shaped.

14. The semiconductor device of claim 11, wherein, The isolation component is a first isolation component, the gate isolation fin is a first gate isolation fin, the low-k dielectric layer is a first low-k dielectric layer, and the high-k dielectric layer is a first high-k dielectric layer, and wherein the semiconductor device further comprises: a second isolation component disposed above the substrate and between the second fin portion and a third fin portion extending from the substrate; a second gate isolation fin disposed above the second isolation component, wherein the second gate isolation fin includes a second low-k dielectric layer disposed above a second high-k dielectric layer and an oxide layer disposed above the second low-k dielectric layer; and a third multi-gate device having a third channel layer disposed at the channel region above the third fin portion, a third metal gate wrapping the third channel layer, and a third source / drain component at the source / drain region, wherein the third metal gate is disposed between the third channel layer and the third fin portion, and wherein the second gate isolation fin separates the third metal gate of the third multi-gate device from the second metal gate of the second multi-gate device. a third gate isolation fin separating the second metal gate of the second multi-gate device and the third metal gate of the third multi-gate device.

15. The semiconductor device of claim 14, wherein, a first spacing between the first fin portion and the second fin portion, and a second spacing between the second fin portion and the third fin portion, and the second spacing is greater than the first spacing.

16. The semiconductor device of claim 14, further comprising: a first metal cap layer and a second metal cap layer, wherein the first metal cap layer is disposed over the first metal gate, the first gate isolation fin, and the second metal gate, and the second metal cap layer is disposed over the third metal gate; a first dielectric cap layer disposed over the first metal cap layer and a second dielectric cap layer disposed over the second metal cap layer; and a gate isolation end cap disposed between the first metal cap layer and the second metal cap layer and between the first dielectric cap layer and the second dielectric cap layer, wherein the gate isolation end cap physically contacts the second gate isolation fin.

17. A method of forming a semiconductor device, comprising: forming an isolation component in a lower portion of a trench; forming a gate isolation fin over the isolation component, wherein the gate isolation fin is formed in an upper portion of the trench by: depositing a first dielectric layer having a first dielectric constant along a bottom and sidewalls of the upper portion of the trench, depositing a second dielectric layer in the upper portion of the trench over the first dielectric layer, wherein the second dielectric layer has a second dielectric constant that is less than the first dielectric constant, and applying a planarization process to the first dielectric layer and the second dielectric layer; and after forming the gate isolation fin, forming a first multi-gate device and a second multi-gate device, wherein: the first multi-gate device has a first channel layer, a first metal gate, and a first source / drain component, wherein the first channel layer is disposed between the first source / drain component, and the first metal gate surrounds the first channel layer, the second multi-gate device has a second channel layer, a second metal gate, and a second source / drain component, wherein the second channel layer is disposed between the second source / drain component, and the second metal gate surrounds the second channel layer, and the third multi-gate device has a third channel layer, a third metal gate, and a third source / drain component, wherein the third channel layer is disposed between the third source / drain component, and the third metal gate surrounds the third channel layer. The gate isolation fin is disposed between and separates the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device; wherein forming the first multi-gate device having the first channel layer and the second multi-gate device having the second channel layer includes performing a channel release process, the method further comprising trimming the first dielectric layer of the gate isolation fin after performing the channel release process.

18. The method of claim 17, wherein, The first dielectric layer includes metal and oxygen, and the second dielectric layer includes silicon.

19. The method of claim 17, wherein, The first and second dielectric layers partially fill an upper portion of the trench, and forming the gate isolation fin further comprises: depositing a third dielectric layer over the second dielectric layer, wherein the third dielectric layer fills a remaining portion of the upper portion of the trench, and the third dielectric layer has a third dielectric constant that is less than the first dielectric constant; and performing the planarization process on the third dielectric layer.

20. The method of claim 19, wherein, forming a fourth dielectric layer over the third dielectric layer, wherein the fourth dielectric layer has a fourth dielectric constant that is less than the first dielectric constant.

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