Memory cell, semiconductor device and method for forming the same

Abstract

The memory cell includes a ferroelectric (FE) material in contact with a word line; and an oxide semiconductor (OS) layer in contact with a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer includes: a first region adjacent to the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent to the source line, the second region having a second concentration of a semiconductor element; and a third region located between the first region and the second region, the third region having a third concentration of a semiconductor element, the third concentration being greater than the second concentration and less than the first concentration. Embodiments of the present invention also relate to semiconductor devices and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory cells, semiconductor devices, and methods of forming the same. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications, including, for example, radios, televisions, cell phones, and personal computing devices. Semiconductor memory includes two main categories. One is volatile memory; the other is nonvolatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories: static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the stored information when power is removed.

[0003] On the other hand, nonvolatile memory can keep data stored on it. One type of nonvolatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include fast read and write speeds and small size. Summary of the invention

[0004] An embodiment of the present invention provides a memory cell, comprising: a ferroelectric (FE) material, in contact with a word line; and an oxide semiconductor (OS) layer, in contact with a source line and a bit line, wherein the ferroelectric material is arranged between the oxide semiconductor layer and the word line; and wherein the oxide semiconductor layer comprises: a first region, adjacent to the ferroelectric material, the first region having a first concentration of a semiconductor element; a second region, adjacent to the source line, the second region having a second concentration of the semiconductor element; and a third region, located between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration being greater than the second concentration and less than the first concentration.

[0005] Another embodiment of the present invention provides a semiconductor device, comprising: a semiconductor substrate; a first memory unit located above the semiconductor substrate, the first memory unit comprising a first thin film transistor, wherein the first thin film transistor comprises: a first portion of a ferroelectric material, the first portion of the ferroelectric material being in contact with a first word line; and a first channel region, the first channel region comprising: a first portion of a first semiconductor layer being in contact with the ferroelectric material; a first portion of a second semiconductor layer being in contact with the first semiconductor layer, the indium concentration of the first semiconductor layer being greater than the indium concentration of the second semiconductor layer; and a first portion of a third semiconductor layer being in contact with the second semiconductor layer, the indium concentration of the third semiconductor layer being less than the indium concentration of the second semiconductor layer; and a second memory unit located above the first memory unit.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: patterning a first trench, the first trench extending through a first wire; depositing a ferroelectric (FE) material along the sidewalls and bottom surface of the first trench; depositing an oxide semiconductor (OS) layer above the ferroelectric material, the oxide semiconductor layer extending along the sidewalls and the bottom surface of the first trench, depositing the oxide semiconductor layer comprising: depositing a first region of the oxide semiconductor layer above the ferroelectric material, the first region having a first concentration of a semiconductor element; depositing a second region of the oxide semiconductor layer above the first region of the oxide semiconductor layer, the second region having a second concentration of the semiconductor element, the second concentration of the semiconductor element being less than the first concentration of the semiconductor element; and depositing a third region of the oxide semiconductor layer above the second region of the oxide semiconductor layer, the third region having a third concentration of the semiconductor element, the third concentration being less than the second concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1B A perspective view and a circuit diagram of a memory array according to some embodiments are shown.

[0009] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig. 18C , Figures 19 to 25 , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B and Fig. 30C Various views of fabricating a memory array are shown in accordance with some embodiments.

[0010] Fig.31A and Fig.31B Various views of a memory array are shown in accordance with some embodiments.

[0011] Fig.32A and Fig.32B Various views of a memory array are shown in accordance with some embodiments.

[0012] Fig.33 A graph showing semiconductor concentration in a channel region according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] Various embodiments provide a 3D memory array with multiple vertically stacked memory cells. Each memory cell includes a thin film transistor (TFT), and the TFT has a word line region used as a gate electrode, a bit line region used as a first source / drain electrode, and a source line region used as a second source / drain electrode. Each TFT also includes a ferroelectric (FE) gate dielectric layer and an oxide semiconductor (OS) channel region. The OS channel region can have at least three different regions, each region having a different semiconductor element (e.g., indium) concentration. For example, the indium concentration of the OS channel can be reduced in the direction away from the gate electrode / FE gate dielectric. By providing at least three different concentrations of semiconductor elements, advantages can be achieved. For example, by having a relatively high concentration of semiconductor elements closest to the gate electrode, the carrier mobility in the OS channel region can be increased. By having a relatively low concentration of semiconductor elements at the exposed surface of the OS channel region away from the gate electrode, process damage during subsequent processing of the OS channel region can be reduced. In addition, by including a medium concentration of semiconductor elements between a relatively low concentration region and a relatively high concentration region of the OS channel region, electron scattering between the low concentration region and the high concentration region can be reduced. Therefore, device performance can be improved by reducing manufacturing defects.

[0016] Figure 1A and Figure 1B An example of a memory array according to some embodiments is shown. Figure 1A An example of a portion of a memory array 200 according to some embodiments is shown in a three-dimensional view, and Figure 1B A circuit diagram of a memory array 200 is shown. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back-end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate. In some embodiments, the memory array may be disposed in a top metal layer of an interconnect layer, such as above all other interconnect layers in a semiconductor die. In other embodiments, the memory array may be disposed in an intermediate metal layer of an interconnect layer, and the semiconductor die may include, for example, additional interconnect layers above and below the memory array.

[0017] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array, etc. Each memory cell 202 may include a thin film transistor (TFT) 204 having a ferroelectric (FE) material as a gate dielectric. In some embodiments, the gate of each TFT 204 is electrically coupled to a corresponding word line, the first source / drain region of each TFT 204 is electrically coupled to a corresponding bit line, and the second source / drain region of each TFT 204 is electrically coupled to a corresponding source line, which electrically couples the second source / drain region to ground. The memory cells 202 in the same horizontal row of the memory array 200 may share a common word line, and the memory cells in the same vertical column of the memory array 200 may share a common source line and a common bit line.

[0018] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines) with a dielectric layer 52 disposed between adjacent conductive lines 72. The conductive lines 72 are parallel to the underlying substrate (eg, at Figure 1A and Figure 1B The conductor 72 may have a stepped configuration such that the lower conductor 72 is longer than the upper conductor 72 and extends laterally beyond the end point of the upper conductor 72. For example, Figure 1A , a stacked layer of conductive lines 72 is shown, wherein the topmost conductive line 72 is the shortest and the bottommost conductive line 72 is the longest. The respective lengths of conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, portions of each conductive line 72 may be accessed from above the memory array 200, and conductive contacts may be made to the exposed portions of each conductive line 72.

[0019] The memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). Each of the conductive lines 106 and 108 may extend in a direction perpendicular to the conductive line 72. A dielectric material 102 is disposed between the conductive lines 106 and 108 and isolates adjacent conductive lines 106 and 108. The paired conductive lines 106 and 108 and the intersecting conductive lines 72 define the boundaries of each memory cell 202, and a dielectric material 98 is disposed between adjacent pairs of conductive lines 106 and 108 and isolates adjacent pairs of conductive lines 106 and 108. In some embodiments, the conductive line 108 is electrically coupled to ground. Although Figure 1A A particular placement of conductors 106 relative to conductors 108 is shown, but it should be understood that in other embodiments, the placement of conductors 106 and 108 may be reversed.

[0020] The memory array 200 may further include an oxide semiconductor (OS) layer 92. The OS layer 92 may provide a channel region for the TFT 204 of the memory cell 202. For example, when an appropriate voltage (e.g., higher than a corresponding threshold voltage (V th )), the area of ​​OS layer 92 that intersects conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (eg, in the direction indicated by arrow 206).

[0021] The FE material 90 is disposed between the conductive line 72 and the OS layer 92, and the FE material 90 can provide a gate dielectric for the TFT 204. Therefore, the memory array 200 can also be referred to as a ferroelectric random access memory (FERAM) array. The FE material 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference on the FE material 90 and generating an appropriate electric field. The polarization can be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the FE material 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the FE material 90, the threshold voltage of the corresponding TFT 204 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the FE material 90 has a first electrical polarization direction, the corresponding TFT 204 can have a relatively low threshold voltage, and when a region of the FE material 90 has a second electrical polarization direction, the corresponding TFT 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (eg, less error-prone) to read the digital value stored in the corresponding memory cell 202 .

[0022] In order to perform a write operation on the memory cell 202, a write voltage is applied to the portion of the FE material 90 corresponding to the memory cell 202. For example, the write voltage can be applied by applying an appropriate voltage to the corresponding wire 72 (e.g., word line) and the corresponding wire 106 / 108 (e.g., bit line / source line). By applying the write voltage to the portion of the FE material 90, the polarization direction of the region of the FE material 90 can be changed. As a result, the corresponding threshold voltage of the corresponding TFT 204 can also be switched from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in the memory cell 202. Because the wire 72 intersects with the wires 106 and 108, a separate memory cell 202 can be selected for a write operation.

[0023] To perform a read operation on the memory cell 202, a read voltage is applied to the corresponding conductive line 72 (e.g., the word line / gate electrode of the TFT 204), and a current is applied to the corresponding conductive line 106 (e.g., the bit line). The applied read voltage may be between the low threshold voltage and the high threshold voltage of the TFT 204. Depending on the polarization direction of the corresponding region of the FE material 90, the TFT 204 of the memory cell 202 may or may not be conducting. As a result, the conductive line 106 may or may not be discharged through the conductive line 108 (e.g., coupled to the grounded source line), and the digital value stored in the memory cell 202 may be determined. Because the conductive line 72 intersects the conductive lines 106 and 108, an individual memory cell 202 may be selected for a read operation.

[0024] Figure 1A Reference cross sections of memory array 200 used in subsequent figures are also shown. Cross section BB' is along the longitudinal axis of conductive line 72 and in a direction parallel to, for example, the current flow direction of TFT 204. Cross section CC' is perpendicular to cross section BB' and parallel to the longitudinal axis of conductive line 72. Cross section CC' extends through conductive line 106. Cross section D-D' is parallel to cross section CC' and extends through dielectric material 102. For clarity, subsequent figures refer to these reference cross sections.

[0025] Figures 2 to 30C is a diagram of an intermediate stage in the fabrication of a memory array 200 according to some embodiments. Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig. 30A Along Figure 1A The reference cross section BB' shown in FIG. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B and Fig.18B Along Figure 1AThe reference cross section CC' shown in FIG. Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.28B and Fig.29B Along Figure 1A The reference cross-sectional view D-D' shown shows Fig.26B and Fig.27B . Fig.25 , Fig.26A , Fig.27A , Fig.28A and Fig.29A A top view is shown.

[0026] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. In some embodiments, active devices (eg, transistors, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may be formed on the top surface of substrate 50 .

[0027] Figure 2 Also shown is a circuit that may be formed over the substrate 50. The circuit includes a transistor located at the top surface of the substrate 50. The transistor may include a gate dielectric layer 202 located over the top surface of the substrate 50 and a gate electrode 204 located over the gate dielectric layer 202. Source / drain regions 206 are disposed in the substrate 50 on opposite sides of the gate dielectric layer 202 and the gate electrode 204. Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 202 and separate the source / drain regions 206 from the gate electrode 204 by an appropriate lateral distance. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (finFET), a nano field effect transistor (nanoFET), etc.

[0028] The first ILD 210 surrounds and isolates the source / drain regions 206, the gate dielectric layer 202, and the gate electrode 204, and the second ILD 212 is located above the first ILD 210. The source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and the gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 204. An interconnect structure 220 (including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224) is located above the second ILD 212, the source / drain contacts 214, and the gate contact 216. Although Figure 2 Two stacked dielectric layers 224 are shown, but it should be understood that the interconnect structure 200 may include any number of dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source / drain contacts 214 to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 220 may include a logic circuit, a memory circuit, a sense amplifier, a controller, an input / output circuit, an image sensor circuit, etc., or a combination thereof. Although Figure 2 Transistors formed on substrate 50 are discussed, but other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuits.

[0029] exist Figure 3A and Figure 3B in Figure 2 A multilayer stack 58 is formed above the structure. For simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structure 120 may be omitted from subsequent figures. Although the multilayer stack 58 is shown as being in contact with the dielectric layer 224 of the interconnect structure 220, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, the multilayer stack 58 may be located above the interconnect structure 220, and one or more interconnect layers (including conductive features located in an insulating layer (e.g., a low-k dielectric layer)) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines for active devices on the substrate 50 and / or the memory array 200 (see Figure 1A and Figure 1B ).

[0030] The multilayer stack 58 includes alternating layers of conductive layers 54A-E (collectively, conductive layers 54) and dielectric layers 52A-D (collectively, dielectric layers 52). The conductive layers 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). The conductive layers 54 may include conductive materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and the dielectric layers 52 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Each of the conductive layers 54 and the dielectric layers 52 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), and the like. Although Figure 3A and Figure 3B A particular number of conductive layers 54 and dielectric layers 52 are shown, but other embodiments may include different numbers of conductive layers 54 and dielectric layers 52 .

[0031] exist Figure 4A and Figure 4B , a photoresist 56 is formed over the multilayer stack 58. The photoresist 56 may be formed by using a spin coating technique, and the photoresist 56 may be patterned using an acceptable photolithography technique. The patterned photoresist 56 may expose the multilayer stack 58 in the region 60 while masking the remaining portion of the multilayer stack 58. For example, the topmost layer of the multilayer stack 58 (e.g., the conductive layer 54E) may be exposed in the region 60.

[0032] exist Figure 5A and Figure 5B In the embodiment of the present invention, the exposed portion of the multilayer stack 58 in the region 60 is etched using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet etching or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may remove portions of the conductive layer 54E and the dielectric layer 52D in the region 60 and define the opening 61. Since the conductive layer 54E and the dielectric layer 52D have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, when etching the conductive layer 54E, the dielectric layer 52D is used as an etching stop layer, and when etching the dielectric layer 52D, the conductive layer 54D is used as an etching stop layer. As a result, portions of the conductive layer 54E and the conductive layer 54D may be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 may extend to a desired depth. Optionally, after the opening 61 reaches the desired depth, a timed etching process may be used to stop etching the opening 61. In the resulting structure, conductive layer 54D is exposed in region 60 .

[0033] exist Fig. 6A and Figure 6BIn the embodiment of the present invention, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60 and 62 may be exposed. For example, the top surface of conductive layer 54D may be exposed in region 60, and the top surface of conductive layer 54E may be exposed in region 62.

[0034] exist Figure 7 In the embodiment of the present invention, the conductive layer 54E, the dielectric layer 52D, the conductive layer 54C, and the dielectric layer 52C in the regions 60 and 62 are removed by an acceptable etching process using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet etching or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The etching may extend the opening 61 further into the multilayer stack 58. Since the conductive layers 54E / 54D and the dielectric layers 52D / 52C have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, when etching the conductive layer 54E, the dielectric layer 52D is used as an etching stop layer; when etching the dielectric layer 52D, the conductive layer 54D may be used as an etching stop layer; when etching the conductive layer 54D, the dielectric layer 52C is used as an etching stop layer; and when etching the dielectric layer 52C, the conductive layer 54C is used as an etching stop layer. As a result, portions of conductive layer 54E / 54D and dielectric layer 52D / 52C can be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 can be extended to a desired depth. In addition, during the etching process, the unetched portions of conductive layer 54 and dielectric layer 52 serve as masks for the underlying layers, and as a result, the previous patterns of conductive layer 54E and dielectric layer 52D (see FIG. Fig. 6A and Figure 6B ) can be transferred to the underlying conductive layer 54D and dielectric layer 52C. In the resulting structure, conductive layer 54C is exposed in region 60, and conductive layer 54D is exposed in region 62.

[0035] exist Figure 8 6, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. Photoresist may be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 located in regions 60, 62, and 64 may be exposed. For example, the top surface of conductive layer 54C may be exposed in region 60; the top surface of conductive layer 54D may be exposed in region 62; and the top surface of conductive layer 54E may be exposed in region 64.

[0036] exist Fig. 9, using photoresist 56 as a mask, portions of conductive layers 54E, 54D, and 54C and dielectric layers 52D, 52C, and 52B in regions 60, 62, and 64 are removed by an acceptable etching process. The etching may be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The etching may extend opening 61 further into multilayer stack 58. Since conductive layers 54E, 54D, and 54C and dielectric layers 52D, 52C, and 52B have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, when etching conductive layer 54E, dielectric layer 52D serves as an etch stop layer; when etching dielectric layer 52D, conductive layer 54D serves as an etch stop layer; when etching conductive layer 54D, dielectric layer 52C serves as an etch stop layer; when etching dielectric layer 52C, conductive layer 54C serves as an etch stop layer; when etching conductive layer 54C, dielectric layer 52B serves as an etch stop layer; and when etching dielectric layer 52B, conductive layer 54B serves as an etch stop layer. As a result, portions of conductive layers 54E / 54D / 54C and dielectric layers 52D / 52C / 52B can be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 can be extended to a desired depth. In addition, during the etching process, the unetched portions of conductive layer 54 and dielectric layer 52 serve as masks for the underlying layers, and as a result, the previous patterns of conductive layers 54E / 54D and dielectric layers 52D / 52C (see Figure 8 ) can be transferred to the underlying conductive layer 54D / 54C and dielectric layer 52C / 52B. In the resulting structure, conductive layer 54B is exposed in region 60; conductive layer 54C is exposed in region 62; and conductive layer 54B is exposed in region 64.

[0037] exist Fig.10 5. In the embodiment of the present invention, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 located in regions 60, 62, 64, and 66 may be exposed. For example, the top surface of conductive layer 54B may be exposed in region 60; the top surface of conductive layer 54C may be exposed in region 62; the top surface of conductive layer 54D may be exposed in region 64; and the top surface of conductive layer 54E may be exposed in region 66.

[0038] exist Fig.11In the embodiment of the present invention, portions of conductive layers 54E, 54D, 54C, and 54B in regions 60, 62, 64, and 66 are removed by an acceptable etching process using photoresist 56 as a mask. Etching may be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic. Etching may extend opening 61 further into multilayer stack 58. In some embodiments, dielectric layer 52D is used as an etch stop layer when etching conductive layer 54E; dielectric layer 52C is used as an etch stop layer when etching conductive layer 54D; dielectric layer 52B is used as an etch stop layer when etching conductive layer 54C; and dielectric layer 52A is used as an etch stop layer when etching conductive layer 54B. As a result, portions of conductive layers 54E, 54D, 54C, and 54B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Furthermore, during the etching process, each dielectric layer 52 acts as a mask for the underlying layers, and as a result, the previous pattern of dielectric layers 52D / 52C / 52B (see Fig.10 ) can be transferred to the underlying conductive layer 54D / 54C / 54B. In the resulting structure, dielectric layer 52A is exposed in region 60; dielectric layer 52B is exposed in region 62; dielectric layer 52C is exposed in region 64; and dielectric layer 52D is exposed in region 66.

[0039] exist Fig. 12A and Fig. 12B , the photoresist 56 may be removed, such as by an acceptable ashing or wet stripping process. Thus, a stair structure 68 is formed. The stair structure includes a stack of alternating conductive layers 54 and dielectric layers 52. The lower conductive layers 54 are longer and extend laterally beyond the upper conductive layers 54, and the length of each conductive layer 54 increases in a direction toward the substrate 50. For example, conductive layer 54A may be longer than conductive layer 54B; conductive layer 54B may be longer than conductive layer 54C; conductive layer 54C may be longer than conductive layer 54D; and conductive layer 54D may be longer than conductive layer 54E. As a result, in subsequent processing steps, conductive contact may be made from above the stair structure 68 to each conductive layer 54.

[0040] exist Fig.13A and Fig. 13BIn the embodiment of the present invention, an intermetallic dielectric (IMD) 70 is deposited above the multilayer stack 58. The IMD 70 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. The IMD 70 extends along the sidewalls of the conductive layers 54E, 54D, 54C, and 54B and the sidewalls of the dielectric layers 52D, 52C, and 52B. In addition, the IMD 70 can contact the top surface of each dielectric layer 52.

[0041] exist Fig.14A and Fig. 14B In the embodiment of the present invention, a removal process is then applied to IMD 70 to remove excess dielectric material above multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc. may be utilized. The planarization process exposes multilayer stack 58 so that after the planarization process is completed, the top surfaces of multilayer stack 58 and IMD 70 are flush.

[0042] exist FIG. 15A to FIG. 18C In the embodiment, trenches are formed in the multilayer stack 58, thereby defining conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may further provide gate electrodes of the resulting TFTs of the memory array 200. FIG. 15A to FIG. 18C The figure ending with "A" shows a perspective view, and the figure ending with "B" shows a perspective view along the Figure 1A The cross-sectional view of the line BB' and the figure ending with "C" shows the cross-sectional view along the line BB'. Figure 1A For ease of explanation, Fig.15A , Fig.16A and Fig.17A Region 200A is shown (see Fig. 14B ) in a portion of a multilayer stack 58.

[0043] exist Fig.15A , Fig. 15B and Fig. 15C In the embodiment of the present invention, a hard mask layer 80 is deposited over the multilayer stack 58 and the intermetallic dielectric 70. The hard mask layer 80 may include, for example, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, PVD, ALD, PECVD, etc. A photoresist 82 is formed over the hard mask layer 80 and the photoresist 82 is patterned. The photoresist 82 may be formed by using a spin coating technique, and the photoresist 82 may be patterned using an acceptable photolithography technique.

[0044] exist Fig.16A , Fig. 16B and Fig. 16C In the embodiment of the present invention, the pattern of the photoresist 82 is transferred to the hard mask layer 80 using an acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. Thus, trenches 86 are formed in the hard mask layer 80 to form a hard mask 84.

[0045] exist Fig.17A , Fig. 17B and Fig. 17C In the embodiment of the present invention, the pattern of the hard mask 84 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process can be anisotropic. Therefore, the trench 86 extends through the multilayer stack 58, and the conductive lines 72 (e.g., word lines) are formed from the conductive layer 54. By etching the trench 86 through the conductive layer 54, adjacent conductive lines 72 can be separated from each other. Subsequently, in Fig.18A , Fig.18B and Fig. 18C The hard mask 84 may then be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, or the like.

[0046] Figures 19 to 25 TFT 204 is shown in trench 86 (see Figure 1A ) is formed and patterned in the channel region. Figures 19 to 25 In, along Figure 1A Line CC' provides a cross-sectional view.

[0047] exist Fig.19 In the embodiment, FE material 90 is conformally deposited in trench 86. FE material 90 may be a material that can be switched between two different polarization directions by applying an appropriate voltage difference across FE material 90. For example, FE material 90 may be a high-k dielectric material, such as a hafnium (Hf)-based dielectric material. In some embodiments, FE material 90 includes hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, and the like. In other embodiments, FE material 90 may include a plurality of SiO2-doped ferrites disposed between two SiO2-doped ferrites. x SiN between layers x In other embodiments, the FE material 90 may include different ferroelectric materials or different types of memory materials. The FE material 90 may be deposited by CVD, PVD, ALD, PECVD, etc. to extend along the sidewalls and bottom surface of the trench 86.

[0048] exist Fig. 20In the embodiment, the OS layer 92 is conformally deposited in the trench 86 above the FE material 90. The OS layer 92 includes a plurality of layers suitable for providing a plurality of TFTs (e.g., TFT 204, see Figure 1A ) provides a material for the channel region. In some embodiments, the OS layer 92 includes an indium-containing material, such as In x Ga y Zn z MO, where M can be Ti, Al, Ag, Si, Sn, etc. Each of X, Y and Z can be any value between 0 and 1.

[0049] The OS layer 92 may have a varying concentration of semiconductor elements (eg, indium), and the concentration of the semiconductor elements may increase in a direction toward the FE material 90. Fig. 20 As shown in the embodiment of FIG. 1 , the OS layer 92 may have a three-layer structure including a bottom OS layer 92A, an intermediate OS layer 92B located above the bottom OS layer 92A and forming an interface with the bottom OS layer 92A, and a top OS layer 92C located above the intermediate OS layer 92B and forming an interface with the intermediate OS layer 92B. The indium concentration of the bottom OS layer 92A may be higher than the indium concentration of the intermediate OS layer 92B, and the indium concentration of the intermediate OS layer 92B may be higher than the indium concentration of the top OS layer 92C. Each of the OS layers 92A, 92B, and 92C may include an indium-containing material, such as In x Ga y Zn z MO, where M can be Ti, Al, Ag, Si, Sn, etc. Each of OS layers 92A, 92B, and 92C can be individually deposited over FE material 90 using a conformal deposition process such as CVD, ALD, PECVD, etc., such that the resulting OS layer 92 extends along the sidewalls and bottom surface of trench 86. For example, the OS layer 92A, 92B, and 92C can be deposited separately ... x The indium concentration of each of OS layers 92A, 92B, and 92C is adjusted by supplying and flowing (3-dimethylaminopropynyl)-dimethylindium (DADI), etc.) to the deposition chamber. After depositing OS layer 92, an annealing step may be performed at 300° C. to 450° C. in an oxygen-related environment to activate charge carriers of OS layer 92.

[0050] In some embodiments, the indium concentration of bottom OS layer 92A may be in the range of about 40% to about 100% of the maximum indium concentration of OS layer 92; the indium concentration of middle OS layer 92B may be in the range of about 20% to about 40% of the maximum indium concentration of OS layer 92; and the indium concentration of top OS layer 92C may be less than 20% of the maximum indium concentration of OS layer 92. In some embodiments, the maximum indium concentration of OS layer 92 may be in the range of about 10% to about 45%, and the charge carrier concentration in OS layer 92 may be about 10 14 cm -3 Up to 10 20 cm -3 In addition, the combined thickness of the top OS layer 92C and the middle OS layer 92B (eg, thickness T1 plus thickness T2) may be greater than the thickness of the bottom OS layer 92A.

[0051] By providing three discrete indium concentration regions in the OS layer 92 within the above ranges, advantages can be achieved. For example, a high concentration of indium in the bottom OS layer 92A provides a higher charge carrier concentration in the resulting channel region, which advantageously increases carrier mobility. For example, by providing a sufficiently high indium concentration in the bottom OS layer 92A, mobility can be increased from approximately 20 cm 2 / Vs increases to about 40cm 2 / Vs. In addition, the middle OS layer 92B can be used as a barrier layer to prevent or at least reduce electron scattering from the bottom OS layer 92A. For example, the middle OS layer 92B can be used as a transition interface layer between the bottom OS layer 92A and the top OS layer 92C of different indium concentrations, which reduces undesirable lattice mismatch and scattering. As a result, the mobility in the resulting channel can be increased. The top OS layer 92A can be used as a passivation layer that protects the underlying OS layer (e.g., the bottom OS layer 92C) from process damage and passivates the oxygen defects in the underlying OS layer (e.g., the middle OS layer 92B and the bottom OS layer 92A). For example, due to its relatively high indium concentration, the surface of the bottom OS layer 92A may be more susceptible to process damage (e.g., water absorption, etching damage, metal diffusion, undesirable interface layer formation with adjacent oxide layers, etc.), while the top OS layer 92C is not susceptible to such damage due to its reduced indium concentration (e.g., within the above range). Therefore, the top OS layer 92C can protect the underlying layers from the adverse effects of subsequent processing.

[0052] exist Fig.21 , dielectric layer 98A is deposited in trench 86 above OS layer 92. Dielectric layer 98A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric layer 98A may extend along the sidewalls and bottom surface of trench 86 above OS layer 92.

[0053] exist Fig. 22 In the embodiment of the present invention, a lateral portion of the dielectric layer 98A in the trench 86 is removed, for example, using a combination of photolithography and etching. The etching can be any acceptable etching process, such as by wet etching or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic.

[0054] Then, as Fig. 22 As shown, dielectric layer 98A may be used as an etch mask to etch through the bottom portion of OS layer 92 in trench 86. The etching may be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The etching may include using an etchant that etches the material of OS layer 92 without significantly etching the underlying FE material 90. Thus, FE material 90 may be used as an etch stop layer when patterning OS layer 92. Etching OS layer 92 may expose portions of FE material 90 on the bottom surface of trench 86. Thus, portions of OS layer 92 located on opposite sidewalls of trench 86 may be separated from each other, which improves the memory array 200 (see Figure 1A ) between memory cells 202.

[0055] exist Fig.23 In the embodiment of the present invention, additional dielectric material 98B may be deposited to fill the remaining portion of trench 86. Dielectric material 98B may have the same material composition as dielectric layer 98A and may be formed using the same process as dielectric layer 98A. Hereinafter, dielectric material 98B and dielectric layer 98A may be collectively referred to as dielectric material 98.

[0056] exist Fig.24 In the embodiment of the present invention, a removal process is then applied to dielectric material 98, OS layer 92, and FE material 90 to remove excess material above multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc. may be utilized. The planarization process exposes multilayer stack 58 so that after the planarization process is completed, the top surfaces of multilayer stack 58 and dielectric material 98 are flush. Fig.25 Shows Fig.24 The corresponding top view of the structure is shown in .

[0057] FIG. 26A to FIG. 29B An intermediate step in fabricating conductive lines 106 and 108 (e.g., source lines and bit lines) in memory array 200 is shown. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive line 72 so that individual cells of memory array 200 may be selected for read and write operations. FIG. 26A to FIG. 27BThe figures ending with "A" show the top view, while the figures ending with "B" show the Figure 1A The corresponding cross-sectional view of the line D-D'. FIG. 28A to FIG. 29B The figures ending with "A" show the top view, while the figures ending with "B" show the Figure 1A Corresponding cross-sectional view along line CC'.

[0058] exist Fig.26A and Fig.26B In the embodiment, trenches 100 are patterned through the OS layer 92 and the dielectric material 98 . Fig.26B Shows Fig.26A 1-1 '. For example, the patterning of the trench 100 may be performed by a combination of photolithography and etching. The trench 100 may be disposed between opposing sidewalls of the FE material 90, and the trench 100 may physically separate adjacent stacks of memory cells in the memory array 200 (see FIG. Fig.26B ).

[0059] exist Fig.27A and Fig.27B In the embodiment of the present invention, a dielectric material 102 is deposited in the trench 100 and fills the trench 100 . Fig.27B Shows Fig.27A . The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The dielectric material 102 may extend along the sidewalls and bottom surface of the trench 86 above the OS layer 92. After deposition, a planarization process (e.g., CMP, etch back, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of the multilayer stack 58, the FE material 90, the OS layer 92, and the dielectric material 102 may be substantially flush (e.g., within process variations). In some embodiments, the materials of the dielectric materials 98 and 102 may be selected so that they may be selectively etched relative to each other. For example, in some embodiments, the dielectric material 98 is an oxide and the dielectric material 102 is a nitride, the dielectric material 98 is a nitride, and the dielectric material 102 is an oxide. Other materials are also possible.

[0060] exist Fig.28A and Fig.28B In the embodiment of the present invention, trenches 104 are patterned for conductive lines 106 and 108 . Fig.28B Shows Fig.28A104. For example, the dielectric material 98 is patterned using a combination of photolithography and etching to pattern the trench 104. The etching can be any acceptable etching process, such as by wet etching or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. The etching process can use an etchant that etches the dielectric material 98 without significantly etching the dielectric material 102. The pattern of the trench 104 can correspond to the conductive lines 106 and 108 (see FIG. Fig.29A and Fig.29B ). For example, portions of dielectric material 98 may remain between each pair of trenches 104 , and dielectric material 102 may be disposed between adjacent pairs of trenches 104 .

[0061] exist Fig.29A and Fig.29B In the embodiment of the present invention, trench 104 is filled with a conductive material to form conductive lines 106 and 108 . Fig.29B Shows Fig.29A Top view of line CC' in . Each of the conductors 106 and 108 may include a conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, each of which may be formed using, for example, CVD, ALD, PVD, PECVD, and the like. After depositing the conductor 106 and the conductive material, planarization (e.g., CMP, etch back, etc.) may be performed to remove excess portions of the conductive material, thereby forming the conductors 106 and 108. As a resultant structure, the top surfaces of the multilayer stack 58, the FE material 90, the OS layer 92, the conductor 106, and the conductor 108 may be substantially flush (e.g., within process variations). The conductor 106 may correspond to a bit line in a memory array, and the conductor 108 may correspond to a source line in the memory array 200. In addition, the conductors 106 and 108 may provide source / drain electrodes for the TFTs in the memory array 200. Although Fig.29B A cross-sectional view showing only conductor 106 is shown, but a cross-sectional view of conductor 108 may be similar.

[0062] like Fig.29A and Fig.29B As shown, dielectric material 98 may be disposed between conductive lines 106 and 108 and separate adjacent conductive lines 106 and 108. In addition, pairs of conductive lines 106 and 108 are separated by dielectric material 102. Each of the longitudinal axes of conductive lines 106 and 108 extends vertically in a direction perpendicular to the major surface of substrate 50. In this manner, vertical columns of stacked memory cells 202 in memory array 200 may share common conductive lines 106 and common conductive lines 108.

[0063] Then, if Fig. 30A , Fig. 30B and Fig. 30CAs shown, contacts may be made to each of wire 72 , wire 106 , and wire 108 . Fig. 30A shows a perspective view of a memory array 200; Fig. 30B shows a top view of memory array 200; and Fig. 30C Shown along Fig. 30A 30C'-30C' of the device and the substrate below. In some embodiments, a conductive contact 110 can be made to the exposed surface of each conductive line 72. The stepped shape of the conductive line 72 can provide a surface on each conductive line 72 for the conductive contact 110 to fall on. Conductive contacts 112 and 114 can be made to the top surfaces of the conductive lines 106 and 108, respectively. Conductive contacts 110, 112 and 114 can be electrically connected to conductive lines 116A, 116B and 116C, respectively, and conductive lines 116A, 116B and 116C connect the memory array to the active devices below and / or signal lines, power lines and ground lines in the semiconductor die. For example, conductive vias 118 can extend through IMD 70 to electrically connect conductive line 116C to the circuits of the interconnect structure 220 below and the active devices on the substrate 50. In an alternative embodiment, routing lines and / or power lines to and from the memory array may be provided by an interconnect structure formed above the memory array 200 in addition to or in place of the interconnect structure 220. Thus, a memory array 200 having a three-layer semiconductor channel region may be completed. The three-layer semiconductor channel region may be disposed in an interconnect structure above the active devices at the top surface of the substrate 50.

[0064] Although Figures 2 to 30C The embodiments shown in FIG. 1 show a particular pattern of conductors 106 and 108, but other configurations are possible. For example, in these embodiments, the conductors 106 and 108 in the same row of the array are all aligned with each other. In some embodiments, the conductors 106 and 108 in a row have a pattern such as Fig.31A and Fig.31B The staggered pattern shown. Fig.31A A top view is shown, and Fig.31B Shown along Fig.31A A cross-sectional view of the line C-C'. Fig.31A and Fig.31B In the drawings, the same reference numerals denote Figures 2 to 30C The same components are formed by the same process.

[0065] In addition, although Figures 2 to 30C The embodiment of FIG. 1 shows that the OS layer 92 has three separately formed layers (eg, a bottom OS layer 92A, a middle OS layer 92B, and a top OS layer 92C), but in other embodiments, such as Fig.32A and Fig.32BAs shown, the OS layer 92 may be a single layer having a gradient semiconductor element (eg, indium) concentration.

[0066] exist Fig.32A and Fig.32B In the drawings, the same reference numerals denote Figures 2 to 30C However, OS layer 92 is a single layer with a gradient indium concentration (e.g., without any internal interface). For example, the indium concentration of OS layer 92 may decrease in the direction of arrow 120 (e.g., away from wire 72, toward wires 106 and 108). The change in indium concentration is determined by Fig.33 Line 122 of the diagram further shows that Fig.33 The indium concentration in OS layer 92 along line 120 is shown.

[0067] In some embodiments, the indium concentration of region 92D (e.g., a region adjacent to FE material 90) may be in a range of about 40% to about 100% of the maximum indium concentration of OS layer 92; the indium concentration of OS layer 92E (e.g., in the middle of OS layer 92) may be in a range of about 20% to about 40% of the maximum indium concentration of OS layer 92; and the indium concentration of region 92F (e.g., a region adjacent to conductive lines 106 and 108) may be less than 20% of the maximum indium concentration of OS layer 92. In some embodiments, the maximum indium concentration of OS layer 92 may be in a range of about 10% to about 45%, and the charge carrier concentration in OS layer 92 may be about 10%. 14 cm -3 Up to 10 20 cm -3 By providing three discrete indium concentration regions in the OS layer 92 within the above range, the above advantages such as increased mobility in the channel region of the TFT, reduced electron scattering, and reduced manufacturing defects can be achieved.

[0068] Various embodiments provide a 3D memory array with a plurality of vertically stacked memory cells. Each TFT also includes a FE gate dielectric layer and an OS material located in the channel region. The OS material may have at least three different regions, each region having a different semiconductor element (e.g., indium) concentration. Advantages may be achieved by providing at least three different concentrations of semiconductor elements. For example, by making the semiconductor element closest to the gate electrode have a relatively high concentration, the carrier mobility in the channel region may be increased. By making the semiconductor element have a relatively low concentration at the exposed surface of the channel region, process damage during subsequent processing of the channel region may be reduced. In addition, by including a medium concentration of semiconductor elements between a relatively low concentration region and a relatively high concentration region in the channel region, electron scattering between low concentration regions and high concentration regions may be reduced. Therefore, device performance may be improved by reducing manufacturing defects.

[0069] In some embodiments, the memory cell includes a ferroelectric (FE) material in contact with a word line; and an oxide semiconductor (OS) layer in contact with a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer includes: a first region adjacent to the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent to the source line, the second region having a second concentration of a semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of a semiconductor element, the third concentration being greater than the second concentration and less than the first concentration. Optionally, in some embodiments, the semiconductor element is indium. Optionally, in some embodiments, the OS layer includes In x Ga y Zn z MO, wherein M is Ti, Al, Ag, Si or Sn, and each of x, y and z is a number between 0 and 1. Optionally, in some embodiments, the first region is located in the first semiconductor layer, the second region is located in the second semiconductor layer, and the third region is located in the third semiconductor layer, the third semiconductor layer forms an interface with the first semiconductor layer, and the third semiconductor layer forms an interface with the second semiconductor layer. Optionally, in some embodiments, the second semiconductor layer extends continuously from the source line to the bit line. Optionally, in some embodiments, the OS layer has a gradient concentration of semiconductor elements that decreases in a direction away from the FE material. Optionally, in some embodiments, the longitudinal axis of the word line extends parallel to the main surface of the semiconductor substrate, the longitudinal axis of the source line extends perpendicular to the main surface of the semiconductor substrate, and the longitudinal axis of the bit line extends perpendicular to the main surface of the semiconductor substrate.

[0070] In some embodiments, a device includes: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell including a first thin film transistor, wherein the first thin film transistor includes: a first portion of a ferroelectric material, the first portion of the ferroelectric material in contact with a first word line; and a first channel region includes: a first portion of a first semiconductor layer in contact with the ferroelectric material; and a first portion of a second semiconductor layer in contact with the first semiconductor layer, the first semiconductor layer having an indium concentration greater than that of the second semiconductor layer; and a first portion of a third semiconductor layer in contact with the second semiconductor layer, the indium concentration of the third semiconductor layer being less than that of the second semiconductor layer; and a second memory cell located above the first memory cell. Optionally, in some embodiments, the third semiconductor layer is in contact with a source line and a bit line. Optionally, in some embodiments, each of the source line and the bit line extends in a direction perpendicular to a main surface of the semiconductor substrate. Optionally, in some embodiments, the second memory cell includes: a second portion of a ferroelectric material, the second portion of the ferroelectric material in contact with a second word line different from the first word line; and the second channel region includes: a second portion of the first semiconductor layer; a second portion of the second semiconductor layer; and a second portion of the third semiconductor layer. Optionally, in some embodiments, the second word line is disposed above the first word line, and the dielectric material separates the second word line from the first word line. Optionally, in some embodiments, the first word line is longer than the second word line. Optionally, in some embodiments, each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends continuously from the first channel region to the second channel region. Optionally, in some embodiments, each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes In x Ga y Zn z MO, wherein M is Ti, Al, Ag, Si or Sn, and each of x, y and z is a number between 0 and 1.

[0071] In some embodiments, a method includes: patterning a first trench, the first trench extending through a first conductive line; depositing a ferroelectric (FE) material along the sidewalls and bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the FE material, the OS layer extending along the sidewalls and bottom surface of the first trench, depositing the OS layer includes: depositing a first region of the OS layer over the FE material, the first region having a first concentration of a semiconductor element; depositing a second region of the OS layer over the first region of the OS layer, the second region having a second concentration of the semiconductor element, the second concentration of the semiconductor element being less than the first concentration of the semiconductor element; and depositing a third region of the OS layer over the second region of the OS layer, the third region having a third concentration of the semiconductor element, the third concentration being less than the second concentration. Optionally, in some embodiments, the semiconductor element is indium. Optionally, in some embodiments, the method also includes removing a portion of the OS layer along the bottom surface of the first trench; and filling the remaining portion of the first trench with a first dielectric material. Optionally, in some embodiments, the method further comprises patterning a second trench in the first dielectric material; filling the second trench with a second dielectric material; patterning a third trench and a fourth trench in the second dielectric material; and filling the third trench and the fourth trench with a conductive material to form a second conductive line and a third conductive line. Optionally, in some embodiments, the first trench extends through a multilayer stack, the multilayer stack comprises a plurality of stacked conductive lines, the plurality of stacked conductive lines comprising the first conductive line.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A memory cell, comprising: Ferroelectric (FE) material, contacting the word line; as well as an oxide semiconductor (OS) layer in contact with a source line and a bit line, wherein the ferroelectric material is disposed between the oxide semiconductor layer and the word line; and wherein the oxide semiconductor layer comprises: a first region adjacent to the ferroelectric material, the first region having a first concentration of a semiconductor element, wherein the semiconductor element is indium; a second region, adjacent to the source line, the second region having a second concentration of the semiconductor element; and a third region located between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration being greater than the second concentration and less than the first concentration, wherein the longitudinal axis of the word line extends parallel to the main surface of the semiconductor substrate, the longitudinal axis of the source line extends perpendicular to the main surface of the semiconductor substrate, and the longitudinal axis of the bit line extends perpendicular to the main surface of the semiconductor substrate, The oxide semiconductor layer has a gradient concentration of the semiconductor element that decreases in a direction away from the ferroelectric material.

2. The memory cell according to claim 1, wherein: The first concentration is between 40% and 100% of the maximum concentration of the oxide semiconductor layer.

3. The memory cell according to claim 2, wherein: The oxide semiconductor layer includes In x Ga y Zn z MO, wherein M is Ti, Al, Ag, Si or Sn, and each of x, y and z is a number between 0 and 1.

4. The memory cell according to claim 1, wherein: The first region is located in a first semiconductor layer, the second region is located in a second semiconductor layer, and the third region is located in a third semiconductor layer, the third semiconductor layer forms an interface with the first semiconductor layer, and the third semiconductor layer forms an interface with the second semiconductor layer.

5. The memory cell according to claim 4, wherein: The second semiconductor layer continuously extends from the source line to the bit line.

6. The memory cell according to claim 1, wherein: The combined thickness of the second region and the third region is greater than the thickness of the first region.

7. The memory cell according to claim 4, wherein: The indium concentration of the first semiconductor layer is at least 40%.

8. A semiconductor device comprising: Semiconductor substrate; A first memory unit is located above the semiconductor substrate, wherein the first memory unit includes a first thin film transistor, wherein the first thin film transistor includes: a first portion of a ferroelectric material, the first portion of the ferroelectric material contacting a first word line; and A first channel region, wherein the first channel region comprises: a first portion of the first semiconductor layer in contact with the ferroelectric material; a first portion of a second semiconductor layer in contact with the first semiconductor layer, the first semiconductor layer having an indium concentration greater than an indium concentration of the second semiconductor layer; and a first portion of a third semiconductor layer in contact with the second semiconductor layer, wherein an indium concentration of the third semiconductor layer is less than an indium concentration of the second semiconductor layer; and a second memory unit, located above the first memory unit, The first channel region has an indium concentration that decreases in a direction away from the ferroelectric material.

9. The semiconductor device according to claim 8, wherein: The third semiconductor layer contacts the source line and the bit line.

10. The semiconductor device according to claim 9, wherein Each of the source line and the bit line extends in a direction perpendicular to a main surface of the semiconductor substrate.

11. The semiconductor device according to claim 8, wherein The second memory unit comprises: a second portion of the ferroelectric material, the second portion of the ferroelectric material contacting a second word line different from the first word line; and A second channel region, wherein the second channel region comprises: a second portion of the first semiconductor layer; a second portion of the second semiconductor layer; and a second portion of the third semiconductor layer.

12. The semiconductor device according to claim 11, wherein The second word line is disposed above the first word line, and a dielectric material separates the second word line from the first word line.

13. The semiconductor device according to claim 11, wherein The first word line is longer than the second word line.

14. The semiconductor device according to claim 11, wherein Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer continuously extends from the first channel region to the second channel region.

15. The semiconductor device according to claim 8, wherein Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes In x Ga y Zn z MO, wherein M is Ti, Al, Ag, Si or Sn, and each of x, y and z is a number between 0 and 1.

16. A method of forming a semiconductor device, comprising: patterning a first trench extending through a first conductive line; depositing a ferroelectric (FE) material along the sidewalls and bottom surface of the first trench; Depositing an oxide semiconductor (OS) layer over the ferroelectric material, wherein the oxide semiconductor layer extends along the sidewalls and the bottom surface of the first trench, wherein depositing the oxide semiconductor layer comprises: depositing a first region of the oxide semiconductor layer over the ferroelectric material, the first region having a first concentration of a semiconductor element, wherein the semiconductor element is indium; depositing a second region of the oxide semiconductor layer over the first region of the oxide semiconductor layer, the second region having a second concentration of the semiconductor element, the second concentration of the semiconductor element being less than the first concentration of the semiconductor element; and A third region of the oxide semiconductor layer is deposited over the second region of the oxide semiconductor layer, the third region having a third concentration of the semiconductor element, the third concentration being lower than the second concentration.

17. The method according to claim 16, wherein: The first concentration is between 40% and 100% of the maximum concentration of the oxide semiconductor layer.

18. The method according to claim 16, further comprising: removing a portion of the oxide semiconductor layer along the bottom surface of the first trench; as well as The remaining portion of the first trench is filled with a first dielectric material.

19. The method according to claim 18, further comprising: patterning a second trench in the first dielectric material; filling the second trench with a second dielectric material; patterning a third trench and a fourth trench in the second dielectric material; as well as The third trench and the fourth trench are filled with a conductive material to form a second conductive line and a third conductive line.

20. The method according to claim 18, wherein: The first trench extends through a multi-layer stack including a plurality of stacked conductive lines including the first conductive line.

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