Storage device and method of triggering a response to a command issued to the storage device

Abstract

A storage device and a method of triggering a response to a command issued by a host device to the storage device are disclosed. The storage device includes a storage controller to receive one or more notifications corresponding to host data transferred from the host device to the storage device over a storage interface and a response circuit coupled to the storage controller to trigger a response to the host device and including a first counter to track the one or more notifications corresponding to all of the host data in a manner that each notification corresponds to a portion of the host data, a second counter to track one or more acknowledgements received from the storage controller corresponding to the one or more notifications in a manner that each acknowledgement corresponds to one notification, and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Description

[0001] This application claims priority and benefit to U.S. Provisional Application No. 62 / 988,214, filed March 11, 2020, entitled “Storage Device with Configurable Command Response Trigger”, and U.S. Non-Provisional Application No. 16 / 834,584, filed March 30, 2020, entitled “Storage Device with Configurable Command Response Trigger”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more exemplary embodiments of this disclosure relate to storage devices, and more specifically, to storage devices having configurable command response triggers and methods including the storage device. Background Technology

[0003] A storage system typically includes a host device and one or more storage devices. The host device can store data in the storage device by sending commands to it. For example, the host device can send a write command (WRITE command) to the storage device to store the host data corresponding to the write command. In this case, the write command can include several phases, such as a command issuance phase, a data transfer phase, and a response phase. During the command issuance phase, the host device can issue the write command to the storage device, and during the data transfer phase, the host device can transfer the host data to the storage device. Once all the host data has been written to the storage device, the storage device can send a response to the host device during the response phase, indicating that the write command was successfully completed.

[0004] The information disclosed in this background section is intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] Technical issues

[0006] The purpose of this disclosure is to provide a storage device and method thereof with reduced latency and improved throughput.

[0007] Technical solution

[0008] One or more embodiments of this disclosure relate to a storage device including a hardware module (e.g., response circuitry) with configurable command response triggers. The hardware module can track various state information of host data as host data is transferred to the storage device, and can automatically send appropriate responses to the host device based on the state information of the host data, instead of using hardware or software (e.g., a processor executing instructions) to maintain state information and initiate response transmissions. Therefore, latency can be reduced and / or the throughput of the storage device can be improved.

[0009] According to one or more embodiments of this disclosure, a storage device includes a storage controller, a storage memory, and response circuitry connected to the storage controller. The storage controller is configured to receive one or more notifications corresponding to host data transmitted to the storage device from a host device via a storage interface. The response circuitry is configured to trigger a response to the host device and includes: a first counter configured to track the one or more notifications, the one or more notifications corresponding to all the host data such that each notification corresponds to a portion of the host data; a second counter configured to track one or more acknowledgments received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each acknowledgment corresponds to one of the one or more notifications; and a response trigger configured to select one of the first counter and the second counter to trigger a response to the host device. The response circuitry is configured to send a response to the host device based on the state of the selected counter of the first counter and the second counter.

[0010] In an example embodiment, the state may correspond to the count value of the selected counter among the first counter and the second counter.

[0011] In an example implementation, the count value can be initialized based on the command transmission length associated with the host data.

[0012] In an example embodiment, the first counter may be one of a first counter and a second counter, and the count value of the first counter may be decremented for each of the one or more notifications sent to the storage controller.

[0013] In an example embodiment, the response trigger may include a comparator, and the comparator may be configured to compare a count value with a threshold.

[0014] In an example embodiment, the response circuit can be configured to determine that host data has been received and notified in response to a count value equal to a threshold.

[0015] In an example embodiment, the second counter may be one of the first and second counters, and the count value of the second counter may be decremented for each of the one or more acknowledgments received from the storage controller.

[0016] In an example embodiment, the storage controller may be configured to send one of the one or more acknowledgments in response to processing a corresponding notification.

[0017] In an example embodiment, the response trigger may include a comparator that can be configured to compare a count value with a threshold, and the response circuitry can be configured to determine that host data has been processed by the storage controller in response to the count value being equal to the threshold.

[0018] In an example embodiment, the storage controller may be configured to persistently store host data in storage memory, at least in part, based on notifications.

[0019] According to one or more example embodiments of this disclosure, a method for triggering a response to a command issued by a host device to a storage device includes receiving one or more notifications by a storage controller, triggering a response to the host device by response circuitry connected to the storage controller, the one or more notifications corresponding to host data transmitted from the host device to the storage device via a storage interface, the host data corresponding to the command, wherein the triggering step includes: tracking the one or more notifications by a first counter of the response circuitry, the one or more notifications corresponding to all the host data such that each notification corresponds to a portion of the host data; receiving one or more acknowledgments from the storage controller by the response circuitry, the one or more acknowledgments corresponding to the one or more notifications such that each acknowledgment corresponds to one of the one or more notifications; tracking the acknowledgments by a second counter of the response circuitry; selecting one of the first counter and the second counter by a response trigger of the response circuitry to trigger a response; and sending a response to the host device by the response circuitry based on the state of the selected counter among the first counter and the second counter.

[0020] In an example embodiment, the state may correspond to the count value of the selected counter among the first counter and the second counter.

[0021] In an example embodiment, the method may further include: initializing a count value by a response circuit based on a command transmission length associated with host data.

[0022] In an example embodiment, the first counter may be one of a first counter and a second counter, and the method may further include: decrementing the count value of the first counter by a response circuit for each of the one or more notifications sent to the storage controller.

[0023] In an example embodiment, the response trigger may include a comparator, and the method may further include comparing a count value with a threshold by the comparator.

[0024] In an example embodiment, the method may further include: a response circuit determining that host data has been received and notified in response to a count value equal to a threshold.

[0025] In an example embodiment, the second counter may be a selected counter among the first and second counters, and the method may further include: decrementing the count value of the second counter by a response circuit for each of the one or more acknowledgments received from the storage controller.

[0026] In an example embodiment, the method may further include: processing a corresponding notification among the one or more notifications by a storage controller; and sending one of the one or more acknowledgments by the storage controller in response to processing the corresponding notification.

[0027] In an example embodiment, the response trigger may include a comparator, and the method may further include: comparing a count value with a threshold by the comparator; and determining, by the response circuitry, that host data has been processed by the storage controller in response to the count value being equal to the threshold.

[0028] In an example embodiment, the method may further include: persistently storing host data in a storage memory by a storage controller, at least in part, based on a notification.

[0029] Technical effect

[0030] According to one or more example embodiments of this disclosure, a storage device may include hardware modules (e.g., response circuitry) to track one or more states of host data transmitted from a host device to the storage device, instead of using firmware or software (e.g., a processor executing instructions, such as a storage controller) to maintain and process the state information of the host data. Therefore, latency can be reduced and / or the throughput of the storage device can be improved. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

[0032] Figure 1This is a system diagram of a storage system according to one or more exemplary embodiments of the present disclosure.

[0033] Figure 2 This is a block diagram of the response circuitry of a storage device according to one or more exemplary embodiments of the present disclosure.

[0034] Figure 3 This is a schematic circuit diagram illustrating a configurable command response trigger of a response circuit according to one or more example embodiments of the present disclosure.

[0035] Figure 4 This is a flowchart of a method for generating a response to a write command according to one or more example embodiments of the present disclosure. Detailed Implementation

[0036] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout denote the same elements. However, this disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description need not be repeated.

[0037] Typically, the command issuance phase, data transfer phase, and response phase are completed sequentially according to the storage interface (e.g., interface bus), such that the processor (e.g., storage controller and / or general-purpose processor, etc.) using the instructions executed thereon (e.g., firmware and / or software, etc.) maintains state information of the host data during the data transfer phase to determine when all host data has been received and stored. Once the processor determines that all host data has been received and stored, it can initiate sending a response back to the host device, indicating that the command was successfully executed. However, in this case, having the processor maintain state information and initiate responses may introduce latency and / or potentially reduce the throughput of the storage device (e.g., total throughput).

[0038] According to one or more example embodiments of this disclosure, a storage device may include a hardware module (e.g., response circuitry) for tracking state information of host data as it is transferred to the storage device, instead of using firmware or software (e.g., a processor executing instructions, such as a storage controller) to maintain and process the state information of the host data. In some embodiments, the hardware module may include a configurable command response trigger (or “configurable command response trigger”) for providing an appropriate response to the host device based on various different states of the host data being transferred to the storage device and the configuration of the command response trigger. Therefore, latency (e.g., processing time) can be reduced, and / or the throughput of the storage device can be improved.

[0039] In some embodiments, the command response triggers can be dynamically configured based on various characteristics of the storage device 104 and / or host data (e.g., implementation, application, data type, acceptability of data loss, operational health, and / or user requirements (e.g., Service Level Agreement, etc.)). Therefore, in some embodiments, taking into account various characteristics of the storage device and / or host data, and based on a balance between the expected or suitable performance of the storage device and the expected or suitable reliability, the command response triggers of the hardware module can be dynamically configured at start time, runtime, and / or based on each command. These and other aspects and features of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0040] Figure 1 This is a system diagram of a storage system according to one or more exemplary embodiments of the present disclosure.

[0041] In short, a storage system 100 according to one or more embodiments of this disclosure may include a host device (e.g., a host computer) 102 and a storage device 104. The host device 102 may issue a command to the storage device 104, causing the storage device 104 to store host data associated with that command. For example, the host device 102 may (e.g., via storage interface 110) be communicatively connected to the storage device 104 and may issue a write command (WRITE command) to the storage device 104, causing the host data corresponding to the write command to be transferred and stored in the storage device 104 (e.g., written to the storage device 104). Once all host data has been successfully received and / or stored, the storage device 104 may send an appropriate response to the host device 102, indicating that the command was successfully executed.

[0042] In one or more example embodiments, storage device 104 may include a hardware module (e.g., response circuitry 112) for tracking the status information of host data as it is transmitted to storage device 104, instead of using firmware or software (e.g., a processor executing instructions, such as storage controller 114) to maintain and process the status information of the host data. For example, the hardware module (e.g., response circuitry 112) can automatically send an appropriate response back to host device 102 based on the status information of the host data being transmitted, instead of waiting for firmware or software to maintain and process the status information corresponding to the host data transmission to determine when to initiate sending a response back to host device 102. Therefore, latency (e.g., processing time) can be reduced, and / or the throughput of storage device 104 can be improved.

[0043] In one or more example embodiments, a hardware module (e.g., response circuitry 112) may include a configurable command response trigger for providing an appropriate response to the host device 102 based on various states of host data being transmitted to the storage device 104 and the configuration of the command response trigger. For example, an earlier response (e.g., when in a state where all host data has been received but before it is actually stored in persistent memory) may improve performance (e.g., increase speed) but may also reduce reliability (e.g., increase the risk of data loss), while a later response (e.g., when in a state where all host data has been stored in persistent memory) may reduce the risk of data loss but may also increase latency. Therefore, in some embodiments, the command response trigger may be configured to balance the performance and reliability of the storage device 104.

[0044] In one or more example embodiments, the command response trigger can be dynamically configured based on various characteristics of storage device 104 and / or host data, such as implementation, application, data type, acceptability of data loss, operational health, and / or user requirements (such as service level agreements (SLAs)). For example, in some embodiments, the internal timing of storage device 104 for each stage can vary depending on the implementation and / or application of storage device 104. As an illustrative example, for storage device 104 implementing a volatile writeback cache, a hardware module (e.g., response circuitry 112) can be configured to send a response to host device 102 after host data has been placed (e.g., temporarily stored) in the volatile data cache, while for storage device 104 not implementing a volatile writeback cache, the hardware module (e.g., response circuitry 112) can first ensure that host data is stored in non-volatile memory before sending a response to host device 102. In the former case, the command response trigger can be configured to cause the hardware module (e.g., response circuit 112) to provide a response to the host device 102 earlier than in the latter case, but the risk of data loss increases compared to the latter case. Therefore, in some embodiments, taking into account the various characteristics of the storage device 104 and / or the host data, and based on the balance between the expected or suitable performance and the expected or suitable reliability of the storage device 104, the command response trigger of the hardware module (e.g., response circuit 112) can be dynamically configured at start time, runtime, and / or based on each command.

[0045] For more details, see [link to relevant documentation]. Figure 1The host device 102 may include a host processor 106 and a host memory 108. The host processor 106 may be a general-purpose processor, such as a central processing unit (CPU) core like that of the host device 102. The host memory 108 can be considered as a high-performance main memory (e.g., a level 1 memory) of the host device 102. For example, in some embodiments, the host memory 108 may include (or may be) volatile memory, such as dynamic random access memory (DRAM). However, this disclosure is not limited thereto, and the host memory 108 may include (or may be) any suitable high-performance main memory (e.g., a level 1 memory) known to those skilled in the art for use in the host device 102. For example, in other embodiments, the host memory 108 may be a relatively high-performance non-volatile memory (such as NAND flash memory, phase-change memory (PCM), resistive RAM, spin-transfer torque RAM (STTRAM), any suitable memory based on PCM technology, memristor technology, and / or resistive random access memory (ReRAM)), and may include, for example, chalcogenides.

[0046] Storage device 104 can be considered as secondary memory capable of persistently storing data accessible by host device 102. In this context, storage device 104 may include (or may be) relatively slow memory compared to the high-performance memory of host memory 108. For example, in some embodiments, storage device 104 may be secondary memory of host device 102, such as a solid-state drive (SSD). However, this disclosure is not limited thereto, and in other embodiments, storage device 104 may include (or may be) any suitable storage device, such as magnetic storage devices (e.g., hard disk drives (HDDs), etc.), optical storage devices (e.g., Blu-ray disc drives, compact disc (CD) drives, digital versatile disc (DVD) drives, etc.) and / or other types of flash memory devices (e.g., USB flash drives, etc.). In various embodiments, storage device 104 may conform to large form factor standards (e.g., 3.5-inch hard disk drive form factor), small form factor standards (e.g., 2.5-inch hard disk drive form factor), M.2 form factor, and / or E1.S form factor, etc. In other embodiments, storage device 104 may conform to any suitable or desired derivative of these form factors. For convenience, storage device 104 may be described in the context of an SSD below, but this disclosure is not limited thereto.

[0047] Storage device 104 can be communicatively connected to host device 102 via storage interface 110. Storage interface 110 can (e.g., using connectors and protocols) facilitate communication between host device 102 and storage device 104. In some embodiments, storage interface 110 can facilitate the exchange and response of storage requests between host device 102 and storage device 104. In some embodiments, storage interface 110 can facilitate data transfer from storage device 104 to host memory 108 of host device 102 and from host memory 108 of host device 102 to storage device 104. For example, in embodiments, storage interface 110 (e.g., connectors and protocols of storage interface 110) may include (or may conform to) Small Computer System Interface (SCSI) and / or Non-Volatile Memory Faster (NVMe), etc. In this case, a write command from host device 102 via storage interface 110 may include a command issuance phase, a data transfer phase, and a response phase. However, this disclosure is not limited thereto. In other embodiments, storage interface 110 (e.g., the connector and protocol of storage interface 110) may conform to other suitable storage interfaces, such as Peripheral Component Interconnect Express (PCIe), Remote Direct Memory Access over Ethernet (RDMA), Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), and / or NVMe over Fabric (NVMe-oF), etc. In other embodiments, storage interface 110 (e.g., the connector and protocol of storage interface 110) may include (or may conform to) various general-purpose interfaces, such as Ethernet and / or Universal Serial Bus (USB), etc. For convenience, storage interface 110 may be described in the context of a SCSI interface below, but this disclosure is not limited thereto.

[0048] In some embodiments, storage device 104 may include storage controller 114 and storage memory 116. Storage controller 114 may be connected to storage interface 110 (e.g., via response circuitry 112) and may respond to input / output (I / O) requests received from host device 102 via storage interface 110. Storage controller 114 may provide an interface to control storage memory 116 and may provide access to and from storage memory 116. For example, storage controller 114 may include at least one processing circuitry embedded thereon for interfacing with host device 102 and storage memory 116. The processing circuitry may include, for example (e.g., via firmware and / or software) digital circuitry (e.g., microcontroller, microprocessor, digital signal processor, or logic device (e.g., field-programmable gate array (FPGA) and / or application-specific integrated circuit (ASIC) etc.)) capable of executing data access instructions, said digital circuitry for providing access to and from data stored in storage memory 116 according to the data access instructions. For example, data access instructions may include any suitable data storage and retrieval algorithm (e.g., read / write) instructions and / or similar instructions. Storage memory 116 may persistently store data received from host device 102. In embodiments, storage memory 116 may include non-volatile memory, such as NAND flash memory. However, this disclosure is not limited thereto, and storage memory 116 may include any suitable memory depending on the type of storage device 104 (e.g., disk, magnetic tape, and / or optical disc, etc.).

[0049] In one or more example embodiments, the storage device 104 may further include a response circuit 112. The response circuit 112 may be implemented as a hardware module (e.g., electronic circuitry) communicatively connected between the storage interface 110 and the storage controller 114. For example, in an embodiment, the response circuit 112 may be implemented as an integrated circuit (IC) attached to (or mounted on) the storage device 104 (e.g., the response circuit 112 may be embedded on the same board or circuit board as the storage device 104). For example, the response circuit 112 may be implemented as a system-on-a-chip (SOC) on the storage device 104 (e.g., it may be attached to or mounted on the storage device 104). However, this disclosure is not limited thereto; for example, in another embodiment, the response circuit 112 may be implemented on a circuit board separate from the circuit board (e.g., a printed circuit board PCB) of the storage device 104 and may be connected between the storage interface 110 and the storage device 104.

[0050] In one or more example embodiments, when host data is being transferred from host device 102 to storage device 104 via storage interface 110, response circuitry 112 can receive the host data and track status information corresponding to one or more states of the transferred host data. Response circuitry 112 may include a configurable command response trigger such that an appropriate response is automatically sent back to host device 102 based on the one or more states of the transferred host data and the configuration (e.g., mode) of the configurable command response trigger. Therefore, instead of having a processor (e.g., storage controller 114) executing firmware and / or software track the one or more states to send back a response to host device 102, response circuitry 112 can track the one or more states to automatically generate an appropriate response based on the one or more states and send that appropriate response to host device 102. This can reduce latency and / or improve throughput of storage device 104. Reference will now be made to this further. Figures 2 to 4 The response circuit 112 is described in more detail.

[0051] Figure 2 This is a block diagram of a response circuit 112 according to one or more exemplary embodiments of the present disclosure.

[0052] In short, the response circuit 112 may be a hardware module (e.g., electronic circuitry) connected between the storage interface 110 and the storage controller 114. The response circuit 112 may include a data path (e.g., a data path receiving circuit 202) for receiving host data while host data is being transferred from host device 102 to storage device 104 via the storage interface 110. The response circuit 112 may track the status information of the host data while it is being transferred from host device 102 via the storage interface 110 (e.g., using one or more counters 208 and 210), and may provide an appropriate response to host device 102 based on the status information of the host data.

[0053] For example, in one embodiment, when a portion (e.g., a block) of transmitted host data is received at a data path (e.g., receive data path circuitry 202), response circuitry 112 may send a notification corresponding to the received portion of the host data to storage controller 114 (or another processor executing firmware or software) to inform storage controller 114 that the portion of the host data has been received. Storage controller 114 may process the notification to persistently store the host data in storage memory 116 and may send an acknowledgment back to response circuitry 112 indicating that the notification has been processed. In this case, response circuitry 112 may (e.g., via notification counter 208) track the notification being sent to storage controller 114 and may (e.g., via acknowledgment counter 210) track the acknowledgment received from storage controller 114 corresponding to the notification, indicating that the notification has been processed by storage controller 114.

[0054] In some embodiments, depending on the configuration of the response circuit 112 (e.g., a mode) (e.g., a configuration of a configurable command response trigger), the response circuit 112 can automatically send a response to the host device 102 based on a notification and / or acknowledgment, indicating that the command was successfully executed. For example, the response circuit 112 can be configured to automatically send a response to the host device 102 once all host data has been received and notified but not necessarily processed by the storage controller 114, and / or can be configured to automatically send a response to the host device 102 after all acknowledgments corresponding to the notification have been received from the storage controller 114, indicating that all notifications have been processed by the storage device 104. In the former case, the response can be sent to the host device 102 earlier than in the latter case, but this may increase the risk of data loss compared to the latter case.

[0055] For more details, see [link to relevant documentation]. Figure 2According to one or more example embodiments of this disclosure, the response circuit 112 may include a receive data path circuit 202, a response trigger circuit 204, and a response generator circuit 206. In some embodiments, when host data is being transferred from host device 102 to storage device 104 via storage interface 110, the receive data path circuit 202 may receive a portion of the host data. For example, a command transmission length may indicate that the host data used for a corresponding write command includes, for example, multiple data blocks, such that a portion of the host data may correspond to one of the multiple data blocks. In this case, when a portion (e.g., a block) of host data is received, the receive data path circuit 202 may send a notification to the storage controller 114 (or another processor executing firmware and / or software) to inform the storage controller 114 that the portion of the host data has been received. The storage controller 114 may process the notification and may send an acknowledgment to the response trigger circuit 204 indicating that the notification has been processed.

[0056] In some embodiments, the notification may include information identifying the portion of the host data and the location (e.g., temporary location) where the portion of the host data is placed (e.g., temporarily stored), such that the storage controller 114 can process the notification to persistently store the host data in the storage memory 116 according to the notification. For example, in some embodiments, the receive data path circuitry 202 may be connected to (or may include) a cache (e.g., a volatile data cache) that temporarily stores portions of host data as they are received via the storage interface 110 until the storage controller 114 processes the notification and / or persistently stores the host data in the storage memory 116. In this case, in embodiments, although the storage controller 114 may typically send a corresponding acknowledgment when each notification is processed and the corresponding portion of the host data is persistently stored in the storage memory 116, this disclosure is not limited thereto. For example, a corresponding acknowledgment for each portion of the host data may be sent before, after, or during the storage of each portion of the host data in the storage memory 116, as long as it relatively ensures that the host data is persistently stored in the storage memory 116.

[0057] Although the receiving data path circuit 202 is in Figure 2The data receiving path circuit 202 is shown as a component of the response circuit 112, but this disclosure is not limited thereto. For example, in another embodiment, the data receiving path circuit 202 may be implemented separately from the response circuit 112 and may send notifications to the storage controller 114 (or another processor executing firmware and / or software) for processing the notifications. In this case, the data receiving path circuit 202 may also send notifications (or signals indicating the sending of notifications) to the response circuit 112, allowing the response circuit 112 to track the notification status of the host data. For example, in various embodiments, the data receiving path circuit 202 may be implemented on the same board as the storage device 104 (e.g., the same circuit board), may be a separate module communicatively connected to the storage interface 110 and the storage device 104 (e.g., a separate hardware module or a separate processor executing instructions), and / or may be implemented as a component of the storage controller 114, etc.

[0058] In some embodiments, the response trigger circuit 204 may include one or more counters for tracking status information of the host data, which is used to determine, for example, whether the transmitted host data is in an appropriate state to trigger an automatic response back to the host device 102. For example, one or more counters may track the notification status of the host data (e.g., whether the storage controller 114 has been notified that all host data has been received) and / or may track the acknowledgment status of the host data (e.g., whether all notifications have been processed and acknowledged by the storage controller 114). In this case, the response generator circuit 206 may automatically send an appropriate response to the host device 102 based on (e.g., depending on) the status information of the host data (e.g., based on the status of one or more counters).

[0059] For example, in some embodiments, one or more counters may include a notification counter 208 and an acknowledgment counter 210. In some embodiments, the notification counter 208 and the acknowledgment counter 210 may be initialized based on the size of the host data. As an illustrative example, if the command transmission length indicates that the host data comprises 5 blocks, then each of the notification counter 208 and the acknowledgment counter 210 may be initialized to have an initial value of 5. In this example, the notification counter 208 may be decremented when the receive data path circuit 202 sends a notification to the storage controller 114 for each block of host data received at the receive data path circuit 202. Similarly, in this example, the acknowledgment counter 210 may be decremented when the storage controller 114 acknowledges each notification for each of the 5 blocks of host data. Therefore, the value of the notification counter 208 may be 0 when all host data has been received and notified to the storage controller 114, and the value of the acknowledgment counter 210 may be 0 when all notifications have been processed and acknowledged by the storage controller 114.

[0060] In some embodiments, the response generator circuit 206 can automatically send an appropriate response to the host device 102 based on the status of the notification counter 208 and / or the status of the acknowledgment counter 210. For example, in some embodiments, the response generator circuit 206 can be connected to the notification counter 208 and / or the acknowledgment counter 210 and can determine when one or both of the notification counter 208 and / or the acknowledgment counter 210 have a value of 0. In this case, the response generator circuit 206 can automatically send an appropriate response to the host device 102 when the value of the notification counter 208 decrements to 0 and / or when the value of the acknowledgment counter 210 decrements to 0. For example, when the value of the notification counter 208 decrements to 0, the response generator circuit 206 may send the response to the host device 102 earlier, but the risk of data loss may increase because the storage controller 114 may not have processed all the notifications yet. On the other hand, when the value of the acknowledgment counter 210 decreases to 0, the risk of data loss can be reduced, but because the response generator circuit 206 waits until all notifications have been processed and acknowledged by the storage controller 114 before sending the response to the host device 102, the response to the host device 102 will be sent later.

[0061] Therefore, in some embodiments, the response circuit 112 may have a configurable command response trigger such that the response generator circuit 206 sends a response to the host device 102 according to the configuration (e.g., mode) of the command response trigger. For example, see the following... Figure 3In more detail, in some embodiments, the configurable command response trigger may be implemented as a component of the response trigger circuit 204. In other embodiments, the configurable command response trigger may include a counter of the response trigger circuit 204 and may be implemented as a component of the response generator circuit 206.

[0062] Figure 3 This is a schematic circuit diagram illustrating a configurable command response trigger of a response circuit according to one or more example embodiments of the present disclosure. Figure 3 The portion of the response circuit 112 corresponding to the configurable command response trigger is shown, for example, the portion including the notification counter 208 and the acknowledgment counter 210 of the response trigger circuit 204 and / or the portion of the response generator circuit 206.

[0063] Reference Figure 3 In some embodiments, the response circuit 112 may include a configurable command response trigger such that a response is automatically sent to the host device 102 based on the state of the notification counter 208 and / or the acknowledgment counter 210 and the configuration (e.g., mode) of the configurable command response trigger. For example, each of the notification counter 208 and the acknowledgment counter 210 may include (e.g., may be implemented as) binary counters 302 and 304. The binary counters 302 and 304 of each of the notification counters 208 and the acknowledgment counter 210 may be initialized based on the size of the host data (e.g., based on (e.g., based on) the command transmission length associated with the host data). As a notification is sent (e.g., from the receive data path circuitry 202) to the storage controller 114, the binary counter 302 of the notification counter 208 may be decremented. As an acknowledgment is received from the storage controller 114 (e.g., via the response trigger circuitry 204), the binary counter 304 of the acknowledgment counter 210 may be decremented.

[0064] In some embodiments, each of binary counters 302 and 304 may provide its current value to a corresponding comparator 306 and 308. Each of comparators 306 and 308 may determine whether the value of the corresponding binary counter 302 and 304 has reached a threshold (e.g., has decremented to 0). For example, in some embodiments, each of comparators 306 and 308 may compare the current value of the corresponding binary counter 302 and 304 with a threshold (e.g., 0) to determine whether the current value of the corresponding binary counter 302 and 304 has reached the threshold (e.g., has decremented to 0). In some embodiments, each of comparators 306 and 308 may output a comparison result based on (e.g., on) the comparison. For example, in some embodiments, if the current value of the corresponding binary counter 302 and 304 has reached the threshold (e.g., 0), the corresponding comparators 306 and 308 may output a high-level signal (e.g., 1) as a comparison result. On the other hand, if the corresponding binary counters 302 and 304 have values ​​other than the threshold (e.g., values ​​greater than 0), the corresponding comparators 306 and 308 can output low-level signals (e.g., 0) as the comparison result.

[0065] In some embodiments, each of comparators 306 and 308 may provide a comparison result to the corresponding first logic gates (e.g., to the corresponding AND logic gates) 310 and 312. In embodiments, the first logic gates 310 and 312 may be used to select one of the notification counter 208 and the acknowledgment counter 210 as a trigger for automatically sending a response (e.g., via response generator circuit 206) to the host device 102. For example, each of the first logic gates 310 and 312 may receive a configuration signal (Config), such that one of the first logic gates 310 and 312 may be selected at a time based on the Config signal. In this case, considering the various characteristics of the storage device 104 and / or the host data and based on the balance between the performance of the storage device 104 and the desired reliability, the Config signal may be provided at the start time, runtime, and / or based on each command, such that one of the first logic gates 310 and 312 is selected at a time, thus selecting one of the notification counters 208 and the acknowledgment counter 210. For example, Config signals can be provided from storage controller 114, host processor 106, another controller or processor connected to storage device 104, and / or any other suitable controller, processor, and / or device connected to storage device 104.

[0066] For example, in an embodiment, when the first logic gates 310 and 312 are AND gates, the selection signal (e.g., a high-level signal) of the Config signal can be provided to the selected AND gate among the AND gates 310 and 312, and the deactivation signal (e.g., a low-level signal) of the Config signal can be provided to the other AND gate among the AND gates 310 and 312 (e.g., the unselected AND gate). In this case, for example, the selected AND gate among the AND gates 310 and 312 that receives the selection signal (e.g., a high-level signal) of the Config signal can output a high-level signal (e.g., 1) when it receives a high-level signal as a comparison result from the corresponding comparators 306 and 308 (e.g., indicating that the current value of the corresponding binary counters 302 and 304 has reached a threshold), and can output a low-level signal in other cases (e.g., when the comparison result has a low-level signal, indicating that the current value of the corresponding binary counters 302 and 304 has not yet reached a threshold). Due to the deactivation signal (e.g., a low-level signal), an AND gate in logic gates 310 and 312 that receives the Config signal and whose deactivation signal (e.g., a low-level signal) is not selected can output a low-level signal (e.g., 0), regardless of the comparison result from the corresponding comparators 306 and 308.

[0067] In an embodiment, such as Figure 3As shown, the same Config signal can be provided to each of the first logic gates 310 and 312. For example, one of the first logic gates 310 and 312 may have an inverter (or NOT gate) connected to its input for inverting the level of the Config signal, and the other of the first logic gates 310 and 312 may receive the level of the Config signal as is, such that the same Config signal can be provided to select one of the first logic gates 310 and 312. In this case, for example, when the Config signal has a low level, the inverter can invert the low-level signal to a selection signal (e.g., a high-level signal) for said one of the first logic gates 310 and 312, and said one of the first logic gates 310 and 312 may receive the low level of the Config signal as a deactivation signal (e.g., a low-level signal). Similarly, when the Config signal is high, the inverter can invert the high-level signal to a deactivation signal (e.g., a low-level signal) for one of the first logic gates 310 and 312, and the other of the first logic gates 310 and 312 can receive the high level of the Config signal as a selection signal (e.g., a high-level signal). However, this disclosure is not limited thereto; in other embodiments, different Config signals can be provided to each of the first logic gates 310 and 312 to select the desired or suitable one of the first logic gates 310 and 312.

[0068] In some embodiments, the outputs of the first logic gates (e.g., AND gates) 310 and 312 can be provided to the second logic gate (e.g., OR gate) 314, such that a trigger signal can be generated by the second logic gate 314. The trigger signal can be used (e.g., via response generation circuitry 206) to automatically send a response to the host device 102. For example, in an embodiment, when the second logic gate 314 is an OR gate, the OR gate 314 can provide a trigger signal as a high-level signal (e.g., 1) when either of the first logic gates (e.g., AND gates) 310 and 312 provides a high-level signal (e.g., indicating that the current value of the corresponding binary counters 302 and 304 has reached a threshold), and in other cases can output a low-level signal (e.g., 0). Because one of the first logic gates (e.g., AND gates) 310 and 312 that is deactivated can provide a low-level signal (e.g., 0), and one of the first logic gates (e.g., AND gates) 310 and 312 that is selected can provide a high-level signal (e.g., 1) only when it receives a high-level signal as a comparison result from the corresponding comparators 306 and 308 (e.g., indicating that the current value of the corresponding binary counters 302 and 304 has reached a threshold), the OR gate 314 can provide a trigger signal with a high-level signal only when the current value of the selected counter among the notification counter 208 and the confirmation counter 210 has reached a threshold (e.g., 0) to trigger an automatic response.

[0069] Therefore, in one or more embodiments, the response circuit 112 can be configured to provide an automatic response to the host device 102 based on the states of counters 208 and 210 and the configuration (e.g., mode) of the configurable command response trigger of the response circuit 112. Although Figure 3 An example implementation of a configurable command-response trigger for response circuitry 112 is shown, but this disclosure is not limited thereto, and various modifications can be made to the configurable command-response trigger for response circuitry 112 in accordance with the spirit and scope of this disclosure. For example, as those skilled in the art will recognize upon studying this disclosure and / or as learned from practicing one or more embodiments of this disclosure, a configurable command-response trigger may include (e.g., may be implemented as) various suitable hardware structures, electronic components, and / or assemblies, such as various other suitable logic gates (e.g., NAND gates, NOR gates, XOR gates, NOT gates, EXOR gates, and / or EXNOR gates, etc.), various suitable switches, various suitable transistors, various suitable resistors, various suitable capacitors, various suitable registers, various suitable flip-flops, various kinds of counters, and / or various kinds of comparators, etc.

[0070] Figure 4 This is a flowchart of a method for generating a response to a write command according to one or more example embodiments of the present disclosure. However, the present disclosure is not limited to... Figure 4 The order or number of operations of the method 400 shown is not fixed, but can be changed to any desired order or number of operations as would be recognized by one of ordinary skill in the art. For example, in some embodiments, the order may be varied, or the method may include fewer or additional operations.

[0071] Reference Figure 4 Method 400 begins when a write command is issued from host device 102, causing the write command to be received by storage device 104 through storage interface 110. In operation 405, counters are initialized according to the command transmission length of the write command. For example, notification counter 208 and acknowledgment counter 210 can be initialized to initial values ​​based on the command transmission length of the write command. In operation 410, data transmission of host data associated with the write command begins. For example, host device 102 may begin transmitting host data associated with the write command to storage device 104 through storage interface 110. In operation 415, a portion (e.g., a block) of host data transmitted from host device 102 is received. For example, receive data path circuitry 202 may receive a block of host data from host device 102 through storage interface 110.

[0072] In operation 420, the storage controller 114 (or another processor executing firmware and / or software) may be notified of the received block of host data. For example, the receive data path circuit 202 may send a notification to the storage controller 114 that the block of host data has been received. In this case, after operation 420, two cycles may begin, a first cycle beginning with operation 425 and a second cycle beginning with operation 440. For convenience, the first cycle beginning with operation 425 will be described first, followed by the second cycle beginning with operation 440, but this disclosure is not limited to this order or timing. For example, the first cycle beginning with operation 425 may begin concurrently (e.g., simultaneously) with the second cycle beginning with operation 440, or the second cycle beginning with operation 440 may begin after one or more operations of the first cycle beginning with operation 425.

[0073] In operation 425, the current value of notification counter 208 can be decremented. For example, the current value of notification counter 208 can be decremented in response to a notification sent to storage controller 114. In this case, in operation 430, the current value of notification counter 208 can be compared with a threshold (e.g., 0) to determine whether the current value of notification counter 208 has reached the threshold (e.g., has been decremented to 0). For example, comparator 306 of the configurable command response trigger of response circuit 112 can compare the current value of notification counter 208 with the threshold (e.g., 0) to determine whether all host data has been received and notified. If the current value of notification counter 208 has not yet reached the threshold (e.g., has not been decremented to 0) in operation 430 (e.g., no), then method 400 can loop back to operation 415, such that another portion (e.g., another block) of host data is received in operation 415, and method 400 continues in operation 420 until all blocks of host data have been received in operation 430 (e.g., notification counter 208 has been decremented to 0).

[0074] On the other hand, if the current value of the counter 208 is notified in operation 430 that it has reached a threshold (e.g., has decremented to 0) (e.g., yes), then the response circuit 112 (e.g., a configurable command response trigger of the response circuit) can determine in operation 435 whether the configurable command response trigger is configured to operate in the first mode. For example, in an embodiment, the comparison result of comparator 306 can be provided to a first logic gate (e.g., an AND gate) 310, and the first logic gate 310 can perform an operation (e.g., an AND operation) between the comparison result and the Config signal. In this case, if the Config signal is provided as a selection signal (e.g., a high-level signal), then in operation 435 it can be determined that the first mode is configured (e.g., yes), thereby triggering a response in operation 460, and sending the response to the host device 102 in operation 465 (e.g., via the response generator circuit 206). On the other hand, if the Config signal is provided as a deactivation signal (e.g., a low-level signal), then in operation 435 it can be determined that the first mode is not configured (e.g., no). In this case, during operation 435, response circuit 112 (e.g., a configurable command response trigger of response circuit 112) can determine that the configurable command response trigger is configured to operate in a second mode (e.g., based on an inverter), so that response circuit 112 can wait until operation 450 confirms that the current value of counter 210 has reached a threshold (e.g., decremented to 0).

[0075] Returning to operation 420, in response to the notification sent to storage controller 114 in operation 420, storage controller 114 can process the notification, allowing it to send an acknowledgment to response circuit 112 (e.g., response trigger circuit 204) indicating that the notification has been processed. Therefore, in operation 440, it can be determined whether an acknowledgment has been received. For example, response trigger circuit 204 can determine whether an acknowledgment has been received from storage controller 114. If no acknowledgment has been received in operation 440 (e.g., no), then method 400 can loop back to operation 440 until an acknowledgment corresponding to the notification of operation 420 is received.

[0076] On the other hand, if an acknowledgment (e.g., yes) is received in operation 440, the current value of the acknowledgment counter 210 can be decremented in operation 445. In this case, in operation 450, the current value of the acknowledgment counter 210 can be compared with a threshold (e.g., 0) to determine whether the current value of the acknowledgment counter 210 has reached the threshold (e.g., has been decremented to 0). For example, the comparator 308 of the configurable command response trigger of the response circuit 112 can compare the current value of the acknowledgment counter 210 with the threshold (e.g., 0) to determine whether all notifications related to host data have been processed by the storage controller 114. If the current value of the acknowledgment counter 210 has not yet reached the threshold (e.g., has not been decremented to 0) in operation 450 (e.g., no), then method 400 can loop back to operation 440, such that in operation 440 the response trigger circuit 204 can determine whether another acknowledgment related to another notification has been received from the storage controller 114, until all acknowledgments related to host data have been received in operation 450 (e.g., the current value of the acknowledgment counter 210 has been decremented to 0).

[0077] On the other hand, if operation 450 confirms that the current value of counter 210 has reached a threshold (e.g., has decremented to 0) (e.g., yes), then a response can be triggered in operation 460. For example, in an embodiment, the comparison result of comparator 308 can be provided to a first logic gate (e.g., AND gate) 312, and the first logic gate 312 can perform an operation between the comparison result and the Config signal (e.g., AND operation). In this case, because operation 435 determines that the configurable command response trigger is configured to operate in the second mode (e.g., no), the Config signal is provided as a selection signal (e.g., a high-level signal) to the first logic gate 312 (e.g., based on an inverter), causing a response to be triggered in operation 460, and in operation 465 the response is sent to host device 102 (e.g., via response generator circuit 206).

[0078] Although one or more embodiments of this disclosure have been described above as including two modes corresponding to two counters (e.g., notification counter 208 and acknowledgment counter 210) in the command response trigger, this disclosure is not limited thereto. The command response trigger may include more or fewer modes and / or more or fewer counters. For example, in one embodiment, the command response trigger may include a third mode for triggering an automatic response, for example, when host data is received but not yet notified. In this case, a response to host device 102 may be provided even earlier than other modes, but the risk of data loss may be greatest. For example, in this case, the command response trigger may include a third counter for tracking when all host data has been received but not yet notified, and when operating under this configuration (e.g., in this mode), a response may be automatically generated even before the storage controller 114 is notified of all host data.

[0079] As described above, according to one or more example embodiments of this disclosure, the storage device may include hardware modules (e.g., response circuitry) for tracking one or more states of host data transmitted from a host device to the storage device, instead of using firmware or software (e.g., a processor for executing instructions, such as a storage controller) for maintaining and processing state information of the host data. Therefore, latency can be reduced and / or the throughput of the storage device can be improved.

[0080] As described above, according to one or more example embodiments of this disclosure, a hardware module (e.g., a response circuit) may include a configurable command response trigger for providing an appropriate response to the host device based on various states of host data being transferred to storage device 104 and the configuration (or mode) of the command response trigger. Therefore, considering the various characteristics of the storage device and / or host data and based on a balance between the performance and reliability of the storage device, the command response trigger can be dynamically configured at start time, runtime, and / or based on each command.

[0081] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of this disclosure, the aforementioned first element, first component, first region, first layer, or first portion may be referred to as a second element, second component, second region, second layer, or second portion.

[0082] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, connected to, or bonded to the other element or layer, or one or more intermediate elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may be present.

[0083] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that the terms “comprising,” “including,” “having,” and variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when following a list of elements, without modifying any individual elements in that list.

[0084] As used herein, the terms “basically,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to take into account the inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively.

[0085] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0086] Although some exemplary embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A storage device, the storage device comprising: The storage controller is configured to: receive one or more notifications corresponding to host data transmitted from the host device to the storage device via the storage interface, process the one or more notifications to persistently store the host data in the storage memory, and send one of one or more acknowledgments back to the response circuit in response to processing the corresponding notification; Storage memory; as well as The response circuit, connected between the storage interface and the storage controller, is configured to trigger a response to the host device. The response circuit includes: The data receiving path circuit is configured to: receive a portion of the host data while the host data is being transmitted from the host device to the storage device through the storage interface, and send a notification to the storage controller corresponding to the received portion of the host data in one or more notifications to inform the storage controller that the portion of the host data has been received; The response trigger circuit includes a first counter, a second counter, and a response trigger; and Response generator circuit, The first counter is configured to track the one or more notifications, each notification corresponding to a portion of the total host data. The second counter is configured to track the one or more acknowledgments received from the storage controller, wherein each acknowledgment corresponds to one of the one or more notifications. The response trigger is configured to select one of the first and second counters to trigger a response to the host device. The response generator circuit is configured to send the response to the host device based on the state of the selected counter, either the first counter or the second counter.

2. The storage device according to claim 1, wherein, The state corresponds to the count value of the selected counter among the first counter and the second counter.

3. The storage device according to claim 2, wherein, The count value is initialized based on the command transmission length associated with the host data.

4. The storage device according to claim 3, wherein, The first counter is a counter selected by the response trigger, and the count value of the first counter is decremented for each of the one or more notifications sent to the storage controller.

5. The storage device according to claim 4, wherein, The response trigger includes a comparator, and the comparator is configured to compare the count value with a threshold.

6. The storage device according to claim 5, wherein, The response circuit is configured to: in response to a count value equal to a threshold, determine that host data has been received and notified, trigger a response to the host device, and send the response to the host device.

7. The storage device according to claim 3, wherein, The second counter is a counter selected by the response trigger, and the count value of the second counter is decremented for each of the one or more acknowledgments received from the storage controller.

8. The storage device according to claim 7, wherein: The response trigger includes a comparator, and the comparator is configured to compare a count value with a threshold. and The response circuit is configured to: in response to a count value equal to a threshold, determine that the host data has been processed by the storage controller, trigger a response to the host device, and send the response to the host device.

9. A method for triggering a response to a command issued by a host device to a storage device, the method comprising the steps of: The data path circuit of the response circuit receives a portion of the host data while the host data is being transmitted from the host device to the storage device through the storage interface, and sends one or more notifications to the storage controller corresponding to the received portion of the host data to inform the storage controller that the portion of the host data has been received. The storage controller receives one or more notifications, which correspond to host data transmitted from the host device to the storage device via the storage interface, and the host data corresponds to a command. The storage controller processes the one or more notifications to persistently store host data in the storage memory, and in response to processing the corresponding notification, sends one of the one or more acknowledgments back to the response circuit. The response to the host device is triggered by the response circuitry connected between the storage interface and the storage controller. The triggering steps include: The first counter of the response circuit tracks the one or more notifications, which correspond to all host data in such a way that each notification corresponds to a portion of the host data in all host data; The response circuit receives the one or more acknowledgments from the storage controller, wherein each acknowledgment corresponds to one of the one or more notifications in such a manner as each acknowledgment corresponds to one of the one or more notifications. The second counter of the response circuit tracks the one or more confirmations; The response circuit selects one of the first and second counters to trigger the response; The response generator circuit of the response circuit sends the response to the host device according to the state of the selected counter among the first counter and the second counter.

10. The method according to claim 9, wherein, The state corresponds to the count value of the selected counter among the first counter and the second counter.

11. The method according to claim 10, further comprising: The counter value is initialized by the response circuit based on the command transmission length associated with the host data.

12. The method according to claim 11, wherein, The first counter is a counter selected by a response trigger, and the method further includes: The response circuit decrements the count value of the first counter for each of the one or more notifications sent to the storage controller.

13. The method according to claim 12, wherein, The response trigger includes a comparator, and the method further includes: The comparator compares the count value with the threshold.

14. The method according to claim 13, further comprising: The response circuit determines that the host data has been received and notified in response to the count value being equal to the threshold, triggers a response to the host device, and sends the response to the host device.

15. The method according to claim 11, wherein, The second counter is a counter selected by a response trigger, and the method further includes: The response circuit decrements the count value of the second counter for each of the one or more acknowledgments received from the storage controller.

16. The method according to claim 15, wherein, The response trigger includes a comparator, and the method further includes: The comparator compares the count value with a threshold; and The response circuit determines that the host data has been processed by the storage controller in response to the count value being equal to the threshold, triggers a response to the host device, and sends the response to the host device.

Images