Systems, methods and apparatus for high-speed input / output margin testing

Abstract

Systems, apparatus, and methods for high-speed I / O margin testing can screen large numbers of pre-production and production components and identify situations where electrical characteristics have changed sufficiently to affect operation. The disclosed margin testers are less expensive, easier to use, and faster than conventional BERTs and oscilloscopes, and can operate on all multi-channel I / O links under their standard operating conditions with full load and crosstalk. The margin testers simultaneously evaluate the electrical receiver margin of the operating multi-channel high-speed I / O links of the device under test in one or both directions. In one embodiment for a particular art, embodiments of the margin tester may be implemented as a card insertion margin tester to test motherboard slots on a motherboard under test, or as a motherboard with slots to test insertion cards.

Description

Technical Field

[0001] This disclosure relates to test and measurement systems, and more specifically to systems and methods for performing high-speed electrical margin tests on electrical devices under test (DUTs). Attached Figure Description

[0002] The components in the accompanying drawings are not necessarily proportional to each other. The same reference numerals are used throughout several drawings to indicate corresponding parts.

[0003] Figure 1 This is a general block diagram illustrating an example environment of an embodiment of a system, apparatus, and method for high-speed input / output (I / O) margin testing, according to an example embodiment.

[0004] Figure 2 This is a block diagram illustrating an example-specific insert card margin tester according to an example embodiment, which is compatible with the Fast Peripheral Component Interconnect (PCI) high-speed serial computer expansion bus standard for margin testing of Fast PCI motherboard slots.

[0005] Figure 3 This is a block diagram illustrating a motherboard with slots compatible with the Fast PCI high-speed serial computer expansion bus standard for margin testing of Fast PCI insert cards, according to an example embodiment.

[0006] Figure 4 This is a diagram showing the results of an example margin test performed by a high-speed I / O margin tester according to an example embodiment, and a graph identifying potential DUT assembly or manufacturing problems based on the margin test results.

[0007] Figure 5 This is a diagram showing the results of another example margin test performed by a high-speed I / O margin tester according to an example embodiment, and a graph identifying potential DUT assembly or manufacturing problems based on the results of the margin test.

[0008] Figure 6 This is a block diagram illustrating a general margin tester according to an example embodiment. The general margin tester has multiple interfaces configured to be cable-connected to at least one test fixture to evaluate the electrical margin of a DUT's multi-channel high-speed I / O link in both the transmit (Tx) and receive (Rx) directions.

[0009] Figure 7 This is a low-level block diagram of a margin tester for testing the electrical margin of a multi-channel high-speed I / O link of a DUT in both the Tx and Rx directions, according to an example embodiment.

[0010] Figure 8This is a block diagram of an example of a field-programmable gate array (FPGA) configured according to an example embodiment, which can be used in the controller of an electrical margin tester for testing the electrical margin margin of a multi-channel high-speed I / O link of a DUT in both the Tx and Rx directions.

[0011] Figure 9 This is a block diagram of example output drive options for an FPGA according to an example embodiment, which can be used in the controller of a margin tester for testing the electrical margin of a multi-channel high-speed I / O link of a DUT in the Tx direction.

[0012] Figure 10 This is a flowchart of an example method for performing margin testing on a DUT according to an example embodiment.

[0013] Figure 11 This is a flowchart of an example method, according to an example embodiment, for identifying potential DUT assembly or manufacturing problems by performing margin testing on the electrical margin of the DUT's multi-channel high-speed I / O links in both the Tx and Rx directions.

[0014] Figure 12 This is a flowchart of an example method for performing an evaluation of electrical margin initiated by a margin tester based on user-selectable options, according to an example embodiment.

[0015] Figure 13 This is a flowchart of an example method for providing a calibrated margin tester according to an example embodiment.

[0016] Figure 14 This is a flowchart of an example method for configuring a DUT to run a margin test, according to an example embodiment. Detailed Implementation

[0017] Designers and manufacturers of electrical equipment require test and measurement instruments and appropriate testing procedures to ensure that the equipment functions properly. Such testing can be conducted during the engineering characterization phase of designing new equipment to compare, for example, the actual electrical performance of the equipment with simulated performance, ensuring that the equipment performs as designed. Such testing can also be conducted in a manufacturing environment after the engineering design is completed to identify any manufacturing defects in each piece of equipment produced.

[0018] Many electrical devices are designed to include high-speed I / O signal paths or buses. For example, modern personal computer (PC) motherboards and other types of electrical devices typically include a high-speed serial Fast PCI (also known as PCIe or PCI-e) bus, which is a bus that conforms to and implements the Fast PCI High-Speed ​​Serial Computer Extension Bus standard. The format specification of the Fast PCI standard is maintained and developed by the PCI Special Interest Group (PCI-SIG). These buses are typically used for communication between the motherboard and plug-in / daughter cards inserted into PCIe connector slots or ports on the motherboard. Many other electrical devices besides the motherboard also use PCIe buses and connectors for high-speed I / O. Generation 4 PCIe (Gen 4 or version 4) devices can achieve bandwidths of up to 16 gigabits per second (GT / s). Generation 5 PCIe (Gen 5 or version 5) devices can achieve bandwidths of up to 32 GT / s.

[0019] PCIe devices communicate via logical connections known as interconnects or links. A link is a point-to-point communication channel between two PCIe ports, allowing simultaneous bidirectional traffic. At the physical layer, a link consists of one or more channels. Low-speed PCIe devices use single-channel (x1) links, while high-speed PCIe devices, such as graphics adapters, typically use much wider and faster 16-channel (x16) links. A channel consists of two differential signal pairs, one pair for receiving data and the other for transmitting. Therefore, each channel consists of four wires or signal traces. Traditionally, a Bit Error Rate Tester (BERT) and / or a high-speed signal generator and oscilloscope are used to test the performance of PCIe device channels.

[0020] During the engineering bench testing and / or engineering characterization phases of printed circuit board (PCB) development, model boards are designed with high-speed routing (e.g., PCIe interconnects) or follow a design “recipe” or reference design. Pre-production board samples are then typically built and tested. However, due to cost, time, and complexity limitations, testing every board sample and every channel for all high-speed I / O with bit error rate test instruments (BERTs) and oscilloscopes is often impractical. In particular, traditional BERTs and oscilloscopes used for testing high-speed I / O standards such as PCIe become increasingly expensive and complex with increasing data rates. A single Tx and Rx test station for testing a single PCIe channel at a time can cost over a million dollars. Such instruments are also difficult to use for traditional Tx and Rx testing and calibration, as well as for expert (often PhD-level) users, and require significant time to ensure correct measurements and that the instruments remain in good working order. Due to these limitations, traditional BERTs and oscilloscopes are rarely used for batch electrical testing of pre-production silicon, boards, PCBs, and cables, and are often not used for production testing at all.

[0021] However, with the increasing data rates of fast PCI 5.0 I / O links, such as 32.0 GT / s, the risk of even small or minor issues significantly impacting the performance of these I / O links also increases. The importance of conducting tests to flag electrical performance issues on each pre-production sample, port, and channel to prevent pre-production problems, and testing the electrical performance on each unit on the production line to catch production-related issues (defective parts, etc.) before they cause customer problems and returns, is also increasing. Furthermore, traditional BERTs and oscilloscopes only allow testing on a single channel at a time, meaning testing occurs in an environment different from the actual operation of these I / O links, which often form multi-channel links and may suffer from significant crosstalk and load issues during real-world operation. Even when testing does / may occur, this can be missed by traditional BERT and oscilloscope testing. Similarly, in manufacturing test environments, when assembling and testing multiple PCBs of a given design, production lines typically do not use BERTs and oscilloscopes for high-speed I / O testing due to cost, time, and complexity constraints.

[0022] Therefore, there is a growing need for new instruments capable of screening large numbers of pre-production and production components and identifying situations where electrical characteristics have changed sufficiently to affect operation. Such an instrument is most valuable if it is low-cost, extremely easy to use, and very fast compared to traditional BERTs and oscilloscopes, and can operate at full load and with crosstalk across all multi-channel I / O links in its standard operating conditions. In summary, knowing the electrical margin (statistically effective operating margin) of each high-speed I / O channel in each direction is valuable in increasing the likelihood of discovering both design problems (e.g., each channel across all production samples) and assembly problems across all production samples (e.g., a specific board / channel instance).

[0023] Some traditional solutions rely solely on functional testing as the best approximation (e.g., simply plug in a "gold" or reference device and the test link will come up at full speed). Other companies use die-on power margins in silicon for their boards, but this only gives them information in one direction and is not calibrated / characterized like test instruments, leaving a significant amount of work to process and understand the unit-to-unit variations in the insert cards they choose for this purpose.

[0024] This article discloses systems, devices, and methods for high-speed input / output (I / O) margin testing that address the aforementioned technical problems.

[0025] Figure 1This is a general block diagram illustrating an example environment for implementing an embodiment of a system, apparatus, and method for high-speed I / O margin testing, according to an example embodiment. In one embodiment, a margin tester 102 is shown, which evaluates the electrical receiver margin of an example DUT 104's operating multi-channel high-speed I / O link 110 in either or both of the Tx and Rx directions. Figure 1 The margin tester 102 represents one or more embodiments of the margin tester disclosed herein.

[0026] The margin tester 102 can be coupled to a test station, PC, terminal, or other display device 106, which can process, reproduce, and / or present an eye pattern display or data eye diagram 108 representing various aspects of the multi-channel high-speed I / O link 110. In some embodiments, the test station, PC, terminal, or other display device 106 may be integrated with or as part of the margin tester 102. The eye pattern display or data eye diagram 108 is a representation of a high-speed digital signal that allows key parameters of the signal's electrical quality to be quickly visualized and determined, and thus the data derived therefrom can be used to determine the statistically effective operating margin of the DUT. The eye pattern display or data eye diagram 108 is constructed from a digital waveform by folding waveform portions corresponding to each individual bit into a single graphic, where the signal amplitude is on the vertical axis and time is on the horizontal axis. By repeating this construction over multiple samples of the waveform, the resulting diagram will represent the average statistics of the signal and will resemble an eye. The eye opening corresponds to one bit period and is generally referred to as the unit interval (UI) width of the eye pattern display or data eye diagram 108. Bit period is a measure of the horizontal opening of an eye diagram at the eye's crossover point, and is typically measured in picoseconds for high-speed digital signals (i.e., 200 ps for a 5 Gbps signal). The data rate is the reciprocal of the bit period (1 / bit period). When describing an eye diagram, the bit period is often referred to as the unit interval (UI). The advantage of using UI instead of the actual time on the horizontal axis is that it is normalized and allows for easy comparison of eye diagrams with different data rates. Eye width is a measure of the horizontal opening of an eye diagram. It is calculated by measuring the difference between the statistical means of the eye's crossover points. Rise time is a measure of the average transition time of data on the upward slope of the eye diagram. It is typically measured at slope levels of 20% and 80% or 10% and 90%. Fall time is a measure of the average transition time of data on the downward slope of the eye diagram. It is typically measured at slope levels of 20% and 80% or 10% and 90%. Jitter is the time deviation from the ideal timing of data bit events and an important characteristic of high-speed digital data signals. To calculate jitter, the time deviation of the transition between the rising and falling edges of the eye diagram at the crossover point is measured. Fluctuations can be random and / or deterministic. The time histogram of the deviation can be analyzed to determine the amount of jitter. Peak-to-peak (pp) jitter is defined as the full width of the histogram, meaning that all data points are present. Root mean square (RMS) jitter is defined as the standard deviation of the histogram. The unit for jitter measurement used for high-speed digital signals is typically picoseconds.

[0027] Embodiments of the margin tester 102 can take at least two forms: technology-specific and general-purpose. The margin tester 102 can be used with any high-speed I / O protocol link of any link width (number of channels) and using any form of high-speed differential signaling, including but not limited to Non-Return-to-Zero (NRZ), Pulse Amplitude Modulation-3 (PAM-3), and Pulse Amplitude Modulation-4 (PAM-4). For the sake of the specific example embodiment being tested, Fast PCI will be used. However, different high-speed serial bus standards, hardware, and protocols may also be used.

[0028] Figure 2 This is a block diagram illustrating an example-specific insert card margin tester 202 according to an example embodiment, which conforms to the Fast PCI High-Speed ​​Serial Computer Expansion Bus standard to perform margin testing on Fast PCI motherboard slots 206.

[0029] In a technology-specific embodiment, the margin tester may be implemented as a Fast PCI Insert Card Margin Tester 202 to test the Fast PCI motherboard slot 206 of the motherboard 204 under test. For example, the Fast PCI Insert Card Margin Tester 202 may be an insert card with a Fast PCI x16 card electromechanical specification (CEM) form factor. In another technology-specific embodiment, the margin tester may be implemented as a motherboard having one or more Fast PCI slots to test Fast PCI insert cards (such as…). Figure 3 (As shown).

[0030] The Fast PCI Insertion Card Margin Tester 202 may have a form factor for a standard Fast PCI compatible insertion card for a specific Fast PCI form factor (e.g., CEM or M.2 (often referred to as Next Generation Form Factor (NGFF) or U.2 (often referred to as SFF-8639)). The Fast PCI Insertion Card Margin Tester 202 may include one or more printed circuit boards (PCBs), such as PCB 212, and one or more components that implement a compatible Fast PCI physical and logical link layer for each channel. The Fast PCI Insertion Card Margin Tester 202 may include multiple interfaces (such as connectors 208) coupled to PCB 212 and controller 210. For example, such an interface may include multiple connectors 208 connecting to the motherboard slot 206 and the margin tester transmitter, which, under the control of the controller 210, optionally include the ability to inject controlled noise through, for example, voltage swings and sinusoidal jitter, such that the expected eye diagram margin at the receiver of the motherboard under test 204 can be varied to a specific target for timing or voltage margin, without requiring software running on the motherboard under test 204. The controller 210 may also be coupled to a memory 214, which may store instructions and other data that the controller 210 can read, use, and / or execute to perform the functions described herein.

[0031] Various embodiments of the margin tester 102 (including the technology-specific Fast PCI Insert Card Margin Tester 202, the technology-specific Motherboard Margin Tester 302, and the general-purpose margin tester 602) may or may not have noise injection. For cost-controlled production testing, embodiments without noise injection may be more attractive. The margin tester receiver in a compliant physical layer implementation may include the ability to provide link margin as defined in the Fast PCI 4.0 / 5.0 lane margin specification, but may also include additional and more complex on-die margin capabilities. In one embodiment, the margin tester receiver can measure eye diagram margin by moving a separate error detector and comparing it with a mismatch with a data sampler. In one implementation, the controller 210 that enables the margin tester 102 (including the technology-specific Fast PCI Insert Card Margin Tester 202, the technology-specific Motherboard Margin Tester 302, and the general-purpose margin tester 602) to perform the functions described herein can be implemented using a field-programmable gate array (FPGA) and FPGA I / O, which in Figures 7 to 9 This is illustrated in further detail below. However, other combinations of configurable controller hardware, firmware, and / or software can be used.

[0032] Figure 3 This is a block diagram illustrating an example-technology-specific motherboard margin tester 302 according to an example embodiment, the motherboard margin tester having a slot compatible with the Fast PCI high-speed serial computer expansion bus standard for margin testing of Fast PCI insert cards.

[0033] The motherboard margin tester 302 is another example of a technology-specific embodiment of the margin tester 102 disclosed herein, implemented as a motherboard margin tester 302 having one or more fast PCI slots 306 to test, for example, Figure 3 The PCIe x16 insertion card DUT 304 shown is a fast PCI insertion card. The motherboard margin tester 302 may include multiple interfaces (e.g., one or more fast PCI slots 306) coupled to the PCB 312 and the controller 210. For example, such interfaces may include multiple or more fast PCI slots 306 into which the PCIe x16 insertion card DUT 304 can be inserted for testing. The margin tester transmitter, under the control of the controller 210, may optionally include, for example, voltage swing and sine wave jitter (see below and reference). Figure 8 and Figure 9(Further description) The ability to inject controlled noise allows the desired eye margin at the receiver of the PCIe x16 insert card DUT 304 to be altered to a specific target of timing or voltage margin without requiring software running on the PCIe x16 insert card DUT 304. For example, controller 210 can be configured to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link by injecting a reduction in eye width aperture (or implementing other eye width aperture reduction methods) at least by injecting jitter (or implementing other eye width aperture reduction methods) on the margin test transmitter. The jitter injection can be selected to be applied simultaneously to all channels of the single-channel or multi-channel high-speed I / O link, or to be applied independently to each channel of the single-channel or multi-channel high-speed I / O link. Furthermore, the controller 210 can be configured to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link by injecting a reduction in eye height aperture through at least a margin test transmitter. The noise injection can be selected to be applied simultaneously to all channels of the single-channel or multi-channel high-speed I / O link, or to be applied independently to each channel of the single-channel or multi-channel high-speed I / O link.

[0034] The controller 210 may also be coupled to the memory 214, which stores instructions and other data that the controller 210 can read, use, and / or execute to perform the functions described herein.

[0035] Durability and insertion count are important issues in the technically specific embodiments of the margin tester 102 (including the technology-specific fast PCI insert card margin tester 202 and the technology-specific motherboard margin tester 302). Therefore, PCBs 212 and 312 can be implemented using adapters, and the margin is characterized in that the adapter is configured to be replaced at low cost when worn, without replacing the rest of the margin test unit. For example, the replaceable adapter can be coupled to one or more fast PCI slots 306 and / or connectors 208 and is configured to wear after a certain amount of use. Once worn, the adapter can be replaced without replacing the fast PCI insert card margin tester 202 or the rest of the motherboard margin tester 302, as applicable.

[0036] Figure 4 This is a diagram 402 showing the results of example margin tests performed by a high-speed I / O margin tester 102 on several DUTs according to an example embodiment, and identifying potential DUT assembly or production problems based on the results of the margin tests.

[0037] In an example embodiment, margin testing may include: for each of a plurality of Devices Under Test (DUTs), a margin tester 102 evaluates timing eye margin in either or both of the Tx and Rx directions for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link of that DUT. The margin tester 102 can then detect timing eye margin measurements for a plurality of DUTs that are below a predetermined threshold for different channels across the plurality of DUTs. Potential DUT assembly or manufacturing problems can then be detected (visually or automatically by the margin tester 102) based on the detection of timing eye margin measurements for the plurality of DUTs, wherein the timing eye margin measurements for the plurality of DUTs are all below the predetermined threshold for different channels across the plurality of DUTs.

[0038] As an example, in one embodiment, such as Figure 2 The insert card margin tester 202 shown can be used for bench testing / characterization of pre-production samples of motherboards with a single PCIe x8 slot. The example test procedure below can be performed using the insert card margin tester 202, where E-6 timing eye width margin (left + right) is measured simultaneously on each channel for a few milliseconds of testing against the slot. This example includes timing only for simplicity, but other embodiments may include other measurements. Each measurement in this example is performed three times. However, in various embodiments, this can be user-programmable. The measurements shown in Figure 402 are performed at the margin tester receiver and at the motherboard DUT receiver. The measurements performed at the motherboard DUT receiver can be performed in two ways. The first way can be using margin tester jitter (Sj) and voltage swing scan. The second way can be using on-die margin testing at the motherboard receiver. For example, on-die margin testing at the motherboard receiver can be performed under the control of the controller 210 of the insert card margin tester 202, by running software on a bootable driver connected to the motherboard DUT or the basic input / output system (BIOS) software on the motherboard DUT to obtain the supported speed. In this example, the measurement is performed at 16 GT / s, but this can be changed and can be user-configurable.

[0039] The example test procedure described above can produce example results of average margin at the test receiver, as shown in Figure 402. As shown in Figure 402, a consistent low margin on channel 2 across all five DUTs (DUT #1 to DUT #5) can be an indication of a potential design problem. Conversely, low margins on channel 4 of DUT #1, low margins on channel 0 of DUT #3, and low margins on channel 6 of DUT #4 can be indicators of potential assembly or manufacturing problems on those specific channels of those specific DUTs.

[0040] Figure 5 This is a diagram showing the results of another example margin test performed by a high-speed I / O margin tester according to an example embodiment, and a graph identifying potential DUT assembly or manufacturing problems based on the results of the margin test.

[0041] exist Figure 5 Similar indicators of potential design and / or assembly problems can be seen in the example results of voltage swing and average margin of Sj at the DUT receiver shown in Figure 502: as shown in Figure 502, a consistent low margin on channel 1 on all five DUTs (DUT #1 to DUT #5) can be an indicator of potential design problems. In contrast, low margins on channel 0 of DUT #1, low margins on channel 5 of DUT #1, and low margins on channel 7 of DUT #2 can be indicators of potential assembly or manufacturing problems concerning those specific channels on those specific DUTs.

[0042] Additional features of embodiments of the disclosed technology may include the following functions that can be performed under the control of controller 210 (e.g., executing and / or reading instructions from another non-transitory computer-readable storage medium according to a configured FPGA): selecting one or more different high-speed I / O protocols for performing margin testing based on the multi-channel high-speed I / O links of the DUT; simultaneously testing multiple ports of the DUT using a hybrid protocol; outputting the variation of margin between runs on any number of margin test runs of the margin tester on the multi-channel high-speed I / O links; and implementing fixed Tx equalization (EQ) on the DUT to test how much margin variation is due to Tx The impact of EQ training variations; testing the effect of receiver equalization on the margin of the DUT's multi-channel high-speed I / O link using fixed continuous-time linear equalization (CTLE) in the receiver of the margin tester; testing the effect of receiver equalization on the margin of the DUT's multi-channel high-speed I / O link using decision feedback equalization (DFE) in the receiver of the margin tester; calculating the expected margin for the margin tester based on the target channel; automatically generating debugging information when low margin is detected as a result of the evaluation of the electrical margin of the multi-channel high-speed I / O link; switching to use a variable inter-symbol interference (ISI) source to find out how much ISI caused channel failure in the multi-channel high-speed I / O link; testing each channel individually to identify the amount of margin loss due to crosstalk in the DUT's multi-channel high-speed I / O link; turning off the DFE in the receiver of the margin tester to evaluate the margin with and without the DFE and the amount of nonlinear discontinuity in each channel associated with the multi-channel high-speed I / O link; showing comparisons with a reference receiver and typical... The expected margin of the channel and allows marking of lower-than-expected margins even when all channels of the multi-channel high-speed I / O link across the DUT and multiple DUTs are consistent; selection from multiple speeds of the multi-channel high-speed I / O link on which electrical margin assessment is performed; using protocol-specific knowledge, the margin tester infers when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on the multi-channel high-speed I / O link so that the margin tester can perform margin testing on the production line without software on the DUT; automatic capture of time-domain reflectometry (TDR) readings of low-margin channels detected as a result of electrical margin assessment of the multi-channel high-speed I / O link; automatic connection to an oscilloscope to automatically capture digitized waveforms when low margin is detected as a result of electrical margin assessment of the multi-channel high-speed I / O link; and provision of software plug-ins to configure one or more user-selectable options for the DUT by configuring the DUT silicon to implement one or more user-selectable options. Under the control of controller 210, some or all of the above functions may also be provided as selectable options for the user operating the margin tester 102.

[0043] Figure 6 This is a block diagram illustrating a general margin tester 602 with multiple interfaces 604 according to an example embodiment. The multiple interfaces are configured, for example, to be connected to at least one test fixture via one or more cables to evaluate the electrical margin of the DUT's multi-channel high-speed I / O links in either or both of the Tx and Rx directions.

[0044] The general-purpose margin tester 602 includes a controller 210 and an associated memory 214 that can store instructions and other data that the controller 210 can read, use, and / or execute to perform the functions described herein. The general-purpose margin tester 602 may include a number of channels that can be connected (e.g., cable-connected) to a standard test fixture via an interface 604 (such as a standard Fast PCI Compatible Load Board (CLB)) to perform the same tests as those in technology-specific embodiments of margin testers (e.g., insert card margin tester 202 and motherboard margin tester 302) under the control of the controller 210. Furthermore, the general-purpose margin tester 602 supports multiple protocols, and its configuration software includes options for configuring channels for different protocols and host / device roles. The general-purpose margin tester 602 can also be used to test insert cards, including standard Fast PCI Compatible Load Boards (CBBs) for testing insert cards, via cable connection to a test fixture. The interface 604 of the general margin tester 602 may include standard coaxial connectors and cables for each high-speed differential signal, or in various other embodiments, custom high-density connectors and fixtures to minimize cable count and make switching from one DUT to another more efficient.

[0045] Figure 7 This is a low-level block diagram of a margin tester 102 for testing the electrical margin of a multi-channel high-speed I / O link of a DUT in either or both of the Tx and Rx directions, according to an example embodiment.

[0046] An FPGA 714 is shown operatively coupled to a support unit 710 (which may include Ethernet and other communication functions), a time base unit 708 for providing a system reference clock, a high-speed I / O (HSIO) output unit 702, and an HSIO input unit 704. The margin tester 102 may also be powered via an AC / DC power unit 716. The HSIO output unit 702 and the HSIO input unit 704 are also operatively coupled to an I / O connector 706. The FPGA 714 is a semiconductor device based on a matrix of configurable logic blocks (CLBs) connected via a programmable interconnect. In various embodiments, the margin tester 102 may have fewer or more components than shown, and some components or functions of the shown components, while operatively communicating with the margin tester 102, may be located outside or separate from the margin tester 102, or located within or integrated into the FPGA 714.

[0047] The FPGA 714 can be reprogrammed post-manufacturing to meet desired application or functional requirements, such as performing the functions of the margin tester 102 described herein. For example, the firmware on the FPGA 714 can act as a standard Fast PCI upstream port (for testing motherboards, as in the embodiment of the insert card margin tester 202) or a standard Fast PCI root port (for testing insert cards, as in the embodiment of the motherboard margin tester 302), including some link-layer logic for the margin tester 102 to infer when an error begins at the DUT receiver based on traffic in the opposite direction, and to rapidly reduce margin pressure once an error occurs to prevent catastrophic link failure. In some embodiments, the FPGA 714 can be implemented using a System-on-Module (SoM) architecture or can otherwise include a System-on-Module (SoM) architecture that incorporates memory, interfaces, etc., within the FPGA 714. For example, the SoM can be implemented using an Advanced Reduced Instruction Set Computing (RISC) machine, originally the Acorn RISC machine (ARM) architecture.

[0048] Configuration applications and / or scripts can be implemented via FPGA 714 or stored on another accessible memory device or other non-transitory computer-readable storage medium, enabling end users to easily configure margin tester options for margin tester 102, including multiple runs with one or more of the following options. In some embodiments, options may be available for setting bit error rate (BER) targets for margin scans (milliseconds for E-6 margin and minutes for E-12 margin). For example, such targets may include, but are not limited to, targets related to: margin count, margin timing and / or voltage; fixed Tx equalization of the margin tester or DUT transmitter; and fixed Rx CTLE and DFE of the margin tester receiver. In some embodiments, optional applications and / or scripts are provided that remove data from margin tester 102 and provide users with visualization tools to view large margin datasets across multiple products / samples and to view averages, changes and trends between runs over time, and to compare margins across multiple runs on the same DUT with different configuration options (fixed Tx equalization, etc.). In some embodiments, an optional application is provided that can be implemented on a bootable driver for installation on the motherboard under test, which unlocks additional options for motherboard testing, including but not limited to: running in loopback instead of L0, and using specific modes; using die margin characteristics in the DUT silicon instead of voltage swing and Sj margin from the DUT emitter, and running both modes and comparing the results.

[0049] In some embodiments, an optional plug-in model is provided that, if a plug-in is provided for that particular DUT silicon, allows the margin tester configuration application to also configure the RX equalization settings on the DUT silicon. In some embodiments, an optional IBIS-AMI (or similar) software model is provided for each individual margin test unit, which can be used by designers and system integrators to include in their simulations to help establish test constraints / methods for specific customer settings. IBIS-AMI is a modeling standard for the physical layer (PHY) of serializer / deserializer (SerDes), enabling fast, accurate, and statistically significant simulation of multi-gigabit serial links. In some embodiments, the optional IBIS-AMI model is provided to the margin test unit along with a customer model (IBIS-AMI or scattering (S) parameters) and can also be utilized through subsequent efforts to include some level of system de-embedding to improve accuracy and repeatability.

[0050] Figure 8This is a block diagram of an example of a field-programmable gate array (FPGA) 714 configured according to an example embodiment, which can be used in the controller 210 of a margin tester 102 to test the electrical margin of a multi-channel high-speed I / O link of a DUT in either or both of the Tx and Rx directions.

[0051] In various embodiments, FPGA 714 may have fewer or more components than shown, and the functionality of some of the components shown and / or those operatively communicating with FPGA 714 may be located outside or separated from FPGA 714. A register interface 804 is shown, operatively coupled to a local area network (LAN) connection 802 that may include SerDes. Register interface 804 is also operatively coupled to a Link Training and State Machine (LTSSM) and an Rx controller 806. One of the physical layer processes of the operation of margin tester 102 is link initialization and training processing. In high-speed PCI devices, this process establishes many important tasks such as link width negotiation, link data rate negotiation, per-channel bit locking, per-channel symbol locking / block alignment, etc. All these functions are performed by an LTSSM device that observes stimuli from remote link partners and the current state of the link and responds accordingly. Register interface 804 is also operatively coupled to one or more additional LTSSM controller units, such as LTSSM Universal Serial Bus (USB) controller 808 and additional LTSSM USB controller 810. In the example embodiment shown, LTSSM Rx controller 806 is operatively coupled to PCIe Physical Layer (PHY) 16xSerDes 812, and LTSSM USB controller 808 is operatively coupled to USB / Thunderbolt / DisplayPort (USB / TBT / DP) PHY x4 unit 814. Jitter control unit 816 is also present as part of, or operatively coupled to, FPGA 714 for controlling jitter insertion units such that the desired eye margin at the DUT receiver can be modified to a specific target for timing or voltage margin without requiring software running on the DUT.

[0052] Figure 9 This is a block diagram of example output drive options for an FPGA (such as FPGA 714) that can be used in the controller (such as controller 210) of a margin tester, according to an example embodiment, for testing the electrical margin of a multi-channel high-speed I / O link of a DUT in either or both of the Tx and Rx directions.

[0053] The first output drive option is FPGA direct drive option 818, which is not cached and does not include any varactor diode delay injection or jitter injection. The second output drive option is cached drive option 820, which includes a linear buffer or limiting amplifier 826 with a differential output voltage (Vod) that does not include any varactor diode delay injection or jitter injection. The third output drive option is varactor diode delay injection option 822, which includes a linear buffer 826 and a varactor diode assembly 828, resulting in inter-symbol interference (ISI) plus some delay, for example, this delay could be ~3-5 ps. The fourth output drive option is jitter injection option 824, which in one embodiment may include a linear buffer 826 (which may or may not be included) and a delay application-specific integrated circuit (ASIC) 830 (approximately 100 ps at 32 GBd), which may also be available from ADSANTEC. In some embodiments, the linear buffer 826 is not included. For example, in such an embodiment that does not include the linear buffer 826, jitter injection can be performed via differential noise injection.

[0054] In various embodiments, different types of stress can be used by the margin tester 102 to identify various corresponding failure modes, including but not limited to failure modes associated with: assembly; interconnects (surface mount technology (SMT), packages, connectors, vias, etc.); defects; series shock resistance; failure modes causing ISI and baseline drift; eye-closing shocks; failure modes causing failure modes other than width closure; functional test escape; operator configuration errors; material ingress; process variations; receiver bandwidth, which is similar to interconnect variations; power supply rejection ratio (PSRR); vertical / horizontal eye closure; PLL stability; design; incremental changes between channels. A varactor diode-based approach for jitter insertion may be more effective in exacerbating assembly-related defects.

[0055] Figure 10 This is a flowchart of an example method 1000 for performing margin testing on a DUT according to an example embodiment.

[0056] At position 1002, the margin tester 102 establishes a multi-channel high-speed I / O link for the device under test (DUT).

[0057] At 1004, margin tester 102 evaluates the electrical margin of each high-speed input / output (I / O) channel of a multi-channel high-speed I / O link in either or both of the transmit (Tx) and receive (Rx) directions. For example, evaluating the electrical margin may include injecting adjustable stress onto the margin test transmitter of the multi-channel high-speed I / O link. The adjustable stress may include injecting jitter and applying voltage swings simultaneously onto all channels of the multi-channel high-speed I / O link. Evaluating the electrical margin may also include simultaneously evaluating the electrical margin for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link in both the transmit (Tx) and receive (Rx) directions.

[0058] Figure 11 This is a flowchart of an example method 1100, based on an example embodiment, for identifying potential DUT assembly or manufacturing problems by performing margin testing on the electrical margin of the DUT's multi-channel high-speed I / O links in one or both of the Tx and Rx directions.

[0059] At 1102, the margin tester 102 evaluates the timing eye margin for each high-speed input / output (I / O) channel of the multi-channel high-speed I / O link of each of the plurality of DUTs, in either the Tx and receive Rx directions or both.

[0060] At 1104, the margin tester 102 performs a timed eye margin measurement for each of the multiple DUTs based on this evaluation, and for the same channel across the multiple DUTs, the timed eye margin measurement is consistently below a predetermined threshold.

[0061] At 1106, the margin tester 102 identifies potential DUT design problems based on the detection of timing eye margin measurements for each of a plurality of DUTs, wherein the timing eye margin measurements are consistently below a predetermined threshold for the same channel across the plurality of DUTs. The detection may also, or alternatively, include detecting, based on the evaluation, timing eye margin measurements for multiple DUTs that are below the predetermined threshold for different channels across the plurality of DUTs.

[0062] Figure 12 This is a flowchart of an example method 1200 for performing an evaluation of electrical margin initiated by a margin tester 102 based on user-selectable options, according to an exemplary embodiment.

[0063] At 1202, margin tester 102 provides user-selectable options for establishing a multi-channel high-speed input / output (I / O) link of the device under test (DUT) and evaluating the electrical margin of the multi-channel high-speed I / O link in either or both of the transmit (Tx) and receive (Rx) directions. User-selectable options may include customization of the electrical margin evaluation for the multi-channel high-speed I / O link.

[0064] At 1204, the margin tester 102 receives an instruction to select one or more user-selectable options for the margin tester 102.

[0065] At 1206, the margin tester 102 initiates an evaluation of the electrical margin of a multi-channel high-speed I / O link based on an instruction to select one or more user-selectable options for the margin tester 102. The user-selectable options may include, but are not limited to, one or more of the following: an option to select one or more different high-speed I / O protocols for performing margin testing based on the multi-channel high-speed I / O link of the DUT; an option to simultaneously test multiple ports of the DUT using a hybrid protocol; an option to output the variation in margin between any number of margin test runs of the margin tester on the multi-channel high-speed I / O link; and an option to implement a fixed Tx equalization (EQ) on the DUT to test how much margin variation is due to TxEQ training variations. Selected options: an option to test the impact of receiver equalization on the margin of the DUT's multi-channel high-speed I / O link using a fixed CTLE in the receiver of the margin tester; an option to test the impact of receiver equalization on the margin of the DUT's multi-channel high-speed I / O link using decision feedback equalization (DFE) in the receiver of the margin tester; an option to calculate the expected margin of the margin tester based on the target channel; an option to automatically generate debugging information when a low margin is detected as a result of the evaluation of the electrical margin of the multi-channel high-speed I / O link; using The optional options for the margin tester include: switching to use a variable inter-symbol interference (ISI) source to discover how much ISI caused channel failure of the multi-channel high-speed I / O link; optional options for the margin tester to test each channel individually to identify the amount of margin loss due to crosstalk in the multi-channel high-speed I / O link of the DUT; optional options for the margin tester to disable the DFE in the receiver of the margin tester to evaluate the margin with and without the DFE and the amount of nonlinear discontinuity in each channel associated with the multi-channel high-speed I / O link; and options for illustrating the expected values ​​of a reference receiver and a typical channel. The margin and optional options for characterization data for the margin tester to mark the lower-than-expected margin even when all channels of the multi-channel high-speed I / O link across the DUT and multiple DUTs are consistent; optional options for selecting from multiple speeds of the multi-channel high-speed I / O link on which electrical margin assessment is performed; optional options for using protocol-specific knowledge by the margin tester to infer when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on the multi-channel high-speed I / O link so that the margin tester can perform margin testing on the production line without software on the DUT.Selectable options for automatically capturing time-domain reflectometry (TDR) readings of low-margin channels detected as a result of an evaluation of the electrical margin of a multi-channel high-speed I / O link; selectable options for automatically connecting to an oscilloscope to automatically capture digitized waveforms when low margin is detected as a result of an evaluation of the electrical margin of a multi-channel high-speed I / O link; and selectable options for configuring one or more user-selectable options for the DUT by configuring one or more user-selectable options to implement one or more user-selectable options for the DUT silicon.

[0066] Figure 13 This is a flowchart of an example method 1300 for providing a calibrated margin tester according to an exemplary embodiment.

[0067] At 1302, the margin tester 102 may provide the option to perform, or may perform calibration of the margin tester 102, thereby enabling the user to receive a set of expected margins with a series of reference channels.

[0068] At 1304, a calibrated margin tester is provided, configured to measure the electro-eye margin of the device under test (DUT) in either or both of the transmit (Tx) and receive (Rx) directions on a fully operational link of the DUT without a special test mode, and to capture full load and crosstalk effects. Separately calibrated models for the margin tester are also provided, enabling the calculation of expected margins using one or more of the following: a personalized system channel, a receiver model, and a transmitter model. Features in the DUT silicon are also provided, enabling the margin tester to use vendor-defined messages or another protocol mechanism to indicate that a margin test will be performed by the margin tester, allowing the DUT silicon to disable logic that would degrade link width or speed due to errors during the margin test duration.

[0069] Software applications for margin testers are also provided, enabling testing of channel components under test (e.g., bare printed circuit boards (PCBs) or cables) in a test configuration using the margin tester, wherein the margin tester is used on either side or both sides of the channel component under test. In some embodiments, the hardware of the margin tester is provided to a company that manufactures printed circuit boards (PCBs), and data associated with the use of the margin tester is provided to a silicon company that provides silicon used in the production of PCBs.

[0070] Figure 14 This is a flowchart of an example method 1400 for configuring a DUT to run a margin test, according to an example embodiment.

[0071] At 1402, the margin tester 102 receives the configuration settings of the device under test (DUT).

[0072] At 1404, the margin tester 102 configures the DUT to run margin tests under different silicon conditions of the DUT through the margin tester 102. The margin tester 102 can receive software plugins that implement the configuration and DUT silicon parameters for running margin tests under different silicon conditions of the DUT through the margin tester 102. The DUT silicon parameters may include, but are not limited to, one or more of the following: parameters related to the receiver continuous time CTLE and parameters related to the DFE.

[0073] The benefits, advantages, and improvements of the disclosed embodiments include, but are not limited to, the following features. Some embodiments can be implemented almost entirely with off-the-shelf components including standard FPGAs and sinusoidal jitter injection chips or delay lines, and at a very low cost compared to conventional BERT and range. Example embodiments can run on a full multi-channel link operating in normal operating conditions without requiring special software or capturing any effects caused by simultaneous operation of all channels. Another advantage is that the embodiments of this disclosure can be tested in either one or both directions (Tx and Rx) in a single self-contained unit. Various embodiments can also be run in production environments (e.g., in motherboard production test environments) without requiring any software or modifications to the DUT. Protocol-specific test logic can be provided in the silicon / firmware of the margin tester 102 to very quickly identify when an error occurs at the DUT receiver based on data transmitted back to the margin tester by the device under test. Some example embodiments include features implemented in the DUT silicon to identify upcoming margin testing via Fast PCI vendor-specific messages or other standard protocol features, and to place the DUT silicon in a state where it will not normally degrade link width and / or speed due to errors. This helps ensure that margin processes can occur with the DUT receiver using noise injection or voltage swing adjustment without the risk of link width or speed degradation through normal protocol mechanisms. This is an alternative to special logic to quickly infer when an error begins and reduce stress before link or speed degradation may occur.

[0074] Another improvement provided by the example embodiments described herein is that each of the multiple margin tester units is individually calibrated and characterized, so that the user knows the expected margin value for each particular unit and can mark deviations from the expected, even minimal, across its pre-production and production units. As part of this individual characterization and calibration, a model such as the IBIS-AMI model can be provided for each individual margin tester 102, enabling the end user to calculate the expected margin of their particular channel model based on simulated or measured S-parameters.

[0075] This disclosure describes a compact margin tester that is both very fast and very easy to use. Convenient and efficient configuration software is provided for length margin measurements and a variety of user-configurable options. Once configured, the margin tester 102 takes the link as any standard device and then automatically measures the operating link. Testing is performed simultaneously on all channels, and fast electrical margin scans can occur in milliseconds. This enables batch testing, including full testing of all high-speed I / O ports and channels. Various embodiments provide different margin testing modes to achieve a certain level of problem characterization without the need for conventional instrumentation, including but not limited to: repeated counting and analysis of margin variability between runs; selection of Tx equalization (for both the DUT and the margin tester) and selection of Rx equalization (for the margin test receiver); and the possibility of training problems in the DUT Tx or Rx training algorithm during testing; fixing the transmitter equalization in either direction and observing its effect on the margin; fixing the receiver equalization (CTLE) and the number of DFE taps (including zero) in the margin tester receiver and observing its effect on the margin value. For example, if the DFE can be turned off, a significant change in margin indicates a significant discontinuity in a particular channel.

[0076] Another advantage offered by the various embodiments of the margin tester 102 is that every high-speed I / O port and channel of a particular DUT can be tested to obtain electrical margins on all pre-production units and in actual production, creating an unprecedented ability to flag problems and potential problems before they even affect production or before they reach the customer. The various embodiments also enable margin analysis before and after various link events such as power state transitions (in some cases, using software on the DUT).

[0077] Existing solutions employ highly general and characteristic jitter and noise injection methods. The various embodiments of this disclosure offer advantages over those solutions by significantly simplifying, but not eliminating, jitter / amplitude stress in accomplishing this desired task. This simplicity translates into lower operating costs, faster results, and increased product confidence (through large datasets) compared to existing methods.

[0078] The aspects of this disclosure can operate on specially created hardware, on firmware, on a digital signal processor, or on a specially programmed general-purpose computer including a processor that operates according to programmed instructions. The terms controller or processor as used herein are intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and special-purpose hardware controllers. One or more aspects of this disclosure can be implemented with computer-usable data and computer-executable instructions, such as as one or more program modules, executed by one or more computers (including monitoring modules and controllers) or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform a specific task or implement a specific type of abstract data. Computer-executable instructions can be stored on a non-transitory computer-readable storage medium, such as a hard disk, optical disk, removable storage medium, solid-state memory, DDR memory, random access memory (RAM), etc. As will be understood by those skilled in the art, the functionality of program modules in each aspect can be combined or distributed as desired. Furthermore, functionality can be implemented wholly or partially in firmware or hardware equivalents, such as integrated circuits, FPGAs, etc. Certain data structures may be used to more efficiently implement one or more aspects of this disclosure, and such data structures are conceived to be within the scope of the computer-executable instructions and computer-available data described herein.

[0079] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented by instructions carried on or stored on one or more non-transitory computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium means any medium accessible by a computing device. By way of example and not limitation, computer-readable media may include computer storage media and communication media.

[0080] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital video disc (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and temporary forms of signal transmission.

[0081] A communication medium is any medium that can be used for the communication of computer-readable information. By way of example and not limitation, a communication medium may include coaxial cable, fiber optic cable, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0082] Furthermore, this written description refers to specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. For example, where a specific feature is disclosed in the context of a particular aspect, that feature may also be used in the context of other aspects to the extent possible.

[0083] Furthermore, when a method having two or more defined steps or operations is mentioned in this application, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes those possibilities.

[0084] Although specific aspects of this disclosure have been illustrated and described for illustrative purposes, it should be understood that various modifications may be made without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be limited except by the appended claims.

Claims

1. A testing device, comprising: One or more printed circuit boards (PCBs); At least one interface is coupled to one or more PCBs; One or more margin test circuits on a PCB, the margin test circuits comprising: Margin test transmitter and / or margin test receiver; and The controller is coupled to at least one interface. The margin test transmitter and / or margin test receiver are under the control of the controller, and The controller is configured to: Establish a single-channel or multi-channel high-speed input / output (I / O) link for the device under test (DUT), wherein for one or more channels of the single-channel or multi-channel high-speed I / O link, the controller implements physical and logical link layers, which communicatively connect the test device's margin test circuitry to the DUT via at least one interface; and Evaluate the electrical margin of one or more channels in a single-channel or multi-channel high-speed I / O link in either or both of the transmit (Tx) and receive (Rx) directions, wherein in the Tx direction, the controller causes the margin test transmitter to transmit data generated by the margin test circuit to the DUT, and in the Rx direction, the margin test receiver receives data from the DUT. The assessment of electrical margin includes: For each of the multiple Devices Under Test (DUTs), and for each high-speed I / O channel of the DUT's multi-channel high-speed I / O link, evaluate the timing eye margin in either or both of the Tx and receive Rx directions. Based on the evaluation, a timing eye margin measurement is detected for each of a plurality of DUTs, wherein the timing eye margin measurement is consistently below a predetermined threshold for the same channel across the plurality of DUTs; and Potential DUT design problems are identified by detecting eye width and / or eye height margin measurements for each of a plurality of DUTs, wherein the eye width and / or eye height margin measurements are consistently below a predetermined threshold for the same channel across the plurality of DUTs.

2. The testing equipment according to claim 1, wherein, The at least one interface includes at least one channel configured to be connected to at least one test fixture to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link of the DUT in either or both of the Tx and Rx directions.

3. The testing equipment according to claim 2, wherein, The at least one channel includes multiple channels, and the controller is configured to support multiple different protocols for testing devices to test multiple different devices operating according to different protocols, and provides options to configure multiple channels for different device roles and multiple different protocols.

4. The testing equipment according to claim 3, wherein, The multiple channels are configured to be connected to at least one test fixture to evaluate the electrical margin of one or more of the following multi-channel high-speed I / O links: motherboard and plug-in card.

5. The testing equipment according to claim 3, wherein, The multiple channels are configured to be connected to a test fixture to evaluate the power margin of a multi-channel high-speed I / O link for at least one motherboard and at least one insert card.

6. The testing equipment according to claim 4, wherein, The at least one test fixture includes one or more of the following: a Fast Peripheral Component Interconnect (Fast PCI) compatible load board (CLB) and a Fast PCI compatible base board (CBB).

7. The testing equipment according to claim 1, wherein, The single-channel or multi-channel high-speed I / O link of the DUT is a fully operational link without any special test modes.

8. The testing equipment according to claim 1, wherein, The one or more PCBs include the PCB of the insert card, and the DUT is a motherboard, wherein the insert card is configured to be inserted into a connector on the motherboard to implement the physical and link logic layers for each channel of a single-channel or multi-channel high-speed I / O link.

9. The testing equipment according to claim 8, wherein, The card is a fast PCI insertion card.

10. The testing equipment according to claim 1, wherein, The controller is configured to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link by injecting adjustable stress onto a margin test transmitter, the adjustable stress including one or more of the following: a reduction in eye width aperture and a reduction in eye height aperture.

11. The testing apparatus according to claim 10, wherein, The controller is configured to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link by injecting a reduction in eye width aperture through jitter injection on a margin test transmitter. The jitter injection may be selected to be applied simultaneously to all channels of the single-channel or multi-channel high-speed I / O link, or applied independently to each channel of the single-channel or multi-channel high-speed I / O link.

12. The testing equipment according to claim 10, wherein, The controller is configured to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link by injecting a reduction in eye-height aperture through noise injection on a margin test transmitter. The noise injection may be selected to be applied simultaneously to all channels of the single-channel or multi-channel high-speed I / O link, or to be applied independently to each channel of the single-channel or multi-channel high-speed I / O link.

13. The testing equipment according to claim 10, wherein, The controller is configured to evaluate the electrical margin of a single-channel or multi-channel high-speed I / O link by injecting a reduction in eye width and eye height openings through differential noise injection on a margin test transmitter. The differential noise injection may be selected to be applied simultaneously on all channels of the single-channel or multi-channel high-speed I / O link, or applied independently on each channel of the single-channel or multi-channel high-speed I / O link.

14. A method for performing electrical margin testing on a device under test (DUT), the method comprising: A multi-channel high-speed I / O link for the DUT is established by a test device, the test device including a controller coupled to at least one interface, wherein for one or more channels in the multi-channel high-speed I / O link, the controller implements the physical and logical link layers of the test device, which communicatively connects a margin test circuit to the DUT via at least one interface, the margin test circuit including a margin test transmitter and / or a margin test receiver of the test device; as well as The controller of the test equipment controls the margin test transmitter and / or margin test receiver to evaluate the electrical margin of one or more channels of a multi-channel high-speed I / O link in either or both of the transmit (Tx) and receive (Rx) directions, wherein in the Tx direction, the controller causes the margin test transmitter to transmit data generated by the margin test circuit to the DUT, and in the Rx direction the margin test receiver receives data from the DUT. The assessment of electrical margin includes: The timing eye margin is evaluated by the test equipment for each of the multiple devices under test (DUTs) and for each high-speed I / O channel of the multi-channel high-speed I / O link of the DUT, in either or both of the Tx and receive Rx directions. Based on the evaluation, a timing eye margin measurement is detected for each of a plurality of DUTs, wherein the timing eye margin measurement is consistently below a predetermined threshold for the same channel across the plurality of DUTs; and Potential DUT design problems are identified by detecting eye width and / or eye height margin measurements for each of a plurality of DUTs, wherein the eye width and / or eye height margin measurements are consistently below a predetermined threshold for the same channel across the plurality of DUTs.

15. The method according to claim 14, wherein, Assessing electrical margin involves injecting adjustable stress into the margin test transmitter of a multi-channel high-speed I / O link. The adjustable stress includes jitter injection or other methods such as eye-width closure, which can be applied simultaneously to all channels of the multi-channel high-speed I / O link or applied independently to each channel, as well as other methods such as applying noise or eye-height reduction.

16. The method according to claim 15, wherein, Assessing electrical margin involves simultaneously evaluating electrical margin for each high-speed I / O channel of a multi-channel high-speed I / O link in either or both of the Tx and Rx directions.

17. The method of claim 14, wherein, The assessment of electrical margin includes: The eye width and / or eye height margin are evaluated by the test equipment for each of the multiple DUTs and for each high-speed I / O channel of the multi-channel high-speed I / O link of the DUT in either or both of the Tx and Rx directions. Based on the evaluation, timing eye margin measurements were detected for multiple DUTs across multiple DUTs, wherein the timing eye margin measurements were all below a predetermined threshold for different channels across multiple DUTs; and Potential DUT assembly or manufacturing problems are identified by detecting timing eye margin measurements across multiple DUTs, where the timing eye margin measurements are below a predetermined threshold for different channels.

18. A non-transitory computer-readable storage medium having computer-executable instructions stored thereon, said computer-executable instructions causing at least one processor to: User-selectable options are provided for a test device configured to establish a multi-channel high-speed input / output (I / O) link for a device under test (DUT) and to evaluate the electrical margin of one or more channels of the multi-channel high-speed I / O link in either or both of the transmit (Tx) and receive (Rx) directions. The user-selectable options include customization for evaluating the electrical margin of one or more channels of the multi-channel high-speed I / O link. Receive selection of one or more of the user-selectable options for the test equipment; as well as Based on the selection of one or more user-selectable options for the test equipment, the test equipment initiates the evaluation of the electrical margin of one or more channels of a multi-channel high-speed I / O link. The assessment of electrical margin includes: A multi-channel high-speed I / O link is established by the test equipment for the DUT. For one or more channels in the multi-channel high-speed I / O link, a controller coupled to at least one interface in the test equipment implements the physical and logical link layers, which communicatively connects the test equipment's margin test transmitter and / or margin test receiver to the DUT via at least one interface. Under the control of the controller, the margin test transmitter and / or margin test receiver are injected with signals or the timing of signals transmitted between the DUT and the test equipment via the multi-channel high-speed I / O link is adjusted to evaluate the electrical margin of one or more channels of the multi-channel high-speed I / O link in either or both of the transmit (Tx) and receive (Rx) directions, wherein the controller causes the margin test transmitter to transmit data to the DUT in the Tx direction and the margin test receiver to receive data from the DUT in the Rx direction; The assessment of electrical margin includes: The timing eye margin is evaluated by the test equipment for each of the multiple devices under test (DUTs) and for each high-speed I / O channel of the multi-channel high-speed I / O link of the DUT, in either or both of the Tx and receive Rx directions. Based on the evaluation, a timing eye margin measurement is detected for each of a plurality of DUTs, wherein the timing eye margin measurement is consistently below a predetermined threshold for the same channel across the plurality of DUTs; and Potential DUT design problems are identified by detecting eye width and / or eye height margin measurements for each of a plurality of DUTs, wherein the eye width and / or eye height margin measurements are consistently below a predetermined threshold for the same channel across the plurality of DUTs.

19. The non-transitory computer-readable storage medium according to claim 18, wherein, The user-selectable options include one or more of the following: Selectable options for selecting one or more different high-speed I / O protocols for performing margin testing on a DUT-based multi-channel high-speed I / O link; Optional options for simultaneously testing multiple ports of the DUT using a hybrid protocol; Selectable option for outputting the variation of margin between runs on any number of margin test runs of the test equipment on a multi-channel high-speed I / O link; An optional feature for implementing fixed Tx equalization (EQ) on the DUT to test how much margin change is due to Tx EQ training changes; An optional feature for testing the impact of receiver equalization on the margin of the DUT's multi-channel high-speed I / O links using fixed continuous-time linear equalization (CTLE) in the receiver of the test equipment; An optional feature for testing the impact of receiver equalization on the margin of the DUT's multi-channel high-speed I / O links using decision feedback equalization (DFE) in the receiver of the test equipment; Optional options for calculating the expected margin of the test equipment based on the target channel; An optional feature for automatically generating debugging information when low margin is detected as a result of an evaluation of the electrical margin of a multi-channel high-speed I / O link. An optional option for testing equipment to switch to using a variable inter-symbol interference (ISI) source to discover how much ISI caused a channel failure in a multi-channel high-speed I / O link; Optional options for test equipment to individually test each channel to identify the margin loss caused by crosstalk in the DUT's multi-channel high-speed I / O links; An optional option for disabling the DFE in the receiver of the test equipment to evaluate the margin with and without DFE, as well as the amount of nonlinear discontinuity in each channel associated with a multi-channel high-speed I / O link; An optional feature for characterizing test equipment, showing the expected margins of the reference receiver and typical channels, and allowing the marking of lower-than-expected margins for characterization data even when all channels across the DUT and multiple DUTs' multi-channel high-speed I / O links are consistent with the lower-than-expected margins; Selectable options for choosing from multiple speeds of a multi-channel high-speed I / O link on which electrical margin is evaluated; An optional option for using protocol-specific knowledge to infer when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on a multi-channel high-speed I / O link, enabling the test equipment to perform margin testing on the production line without software on the DUT; An optional feature for automatically capturing time-domain reflectometry (TDR) readings of low-margin channels detected as a result of an assessment of the electrical margin of multi-channel high-speed I / O links. An optional option to automatically connect to the oscilloscope to automatically capture digitized waveforms when a low margin is detected as a result of an evaluation of the electrical margin of a multi-channel high-speed I / O link. as well as This is used to configure one or more user-selectable options for the DUT silicon by configuring one or more user-selectable options.

20. The non-transitory computer-readable storage medium according to claim 18, wherein, When executed, the computer-executable instructions cause the at least one processor to cause the test device to perform one or more of the following: Based on the DUT, a multi-channel high-speed I / O link selection is used to perform one or more different high-speed I / O protocols for margin testing; Simultaneously test multiple ports of the DUT using a hybrid protocol; Outputs vary between runs of any number of margin test runs on a test device on a multi-channel high-speed I / O link; Implement fixed Tx equalization (EQ) on the DUT to test how much margin change is due to Tx EQ training changes; Fixed continuous-time linear equalization (CTLE) was used in the receiver of the test equipment to test the impact of receiver equalization on the margin of the DUT's multi-channel high-speed I / O link; Decision feedback equalization (DFE) is used in the receiver of the test equipment to test the impact of receiver equalization on the margin of the DUT's multi-channel high-speed I / O link; Calculate the expected margin for the test equipment based on the target channel; When low margin is detected as a result of an assessment of the electrical margin of a multi-channel high-speed I / O link, debugging information is automatically generated. Switch to using a variable inter-symbol interference (ISI) source to detect how much ISI caused a channel failure in a multi-channel high-speed I / O link; Each channel was tested individually to identify the margin loss caused by crosstalk from the DUT's multi-channel high-speed I / O links; The DFE in the receiver of the test equipment was turned off to evaluate the margin with and without DFE and the amount of nonlinear discontinuity in each channel associated with a multi-channel high-speed I / O link; The expected margins with reference receivers and typical channels are shown, and the lower-than-expected margins are allowed to be marked even when all channels across the DUT and multiple DUTs' multi-channel high-speed I / O links are consistent with the lower-than-expected margins. Choose from multiple speeds of the multi-channel high-speed I / O link on which the electrical margin assessment is performed; Using protocol-specific knowledge, the test equipment infers when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on a multi-channel high-speed I / O link, enabling the test equipment to perform margin testing on the production line without software on the DUT. Automatically capture time-domain reflectometry (TDR) readings of low-margin channels detected as a result of an assessment of the electrical margin of multi-channel high-speed I / O links; When a low margin is detected as a result of an evaluation of the electrical margin of a multi-channel high-speed I / O link, an automatic connection to the oscilloscope is executed to automatically capture the digitized waveform. as well as Provide software plugins to configure one or more user-selectable options for the DUT by configuring the DUT silicon.

21. A margin tester, comprising: Motherboard, including a printed circuit board with multiple slots on a printed circuit board; as well as The controller, integrated on the motherboard, communicates with at least one of the multiple slots. The controller on the motherboard is configured to perform a margin test on at least one insert card via at least one of the plurality of slots when at least one insert card is inserted into at least one of the plurality of slots. The controller on the motherboard is configured to evaluate the electrical margin of the multi-channel high-speed serial input / output (I / O) link of the insert card in either or both of the transmit (Tx) and receive (Rx) directions after the insert card is inserted into at least one slot. The motherboard is configured to evaluate the electrical margin of a multi-channel high-speed I / O link by at least being configured to inject jitter onto a margin test transmitter. The motherboard is configured to inject jitter into the margin test transmitter by means of at least the electrical length configured as the modulation signal path to achieve jitter characteristics relative to an assumed ideal constant timing reference. The assessment of electrical margin includes: The timing eye margin is evaluated by the test equipment for each of the multiple devices under test (DUTs) and for each high-speed I / O channel of the multi-channel high-speed I / O link of the DUT, in either or both of the Tx and receive Rx directions. Based on the evaluation, a timing eye margin measurement is detected for each of a plurality of DUTs, wherein the timing eye margin measurement is consistently below a predetermined threshold for the same channel across the plurality of DUTs; and Potential DUT design problems are identified by detecting eye width and / or eye height margin measurements for each of a plurality of DUTs, wherein the eye width and / or eye height margin measurements are consistently below a predetermined threshold for the same channel across the plurality of DUTs.

22. The margin tester according to claim 21, wherein, The multi-channel high-speed I / O link of the inserted card is a fully operational link without special test modes.

23. The margin tester according to claim 21, wherein, The motherboard is configured to evaluate the power margin of a multi-channel high-speed I / O link by being configured to perform at least the following operations: Controlled noise is injected into the margin test transmitter; as well as The expected eye margin at the receiver on the motherboard will be changed to a specific target of timing or voltage margin.

24. The margin tester according to claim 21, wherein, The motherboard is configured to evaluate the power margin of a multi-channel high-speed I / O link by being configured to perform at least the following operations: Inject jitter into the margin test transmitter; as well as The expected eye margin at the receiver on the motherboard will be changed to a specific target of timing or voltage margin.

25. The margin tester according to claim 21, wherein, The motherboard is configured to evaluate the electrical margin of a multi-channel high-speed I / O link by at least by configuring a margin test receiver to measure eye margin by moving an independent error detector and comparing it with a mismatch with a data sampler.

26. The margin tester according to claim 21, wherein, The motherboard is configured to provide different margin test modes in order to characterize the problems of the inserted card based on the margin test results.

27. The margin tester according to claim 21, wherein, The motherboard is configured to evaluate the electrical margin of a multi-channel high-speed I / O link by injecting a reduction in eye width and eye height openings through differential noise injection on a margin test transmitter. The differential noise injection may be selected to be applied simultaneously to all channels of the multi-channel high-speed I / O link, or applied independently to each channel of the multi-channel high-speed I / O link.

28. The margin tester according to claim 21, wherein, The jitter injection can be selected to be applied simultaneously to all channels of a multi-channel high-speed I / O link, or applied independently to each channel of a multi-channel high-speed I / O link.

29. The margin tester according to claim 21, wherein, The motherboard is configured to inject jitter into the margin test transmitter using a varactor diode-based method.

Images