Chip testing system and chip testing method

Abstract

The application provides a chip testing system, comprising: an automatic testing machine, which generates at least a set of testing signals and a set of adjusting signals, wherein the testing signals comprise positive testing signals and negative testing signals, and the adjusting signals comprise positive adjusting signals and negative adjusting signals; and an adjusting circuit, which comprises a positive adjusting module and a negative adjusting module, the positive adjusting module receives the positive testing signals and the positive adjusting signals, and the negative adjusting module receives the negative testing signals and the negative adjusting signals, so as to continuously adjust the voltage amplitude of the testing signals and / or add common-mode noise to the testing signals based on the adjusting signals. Through the chip testing system provided by the application, the problem that the differential signals of the ATE cannot be continuously changed in voltage amplitude and cannot directly add common-mode noise in the prior testing system using the ATE is solved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing system and a chip testing method. Background Technology

[0002] Serializers / deserializers (SERDES) can achieve higher signal transmission rates due to their lack of a trailing clock and high tolerance to noise jitter. With the increasing speed of signal interconnection today, SERDES has become one of the mainstream high-speed interfaces for chips.

[0003] SERDES typically consist of a transmitter (TX) and a receiver (RX). The most important test for the RX is signal tolerance testing. This test involves sending a pressurized pseudo-random binary sequence (PRBS) signal to the RX via an automated test equipment (ATE). The PRBS checker built into the SERDES is then used to determine whether the RX can correctly receive the signal. Pressurization methods include: reducing the voltage amplitude, adding timing jitter noise, adding voltage noise (i.e., common-mode noise), and increasing or decreasing the data rate.

[0004] For most pressurization methods, ATE can generally provide the corresponding hardware and methods to implement them; however, ATE cannot directly implement the following two special pressurization conditions:

[0005] 1) Adjust the voltage amplitude of the differential signal continuously in real time. For example... Figure 1 As shown, V DP and V DN These are the positive and negative voltages of the differential signal, respectively. The voltage amplitude of the differential signal formed by these voltages in stage 1 is V. OD1 The voltage amplitude in stage 2 is V OD2 The voltage amplitudes in the two stages are different, and the transition from stage 1 to stage 2 is continuous in real time.

[0006] 2) Add common-mode noise to the differential signal. The advantage of differential signals is their ability to resist common-mode interference. For example... Figure 2 As shown, when common-mode noise is present, the single-ended voltage V DP and V DN There is common-mode noise with the same phase on the differential voltage V. DIFF However, this noise is not visible on the screen. The added common-mode noise can be transient or periodic. In addition, the test requires that the voltage amplitude and frequency of the common-mode noise be adjustable.

[0007] For the two pressurization conditions mentioned above, the existing solutions are as follows:

[0008] When testing the RX's ability to receive signals of different amplitudes, a feasible approach is for the ATE to send signals of different voltage amplitudes multiple times, and the chip to determine the correctness of each signal with a different voltage amplitude. The signals sent by the ATE at this time are as follows: Figure 3 As shown, from the voltage amplitude V OD1 Phase 1 to voltage amplitude of V OD2 Phase 2 consists of a time interval T. During this time T, the ATE needs to issue a new instruction to change the voltage amplitude of the transmitted signal, preventing the chip RX from correctly judging the signal during this period. After the voltage amplitude modification is completed and Phase 2 begins, the chip is reset and then re-evaluates the correctness of the received signal.

[0009] Because the ATE (Automatic Test Equipment) cannot handle continuous voltage amplitude changes, the existing solution requires separate testing for signals with different voltage amplitudes. This means the test cannot cover conditions of continuous voltage amplitude changes; furthermore, resetting the chip to enter test mode increases the overall chip testing time. Moreover, the ATE cannot directly introduce common-mode noise, thus failing to cover the RX's tolerance to common-mode noise.

[0010] Another feasible solution is to build a test platform using dedicated test instruments instead of ATE, such as signal generators, DC regulated power supplies and field programmable gate arrays (FPGAs). Based on the test specialization of dedicated test instruments, it is possible to send signals with continuously varying voltage amplitudes and also to add common-mode noise required for the test.

[0011] Compared to test systems using ATE (Automatic Test Equipment), test systems built using dedicated test instruments have several obvious disadvantages in chip mass production: First, the system setup is cumbersome, requiring specialized personnel familiar with the system to participate each time, and the system is unstable, which can easily cause mass production interruptions; Second, the limited number of signal channels of the test instruments restricts the number of chips that can be tested simultaneously, affecting the chip mass production yield. Summary of the Invention

[0012] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a chip testing system and chip testing method to solve the problems in existing test systems using ATE that the differential signal of ATE cannot undergo continuous voltage amplitude changes and cannot directly incorporate common-mode noise.

[0013] To achieve the above and other related objectives, the present invention provides a chip testing system, the chip testing system comprising:

[0014] An automatic testing machine generates at least one set of test signals and one set of adjustment signals, wherein the test signals include positive terminal test signals and negative terminal test signals, and the adjustment signals include positive terminal adjustment signals and negative terminal adjustment signals;

[0015] The adjustment circuit includes a positive terminal adjustment module and a negative terminal adjustment module. The positive terminal adjustment module receives the positive terminal test signal and the positive terminal adjustment signal, and the negative terminal adjustment module receives the negative terminal test signal and the negative terminal adjustment signal to continuously adjust the voltage amplitude of the test signal and / or add common-mode noise to the test signal based on the adjustment signal.

[0016] Optionally, both the positive terminal adjustment module and the negative terminal adjustment module are implemented using a three-resistance power divider.

[0017] Optionally, in the three-resistor power divider, the resistance value of each resistor is 50Ω, and the insertion loss between each port is 6dB.

[0018] Optionally, the chip testing system further includes: a test load board, which carries the adjustment circuit and the chip under test, and performs signal transmission between the automatic tester, the adjustment circuit and the chip under test.

[0019] Optionally, the adjustment circuit is mounted on the test load board using a surface mount method.

[0020] The present invention also provides a chip testing method, the chip testing method comprising:

[0021] Set up the chip testing system as described above;

[0022] The SERDES chip was subjected to signal tolerance testing using the chip testing system described above.

[0023] Optionally, the method for performing signal tolerance testing on the SERDES chip by reducing the voltage amplitude includes:

[0024] The SERDES chip is powered on and enters test mode;

[0025] The automatic testing machine generates two sets of differential signals. One set of differential signals serves as a test signal and has a first voltage amplitude, while the other set of differential signals serves as an adjustment signal and has a second voltage amplitude. The test signal is continuously output within a set time period, and the adjustment signal is continuously output during the first stage of the set time period and stops outputting during the second stage.

[0026] The adjustment circuit continuously adjusts the voltage amplitude of the test signal based on the adjustment signal and generates an input signal, wherein the input signal has a third voltage amplitude in the first stage, a fourth voltage amplitude in the second stage, and the third voltage amplitude is greater than the fourth voltage amplitude.

[0027] The SERDES chip performs a signal tolerance test based on the input signal.

[0028] Optionally, the third voltage amplitude is equal to half the sum of the first voltage amplitude and the second voltage amplitude, and the fourth voltage amplitude is equal to half the first voltage amplitude.

[0029] Optionally, the method for testing the signal tolerance of the SERDES chip by adding common-mode noise includes:

[0030] The SERDES chip is powered on and enters test mode;

[0031] The automatic testing machine generates a set of differential signals and a set of single-ended signals. The differential signals serve as test signals and have a fifth voltage amplitude. The two single-ended signals serve as adjustment signals and have the same voltage amplitude and phase.

[0032] The adjustment circuit adds common-mode noise to the test signal based on the adjustment signal and generates an input signal, wherein the input signal has a sixth voltage amplitude, and the sixth voltage amplitude is less than the fifth voltage amplitude;

[0033] The SERDES chip performs a signal tolerance test based on the input signal.

[0034] Optionally, the sixth voltage amplitude is equal to half of the fifth voltage amplitude.

[0035] As described above, the chip testing system and chip testing method of the present invention, by adding an adjustment circuit to the existing test system using ATE to adjust the differential signal, can realize continuous change of differential signal voltage amplitude and add common-mode noise to the differential signal, thereby realizing the signal tolerance test of SERDES chip using ATE. Attached Figure Description

[0036] Figure 1 This diagram illustrates the continuous adjustment of the differential signal voltage amplitude during signal tolerance testing of a SERDES chip.

[0037] Figure 2 This diagram illustrates the addition of common-mode noise to the differential signal during signal tolerance testing of a SERDES chip.

[0038] Figure 3 This diagram illustrates the adjustment of the differential signal voltage amplitude when using an existing ATE testing system to perform signal tolerance testing on a SERDES chip.

[0039] Figure 4 The diagram shown is a schematic representation of the chip testing system of this invention.

[0040] Figure 5 The diagram shown is a circuit schematic of the three-resistance power divider of the present invention.

[0041] Figure 6 The diagram shows the relevant signal waveforms in the first stage when the chip testing system of this invention performs signal tolerance testing on the SERDES chip based on reducing the voltage amplitude.

[0042] Figure 7 The diagram shows the relevant signal waveforms in the second stage when the chip testing system of this invention performs signal tolerance testing on the SERDES chip based on reducing the voltage amplitude.

[0043] Figure 8 The diagram shows the waveforms of related signals when the voltage amplitude of the input signal in the chip testing system of this invention is continuously switched.

[0044] Figure 9 The diagram shows the relevant signal waveforms when the chip testing system of this invention performs signal tolerance testing on the SERDES chip based on the addition of common-mode noise.

[0045] Component designation explanation

[0046] 10 Chip Testing System

[0047] 100 Automatic Testing Machine

[0048] 101 Power Module

[0049] 102 High-speed digital modules

[0050] 103 Low-speed digital module

[0051] 200 Adjustment Circuit

[0052] 201 Positive End Adjustment Module

[0053] 202 Negative-end adjustment module

[0054] 300 test load board

[0055] 400 chips under test Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 4 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] like Figure 4 As shown, this embodiment provides a chip testing system 10, which includes an automatic tester 100 and an adjustment circuit 200; further, the chip testing system 10 also includes a test load board 300.

[0059] The automatic testing machine 100 generates at least one set of test signals and one set of adjustment signals. The test signals include a positive terminal test signal DP and a negative terminal test signal DN, and the adjustment signals include a positive terminal adjustment signal SP and a negative terminal adjustment signal SN.

[0060] Specifically, the automatic testing machine 100 includes: a power supply module 101, a high-speed digital module 102, and a low-speed digital module 103.

[0061] in,

[0062] In addition to powering the automatic test machine 100 itself, the power module 101 also generates a power supply signal to power the chip under test 400. Of course, when the chip test system 10 also includes a test load board 300, the power module 101 generates another power supply signal to power the test load board 300. The voltage of the two power supply signals can be the same or different, depending on the power supply requirements of the test load board 300 and the chip under test 400.

[0063] The high-speed digital module 102 includes at least two sets of differential circuit units for generating test signals and adjustment signals. Of course, if it is desired to test multiple chips under test 400 simultaneously, the number of differential circuit units in the high-speed digital module 102 and the number of corresponding adjustment circuits 200 can be expanded (for one chip under test 400, two sets of differential circuit units and one adjustment circuit 200 are required). In practical applications, the number of differential circuit units is usually greater than 10, and may even be greater than 20. Among them, the test signals and adjustment signals are high-speed signals, such as GHz-level signals.

[0064] In addition, the automatic tester 100 can control whether each differential circuit unit in the high-speed digital module 102 outputs, when it outputs, and whether it is differential output or single-ended output through a program. It can even control parameters such as the amplitude, phase, and frequency of the output signal. These are the conventional functions of the automatic tester 100, and the details of how to control them will not be explained here.

[0065] The low-speed digital module 103 includes a clock unit and a control unit. The clock unit generates a clock signal, and the control unit generates control signals, such as register configuration signals, to enable the test mode setting of the chip under test 400 based on the clock signal and control signal, so that the chip under test 400 can enter the test mode. The clock signal and control signal are low-speed signals, such as signals at the MHz level.

[0066] The adjustment circuit 200 includes a positive terminal adjustment module 201 and a negative terminal adjustment module 202. The positive terminal adjustment module 201 receives a positive terminal test signal DP and a positive terminal adjustment signal SP, and the negative terminal adjustment module 202 receives a negative terminal test signal DN and a negative terminal adjustment signal SN, so as to continuously adjust the voltage amplitude of the test signal based on the adjustment signal and / or add common-mode noise to the test signal.

[0067] Specifically, such as Figure 5 As shown, both the positive terminal adjustment module 201 and the negative terminal adjustment module 202 are implemented using a three-resistor power divider (also known as a combiner). The three-resistor power divider includes a first resistor R1, a second resistor R2, and a third resistor R3. The first ends of the three resistors are connected to each other, and the second ends serve as the three ports of the three-resistor power divider. For example, the second end of the first resistor R1 serves as port A, the second end of the second resistor R2 serves as port B, and the second end of the third resistor R3 serves as port C.

[0068] More specifically, in this three-resistor power divider, the resistance of each resistor is 50Ω, and the insertion loss between each port is 6dB; that is, R1=R2=R3=50Ω, the insertion loss between port A and port B is 6dB, the insertion loss between port A and port C is 6dB, and the insertion loss between port B and port C is 6dB.

[0069] In this embodiment of the three-resistor power divider, when a signal is input from any one of the ports and output from the other two ports, the voltage amplitude of the signal at the two output ports is half the voltage amplitude of the signal at the input port. Utilizing the symmetry of each port, when a signal is input from two ports and output from the third port, the voltage amplitude of the signal at the output port is half the sum of the voltage amplitudes of the signals at the two input ports. Thus, it is possible to continuously adjust the voltage amplitude of the test signal based on the adjustment signal, and / or to add common-mode noise to the test signal based on the adjustment signal.

[0070] The test load board 300 carries the adjustment circuit 200 and the chip under test 400, and performs signal transmission between the automatic test machine 100, the adjustment circuit 200, and the chip under test 400. For chip testing, using a test load board is beneficial for simultaneous testing of multiple chips and can also prevent chips from being damaged by external forces during the testing process.

[0071] In practical applications, the chip under test 400 can be inserted into the test load board 300 via a mounting card or directly mounted on the test load board 300, which has no substantial impact on this embodiment. Furthermore, the adjustment circuit 200 is directly mounted on the test load board 300. The resistors within it can be either through-hole or surface-mount, thereby improving the overall system stability and simplifying system setup. However, considering factors such as manufacturing process, size, and expansion, surface-mount mounting is generally used; that is, the adjustment circuit 200 is mounted on the test load board 300 using a surface-mount method.

[0072] Accordingly, this embodiment also provides a chip testing method, which includes: building the chip testing system 10 as described above, and performing signal tolerance testing on the SERDES chip based on the chip testing system 10.

[0073] Signal tolerance testing of SERDES chips mainly involves applying a voltage-enhanced input signal (such as a PRBS signal) to the SERDES chip and using the chip's built-in detector (such as a PRBS detector) to determine whether its receiver can correctly receive the signal. This completes the signal tolerance test. The voltage application methods include: reducing the voltage amplitude, adding timing jitter noise, adding voltage noise (i.e., common-mode noise), and increasing or decreasing the input speed.

[0074] Specifically, the signal tolerance test of the SERDES chip is performed by reducing the voltage amplitude. That is, the voltage amplitude of the signal input to the SERDES chip is reduced, and it is determined whether the receiver of the SERDES chip can correctly receive the signal. The method includes the following steps.

[0075] Step 1.1) Power on the SERDES chip and enter test mode.

[0076] The SERDES chip is powered on by the power module 101 in the automatic test machine 100, and the SERDES chip enters the test mode by the clock signal and control signal generated by the low-speed digital module 103.

[0077] Step 1.2) The automatic testing machine 100 generates two sets of differential signals. One set of differential signals serves as a test signal and has a first voltage amplitude, while the other set of differential signals serves as an adjustment signal and has a second voltage amplitude. The test signal is continuously output within a set time period, and the adjustment signal is continuously output during the first stage of the set time period and stops outputting during the second stage.

[0078] The automatic testing machine 100 controls two differential circuit units of the high-speed digital module 102, such that one differential circuit unit continuously outputs a differential signal with a first voltage amplitude within a set time, and the other differential circuit unit continuously outputs a differential signal with a second voltage amplitude in the first stage of the set time and stops outputting in the second stage.

[0079] It should be noted that in this embodiment, the first stage and the second stage within the set time are continuous without any interruption. That is, the start point of the first stage is the start point of the set time, the end point of the first stage is the start point of the second stage, and the end point of the second stage is the end point of the set time.

[0080] Step 1.3) The adjustment circuit 200 continuously adjusts the voltage amplitude of the test signal based on the adjustment signal and generates an input signal, wherein the input signal has a third voltage amplitude in the first stage and a fourth voltage amplitude in the second stage, and the third voltage amplitude is greater than the fourth voltage amplitude.

[0081] The input signals include the positive input signal RXP and the negative input signal RXN;

[0082] In the first stage, the test signal has a first voltage amplitude V1, and the adjustment signal has a second voltage amplitude V2. At this time, the voltage amplitude of the positive terminal test signal... Voltage amplitude of the negative terminal test signal positive terminal adjustment signal voltage amplitude The voltage amplitude of the negative terminal adjustment signal Utilizing the characteristics of a three-resistor power divider, the voltage amplitude of the positive input signal... Voltage amplitude of the negative input signal Therefore, the voltage amplitude of the input signal That is, the input signal has a third voltage amplitude, and the third voltage amplitude is equal to half the sum of the first voltage amplitude and the second voltage amplitude, such as... Figure 6 As shown;

[0083] In the second stage, the test signal has a first voltage amplitude V1, and the adjustment signal is not output, meaning the voltage amplitude of the adjustment signal is zero. At this time, the voltage amplitude of the positive terminal test signal... Voltage amplitude of the negative terminal test signal The voltage amplitude V of the positive terminal adjustment signal SP =0, the negative terminal adjusts the voltage amplitude V of the signal. SN =0; Utilizing the characteristics of a three-resistor power divider, the voltage amplitude of the positive input signal is... Voltage amplitude of the negative input signal Therefore, the voltage amplitude of the input signal That is, the input signal has a fourth voltage amplitude, and the fourth voltage amplitude is equal to half of the first voltage amplitude, such as... Figure 7 As shown;

[0084] Since the first and second stages are consecutive in time, we can obtain the following: Figure 8 The input signal shown is a continuously dynamically switching voltage amplitude. The test signal serves as the main signal with a fixed voltage amplitude, while the adjustment signal serves as the secondary signal. When a large voltage amplitude is required for the input signal, the adjustment signal is output with a fixed voltage amplitude; when a small voltage amplitude is required, the adjustment signal is not output. In this way, the signal input to the SERDES chip can be continuously switched from a large voltage amplitude to a small voltage amplitude without the automatic tester 100 stopping signal transmission midway and waiting for the voltage amplitude change command to take effect before switching back to a small voltage amplitude signal to continue transmission.

[0085] In practical applications, the first voltage amplitude and the second voltage amplitude can be reasonably designed based on the expected voltage amplitude (i.e., the third voltage amplitude) and its reduced value (i.e., the fourth voltage amplitude). The first voltage amplitude and the second voltage amplitude can be the same or different, which has no substantial impact on this embodiment.

[0086] Step 1.4) The SERDES chip performs a signal tolerance test based on the input signal.

[0087] After the input signal is sent to the SERDES chip, the built-in detector of the SERDES chip will determine whether the receiving end has correctly received the input signal, and make a judgment on the function of the SERDES chip based on the judgment result.

[0088] If an input signal with a third voltage amplitude is given to the SERDES chip, the built-in detector of the SERDES chip will determine whether the receiving end correctly receives the input signal. If the receiving end correctly receives the input signal, the SERDES chip is considered to be functioning normally under the test conditions, and the voltage test continues. If the receiving end does not correctly receive the input signal, the SERDES chip is considered to be malfunctioning under the test conditions, the current test conditions are recorded, and the test ends.

[0089] Continue with the voltage test. After the input signal with the fourth voltage amplitude is given to the SERDES chip, the built-in detector of the SERDES chip will determine whether the receiver correctly receives the input signal. If the receiver correctly receives the input signal, the SERDES chip is considered to be functioning normally under the test conditions, and the test ends. If the receiver does not correctly receive the input signal, the SERDES chip is considered to be malfunctioning under the test conditions, the current test conditions are recorded, and the test ends.

[0090] Specifically, the signal tolerance test of the SERDES chip is performed by adding common-mode noise. That is, common-mode noise is added to the signal input to the SERDES chip, and it is determined whether the receiver of the SERDES chip can correctly receive the signal. The method includes the following steps.

[0091] Step 2.1) Power on the SERDES chip and enter test mode.

[0092] The SERDES chip is powered on by the power module 101 in the automatic test machine 100, and the SERDES chip enters the test mode by the clock signal and control signal generated by the low-speed digital module 103.

[0093] Step 2.2) The automatic testing machine 100 generates a set of differential signals and a set of single-ended signals. The differential signals serve as test signals and have a fifth voltage amplitude. The two single-ended signals serve as adjustment signals and have the same voltage amplitude and phase. The frequency of the single-ended signals can be set according to actual needs.

[0094] The two differential circuit units of the high-speed digital module 102 in the automatic test machine 100 are controlled so that one of the differential circuit units outputs a differential signal with a fifth voltage amplitude, and the other differential circuit unit outputs a single-ended signal with a fixed voltage amplitude, frequency and phase.

[0095] Step 2.3) The adjustment circuit 200 adds common-mode noise to the test signal based on the adjustment signal and generates an input signal, wherein the input signal has a sixth voltage amplitude, and the sixth voltage amplitude is less than the fifth voltage amplitude.

[0096] The test signal is a differential signal with a fifth voltage amplitude, and the adjustment signal is a single-ended signal with a fixed voltage amplitude, frequency, and phase, which can be considered as common-mode noise. Utilizing the characteristics of a three-resistor power divider, common-mode noise can be added to the positive terminal test signal DP and the negative terminal test signal DN, thus obtaining the positive terminal input signal RXP and the negative terminal input signal RXN with added common-mode noise, respectively; that is, obtaining the input signal with added common-mode noise. For the differential input signal, its single-ended voltage V... RXP and V RXN The common-mode noise does exist, but due to the suppression effect of the differential signal itself on the common-mode noise, it is ultimately reduced at the differential voltage V. DIFF The common-mode noise is not visible above; moreover, the sixth voltage amplitude is equal to half the fifth voltage amplitude, such as... Figure 9 As shown. In practical applications, the fifth voltage amplitude can be reasonably designed according to the expected voltage amplitude (i.e., the sixth voltage amplitude). Moreover, by reasonably designing the voltage amplitude and frequency of common-mode noise, the expected chip test coverage can be achieved. Step 2.4) The SERDES chip performs signal tolerance testing based on the input signal.

[0097] After the input signal is sent to the SERDES chip receiver, the built-in detector of the SERDES chip will determine whether the receiver has correctly received the input signal, and make a judgment on the function of the SERDES chip based on the judgment result.

[0098] If a common-mode noise with a fixed voltage amplitude and frequency is added to the input signal and then fed to the SERDES chip, the built-in detector of the SERDES chip will determine whether the receiver correctly receives the input signal. If the receiver correctly receives the input signal, the SERDES chip is considered to be functioning normally under the test conditions, and the voltage test continues. If the receiver fails to correctly receive the input signal, the SERDES chip is considered to be malfunctioning under the test conditions, the current test conditions are recorded, and the test ends. Continuing the voltage test involves altering the voltage amplitude and / or frequency of the common-mode noise to worsen the test conditions and repeat the test until the SERDES chip can no longer receive the signal correctly.

[0099] Specifically, the signal tolerance test of the SERDES chip is performed by adding timing jitter noise. That is, timing jitter noise is added to the signal input to the SERDES chip, and it is determined whether the receiving end can correctly receive the signal. The automatic test machine 100 can add timing jitter noise to the signal input to the SERDES chip. Therefore, in this test process, the automatic test machine 100 is controlled to make the adjustment signal have no output. The test scheme is the same as the existing scheme, and will not be described again here.

[0100] The signal tolerance test of the SERDES chip is performed by speeding up or slowing down the input signal rate. That is, the input signal rate to the SERDES chip is increased or decreased, and it is determined whether the receiving end can receive the signal correctly. The automatic test machine 100 can increase or decrease the input signal rate to the SERDES chip. Therefore, in this test process, the automatic test machine 100 is controlled to make the adjustment signal have no output. The test scheme is the same as the existing scheme, and will not be described again here.

[0101] In summary, the chip testing system and method of the present invention, by adding an adjustment circuit to the existing test system using ATE (Automatic Test Equipment), can adjust and process the differential signal, thereby enabling continuous variation of the differential signal voltage amplitude and adding common-mode noise to the differential signal, thus achieving signal tolerance testing of SERDES chips using ATE. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A chip testing system, characterized in that, The chip testing system includes: An automatic testing machine generates at least one set of differential signals as test signals and one set of adjustment signals, wherein the test signals include a positive terminal test signal and a negative terminal test signal, and the adjustment signals include a positive terminal adjustment signal and a negative terminal adjustment signal; An adjustment circuit includes a positive terminal adjustment module and a negative terminal adjustment module. The positive terminal adjustment module receives the positive terminal test signal and the positive terminal adjustment signal, and the negative terminal adjustment module receives the negative terminal test signal and the negative terminal adjustment signal. The adjustment signal is based on another set of differential signals, and the voltage amplitude of the test signal is continuously adjusted based on the adjustment signal. The test signal is continuously output within a set time period, the adjustment signal is continuously output during a first stage within the set time period, and the output stops during a second stage. Alternatively, the adjustment signal is based on two single-ended signals with the same voltage amplitude and phase, and common-mode noise is added to the test signal based on the adjustment signal. Both the positive terminal adjustment module and the negative terminal adjustment module are implemented using a three-resistor power divider.

2. The chip testing system according to claim 1, characterized in that, In the three-resistor power divider, the resistance of each resistor is 50Ω, and the insertion loss between each port is 6dB.

3. The chip testing system according to claim 1 or 2, characterized in that, The chip testing system further includes a test load board, which carries the adjustment circuit and the chip under test, and performs signal transmission between the automatic tester, the adjustment circuit and the chip under test.

4. The chip testing system according to claim 3, characterized in that, The adjustment circuit is mounted on the test load board using a surface mount method.

5. A chip testing method, characterized in that, The chip testing method includes: Construct a chip testing system as described in any one of claims 1-4; The SERDES chip was subjected to signal tolerance testing using the chip testing system described above.

6. The chip testing method according to claim 5, characterized in that, The method for conducting signal tolerance testing on the SERDES chip by reducing the voltage amplitude includes: The SERDES chip is powered on and enters test mode; The automatic testing machine generates two sets of differential signals. One set of differential signals serves as a test signal and has a first voltage amplitude, while the other set of differential signals serves as an adjustment signal and has a second voltage amplitude. The test signal is continuously output within a set time period, and the adjustment signal is continuously output during the first stage of the set time period and stops outputting during the second stage. The adjustment circuit continuously adjusts the voltage amplitude of the test signal based on the adjustment signal and generates an input signal, wherein the input signal has a third voltage amplitude in the first stage, a fourth voltage amplitude in the second stage, and the third voltage amplitude is greater than the fourth voltage amplitude. The SERDES chip performs a signal tolerance test based on the input signal.

7. The chip testing method according to claim 6, characterized in that, The third voltage amplitude is equal to half the sum of the first voltage amplitude and the second voltage amplitude, and the fourth voltage amplitude is equal to half the first voltage amplitude.

8. The chip testing method according to claim 5, characterized in that, The method for testing the signal tolerance of the SERDES chip by adding common-mode noise includes: The SERDES chip is powered on and enters test mode; The automatic testing machine generates a set of differential signals and a set of single-ended signals. The differential signals serve as test signals and have a fifth voltage amplitude. The two single-ended signals serve as adjustment signals and have the same voltage amplitude and phase. The adjustment circuit adds common-mode noise to the test signal based on the adjustment signal and generates an input signal, wherein the input signal has a sixth voltage amplitude, and the sixth voltage amplitude is less than the fifth voltage amplitude; The SERDES chip performs a signal tolerance test based on the input signal.

9. The chip testing method according to claim 8, characterized in that, The sixth voltage amplitude is equal to half of the fifth voltage amplitude.

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