Circuit board

Abstract

The embodiment of the utility model provides a circuit board, which comprises a board body, a chip array arranged on the board body, a power supply module and a processing module, the chip array comprises a power taking unit, the power taking unit comprises at least one chip, the power supply module is used for being connected with a power supply, the power supply module is electrically connected with the power taking unit and is used for supplying power to the power taking unit, and the processing module is electrically connected with the chip. The power supply module is provided with a voltage monitoring point, the processing module is electrically connected with the voltage monitoring point and used for collecting the voltage of the voltage monitoring point, the voltage of the circuit board can be monitored, the stability of the voltage can be guaranteed, and meanwhile a fault point can be rapidly recognized.

Description

[0001] This disclosure claims priority to Chinese Patent Application No. 2025203380449, filed with the Chinese Patent Office on February 27, 2025, entitled "Circuit Board", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic equipment technology, and more particularly to a circuit board. Background Technology

[0003] Under normal circumstances, the operating voltage of the circuit board is sufficient to meet the user's regular needs. However, in actual use, users may add other components due to specific requirements, which can lead to unstable operation of the circuit board and increase the failure rate.

[0004] The existing fault diagnosis of circuit boards requires repeated testing and screening, which is inefficient. Utility Model Content

[0005] This application provides a circuit board to solve or alleviate one or more technical problems in the prior art.

[0006] As one aspect of the embodiments of this application, this application provides a circuit board, including:

[0007] plate body;

[0008] A chip array is disposed on the board, and the chip array includes a power-taking unit, which includes at least one chip.

[0009] The power supply module is located on the board and is used to connect to the power source. The power supply module is electrically connected to the power extraction unit and is used to supply power to the power extraction unit. The power supply module has a voltage monitoring point.

[0010] The processing module is located on the board and is electrically connected to the voltage monitoring point to collect the voltage of the voltage monitoring point.

[0011] In one embodiment, the power supply module includes a first conductive element and a second conductive element, the first conductive element being connected to the negative terminal of the power supply and the second conductive element being connected to the positive terminal of the power supply; the processing module is connected between the first conductive element and the second conductive element.

[0012] In one embodiment, the power supply module includes an electrical connector connected between a first conductive element and a second conductive element, the electrical connector being connected in series with multiple power extraction units, and the electrical connector having a voltage monitoring point.

[0013] In one embodiment, the chip array includes a plurality of power-collecting groups connected in series, the plurality of power-collecting groups being arranged at intervals in a first direction, and each power-collecting group including a plurality of power-collecting units arranged sequentially and connected in series in a second direction.

[0014] The electrical connector has multiple voltage monitoring points evenly distributed along the series path of multiple series-connected power supply groups.

[0015] In one embodiment, the power supply module includes a booster module connected to at least one downstream power-taking unit in the data transmission path, for providing the required voltage for data transmission of the at least one downstream power-taking unit.

[0016] The voltage output terminal of the boost module has a voltage monitoring point.

[0017] In one embodiment, the power supply module includes a voltage regulator module connected between the voltage output terminal of the boost module and at least one downstream power extraction unit.

[0018] The voltage output terminal of the voltage regulator module has a voltage monitoring point.

[0019] In one embodiment, the processing module includes a processor and an analog-to-digital converter (ADC). The ADC is connected to a voltage monitoring point for acquiring the voltage at the monitoring point, and the processor is also connected to the ADC for acquiring the voltage at the monitoring point.

[0020] In one embodiment, there are multiple power-gathering units connected in series, and the total number of power-gathering units is greater than 40 and less than 100.

[0021] In one embodiment, the power-gathering unit includes multiple chips, which are arranged at intervals along a first direction and connected in parallel.

[0022] In one embodiment, the power-gathering unit includes two chips connected in parallel.

[0023] In one embodiment, the heat dissipation airflow flows through the circuit board in a first direction. In the first direction, the chip array includes a first power-taking group and a second power-taking group. The first power-taking group and the second power-taking group each include a plurality of power-taking units arranged sequentially in a second direction.

[0024] The first power take-up group is located near the air inlet side of the panel, and the second power take-up group is located near the air outlet side of the panel.

[0025] In one embodiment, along the second direction, the middle region of the first power-taking group and the middle region of the second power-taking group each have vacancy positions.

[0026] In one embodiment, the first power supply group and the second power supply group each include a plurality of power supply areas arranged sequentially along a second direction;

[0027] In the second direction, the distance between any two adjacent power-collecting areas is greater than the distance between any two adjacent power-collecting units within any power-collecting area.

[0028] In one implementation, the number of power-taking areas in the second power-taking group is greater than the number of power-taking areas in the first power-taking group.

[0029] In one embodiment, the chip array includes at least one third power supply group located between a first power supply group and a second power supply group along a first direction, and the third power supply group includes a plurality of power supply units arranged sequentially along a second direction.

[0030] In one embodiment, there are two third power supply groups, which are arranged at intervals in the first direction.

[0031] In one embodiment, the extension dimension of at least one third power supply group in the second direction is smaller than the extension dimension of the first power supply group in the second direction, and the extension dimension of at least one third power supply group in the second direction is smaller than the extension dimension of the second power supply group in the second direction.

[0032] In one implementation, the number of chips in the first power-supply group is greater than the number of chips in the second power-supply group, and the number of chips in the first power-supply group is less than the number of chips in the third power-supply group.

[0033] In one embodiment, the spacing between the first power supply group, the third power supply group, and the second power supply group increases sequentially along a first direction.

[0034] In one embodiment, the chip array is divided into a first chip array and a second chip array, with the center line of the board extending along the second direction as the dividing line. The total number of chips in the first chip array near the air inlet side of the circuit board is greater than the total number of chips in the second chip array near the air outlet side of the circuit board.

[0035] In one embodiment, the board is provided with a signal interface, which is connected to each chip and processing module respectively.

[0036] In one implementation, the signal interface is connected to each chip sequentially via a signal transmission link;

[0037] The circuit board includes at least two clock frequency generators, one of which is located near the start of the signal transmission link to synchronize the data transmitted at the start of the signal transmission link; at least one clock frequency generator is located near the middle section of the signal transmission link to regenerate or regulate the data transmitted in the middle section of the signal transmission link.

[0038] In one implementation, the signal interface is sequentially connected to the first power supply group, the third power supply group, and the second power supply group via a signal transmission link.

[0039] In the first power-taking group, the chip adjacent to the signal interface is electrically connected to the beginning of the signal transmission link, and in the second power-taking group, the chip adjacent to the second conductive element is electrically connected to the end of the signal transmission link.

[0040] In the first power supply group, the chip adjacent to the first conductive element is electrically connected to the first conductive element, and in the second power supply group, the chip adjacent to the second conductive element is electrically connected to the second conductive element.

[0041] In one embodiment, the first conductive element, the second conductive element, the signal interface, the processing module, the boosting module, and the voltage regulating module are disposed on the same side of the board in the second direction.

[0042] In one embodiment, a signal interface, a processing module, a boosting module, and a voltage stabilizing module are disposed in the area between the first conductive element and the second conductive element.

[0043] In one embodiment, the end of the chip array that is located at the same end as the first conductive element, the second conductive element, and the signal interface in the second direction is referred to as the first end, and the end of the chip array that is opposite to the first conductive element, the second conductive element, and the signal interface in the second direction is referred to as the second end.

[0044] The power-taking unit at the first end of the power-taking group adjacent to the second conductive element is connected to the second conductive element and is sequentially connected in series along the second direction to the power-taking unit at the second end of the power-taking group. The power-taking unit at the second end of the power-taking group is then connected in series with the power-taking unit at the second end of the next adjacent power-taking group, and then sequentially connected in series along the second direction to the power-taking unit at the first end of the power-taking group, and so on, until the power-taking unit at the first end of the last power-taking group is electrically connected to the first conductive element.

[0045] In one embodiment, along the direction of heat dissipation airflow, the upstream side of the power extraction group is the first side, and the downstream side is the second side.

[0046] The chip on the second side of the power-taking unit at the first end of the power-taking group adjacent to the first conductive element is connected to the signal interface and connected to the chip on the first side of the power-taking unit. Then, the chips on the first side and the chips on the second side of the adjacent power-taking units are connected in sequence. The chips on the second side of the power-taking unit at the second end of this power-taking group are connected to the chips on the first side of the power-taking units at the second end of the power-taking group. This process continues until the chips on the first side of the power-taking units at the first end of the last power-taking group are connected.

[0047] In one embodiment, a temperature sensor is included, which is disposed on the plate and used to detect the temperature of the airflow flowing through the plate.

[0048] The processing module is electrically connected to the temperature sensor to collect the temperature detected by the temperature sensor.

[0049] In one embodiment, the number of temperature sensors is at least two, and along the direction of airflow through the circuit board, at least one of the at least two temperature sensors is adjacent to the air inlet side of the board, and at least one temperature sensor is adjacent to the air outlet side of the board.

[0050] In one embodiment, there are two temperature sensors, one of which is located in the area between the first power supply group and the adjacent third power supply group, and the other is located in the area between the second power supply group and the adjacent third power supply group.

[0051] According to another aspect of the embodiments of this application, the embodiments of this application also provide a computing device, including the circuit board of any of the foregoing.

[0052] In the circuit board of this application embodiment, the power supply module has a voltage monitoring point. The processing module is electrically connected to the voltage monitoring point and is used to collect the voltage of the voltage monitoring point. This allows for monitoring of the voltage of the circuit board, ensuring voltage stability, and facilitating rapid identification of fault points.

[0053] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0054] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0055] Figure 1 , Figure 2 A schematic diagram of the circuit board according to an embodiment of this application is shown.

[0056] Figure 3 A partial structural schematic diagram of a circuit board according to an embodiment of this application is shown, wherein the current transmission path is illustrated.

[0057] Figure 4 A partial structural schematic diagram of a circuit board according to an embodiment of this application is shown, in which the signal transmission path is illustrated.

[0058] Explanation of reference numerals in the attached figures:

[0059] Circuit board 21; board body 201; chip 202; voltage monitoring point 203; first voltage monitoring point 2031; second voltage monitoring point 2032; third voltage monitoring point 2033; fourth voltage monitoring point 2034; fifth voltage monitoring point 2035; sixth voltage monitoring point 2036; temperature sensor 205; clock frequency generator 206; first clock frequency generator 2061; second clock frequency generator 2062;

[0060] Chip array 210; first power supply group 211, second power supply group 212; third power supply group 213; power supply unit 2110;

[0061] Power supply module 23; second conductive component 231; first conductive component 232; electrical connector 233; electrical connection unit 2331;

[0062] Boost module 234; Voltage regulator module 235; Processor 24; Analog-to-digital converter 241; Signal interface 25;

[0063] First direction L1; Second direction L2. Detailed Implementation

[0064] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0065] This application provides a circuit board that can be applied to computing devices to achieve high-efficiency computing capabilities. The circuit board includes a board body, a chip array disposed on the board body, a power supply module, and a processing module. The chip array includes a power-harvesting unit, which includes at least one chip. The power supply module is connected to a power source and electrically connected to the power-harvesting unit to supply power to the power-harvesting unit. The power supply module has voltage monitoring points, and the processing module is electrically connected to the voltage monitoring points to collect the voltage at the monitoring points, ensuring voltage stability and facilitating rapid fault identification.

[0066] The processing module can connect to the control board and upload the voltage data collected from the voltage monitoring points. The control board can record and store historical data of the voltage monitoring points on the circuit board. When the voltage data shows abnormal fluctuations, frequent drops, or instability, it indicates that the circuit board is likely to be faulty. By analyzing the historical voltage data, abnormal voltage monitoring points can be identified, thereby quickly determining the location of the fault.

[0067] The processing module may include a memory that records and stores the collected voltage data for maintenance personnel to access, enabling them to quickly locate the fault.

[0068] The processing module may include a processor and an analog-to-digital converter (ADC). The ADC is connected to a voltage monitoring point to acquire the voltage at that point, and the processor is also connected to the ADC to acquire the voltage at the monitoring point. The processor can also compare the acquired voltage with a preset voltage to determine whether the circuit board's operating state is stable.

[0069] The processor can be an MCU (Microcontroller Unit), an FPGA (Field-Programmable Gate Array), a DSP (Digital Signal Processor), or something similar, but is not limited to these.

[0070] The processor can acquire the voltage at different voltage monitoring points on the power supply module through multiple AD (Analog-to-Digital Converter) channels, and then... 2 Communication with the control board via IC (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface) enables power management and fault detection.

[0071] The number of voltage monitoring points can be set based on the hardware resources of the processing module itself, such as the number of pins and the number of analog-to-digital converter channels. If the hardware resources of the processing module are sufficient, more voltage monitoring points can be set on the circuit board; that is, the power supply module can have multiple voltage monitoring points. The processor connects to multiple voltage monitoring points through multiple analog-to-digital converters to monitor the voltage at multiple locations on the circuit board. If the voltage at a certain monitoring point is abnormal (e.g., too high or too low), the specific fault location can be quickly located, thereby shortening fault diagnosis time and improving maintenance efficiency. Historical data from the voltage monitoring points can be used for fault analysis and trend prediction. By analyzing historical voltage change records, potential patterns and problems can be identified, enabling preventative maintenance and preventing future failures.

[0072] Under normal circumstances, based on the total voltage of the circuit board and the number of power-harvesting units connected in series, the voltage drop value at each stage of power-harvesting can be determined. When the value at one or more voltage monitoring points differs significantly from the corresponding voltage value, it can be determined that there is a faulty chip in the upstream power-harvesting unit, thus narrowing down the scope of troubleshooting faulty chips. Based on this, provided the hardware resources of the processing module are sufficient, the number of voltage monitoring points can also be determined according to the number of power-harvesting units in the chip array. The more power-harvesting units there are, the more voltage monitoring points there should be. For example, one voltage monitoring point can be set at intervals of a certain number of power-harvesting units.

[0073] The following detailed description uses specific embodiments and illustrations.

[0074] Figure 1 , Figure 2 A schematic diagram of a circuit board according to an embodiment of this application is shown. Figure 1 and Figure 2 As shown, circuit board 21 has six voltage monitoring points 203. Processor 24 acquires the voltage of each of the six voltage monitoring points 203 through a six-channel analog-to-digital converter 241. In this example, limited by the hardware resources of the processing module itself, the processing module has six pins and six analog-to-digital converter channels. The processing module acquires the voltage of each of the six voltage monitoring points through the six pins and the corresponding analog-to-digital converter channels.

[0075] In other examples, the processing module may have more pins and analog-to-digital converter channels, so more voltage monitoring points can be set on the board, for example, eight, ten or more voltage monitoring points, and not limited to that.

[0076] It should be noted that the above are merely examples and do not constitute a limitation on this application. Those skilled in the art can select different processing modules and set up a corresponding number of voltage monitoring points on the circuit board according to monitoring needs and cost control.

[0077] For example, such as Figure 1 As shown, the power supply module 23 may include a first conductive element 232 and a second conductive element 231. The first conductive element 232 is used to connect to the negative terminal of the power supply, and the second conductive element 231 is used to connect to the positive terminal of the power supply. The processing module is connected between the first conductive element 232 and the second conductive element 231. That is, the second conductive element 231 serves as the current input of the circuit board 21, and the first conductive element 232 serves as the current output of the circuit board 21, thereby realizing the power supply of the circuit board 21.

[0078] For example, such as Figure 1 As shown, the power supply module 23 may include an electrical connector 233, which is connected between the first conductive element 232 and the second conductive element 231. The electrical connector 233 is connected in series with multiple power taking units 2110, and the electrical connector 233 has a voltage monitoring point 203.

[0079] Multiple power-collecting groups can be distributed on the board 201 along the first direction L1. Each power-collecting group includes multiple power-collecting units 2110 arranged sequentially along the second direction L2. Each power-collecting unit 2110 includes multiple chips 202 arranged sequentially along the first direction L1. The multiple chips 202 of each power-collecting unit 2110 are connected in parallel, thus forming a chip array 210 on the board 201.

[0080] like Figure 2 As shown, the electrical connector 233 connects each power-taking unit 2110 in series between the first conductive element 232 and the second conductive element 231, and the multiple chips 202 of each power-taking unit 2110 are connected in parallel. The electrical connector 233 may include multiple electrical connection units 2331. In the second direction L2, an electrical connection unit 2331 is connected between two adjacent chips 202, and in the first direction L1, an electrical connection unit 2331 is connected between two adjacent power-taking groups. In this way, the power-taking units 2110 are connected in series sequentially through the electrical connector 233, which includes multiple electrical connection units 2331.

[0081] Electrical connector 233 can be a metal busbar, such as a conductive copper busbar, to reduce voltage drop.

[0082] For example, the electrical connector may have multiple voltage monitoring points evenly distributed along the series path of multiple series-connected power supply groups.

[0083] like Figure 2 As shown, taking a chip array 210 with four power-taking groups as an example, the bottom one is the first power-taking group 211, the top one is the second power-taking group 212, and the two in the middle are the third power-taking groups 213. The electrical connector 233 has four voltage monitoring points 203, namely the first voltage monitoring point 2031, the second voltage monitoring point 2032, the third voltage monitoring point 2033, and the fourth voltage monitoring point 2034. The input end of the electrical connector 233, that is, one end of the electrical connector 233 connected to the second conductive member 231, has the first voltage monitoring point 2031, which is also the left end of the topmost second power-taking group 212. The electrical connector 233 has a second voltage monitoring point 2032 approximately three-quarters of its length, that is, a position adjacent to the right end of the topmost third power-taking group 213. A third voltage monitoring point 2033 is located approximately halfway down the electrical connector 233, specifically between the left end of the lower third power take-up group 213 and the left end of the lower first power take-up group 211. A fourth voltage monitoring point 2034 is located approximately one-quarterway down the electrical connector 233, specifically near the right end of the first power take-up group 211. Thus, four voltage monitoring points 203 are evenly distributed along the series path of each power take-up group, enabling a comprehensive and real-time understanding of the operating status of the circuit board 21. This ensures stable and efficient operation of the circuit board 21 and allows for rapid detection of power supply problems or voltage anomalies, facilitating fault diagnosis and localization.

[0084] In some examples, such as Figure 2As shown, the power supply module 23 includes a booster module 234, which is connected to at least one downstream power-taking unit 2110 on the data transmission path and is used to provide the required voltage for the data transmission of at least one downstream power-taking unit 2110.

[0085] It should be noted that data transmission between chip 202 and the outside world is achieved through signal interface 25 of circuit board 21. The voltage required for data transmission of chip 202 is generally higher than the voltage required by the internal circuit of chip 202. In order to ensure the stability of data transmission of chip 202, each power supply group is equipped with an auxiliary power supply module. Since the voltage of the current power supply group cannot meet the power supply requirements for data transmission, the auxiliary power supply module needs to take power from each level in sequence along the data transmission direction. For the last power supply group that cannot continue to take power from each level, circuit board 21 is equipped with a booster module 234 to meet the power requirements for data transmission.

[0086] In some examples, such as Figure 2 As shown, the power supply module 23 may also include a voltage regulator module 235. The voltage regulator module 235 is connected between the voltage output terminal of the boost module 234 and at least one downstream power collection unit 2110. That is, the output voltage of the boost module 234 is output to the corresponding power collection unit after passing through the voltage regulator module 235, so as to ensure the stability of the voltage.

[0087] like Figure 2 As shown, the voltage output terminals of the boost module 234 and the voltage output terminal of the voltage regulator module 235 each have voltage monitoring points 203, namely, the fifth voltage monitoring point 2035 of the voltage output terminal of the boost module 234 and the sixth voltage monitoring point 2036 of the voltage output terminal of the voltage regulator module 235. This serves two purposes: firstly, it monitors the output voltage to ensure it meets the data transmission needs of the final power supply groups; secondly, when the voltage is unstable or abnormal, faults can be quickly identified based on the voltage at different monitoring points 203. For example, if the voltage at monitoring point 203 of the voltage output terminal of the boost module 234 is abnormal, the boost module 234 is faulty; if the voltage at monitoring point 203 of the voltage output terminal of the boost module 234 is normal, but the voltage at monitoring point 203 of the voltage output terminal of the voltage regulator module 235 is abnormal, the voltage regulator module 235 is faulty.

[0088] For example, the boost module 234 may include a voltage control chip, an input voltage switching element, an output voltage switching element, an inductor, a capacitor, etc. The voltage control chip is used to control the on / off state of the input voltage switching element and the output voltage switching element according to a preset voltage range. The voltage control chip can monitor the output voltage of the boost module 234 in real time to determine whether the actual output voltage is within the preset voltage range. If the output voltage does not fall within the preset voltage range, the voltage control chip will adjust the on / off time of the input voltage switching element and the output voltage switching element to stabilize the output voltage and bring it within the preset voltage range, thus meeting the power requirements of the chip 202.

[0089] The input voltage switching element and the output voltage switching element can be metal-oxide-semiconductor field-effect transistors, that is, the input voltage switching element is a high-side MOS (Metal Oxide Semiconductor) field-effect transistor and the output voltage switching element is a low-side MOS field-effect transistor, so as to reduce the on-resistance and improve the efficiency of the boost module 234.

[0090] For example, the voltage regulator module 235 can be a low dropout regulator (LDO), which has a lower input-output voltage difference, meaning it can still operate stably when the input voltage is close to the output voltage.

[0091] For example, signal interface 25 is connected to each chip 202 sequentially via a signal transmission link, such as... Figure 2 As shown, the circuit board 21 includes at least two clock frequency generators 206. One clock frequency generator 206 is located near the start of the signal transmission link to synchronize the data transmitted at the start of the signal transmission link, ensuring that the signal has accurate timing characteristics when it is transmitted. At least one clock frequency generator 206 is located near the middle area of ​​the signal transmission link to solve the signal distortion problem caused by signal attenuation, timing offset or electromagnetic interference in long-distance transmission. By regenerating or enhancing the clock signal, the stability of signal transmission is ensured.

[0092] like Figure 2 As shown, there are two clock frequency generators 206 on the signal transmission link. The first clock frequency generator 2061 is set near the beginning of the signal transmission link, and the second clock frequency generator 2062 is set near the middle area of ​​the signal transmission link. They perform timing calibration on the signal, compensate for phase deviation or frequency attenuation caused by the increase in transmission distance, prevent waveform distortion caused by accumulated errors, ensure the stability of signal transmission, and avoid signal distortion.

[0093] For example, the clock frequency generator 206 can be a crystal oscillator.

[0094] For example, such as Figure 2 As shown, the signal interface 25 is sequentially connected to the first power supply group 211, the third power supply group 213, and the second power supply group 212 via a signal transmission link. The chip 202 in the first power supply group 211 adjacent to the signal interface 25 is electrically connected to the starting end of the signal transmission link, and the chip 202 in the second power supply group 212 adjacent to the second conductive element 231 is electrically connected to the ending end of the signal transmission link. Similarly, the chip 202 in the first power supply group 211 adjacent to the first conductive element 232 is electrically connected to the first conductive element 232, and the chip 202 in the second power supply group 212 adjacent to the second conductive element 231 is electrically connected to the second conductive element 231. That is, signal transmission begins from the chip 202 in the first power supply group 211 closest to the signal interface 25, and power transmission begins from the chip 202 in the second power supply group 212 closest to the second conductive element 231, ensuring stable signal transmission and facilitating wiring.

[0095] For example, such as Figure 2 As shown, the first conductive component 232, the second conductive component 231, the signal interface 25, the processing module (processor 24 and analog-to-digital converter 241), the boost module 234 and the voltage regulator module 235 are disposed on the same side of the board 201 in the second direction L2. On the one hand, this provides sufficient space for the arrangement of the chip array 210, and on the other hand, it facilitates the connection between each component and the chip 202.

[0096] For example, such as Figure 2 As shown, a signal interface 25, a processing module (processor 24 and analog-to-digital converter 241), a boost module 234 and a voltage regulator module 235 are provided in the area between the first conductive component 232 and the second conductive component 232 to improve the utilization of the space on the board 201 and facilitate the connection of various components.

[0097] Figure 3 A partial structural schematic diagram of a circuit board 21 according to an embodiment of this application is shown, wherein the current transmission path is illustrated. Figure 4 A partial structural schematic diagram of the circuit board 21 according to an embodiment of this application is shown, in which the signal transmission path is illustrated.

[0098] For example, the end of the chip array 210 located at the same end as the first conductive element 232, the second conductive element 231, and the signal interface 25 in the second direction L2 is referred to as the first end, and the end of the chip array 210 located opposite to the first conductive element 232, the second conductive element 231, and the signal interface 25 in the second direction L2 is referred to as the second end. The power-taking unit 2110 of the first end of the power-taking group adjacent to the second conductive element 231 is connected to the second conductive element 231 and is sequentially connected in series along the second direction L2 to the power-taking unit 2110 of the second end of the same power-taking group. The power-taking unit 2110 of the second end of the same power-taking group is then connected in series with the power-taking unit 2110 of the second end of the next adjacent power-taking group, and then sequentially connected in series along the second direction L2 to the power-taking unit 2110 of the first end of the same power-taking group, and so on, until the power-taking unit 2110 of the first end of the last power-taking group is electrically connected to the first conductive element 232.

[0099] For ease of understanding, Figure 3 The path of current on chip array 210 is shown. Figure 3 The arrangement of the circuit board 21 shown is for reference. The first end of the power-taking group adjacent to the second conductive element 231 is the upper end of the second power-taking group 212. Current is input from the upper end of the second power-taking group 212, and all the power-taking units 2110 of the second power-taking group 212 are connected in series downwards. The power-taking unit 2110 at the lower end of the second power-taking group 212 is connected in series with the lower end of the adjacent third power-taking group 213. The power-taking units 2110 at the lower end of the third power-taking group 213 are connected in series upwards to the power-taking unit 2110 at the upper end of the third power-taking group 213. The power-taking unit 2110 at the upper end of the third power-taking group 213 is connected in series to the left of another power-taking unit 2110 at the upper end of the third power-taking group 213. The power unit 2110 is connected in series downwards to the power unit 2110 at the lower end of the third power group 213. The power unit 2110 at the lower end of the third power group 213 is connected in series to the lower end of the first power group 2110 to the left. The power unit 2110 is connected in series upwards to the power unit 2110 at the upper end of the first power group 211. The power unit 2110 at the upper end of the first power group 211 is connected to the first conductive element 232, thus supplying power to the chips 202 of each power group.

[0100] For example, along the direction of heat dissipation airflow, the upstream side of the power-taking group is the first side, and the downstream side is the second side. The chip 202 on the second side of the power-taking unit 2110 at the first end of the power-taking group adjacent to the first conductive element 232 is connected to the signal interface 25 and connected to the chip 202 on the first side of the power-taking unit 2110. The chip 202 on the first side of the power-taking unit 2110 is sequentially connected to the chip 202 on the first side and the chip 202 on the second side of the adjacent power-taking unit 2110, and sequentially connected to the chip 202 on the second side of the power-taking unit 2110 at the second end of this power-taking group. The chip 202 on the second side of the power-taking unit 2110 at the second end of this power-taking group continues to be connected to the chip 202 on the first side of the adjacent power-taking unit 2110 at the second end of the power-taking group, and so on, until it is connected to the chip 202 on the first side of the power-taking unit 2110 at the last power-taking group.

[0101] For ease of understanding, Figure 4 The signal path on chip array 210 is shown. Figure 4 The arrangement of the circuit board 21 shown is for reference. The heat dissipation airflow is from left to right. The side of the power taking group located upstream is the left side, and the side located downstream is the right side. The first end of the power taking group adjacent to the first conductive element 232 is the upper end of the power taking group. The signal interface 25 first connects to the chip 202 on the right side of the power-taking unit 2110 at the upper end of the first power-taking group 211. That is, the signal enters from the chip 202 on the right side of the power-taking unit 2110 at the upper end of the first power-taking group 211, and connects to the chip 202 on the left side of the power-taking unit 2110. The chip 202 on the left side of the power-taking unit 2110 connects to the left and right chips 202 of the power-taking unit 2110 below in sequence, and so on, until it connects to the chip 202 on the right side of the power-taking unit 2110 at the lower end of the first power-taking group 211. From the chip 202, the signal enters the third power-taking group 213 through the left chip 202 at the lower end of the third power-taking group 213, and connects to all the chips 202 on the third power-taking group 213 in sequence. This connection continues until it directly connects to the chip 202 at the lower end of the first power-taking group 211. The chip 202 at the lower end of the first power-taking group 211 connects to the chip 202 at the upper end of the first power-taking group 211 in sequence. This enables data transmission between each chip 202.

[0102] For example, a temperature sensor 205 is provided on the board 201. The temperature sensor 205 is used to detect the temperature of the airflow flowing through the board 201 in order to monitor the heat dissipation effect of the circuit board 21 and make it easy to adjust the speed of the heat dissipation module, such as the fan, in a timely manner, so as to ensure the heat dissipation effect of the circuit board 21.

[0103] In some examples, there can be multiple temperature sensors, which can be distributed in different areas of the circuit board to monitor the temperature distribution in different areas of the circuit board in real time. This helps to detect local overheating problems in a timely manner and ensure the uniformity of temperature distribution.

[0104] In some examples, multiple temperature sensors can be arranged in areas adjacent to the air inlet and air outlet sides of the board, respectively, with the air inlet and air outlet sides located at two edges of the circuit board, facilitating wiring between the temperature sensors and the processing module.

[0105] In other examples, a temperature sensor may also be placed in the middle area of ​​the plate.

[0106] It should be noted that the above are merely examples and do not constitute a limitation on this application. The number and location of temperature sensors can be flexibly designed according to the temperature uniformity requirements of the circuit board and the convenience of wiring.

[0107] In a specific example, such as Figure 2 As shown, there are two temperature sensors 205 on the board 201. One temperature sensor 205 is located in the area between the first power supply group 211 and the adjacent third power supply group 213, and the other temperature sensor 205 is located in the area between the second power supply group 212 and the adjacent third power supply group 213.

[0108] The chip array comprises multiple power-harvesting groups, which are spaced apart along a first direction L1. Each power-harvesting group includes multiple power-harvesting units arranged sequentially and in series along a second direction L2. Each power-harvesting unit includes multiple chips connected in parallel. The large number of chips in the chip array can enhance the computing power of the circuit board, thereby improving its overall performance. Furthermore, the array arrangement can improve the heat dissipation and temperature uniformity of the multiple chips.

[0109] In some examples, the total number of power-harvesting units 2110 can be greater than 40 and less than 100 to improve the computing power of circuit board 21. For example... Figure 2 As shown, there are 80 power-harvesting units 2110, each including two chips connected in parallel, totaling 160 chips. Specifically, the first power-harvesting group 211 includes 20 power-harvesting units 2110, the two third power-harvesting groups 213 each include 21 power-harvesting units 2110, and the second power-harvesting group 212 includes 18 power-harvesting units 2110. In some examples, the number of power-harvesting units 2110 can also be 50, 70, or 90, etc., and is not limited thereto. It should be noted that this is only an example and does not constitute a limitation of this application; the number of power-harvesting units 2110 can be flexibly designed according to the computing power requirements of the circuit board 21 and the space available on the circuit board 21.

[0110] For example, the rated power of circuit board 21 can be 1500 to 2000W, which can meet the needs of high computing power and expand its application range.

[0111] In one specific example, the rated power of circuit board 21 is 1600W. In another example, the rated power of circuit board 21 can be 1500, 1700, 1800, 1900, 2000W, etc., and is not limited to this.

[0112] It should be noted that the above examples are merely illustrative and do not constitute a limitation of this application. Those skilled in the art will understand that the rated power of circuit board 21 can be selected differently according to computing power requirements.

[0113] For example, such as Figure 2 As shown, the heat dissipation airflow flows through the circuit board 21 along the first direction L1. The first power supply group 211, at least one third power supply group 213, and the second power supply group 212 are arranged in sequence along the first direction L1. That is, the first power supply group 211 is adjacent to the air inlet side of the board 201, the second power supply group 212 is adjacent to the air outlet side of the board 201, and the third power supply group 213 is located between the first power supply group 211 and the second power supply group 212.

[0114] Along the second direction L2, the middle regions of the first power-taking group 211 and the second power-taking group 212 each have vacant spaces. That is, no chip 202 is arranged in the middle regions of the first power-taking group 211 and the second power-taking group 212 to form a larger heat dissipation channel. On the one hand, this can increase the airflow and speed from the middle region of the first power-taking group 211 to the downstream third power-taking group 213 and the second power-taking group 212, reducing wind resistance; on the other hand, it can reduce the number of chips 202 in the downstream second power-taking group 212, improving the heat dissipation effect of the second power-taking group 212, thereby making the overall temperature of the circuit board 21 more uniform.

[0115] For example, the first power supply group 211 and the second power supply group 212 each include a plurality of power supply areas arranged sequentially along the second direction L2; in the second direction L2, the distance between any two adjacent power supply areas is greater than the distance between any two adjacent power supply units 2110 in any power supply area, so as to increase the vacancy on the first power supply group 211 and the second power supply group 212 respectively and improve the heat dissipation effect.

[0116] For example, the number of power-taking areas in the second power-taking group 212 is greater than the number of power-taking areas in the first power-taking group 211, so as to ensure the heat dissipation effect of the second power-taking group 212 located downstream of the heat dissipation airflow, thereby making the overall temperature of the circuit board 21 more uniform.

[0117] like Figure 2As shown, the first power supply group 211 includes four power supply areas, and the second power supply group 212 includes six power supply areas. The spacing between two adjacent power supply areas in the four power supply areas of the first power supply group 211 is greater than the spacing between two adjacent chips 202 in each power supply area. Correspondingly, the spacing between two adjacent power supply areas in the six power supply areas of the second power supply group 212 is greater than the spacing between two adjacent chips 202 in each power supply area. In this way, large-spacing vacancies are formed in the first power supply group 211 and the second power supply group 212, which improves the heat dissipation effect of the circuit board 21 and helps to maintain temperature uniformity.

[0118] For example, along the first direction L1, the spacing between the first power-taking group 211, the third power-taking group 213, and the second power-taking group 212 increases sequentially. That is, along the heat dissipation airflow direction, the spacing between two adjacent power-taking groups increases sequentially, so as to increase the spacing between downstream power-taking groups and make the overall temperature of the circuit board 21 more uniform.

[0119] For example, such as Figure 2 As shown, at least one third power take-up group 213 has a smaller extension dimension in the second direction L2 than the first power take-up group 211, and at least one third power take-up group 213 has a smaller extension dimension in the second direction L2 than the second power take-up group 212. That is to say, the extension dimension of the third power take-up group 213 in the second direction L2 is smaller than that of the first power take-up group 211 and the second power take-up group 212. This allows for the creation of a layout area at the end of the third power take-up group 213, which facilitates the arrangement of wiring and some electrical connection units 2331 of electrical connectors 233 within this area.

[0120] For example, the number of chips 202 in the first power supply group 211 is greater than the number of chips 202 in the second power supply group 212, and the number of chips 202 in the first power supply group 211 is less than the number of chips 202 in the third power supply group 213. Figure 2 As shown, the first power supply group 211 has 40 chips 202, the second power supply group 212 has 36 chips 202, and each third power supply group 213 has 42 chips. This is only an example and does not constitute a limitation of this application. The number of chips 202 in each power supply group can be adjusted according to the space of the board 201, heat dissipation requirements, and computing power requirements.

[0121] For example, taking the center line of the board 201 extending along the second direction L2 as the dividing line, the chip array 210 is divided into a first chip array 210 and a second chip array 210. The total number of chips 202 in the first chip array 210 near the air inlet side of the circuit board 21 is greater than the total number of chips 202 in the second chip array 210 near the air outlet side of the circuit board 21. That is, the number of chips 202 in the second chip array 210 downstream of the heat dissipation airflow is less than the number of chips 202 in the first chip array 210 upstream of the heat dissipation airflow, so as to arrange more chips 202 in the upstream area with a relatively lower temperature and appropriately reduce the number of chips 202 in the upstream area with a relatively higher temperature, thereby ensuring the heat dissipation effect and temperature uniformity of the circuit board 21.

[0122] It should be noted that the circuit boards of the above embodiments can be used in combination with each other, and are not limited to the aforementioned combinations. The features and technical solutions in different embodiments can be flexibly adjusted and combined according to actual needs to achieve optimal performance and functionality.

[0123] This application also provides a computing device including the circuit board 21 of any of the above examples.

[0124] The control board of the computing device can be connected to the signal interface 25 of the circuit board 21 to realize signal transmission and control.

[0125] Other configurations of the circuit board 21 in the above embodiments can be adopted from various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0126] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0127] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0128] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0129] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0130] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. The above drawings are merely illustrative of the processes included in the method according to exemplary embodiments of this application and are not intended to be limiting. It is readily understood that the processes shown in the above drawings do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be performed synchronously or asynchronously in multiple modules, for example.

[0131] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0132] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, include: plate body; A chip array is disposed on the board, the chip array including a power-taking unit, the power-taking unit including at least one chip; A power supply module is disposed on the board and is used to connect to a power source. The power supply module is electrically connected to the power extraction unit and is used to supply power to the power extraction unit. The power supply module has a voltage monitoring point. A processing module is installed on the board and electrically connected to the voltage monitoring point for collecting the voltage of the voltage monitoring point.

2. The circuit board according to claim 1, characterized in that, The power supply module includes a first conductive element and a second conductive element. The first conductive element is used to connect to the negative terminal of the power supply, and the second conductive element is used to connect to the positive terminal of the power supply. The processing module is connected between the first conductive element and the second conductive element.

3. The circuit board according to claim 2, characterized in that, The power supply module includes an electrical connector connected between the first conductive element and the second conductive element. The electrical connector is connected in series with multiple power-taking units and has the voltage monitoring point.

4. The circuit board according to claim 3, characterized in that, The chip array includes multiple power-collecting groups connected in series, the multiple power-collecting groups are spaced apart in a first direction, and each power-collecting group includes multiple power-collecting units that are sequentially arranged and connected in series in a second direction; The electrical connector has multiple voltage monitoring points evenly distributed along the series path of the multiple series-connected power collection groups.

5. The circuit board according to claim 1, characterized in that, The power supply module includes a booster module, which is connected to at least one of the downstream power-taking units in the data transmission path and is used to provide the required voltage for the data transmission of the at least one downstream power-taking unit. The voltage output terminal of the booster module has the voltage monitoring point.

6. The circuit board according to claim 5, characterized in that, The power supply module includes a voltage regulator module, which is connected between the voltage output terminal of the boost module and at least one of the downstream power extraction units. The voltage output terminal of the voltage regulator module has the voltage monitoring point.

7. The circuit board according to claim 1, characterized in that, The processing module includes a processor and an analog-to-digital converter. The analog-to-digital converter is connected to the voltage monitoring point and is used to collect the voltage of the voltage monitoring point. The processor is connected to the analog-to-digital converter and is used to acquire the voltage of the voltage monitoring point.

8. The circuit board according to claim 1, characterized in that, The number of power-gathering units is multiple, and the multiple power-gathering units are connected in series. The total number of power-gathering units is greater than 40 and less than 100.

9. The circuit board according to claim 1, characterized in that, The power extraction unit includes multiple chips, which are arranged at intervals along a first direction and connected in parallel.

10. The circuit board according to claim 1, characterized in that, The power supply unit includes two chips connected in parallel.

11. The circuit board according to claim 1, characterized in that, The heat dissipation airflow flows through the circuit board in a first direction. Along the first direction, the chip array includes a first power-taking group and a second power-taking group. The first power-taking group and the second power-taking group each include a plurality of power-taking units arranged sequentially along the second direction. The first power supply group is located near the air inlet side of the plate, and the second power supply group is located near the air outlet side of the plate.

12. The circuit board according to claim 11, characterized in that, Along the second direction, the middle area of ​​the first power-taking group and the middle area of ​​the second power-taking group each have vacant positions.

13. The circuit board according to claim 11, characterized in that, The first power-taking group and the second power-taking group each include multiple power-taking areas arranged sequentially along the second direction; In the second direction, the distance between any two adjacent power-collecting areas is greater than the distance between any two adjacent power-collecting units within any power-collecting area.

14. The circuit board according to claim 13, characterized in that, The number of power-taking areas in the second power-taking group is greater than the number of power-taking areas in the first power-taking group.

15. The circuit board according to claim 11, characterized in that, The chip array includes at least one third power supply group located between the first power supply group and the second power supply group along a first direction. The third power supply group includes a plurality of power supply units arranged sequentially along a second direction.

16. The circuit board according to claim 15, characterized in that, The number of the third power supply groups is two, and the two third power supply groups are arranged at intervals in the first direction.

17. The circuit board according to claim 15, characterized in that, The extension dimension of the at least one third power take-up group in the second direction is smaller than the extension dimension of the first power take-up group in the second direction, and the extension dimension of the at least one third power take-up group in the second direction is smaller than the extension dimension of the second power take-up group in the second direction.

18. The circuit board according to claim 15, characterized in that, The number of chips in the first power-supply group is greater than the number of chips in the second power-supply group, and the number of chips in the first power-supply group is less than the number of chips in the third power-supply group.

19. The circuit board according to claim 15, characterized in that, Along the first direction, the spacing between the first power-taking group, the third power-taking group, and the second power-taking group increases sequentially.

20. The circuit board according to claim 1, characterized in that, Using the center line extending along the second direction of the board as the dividing line, the chip array is divided into a first chip array and a second chip array. The total number of chips in the first chip array near the air inlet side of the circuit board is greater than the total number of chips in the second chip array near the air outlet side of the circuit board.

21. The circuit board according to claim 1, characterized in that, The board is provided with a signal interface, which is connected to each of the chips and the processing module respectively.

22. The circuit board according to claim 1, characterized in that, The signal interface is connected to each of the aforementioned chips sequentially via a signal transmission link; The circuit board includes at least two clock frequency generators, one of which is located near the start of the signal transmission link to synchronize the data transmitted at the start of the signal transmission link; at least one of the clock frequency generators is located near the middle section of the signal transmission link to regenerate or adjust the data transmitted in the middle section of the signal transmission link.

23. The circuit board according to claim 22, characterized in that, The signal interface is sequentially connected to the first power supply group, the third power supply group, and the second power supply group via a signal transmission link. In the first power-taking group, the chip adjacent to the signal interface is electrically connected to the start end of the signal transmission link, and in the second power-taking group, the chip adjacent to the second conductive element is electrically connected to the end end of the signal transmission link. In the first power-taking group, the chip adjacent to the first conductive element is electrically connected to the first conductive element, and in the second power-taking group, the chip adjacent to the second conductive element is electrically connected to the second conductive element.

24. The circuit board according to claim 22, characterized in that, The first conductive element, the second conductive element, the signal interface, the processing module, the boosting module, and the voltage stabilizing module are disposed on the same side of the plate in the second direction.

25. The circuit board according to claim 24, characterized in that, The signal interface, the processing module, the boosting module, and the voltage stabilizing module are disposed in the area between the first conductive element and the second conductive element.

26. The circuit board according to claim 23, characterized in that, The end of the chip array that is located at the same end as the first conductive element, the second conductive element, and the signal interface in the second direction is referred to as the first end, and the end of the chip array that is opposite to the first conductive element, the second conductive element, and the signal interface in the second direction is referred to as the second end. The power-taking unit at the first end of the power-taking group adjacent to the second conductive element is connected to the second conductive element and is sequentially connected in series along the second direction to the power-taking unit at the second end of the power-taking group. The power-taking unit at the second end of the power-taking group is then connected in series with the power-taking unit at the second end of the next adjacent power-taking group, and then sequentially connected in series along the second direction to the power-taking unit at the first end of the power-taking group, and so on, until the power-taking unit at the first end of the last power-taking group is electrically connected to the first conductive element.

27. The circuit board according to claim 26, characterized in that, Along the direction of heat dissipation airflow, the side of the power supply group located upstream is the first side, and the side located downstream is the second side; The chip on the second side of the power-taking unit at the first end of the power-taking group adjacent to the first conductive element is connected to the signal interface and connected to the chip on the first side of the power-taking unit. Then, the chips on the first side and the chips on the second side of the adjacent power-taking units are connected in sequence. The chips on the second side of the power-taking unit at the second end of this power-taking group are connected to the chips on the first side of the power-taking units at the second end of the power-taking group. This process continues until the chips on the first side of the power-taking units at the first end of the last power-taking group are connected.

28. The circuit board according to claim 1, characterized in that, Includes a temperature sensor, which is disposed on the plate and used to detect the temperature of the airflow flowing through the plate; The processing module is electrically connected to the temperature sensor and is used to collect the temperature detected by the temperature sensor.

29. The circuit board according to claim 28, characterized in that, The number of temperature sensors is at least two. Along the direction of airflow through the circuit board, at least one of the at least two temperature sensors is adjacent to the air inlet side of the board, and at least one of the temperature sensors is adjacent to the air outlet side of the board.

30. The circuit board according to claim 29, characterized in that, The number of temperature sensors is two, one of which is located in the area between the first power supply group and the adjacent third power supply group, and the other of which is located in the area between the second power supply group and the adjacent third power supply group.

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