Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device. The method includes forming a dummy gate over a channel portion of a semiconductor fin; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a nitrided silicon layer over the oxide layer; doping the nitrided silicon layer to form a heavily doped layer in the nitrided silicon layer; implanting dopants in the heavily doped layer into the oxide layer; after implanting the dopants in the heavily doped layer into the oxide layer, forming a plurality of lightly doped drain regions in an uncovered portion of the semiconductor fin; patterning the nitrided silicon layer and the oxide layer to form a pair of gate spacer walls on opposite sidewalls of the dummy gate, wherein a doping concentration at a top portion of one of the lightly doped drain regions is higher than a doping concentration at a bottom portion of one of the pair of gate spacer walls, and a doping concentration at a bottom portion of the one of the lightly doped drain regions is lower than the doping concentration at the bottom portion of the one of the pair of gate spacer walls.

Description

[0001] This application is a divisional application of a patent application with an application date of December 14, 2016, an application number of 201611149521.9, and an invention title of "Semiconductor Element and Manufacturing Method Thereof". Technical Field

[0002] Embodiments of the present invention relate to a semiconductor element, and more particularly to a manufacturing method of a semiconductor element. Background Art

[0003] As the size of integrated circuits shrinks and the demand for their operating speed increases, transistors have smaller and smaller sizes and higher and higher drive currents, thus giving rise to fin field-effect transistors (FinFETs). FinFETs have an increasing channel width. The increase in channel width is achieved by forming a channel that includes portions on the sidewalls of the fin and portions on the top surface of the fin. Since the drive current of a transistor is proportional to the channel width, the drive current of a finFET also increases as the channel width increases. Summary of the Invention

[0004] According to some embodiments of the present invention, a semiconductor element includes a substrate, at least one source-drain feature, a gate structure, and at least one gate spacer. The source-drain feature is at least partially located in the substrate. The gate structure is located on the substrate. The gate spacer is located on at least one sidewall of the gate structure. The bottom portion of the gate spacer has dopants therein.

[0005] According to some other embodiments of the present invention, a semiconductor element includes a substrate, at least one semiconductor fin, a gate structure, and at least one gate spacer. The semiconductor fin is located on the substrate. The semiconductor fin includes at least one channel portion and at least one source-drain portion. The gate structure is located on the channel portion of the semiconductor fin. The gate spacer is adjacent to the gate structure, located on the semiconductor fin, and located between the channel portion and the source-drain portion of the semiconductor fin. The gate spacer includes group VIIIA impurities therein.

[0006] According to still some other embodiments of the present invention, a manufacturing method of a semiconductor element includes forming a semiconductor fin on a substrate. Forming a gate structure on the semiconductor fin. Forming a spacer layer that covers the gate structure and the semiconductor fin. Performing an isotropic doping process to dope the spacer layer. Patterning the spacer layer to form at least one gate spacer on at least one sidewall of the gate structure. Description of the Drawings

[0007] Figure 1 A schematic diagram showing a semiconductor element according to some embodiments of the present invention;

[0008] Figures 2 to 11 A cross-sectional view of a semiconductor component in an intermediate manufacturing stage according to some embodiments of the present invention. Figure 1 in the middle manufacturing stage;

[0009] Figure 12 A profile diagram showing the arsenic concentration of a semiconductor component corresponding to depth according to one or more embodiments of the present invention. Detailed implementation manners

[0010] The following description will provide many different embodiments or examples for implementing the subject matter of the embodiments of the present invention. Specific examples of components or arrangements will be discussed below to simplify the embodiments of the present invention. Of course, these descriptions are only partial examples and the embodiments of the present invention are not limited thereto. For example, forming a first feature on or above a second feature not only includes embodiments where the first feature is in direct contact with the second feature, but also includes embodiments where other features are formed between the first feature and the second feature, and in this case, the first feature and the second feature are not in direct contact. In addition, the embodiments of the present invention may repeat reference numerals or words in different examples. The purpose of repetition is to simplify and clarify the description, rather than to define the relationship between different embodiments and configurations discussed.

[0011] In addition, relative spatial terms such as "below", "beneath", "lower", "above", "upper" and other similar terms are used herein for convenience in describing the relationship of one element or feature in a figure to another element or feature. The relative spatial terms cover not only the orientations depicted in the figures, but also other orientations of the device during use or operation. That is, when the orientation of the device is different from that in the drawings (rotated 90 degrees or in other orientations), the relative spatial terms used herein can be interpreted accordingly.

[0012] The components that can be improved by one or more embodiments shown in the embodiments of the present invention can be semiconductor components. For example, the aforementioned components can be Fin Field-Effect Transistors (FinFET) components. The following embodiments of the invention continue to use FinFETs as an example to describe different embodiments of the embodiments of the present invention. However, it should be understood that the application of the embodiments of the present invention is not limited to specific forms of components.

[0013] Figure 1 A schematic diagram of a semiconductor component according to some embodiments of the present invention. In addition, Figures 2 to 11 A cross-sectional view of a semiconductor component in an intermediate manufacturing stage according to some embodiments of the present invention. Figure 1 in the middle manufacturing stage. Figures 2 to 11 The cross-sectional part is alongFigure 1 Line segment A-A. Please refer to Figure 2 . The substrate 110 can be provided. In some embodiments, the substrate 110 can include silicon. Optionally, the substrate 110 can include germanium, silicon germanium, gallium arsenide, or other suitable semiconductor materials. Optionally, the substrate 110 can include an epitaxial layer. For example, the substrate 110 can have an epitaxial layer covering a bulk semiconductor. Further, for performance improvement, the substrate 110 can thus be strained. For example, the epitaxial layer can include a semiconductor material different from the bulk semiconductor, such as a silicon germanium layer covering a bulk silicon semiconductor or a silicon layer covering a bulk silicon germanium semiconductor. The method of forming such a strained substrate can include selective epitaxial growth (SEG). In addition, the substrate 110 can include a semiconductor-on-insulator (SOI) structure. Optionally, the substrate 110 can include a buried dielectric layer, such as a buried oxide (BOX) layer. In addition, the method of forming the substrate 110 can include, for example, a separation by implanted oxygen (SIMOX) process, a wafer bonding process, a selective epitaxial growth (SEG) process, or other suitable methods.

[0014] At least one semiconductor fin 112 is formed on the substrate 110. In some embodiments, the semiconductor fin 112 can include silicon. For example, the method of forming the semiconductor fin 112 can use a photolithography process to pattern and etch the substrate 110. In some embodiments, a layer of photoresist material (not shown in the figure) can be disposed above the substrate 110. This layer of photoresist material can be irradiated (exposed) according to the pattern design (the pattern designed in this embodiment is the semiconductor fin 112) and developed to remove a portion of the photoresist material. The remaining photoresist material can protect the material it covers in subsequent processes (such as an etching process). It should be understood that other masks (such as oxide or silicon nitride masks) can also be used in the subsequent etching process.

[0015] Please refer to Figure 1Multiple insulating structures 105 may be formed on a substrate 110. The insulating structures 105 may be formed around the semiconductor fins 112 as shallow trench isolation (STI). The method of forming the insulating structures 105 may be a chemical vapor deposition (CVD) process, and tetraethylorthosilicate (TEOS) and oxygen may be used as precursors for the chemical vapor deposition process. In some embodiments, the method of forming the insulating structures 105 may be an ion implantation process, such as implanting oxygen ions, nitrogen ions, carbon ions, or similar ions into the substrate 110. In some other embodiments, the insulating structures 105 are insulating layers of an insulated substrate semiconductor wafer.

[0016] Please refer to Figure 2 。A gate dielectric 120 is formed to cover the semiconductor fin 112. The method of forming the gate dielectric 120 may include a thermal oxidation process, a chemical vapor deposition process, a sputtering process, or other methods known in the art for forming a gate dielectric. Depending on the process used to form the dielectric layer, the thickness of the gate dielectric 120 on the top of the semiconductor fin 112 may be different from the thickness of the gate dielectric 120 on the sidewall (not shown) of the semiconductor fin 112. For example, the gate dielectric 120 may include high-k materials, such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or any combination of the above materials. In some embodiments, the material of the gate dielectric 120 may include hafnium oxide (HfO 2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), strontium titanium oxide (SrTiO 3 , STO), barium titanium oxide (BaTiO 3 , BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), and any combination of the above materials. The gate dielectric 120 may have a multi-layer structure, for example, one layer structure is silicon oxide (such as the interfacial layer) and the other layer structure is a high-k material.

[0017] The dummy layer 130 is formed on the gate dielectric 120. The method of depositing the dummy layer 130 may include a chemical vapor deposition process, a sputtering deposition process, or other methods known in the art for depositing conductive materials. The material of the dummy layer 130 may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). For example, in some embodiments, the dummy layer 130 may include undoped poly-Si deposited by a low-pressure chemical vapor deposition (LPCVD) process. For example, the poly-Si may also include in-situ doped poly-Si deposited by a furnace tube. Optionally, the dummy layer 130 may include other suitable materials. Further, the dummy layer 130 may dope the poly-Si using uniform or non-uniform doping.

[0018] The mask layer 210 is formed with an appropriate thickness on the dummy layer 130 through a suitable process. When the mask layer 210 does not cover other parts of the dummy layer 130, it can also be regarded as the mask layer 210 covering a part of the dummy layer 130. In some embodiments, the mask layer 210 is a hard mask layer containing silicon oxide. In some other embodiments, the material of the mask layer 210 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), spin-on glass (SOG), a low-κ film, tetraethylorthosilicate (TEOS), plasma enhanced CVD oxide (PE-oxide), oxide formed by high-aspect-ratio-process (HARP), amorphous carbon material, other suitable materials, and / or any combination of the above materials. The method for forming the silicon oxide layer may include, but is not limited to, chemical vapor deposition process, physical vapor deposition process, or atomic layer deposition process. In addition, the thickness range of the silicon oxide layer can substantially range from about 100 angstroms to about 500 angstroms. In some embodiments, the mask layer 210 can be a photoresist layer. The photoresist layer is deposited on the dummy layer 130. For example, the method for forming the photoresist layer may include a spin coating process. In addition, for example, the photoresist layer can form a designed pattern through a photolithography process, a developing process, a drying process, an etching process, and other appropriate processes. In some embodiments, the mask layer 210 may include a silicon nitride layer 212 deposited on the dummy layer 130 and an oxide layer 214 deposited on the silicon nitride layer 212.

[0019] Please refer to Figure 3 .. The parts outside the designed pattern in the dummy layer 130 are removed through a removal process (or an etching process) (see Figure 1), to form a dummy gate 132. That is, the portions not covered by the mask layer 210 are removed to form the dummy gate 132. In some embodiments, multiple etching processes may be performed. However, the patterning process is not limited to the photolithography process using photoresist. The patterning process may be performed by an immersion lithography process, an electron beam lithography process, or other suitable processes. Therefore, the pattern of the dummy gate 132 as shown in Figure 3 can be obtained by the above method. At least one portion of the semiconductor fin 112 covered by the dummy gate 132 may be referred to as the channel portion 114 of the semiconductor fin 112, and other portions of the semiconductor fin 112 not covered by the dummy gate 132 may be referred to as the uncovered portions 116. In some embodiments, the gate dielectric 120 may also be patterned such that the semiconductor fin 112 has portions not covered by the gate dielectric 120 and the dummy gate 132 (see Figure 3 ). In some other embodiments, the semiconductor fin 112 may be covered by the gate dielectric 120.

[0020] Please refer to Figure 4 . The spacer layer 140 is formed to cover the dummy gate 132, the mask layer 210, and the semiconductor fin 112. In some embodiments, the spacer layer 140 is a composite layer. This composite layer includes a lower substructure layer 142 and an upper substructure layer 144 having different etching characteristics. In some embodiments, the lower substructure layer 142 is formed of an oxide and may thus also be referred to as a pad oxide layer. The upper substructure layer 144 is formed of a silicon nitride or a silicon oxynitride and may thus also be referred to as a pad nitride layer. In some other embodiments, the spacer layer 140 may have a single-layer or composite-layer structure. This single-layer or composite-layer structure may include an oxide, a silicon nitride, a silicon oxynitride (SiON), and / or other dielectric materials. The method for forming the spacer layer 140 may include, but is not limited to, a plasma enhanced chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process.

[0021] Next, the spacer layer 140 can be doped. In some embodiments, the spacer layer 140 can be doped by a Plasma Doping (PLAD) process. Specifically, a heavily doped layer 150 is formed on the spacer layer 140. For example, the method of forming the heavily doped layer 150 can include a plasma ion assisted deposition (PIAD) process. The heavily doped layer 150 can contain impurities. These impurities are used to form dopants in the spacer layer 140. The material for forming the heavily doped layer 150 can include N-type impurities or P-type impurities. For example, the material of the heavily doped layer 150 can include borides (such as boron fluoride (BF2) or diborane (B2H6)), indium compounds (indium), phosphides (phosphorous), and / or arsenides (arsenic). In some embodiments, the thickness T of the heavily doped layer 150 is substantially about 5 nanometers to about 6 nanometers.

[0022] Please refer to Figure 5 . The dopants in the heavily doped layer 150 are implanted into the spacer layer 140 by a knock-on implantation process. The ions 220 used in the knock-on implantation process can include element ions of Group VIIIA in the periodic table or inert gas ions, such as xenon ions, argon ions, neon ions, helium ions, krypton ions, any combination of the above ions, or other ions that will not have an adverse effect on the characteristics of the fin field effect transistor. In some embodiments, the knock-on implantation process is induced by the scattering of inert gas ions. In some embodiments, in the deposition and ion modes, the plasma ion assisted deposition process and the knock-on implantation process can be regarded as a Plasma Doping (PLAD) process. Since the plasma doping process is induced by the scattering of inert gas ions, the plasma doping process is an isotropic doping process. That is, the portion of the spacer layer 140 on the sidewall of the dummy gate 132 can be doped. Therefore, the spacer layer 140 can contain impurities of elements in Group VIIIA of the periodic table. In some embodiments, the doped spacer layer 140 can diffuse the dopants located therein through at least one annealing process. In some embodiments, when the dopant is an arsenide, the dopant concentration of the arsenide in the spacer layer 140 is substantially in a range from about 6x10 19 atoms / cm 3 to about 1x10 21 atoms / cm 3 . When the dopant is a phosphide, the dopant concentration of the phosphide in the spacer layer 140 is substantially in a range from about 2x10 19 atoms / cm 3to about 3x10 20 atoms / cm 3 . When the dopant is a boride, the dopant concentration of the boride in the spacer layer 140 is substantially in a range from about 1x10 20 atoms / cm 3 to about 1x10 21 atoms / cm 3 . In some embodiments, when the dopant is a xenide, the dopant concentration of the xenide in the spacer layer 140 is substantially in a range from about 2x10 18 atoms / cm 3 to about 5x10 18 atoms / cm 3 .

[0023] Please refer to Figure 6 . A plurality of Light-Doped Drain (LDD) regions 160 are formed in the semiconductor fin 112. In particular, the light-doped drain regions 160 are formed in the uncovered portion 116 of the semiconductor fin 112. A dummy gate 132 is inserted between the two light-doped drain regions 160. That is, the light-doped drain regions 160 are substantially aligned with the sidewalls 134 of the dummy gate 132. The method of forming the light-doped drain regions 160 may include a plasma doping process, an ion implantation process, a diffusion process, and / or other suitable processes. In some embodiments, if the light-doped drain regions 160 are formed by a plasma doping process, the doping of the spacer layer 140 and the formation of the light-doped drain regions 160 can be performed simultaneously. That is, the spacer layer 140 and the light-doped drain regions 160 have substantially the same dopant. However, in some other embodiments, the doping of the spacer layer 140 and the formation of the light-doped drain regions 160 can be performed separately. Depending on the conduction type of the fin field-effect transistor, the light-doped drain regions 160 can be doped with an N-type dopant or a P-type dopant. For example, if the final structure of the fin field-effect transistor is an N-type fin field-effect transistor, the dopant in the light-doped drain regions 160 can be a phosphide, an arsenide, or any combination of the above dopants. However, if the final structure of the fin field-effect transistor is a P-type fin field-effect transistor, the dopant in the light-doped drain regions 160 can be a boride, an indide, or any combination of the above dopants.

[0024] Please refer to Figure 7。The spacer layer 140 may be patterned into a pair of gate spacer walls 140'. These gate spacer walls 140' are located on opposite sidewalls 134 of the dummy gate 132 and on opposite sidewalls of the mask layer 210. A wet etching or dry etching process may be used as the patterning process. The gate spacer walls 140' may include a pad oxide portion (also referred to as an inner portion) and a nitride portion (also referred to as an outer portion).

[0025] Please refer to Figure 8 。The portions of the semiconductor fin 112 exposed by the dummy gate 132 and the gate spacer walls 140' may be removed (or recessed) to form at least one recess R in the semiconductor fin 112. For example, the structure shown by the two recesses R in Figure 8 . In addition, any suitable amount of material may be removed. In some embodiments, portions of the lightly doped drain region 160 may also be removed, and the remaining lightly doped drain region 160 is adjacent to the recess R of the gate spacer walls 140'. The remaining semiconductor fin 112 has a recessed portion 118 and a channel portion 114. The recessed portion 118 is embedded in the substrate 110 and is exposed through the recess R. The channel portion 114 is located under the dummy gate 132 and is the channel of the fin field effect transistor. The lightly doped drain region 160 is located in the channel portion 114 and under the gate spacer walls 140'.

[0026] The method of removing portions of the semiconductor fin 112 may include forming a photoresist layer or a covering layer (such as an oxide covering layer) on Figure 7Above the structure shown, the patterned photoresist layer or the capping layer has an opening exposing a portion of the semiconductor fin 112 and etches back the material of the semiconductor fin 112. In some embodiments, the semiconductor fin 112 can be etched using a dry etching process. Optionally, the etching process can be a wet etching process or a combination of a dry etching process and a wet etching process. Removing a portion of the semiconductor fin 112 can also include a lithography process for performing the etching process. The lithography process can include photoresist coating (e.g., spin coating process), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying, such as hard baking, or other suitable processes or any combination of the above processes. Optionally, the lithography process can be performed or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. In some other embodiments, the lithography process can include nanoimprint technology. In some embodiments, the recess R can be cleaned using hydrofluoric acid (HF) or other suitable solutions through a pre-cleaning process.

[0027] Please refer to Figure 9Multiple epitaxial structures 170 are respectively formed in the recess R and on the recessed portion 118 of the semiconductor fin 112. The epitaxial structure 170 and the recessed portion 118 can form the source-drain portions of the semiconductor fin 112. The epitaxial structure 170 can be formed by one or more epitaxy or epitaxial (epi) processes such that silicon features, silicon germanium features, and / or other suitable features can be formed in a crystalline state on the recessed portion 118 of the semiconductor fin 112. In some embodiments, the lattice constant of the epitaxial structure 170 is different from the lattice constant of the semiconductor fin 112. The epitaxial structure 170 can generate strain or stress such that the semiconductor device has carrier mobility and can improve the performance of the semiconductor device. The epitaxial process can include a chemical vapor deposition process (such as a vapor-phase epitaxy (VPE) process and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, and / or other suitable processes. The epitaxial process can use gaseous and / or liquid precursors. The gaseous and / or liquid precursors can interact with the structure (such as silicon) of the recessed portion 118 of the semiconductor fin 112. Thus, a strained channel can be formed to increase carrier mobility and can improve device performance. The epitaxial structure 170 can be in-situ doped. The types of doping can include P-type dopants (such as borides or boron fluoride (BF2)), N-type dopants (such as phosphorus or arsenic), and / or other suitable dopants and / or any combination of the foregoing dopants. If the epitaxial structure 170 is not in-situ doped, the epitaxial structure 170 can be doped by a second implantation process (such as a junction implant process). One or more annealing processes can act on the epitaxial structure 170. The annealing process can include a rapid thermal annealing (RTA) process and / or a laser annealing process.

[0028] In some embodiments, multiple silicide contacts (not shown in the figures) are respectively located on the epitaxial structure 170. A silicide is a compound formed by a metal and silicon. This silicide is used as a contact in semiconductor devices. The silicide contact is thermally stable, has a lower resistance compared to polysilicon, and is a good ohmic contact. Because the silicidation reaction can reduce the defects at the interface between the contact and the feature, the silicide contact is reliable. A self-aligned silicide ("salicide") process can be used in semiconductor manufacturing. The silicide process can be used in the process of manufacturing high-speed complementary metal oxide semiconductor (CMOS) devices. The silicide process can transform the surface portion of the epitaxial structure 170 into a silicide contact. The silicide process includes a metal deposit that undergoes a silicidation reaction with silicon (Si). To form a silicide contact on the epitaxial structure 170, a metal material silicon can be deposited to cover the epitaxial structure 170. After heating the wafer to a temperature at which silicon can react with the silicon of the epitaxial structure 170 to form a contact, the unreacted metal is removed. After the unreacted metal in a region is removed, a silicide contact can remain in another region above the epitaxial structure 170.

[0029] Next, a dielectric layer 180 is formed on the outer side of the gate spacer 140' and on the substrate 110. That is, the dielectric layer 180 surrounds the gate spacer 140' and the dummy gate 132. The material of the dielectric layer 180 can include silicon oxide, oxynitride, or other suitable materials. The dielectric layer 180 can include a single-layer structure or a multi-layer structure. The method of forming the dielectric layer 180 can include a suitable process, such as a chemical vapor deposition process or an atomic layer deposition process. The excess dielectric layer 180 can be removed by a chemical mechanical planarization (CMP) process, and the top surface of the dummy gate 132 can be exposed in a subsequent process of removing the dummy gate.

[0030] Please refer to Figure 10 . The dummy gate 132 (see Figure 9 ) is removed to form an opening 182, and the gate spacer 140' serves as the sidewall of the opening 182. In some other embodiments, Figure 9The illustrated gate dielectric 120 may also be removed together. Optionally, in some embodiments, the dummy gate 132 may be removed while the gate dielectric 120 is retained. The dummy gate 132 (and the gate dielectric 120) may be removed by a dry etching process, a wet etching process, or a combination of the foregoing processes. For example, the wet etching process may include a solution having hydroxide (such as ammonium hydroxide), deionized water, and / or other suitable etching solutions.

[0031] In Figure 10 , since the gate spacer 140' has been doped, the etching rate of the gate spacer 140' is lower than that of the undoped gate spacer layer. Therefore, when the dummy gate 132 is removed, the gate spacer 140' is not easily removed. Under the foregoing structural configuration, the gate structure 190 formed in the opening 182 (see Figure 11 ) is not connected to the source-drain features (such as the semiconductor fin 112 and / or the epitaxial structure 170). The gate spacer 140' may be a good insulator between the gate structure 190 and the source-drain features.

[0032] Please refer to Figure 11 . The gate structure 190 is formed on the opening 182. In other words, the gate spacer 140' is located on the opposing sidewalls 192 of the gate structure 190. The foregoing formed gate structure 190 may also include a gate dielectric layer, a capping layer, a filling layer, and / or other suitable layered structures that can be designed as a metal gate stack. The work function metal layer included in the gate structure 190 may be an n-type or a p-type work function layer. For example, the p-type work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi 2 ), molybdenum silicide (MoSi 2 ), tantalum silicide (TaSi 2 ), nickel silicide (NiSi 2) and other suitable n-type work function materials or any combination of the foregoing materials. The work function layer may include a plurality of layered structures. The deposition method of the work function layer may include chemical vapor deposition process, physical vapor deposition process, electroplating process and / or other suitable processes. In some embodiments, the formed gate structure 190 is a p-type metal gate including a p-type work function layer. In some embodiments, the capping layer in the gate structure 190 may include a refractory metal and a nitride of the refractory metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN) or tantalum silicon nitride (TaSiN)). The deposition method of the capping layer may include chemical vapor deposition process, physical vapor deposition process, metal-organic chemical vapor deposition (MOCVD) process and atomic layer deposition process. In some embodiments, the filling layer included in the dielectric layer 180 may include tungsten (W). The deposition method of the metal layer may include atomic layer deposition process, physical vapor deposition process, chemical vapor deposition process or other suitable processes. After the gate structure 190 is formed, the structure of the semiconductor device may be as Figure 1 shown.

[0033] Please refer to Figure 1 and Figure 11 . Structurally, the gate spacer 140' has a top portion 140t and a bottom portion 140b. The bottom portion 140b is located between the top portion 140t and the semiconductor fin 112. In some embodiments, the bottom portion 140b of the gate spacer 140' is adjacent to the semiconductor fin 112. Since at least the bottom portion 140b of the gate spacer 140' has been doped, the doping concentration of the bottom portion 140b of the gate spacer 140' is substantially about 6x10 19 atoms / cm 3 to about 1x10 20 atoms / cm 3 , and the etching rate of the gate spacer 140' is lower than that of the undoped gate spacer. Therefore, when the opening 182 is formed. The structure of the gate spacer 140' may not be damaged. Under the foregoing structural configuration, the gate structure 190 formed in the opening 182 is not connected to the source / drain features (such as the semiconductor fin 112 and / or the epitaxial structure 170). The gate spacer 140' can serve as a good insulator between the gate structure 190 and the source / drain features.

[0034] Please refer to Figure 11。The lightly doped drain region 160 of the semiconductor fin 112 has a top portion 160t and a bottom portion 160b. The top portion 160t is located between the bottom portion 160b and the gate spacer wall 140'. The doping concentration of the top portion 160t of the lightly doped drain region 160 can be substantially about 2x10 20 atoms / cm 3 to about 3x10 20 atoms / cm 3 ,while the doping concentration of the bottom portion 160b of the lightly doped drain region 160 can be substantially about 2x10 19 atoms / cm 3 to about 4x10 19 atoms / cm 3 。That is to say, the doping concentration of the bottom portion 140b of the gate spacer wall 140' is higher than the doping concentration of the bottom portion 160b of the lightly doped drain region 160, and the doping concentration of the bottom portion 140b of the gate spacer wall 140' is lower than the doping concentration of the top portion 160t of the lightly doped drain region 160.

[0035] Figure 12 Shows an arsenic concentration-depth profile diagram of a semiconductor device according to one or more embodiments of the present invention. The dopants in the gate spacer wall and the lightly doped drain region are arsenides. The inert gas ions are xenon ions. The material of the gate spacer wall may include oxides and nitrides. The thickness of the top portion of the lightly doped drain region is substantially 18 nanometers, and the thickness of the bottom portion of the lightly doped drain region is substantially 6 nanometers.

[0036] In some embodiments, a method for manufacturing a semiconductor device. The method includes forming a dummy gate over a channel portion of a semiconductor fin; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a nitrided silicon layer over the oxide layer; doping the nitrided silicon layer to form a highly doped layer in the nitrided silicon layer; implanting dopants in the highly doped layer into the oxide layer; after implanting the dopants in the highly doped layer into the oxide layer, forming a plurality of lightly doped drain regions in an uncovered portion of the semiconductor fin; patterning the nitrided silicon layer and the oxide layer to form a pair of gate spacer walls on opposite sidewalls of the dummy gate, wherein a doping concentration at a top portion of one of the lightly doped drain regions is higher than a doping concentration at a bottom portion of one of the pair of gate spacer walls, and a doping concentration at a bottom portion of the one of the lightly doped drain regions is lower than the doping concentration at the bottom portion of the one of the pair of gate spacer walls. Removing a plurality of portions of the semiconductor fin not covered by the dummy gate and the pair of gate spacer walls to form a plurality of recessed portions in the semiconductor fin, the recessed portions being located on opposite sides of the dummy gate; epitaxially forming a plurality of epitaxial structures on the recessed portions of the semiconductor fin; removing the dummy gate to form an opening between the pair of gate spacer walls; and forming a gate structure in the opening between the pair of gate spacer walls.

[0037] In some embodiments, the doping concentration at the bottom portion of the one of the pair of gate spacer walls ranges from 6x10 19 atoms / cm 3 to 1x10 20 atoms / cm 3 .

[0038] In some embodiments, the dopants include arsenic, phosphorus, boron, or any combination of the foregoing dopants.

[0039] In some embodiments, implanting the dopants in the highly doped layer into the oxide layer is performed by scattering the dopants into the oxide layer with inert gas ions.

[0040] In some embodiments, the method further includes: after implanting the dopants in the highly doped layer into the oxide layer and before forming the lightly doped drain regions in the uncovered portion of the semiconductor fin, performing an annealing process to diffuse the dopants located in the oxide layer.

[0041] In some embodiments, a method of manufacturing a semiconductor device. The method includes forming a dummy gate over a semiconductor fin; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a nitridesilicide layer over the oxide layer; performing a plasma ion assisted deposition process to dope a dopant into the nitridesilicide layer; implanting the dopant from the nitridesilicide layer into the oxide layer; after implanting the dopant from the nitridesilicide layer into the oxide layer, performing an annealing process to diffuse the dopant located in the oxide layer; after performing the annealing process, forming a plurality of lightly doped drain regions in the semiconductor fin; patterning the nitridesilicide layer and the oxide layer to form a pair of gate spacer walls on opposite sidewalls of the dummy gate, wherein the doping concentration at the top portion of one of the lightly doped drain regions is higher than the doping concentration at the bottom portion of one of the pair of gate spacer walls, and the doping concentration at the bottom portion of the said one of the lightly doped drain regions is lower than the doping concentration at the bottom portion of the said one of the pair of gate spacer walls; removing a plurality of portions of the semiconductor fin not covered by the dummy gate and the pair of gate spacer walls to form a plurality of recessed portions in the semiconductor fin, the recessed portions being located on opposite sides of the dummy gate; epitaxially forming a plurality of epitaxial structures on the recessed portions of the semiconductor fin; replacing the dummy gate with a gate structure.

[0042] In some embodiments, the dopant is a boride, and the dopant concentration of the boride is in the range from 1x10 20 atoms / cm 3 to 1x10 21 atoms / cm 3 .

[0043] In some embodiments, implanting the dopant from the nitridesilicide layer into the oxide layer is by an implant process.

[0044] In some embodiments, a method of manufacturing a semiconductor device. The method includes forming a dummy gate over a semiconductor fin; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a nitridesilicide layer over the oxide layer; doping an arsenide into the nitridesilicide layer; implanting the arsenide from the nitridesilicide layer into the oxide layer by ions of an element of Group VIIIA, such that the nitridesilicide layer contains an impurity of an element of Group VIIIA, and the dopant concentration of the arsenide is in the range from 6x10 19 atoms / cm 3 to 1x10 21 atoms / cm 3; forming a plurality of lightly doped drain regions in a semiconductor fin; patterning a silicon nitride layer and an oxide layer to form a pair of gate spacer walls on opposite sidewalls of a dummy gate, wherein a doping concentration at a top portion of one of the lightly doped drain regions is higher than a doping concentration at a bottom portion of one of the pair of gate spacer walls, and a doping concentration at a bottom portion of the one of the lightly doped drain regions is lower than a doping concentration at a bottom portion of the one of the pair of gate spacer walls; removing a plurality of portions in the semiconductor fin not covered by the dummy gate and the pair of gate spacer walls to form a plurality of recessed portions in the semiconductor fin, the recessed portions being located on opposite sides of the dummy gate; epitaxially growing a plurality of epitaxial structures on the recessed portions of the semiconductor fin; removing the dummy gate to form an opening between the pair of gate spacer walls; and forming a gate structure in the opening between the pair of gate spacer walls.

[0045] In some embodiments, the impurity of the element of Group VIIIA includes xenon.

[0046] The features of the foregoing embodiments enable those of ordinary skill in the art to better understand various aspects of the embodiments of the present invention. Those of ordinary skill in the art should understand that, for the purpose of achieving the same object and / or the same advantages as those of the embodiments mentioned in the embodiments of the present invention, they can easily design or modify other processes and structures based on the embodiments of the present invention. Those of ordinary skill in the art should also understand that such identical structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, comprising: forming a dummy gate over a channel portion of a semiconductor fin, wherein a plurality of uncovered portions of the semiconductor fin are exposed from the dummy gate; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a silicon nitride layer over the oxide layer; performing a plasma ion-assisted deposition process to deposit a heavily doped layer on the silicon nitride layer; implanting a dopant in the heavily doped layer into the silicon nitride layer and the oxide layer; after implanting the dopant in the heavily doped layer into the silicon nitride layer and the oxide layer, forming a plurality of lightly doped drain regions in the uncovered portions of the semiconductor fin; patterning the silicon nitride layer and the oxide layer to form a pair of gate sidewalls on opposite sidewalls of the dummy gate, wherein a doping concentration at a top portion of one of the lightly doped drain regions is higher than a doping concentration at a bottom portion of one of the pair of gate sidewalls, and a doping concentration at a bottom portion of the one of the lightly doped drain regions is lower than the doping concentration at the bottom portion of the one of the pair of gate sidewalls; removing a plurality of portions of the semiconductor fin not covered by the dummy gate and the pair of gate sidewalls to form a plurality of recessed portions in the semiconductor fin, wherein the recessed portions are located on opposite sides of the dummy gate; epitaxially growing a plurality of epitaxial structures on the recessed portions of the semiconductor fin; removing the dummy gate to form an opening between the pair of gate sidewalls; and forming a gate structure in the opening between the pair of gate sidewalls.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The doping concentration range of the bottom part of this one of the pair of gate spacer walls is 6x10 19 atoms / cm 3 to 1x10 20 atoms / cm 3 .

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, the dopant comprises arsenic, phosphorus, boron, or any combination of the above dopants.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, implanting the dopant in the heavily doped layer into the silicon nitride layer and the oxide layer is by scattering of an inert gas ion to implant the dopant into the silicon nitride layer and the oxide layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, further comprising: after implanting the dopant in the heavily doped layer into the silicon nitride layer and the oxide layer and before forming the plurality of lightly doped drain regions in the uncovered portions of the semiconductor fin, performing an annealing process to diffuse the dopant located in the silicon nitride layer and the oxide layer.

6. A method for manufacturing a semiconductor device, characterized in that, comprising: forming a dummy gate over a semiconductor fin; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a silicon nitride layer over the oxide layer; performing a plasma ion-assisted deposition process to deposit a heavily doped layer on the silicon nitride layer; implanting a dopant in the heavily doped layer into the silicon nitride layer and the oxide layer; After the dopant in the heavily doped layer is implanted into the silicon nitride layer and the oxide layer, an annealing process is performed to diffuse the dopant located in the silicon nitride layer and the oxide layer; After performing the annealing process, a plurality of lightly doped drain regions are formed in the semiconductor fin; The silicon nitride layer and the oxide layer are patterned to form a pair of gate spacer walls on opposite sidewalls of the dummy gate, wherein a doping concentration at a top portion of one of the lightly doped drain regions is higher than a doping concentration at a bottom portion of one of the pair of gate spacer walls, and a doping concentration at a bottom portion of the one of the lightly doped drain regions is lower than the doping concentration at the bottom portion of the one of the pair of gate spacer walls; A plurality of portions of the semiconductor fin not covered by the dummy gate and the pair of gate spacer walls are removed to form a plurality of recessed portions in the semiconductor fin, wherein the plurality of recessed portions are located on opposite sides of the dummy gate; Epitaxial growth is performed to form a plurality of epitaxial structures on the plurality of recessed portions of the semiconductor fin; and The dummy gate is replaced with a gate structure.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The dopant is a boride, and the dopant concentration of the boride is in a range from 1x10 20 atoms / cm 3 to 1x10 21 atoms / cm 3 .

8. The method for manufacturing a semiconductor device according to claim 6, wherein, The implanting of the dopant in the heavily doped layer into the silicon nitride layer and the oxide layer is performed by an implanting process.

9. A method for manufacturing a semiconductor device, wherein, comprises: forming a dummy gate over a semiconductor fin; depositing an oxide layer over the dummy gate and the semiconductor fin; depositing a silicon nitride layer over the oxide layer; performing a plasma ion assisted deposition process to deposit a heavily doped layer over the silicon nitride layer; Perform an impact implantation process to implant an arsenide in the heavily doped layer into the silicon nitride layer and the oxide layer through ions of an element of Group VIIIA, such that the silicon nitride layer and the oxide layer contain impurities of an element of Group VIIIA, and the dopant concentration of the arsenide is in a range from 6x10 19 atoms / cm 3 to 1x10 21 atoms / cm 3 ; forming a plurality of lightly doped drain regions in the semiconductor fin; pattern the silicon nitride layer and the oxide layer to form a pair of gate spacer walls on opposite sidewalls of the dummy gate, wherein a doping concentration at a top portion of one of the lightly doped drain regions is higher than a doping concentration at a bottom portion of one of the pair of gate spacer walls, and a doping concentration at a bottom portion of the one of the lightly doped drain regions is lower than the doping concentration at the bottom portion of the one of the pair of gate spacer walls; removing a plurality of portions of the semiconductor fin not covered by the dummy gate and the pair of gate spacer walls to form a plurality of recessed portions in the semiconductor fin, wherein the plurality of recessed portions are located on opposite sides of the dummy gate; epitaxial growth is performed to form a plurality of epitaxial structures on the plurality of recessed portions of the semiconductor fin; removing the dummy gate to form an opening between the pair of gate spacer walls; and forming a gate structure in the opening between the pair of gate spacer walls.

10. The method for manufacturing a semiconductor device according to claim 9, wherein, the impurity of the Group VIIIA element comprises xenon.

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