Light emitting element array and device using the same

Abstract

A light emitting element array, and a light emitting device, an optical device, a measuring device, and an information processing device using the light emitting element array, the light emitting element array comprising: a plurality of light emitting indication portions arranged toward a first direction; a first light emitting element group, in which a light emitting element group including a plurality of light emitting elements is arranged in a direction intersecting the first direction; a second light emitting element group, in which a light emitting element group including a plurality of light emitting elements is arranged along the first light emitting element group on the first direction side relative to the first light emitting element group; and a plurality of wirings, the plurality of wirings being a plurality of wirings for connecting the plurality of light emitting indication portions and the light emitting element groups of the first light emitting element group and the second light emitting element group to perform light emitting indication.

Description

Technical Field

[0001] The present disclosure relates to a light emitting element array, and a light emitting device, an optical device, a measuring device, and an information processing device using the light emitting element array. Background Art

[0002] Japanese Patent Publication No. 01-238962 describes a light-emitting element array, which is composed of arranging a plurality of light-emitting elements whose threshold voltage or threshold current can be controlled by light from the outside in one dimension, two dimensions, or three dimensions, so that at least a portion of the light generated from each light-emitting element is incident on other light-emitting elements near each light-emitting element, and connecting a clock line to which a voltage or current is applied from the outside to each light-emitting element.

[0003] Japanese Patent Gazette No. 2001-308385 describes a self-scanning light-emitting device, which is a light-emitting element of a pnpnpn six-layer semiconductor structure. Electrodes are set on the p-type first layer and the n-type sixth layer at both ends, and the p-type third layer and the n-type fourth layer in the center, so that the pn layer is responsible for the light-emitting diode function, and the pnpn fourth layer is responsible for the thyristor function.

[0004] Japanese Patent Gazette No. 2009-286048 describes a self-scanning light source head, which includes: a substrate; surface-emitting semiconductor lasers arranged in an array on the substrate; and thyristors as switching elements arranged on the substrate to selectively turn on / off the light emission of the surface-emitting semiconductor lasers. Summary of the invention

[0005] When measuring the three-dimensional shape of an object to be measured based on the so-called time of flight (ToF) method using the flight time of light, the object to be measured may be irradiated with light from a plurality of light emitting element groups.

[0006] The purpose of the present disclosure is to easily construct multiple wirings for instructing a light emitting element group to emit light from a light emitting instruction unit, compared with a case where, in multiple light emitting element groups each including a plurality of light emitting elements, the light emitting element groups are caused to emit light in a direction sequentially instructed by a light emitting instruction unit provided for each light emitting element group.

[0007] According to a first aspect of the present disclosure, there is provided a light emitting element array, comprising: a plurality of light emitting indicating portions arranged toward a first direction; a first light emitting element group, in which a light emitting element group including a plurality of light emitting elements is arranged in a direction intersecting the first direction; a second light emitting element group, in which a light emitting element group including a plurality of light emitting elements is arranged along the first light emitting element group on the first direction side relative to the first light emitting element group; and a plurality of wirings, the plurality of wirings being a plurality of wirings that connect the plurality of light emitting indicating portions and the light emitting element groups of the first light emitting element group and the second light emitting element group to perform light emitting instructions, and being connected in such a manner that, when the plurality of light emitting indicating portions sequentially perform light emitting instructions toward the first direction, the first light emitting element group sequentially emits light in a direction intersecting the first direction, and after the first light emitting element group is lit, the second light emitting element group sequentially emits light in a direction intersecting the first direction.

[0008] According to a second aspect of the present disclosure, the first light emitting element group and the second light emitting element group are arranged adjacent to each other, and the wiring is connected in the following manner, that is, the direction in which the light emitting element groups in the first light emitting element group sequentially emit light is the same as the direction in which the light emitting element groups in the second light emitting element group sequentially emit light.

[0009] According to a third aspect of the present disclosure, the first light emitting element group and the second light emitting element group are arranged adjacent to each other, and the wiring is connected in the following manner, that is, the direction in which the light emitting element groups in the first light emitting element group emit light sequentially is opposite to the direction in which the light emitting element groups in the second light emitting element group emit light sequentially.

[0010] According to the fourth aspect of the present disclosure, the plurality of wirings for connecting the plurality of light-emitting indicator portions and the light-emitting element groups of the first light-emitting element group and the second light-emitting element group to provide light-emitting instructions are arranged so as not to cross each other.

[0011] According to the fifth aspect of the present disclosure, at most one wiring line is provided between the light emitting elements in the light emitting element groups of the first light emitting element group and the second light emitting element group to provide light emitting instructions, each of the plurality of light emitting indicator portions being connected to the light emitting element groups of the first light emitting element group and the second light emitting element group.

[0012] According to a sixth aspect of the present disclosure, the plurality of light-emitting instruction sections perform light-emitting instructions in sequence by self-scanning.

[0013] According to a seventh aspect of the present disclosure, there is provided a light emitting device, comprising: the light emitting element array; and a circular optical element having a size that includes a plurality of light emitting element groups included in the light emitting element array and arranged on an emission path of the plurality of light emitting element groups.

[0014] According to an eighth aspect of the present disclosure, the optical element is a lens that narrows a spread angle of light emitted from the plurality of light emitting element groups.

[0015] According to a ninth aspect of the present disclosure, the light emitting device includes a diffusion member configured to diffuse the light emitted from the plurality of light emitting element groups and transmitted through the optical element and then emit the light.

[0016] According to a tenth aspect of the present disclosure, the light emitting device includes a diffraction member configured to diffract and emit light emitted from the plurality of light emitting element groups and transmitted through the optical element.

[0017] According to an eleventh aspect of the present disclosure, there is provided an optical device including: the light emitting device; and a light receiving unit that receives reflected light emitted from a plurality of light emitting element groups included in the light emitting device and reflected by an object to be measured.

[0018] According to the twelfth scheme of the present disclosure, a measuring device is provided, comprising: the optical device; and a three-dimensional shape determination unit, which measures the three-dimensional shape based on the time from the emission of a plurality of light-emitting element groups included in the optical device to the reception by a light-receiving unit included in the optical device, thereby determining the three-dimensional shape of the object to be measured.

[0019] According to a thirteenth aspect of the present disclosure, there is provided an information processing device, comprising: the measuring device; and an authentication processing unit that performs authentication processing related to the use of its own device based on a determination result in a three-dimensional shape determination unit included in the measuring device.

[0020] (Effect)

[0021] According to the first aspect, compared with the case where the light emitting element groups are caused to emit light in the directions sequentially instructed by the light emitting instruction section provided for each light emitting element group, it is easier to configure a plurality of wirings for instructing the light emitting element groups to emit light from the light emitting instruction section.

[0022] According to the second or third aspect, the direction in which the light emitting element group emits light sequentially can be set.

[0023] According to the fourth aspect, the light emitting element array can be manufactured more easily than in the case where the wirings are arranged to cross each other.

[0024] According to the fifth aspect, the light emitting elements can be arranged at a higher density than when two or more wirings are provided between the light emitting elements.

[0025] According to the sixth aspect, the light emitting element array can be driven more easily than in the case where self-scanning is not performed.

[0026] According to the seventh aspect, compared with a case where no circular optical element is included, it is easier to control the light irradiated to the irradiation area.

[0027] According to the eighth aspect, the structure of the light emitting device becomes easier than when the optical element is not a lens.

[0028] According to the ninth aspect, a wider irradiation area can be obtained compared with a case where no diffusion member is included.

[0029] According to the tenth aspect, a wider irradiation area can be obtained compared with a case where no diffraction member is included.

[0030] According to the eleventh aspect, an optical device capable of acquiring a signal corresponding to a three-dimensional shape can be provided.

[0031] According to the twelfth aspect, a measuring device capable of measuring a three-dimensional shape can be provided.

[0032] According to the thirteenth aspect, it is possible to provide an information processing device equipped with an authentication process based on a three-dimensional shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a diagram showing an example of an information processing device.

[0034] Figure 2 It is a block diagram illustrating the structure of an information processing device.

[0035] Figure 3 This is a diagram for explaining a state in which light is irradiated toward an object to be measured by a light emitting device.

[0036] Figure 4 (a) and Figure 4 (b) is a diagram illustrating a light-emitting device. Figure 4 (a) is a plan view of the light emitting device, Figure 4 (b) is Figure 4 (a) is a cross-sectional view of the light-emitting device along line IVB-IVB.

[0037] Figure 5 (a) and Figure 5 (b) is a diagram showing an arrangement region of light-emitting devices to which the first embodiment is applied and an arrangement region of light-emitting devices to which the first embodiment is not applied for comparison. Figure 5(a) is an arrangement area of ​​the light emitting device to which the first embodiment is applied, Figure 5 (b) is an arrangement region of the light emitting device to which the first embodiment is not applied.

[0038] Figure 6 This is an example of an equivalent circuit of a vertical cavity surface emitting laser (VCSEL) array in the light emitting device to which the first embodiment is applied.

[0039] Figure 7 This is a diagram showing an example of a planar layout of a VCSEL array to which the first embodiment is applied.

[0040] Figure 8 It is a diagram showing the cross-sectional structure of a VCSEL array.

[0041] Fig. 9 (a) to Fig. 9 (c) is a diagram further illustrating the stacked structure of the thyristor and the VCSEL. Fig. 9 (a) is a schematic energy band diagram in a stacked structure of a thyristor and a VCSEL. Fig. 9 (b) is the energy band diagram of the tunneling junction layer under reverse bias state. Fig. 9 (c) shows the current-voltage characteristics of the tunnel junction layer.

[0042] Fig.10 FIG. 1 is a diagram showing an example of a timing chart for controlling light emission and non-light emission of a VCSEL group in a VCSEL array.

[0043] Fig.11 This is a diagram for explaining the arrangement of a VCSEL group in a VCSEL array to which the first embodiment is applied.

[0044] Fig.12 This is a diagram for explaining the arrangement of a VCSEL group in a VCSEL array to which the first embodiment is not applied for comparison.

[0045] Fig.13 This is a diagram for explaining the arrangement of a VCSEL group in a VCSEL array to which the second embodiment is applied. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] For measuring devices that measure the three-dimensional shape of an object to be measured, there are devices that measure the three-dimensional shape based on the so-called time of flight (ToF) method based on the flight time of light. In the ToF method, the time from the time when light is emitted from a light-emitting device included in the self-measuring device to the time when the irradiated light is reflected by the object to be measured and received by a three-dimensional sensor (hereinafter referred to as a 3D sensor) included in the measuring device is measured, and the three-dimensional shape of the object to be measured is determined based on the measured three-dimensional shape. In addition, the object whose three-dimensional shape is measured is recorded as the object to be measured. Sometimes the three-dimensional shape is recorded as a three-dimensional image. Moreover, sometimes the operation recorded as a three-dimensional shape is recorded as three-dimensional measurement, 3D measurement, or 3D perception.

[0048] This type of measuring device is installed in a mobile information processing device and is used for facial authentication of a user who wants to access. In the past, a method of authenticating a user using a password, fingerprint, iris, etc. was used in a mobile information processing device. In recent years, a more secure authentication method is being sought. Therefore, a measuring device for measuring a three-dimensional shape is gradually being installed in a mobile information processing device. That is, the three-dimensional shape of the face of the user who is accessing is obtained, and it is identified whether access is allowed. Only when the user is authenticated as a user who is allowed to access, the use of the device (mobile information processing device) is allowed.

[0049] Here, the information processing device is described as a mobile information processing terminal as an example, and the user is authenticated by recognizing the facial shape captured as a three-dimensional shape. In addition, the information processing device can be applied to information processing devices such as personal computers (PCs) other than mobile information processing terminals.

[0050] The structure, function, method, etc. described in this embodiment can also be applied to the case where the measured object is other than the face and the measured object is identified based on the measured three-dimensional shape. Moreover, this measuring device is also applicable to the case where the three-dimensional shape of the measured object is continuously measured in augmented reality (AR). Moreover, the distance to the measured object is irrelevant.

[0051] [First Embodiment] (Information Processing Device 1)

[0052] Figure 1 1 is a diagram showing an example of the information processing device 1. As described above, the information processing device 1 is, as an example, a mobile information processing terminal.

[0053] The information processing device 1 includes a user interface unit (hereinafter referred to as a UI unit) 2 and an optical device 3 for measuring a three-dimensional shape. The UI unit 2 is, for example, an integrated display device that displays information to a user and an input device that inputs instructions for information processing through user operations. The display device is, for example, a liquid crystal display or an organic electroluminescence (EL) display, and the input device is, for example, a touch panel.

[0054] The optical device 3 includes a light emitting device 4 and a three-dimensional sensor (hereinafter referred to as a 3D sensor) 5. The light emitting device 4 irradiates light toward the object to be measured, which is the face in this example. The 3D sensor 5 obtains the light irradiated by the light emitting device 4 and reflected by the face and returned. Here, the three-dimensional shape is measured based on the so-called ToF method based on the flight time of light. And the three-dimensional shape of the face is determined based on the three-dimensional shape. As described above, the three-dimensional shape can also be measured by using something other than the face as the object to be measured. The 3D sensor 5 is an example of a light receiving unit.

[0055] The information processing device 1 is configured as a computer including a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), etc. In addition, the ROM includes a non-volatile rewritable memory, such as a flash memory. And, by expanding the program or constant stored in the ROM in the RAM and executing the program by the CPU, the information processing device 1 operates to perform various information processing.

[0056] Figure 2 It is a block diagram illustrating the structure of the information processing device 1.

[0057] The information processing device 1 includes the optical device 3, a measurement control unit 8, and a system control unit 9. The measurement control unit 8 controls the optical device 3. In addition, the measurement control unit 8 includes a three-dimensional shape determination unit 8A. The system control unit 9 controls the information processing device 1 as a system. In addition, the system control unit 9 includes an authentication processing unit 9A. In addition, the system control unit 9 is connected to the UI unit 2, the speaker 9B, the two-dimensional camera ( Figure 2 denoted as 2D camera) 9C, etc.

[0058] The three-dimensional shape determination unit 8A included in the measurement control unit 8 measures the three-dimensional shape based on the reflected light from the object to be measured, thereby determining the three-dimensional shape of the object to be measured. The authentication processing unit 9A included in the system control unit 9 identifies whether access is allowed based on the three-dimensional shape determined by the three-dimensional shape determination unit 8A, and authenticates the user who is allowed to access.

[0059] Figure 2 In the embodiment, the measuring device 6 includes an optical device 3 and a measuring control unit 8 .

[0060] (Light emitting device 4)

[0061] Figure 3 4 is a diagram for explaining a state where light is irradiated toward an object to be measured by a light emitting device 4. Here, the light emitting device 4 is shown as viewed from the side opposite to the side from which light is emitted (referred to as the back side). The light emitting device 4 and the irradiation area 40 are arranged in a manner facing each other, but Figure 3 , the light emitting device 4 and the irradiation area 40 are shown staggered along the vertical direction of the paper. In addition, the irradiation area 40 refers to a plane at a certain distance in the direction of the light emitted by the light emitting device 4 and orthogonal to the direction of the light, and is an area where the light emitted by the light emitting device 4 is irradiated toward the object to be measured. Here, the left direction of the paper is set as the x direction, the upper direction of the paper is set as the y direction, and the back side direction of the paper is set as the z direction.

[0062] The irradiation region 40 has a length Sx in the x direction and a length Sy in the y direction. The length Sx in the x direction is greater than the length Sy in the y direction (Sx>Sy). That is, the irradiation region 40 has a shape with the x direction as the long side direction.

[0063] As described later, the light emitting device 4 is composed of a surface emitting laser element group including a plurality of surface emitting laser elements arranged in a two-dimensional shape in an arrangement area 100. The length in the x direction of the arrangement area 100 is Lx, and the length in the y direction is Ly. Furthermore, the ratio of the length Lx in the x direction to the length Ly in the y direction, that is, the aspect ratio of the arrangement area 100, is set to be close to 1:1. In addition, the length Lx in the x direction only needs to be 0.8 times or more and 1.2 times or less of the length Ly in the y direction. Furthermore, it is more preferable that the length Lx in the x direction is 0.9 times or more and 1.1 times or less of the length Ly in the y direction. Furthermore, it is even more preferable that the length Lx in the x direction is 0.95 times or more and 1.05 times or less of the length Ly in the y direction.

[0064] As described above, the shape of the array region 100 where the surface emitting laser element group is arrayed in the light emitting device 4 is set to be different from the shape of the irradiation region 40. The x direction is an example of a first direction, and the y direction is an example of a direction intersecting the first direction and an example of a second direction.

[0065] Figure 4 (a) and Figure 4 (b) is a diagram illustrating the light emitting device 4. Figure 4 (a) is a plan view of the light emitting device 4, Figure 4 (b) is Figure 4(a) is a cross-sectional view of the light-emitting device 4 along line IVB-IVB. Figure 4 In (a), Figure 3 Different from the above, the light emitting device 4 is shown as viewed from the side of the emitting light (referred to as the front side). Therefore, the right direction of the paper is the x direction, the top direction of the paper is the y direction, and the front direction of the paper is the z direction. The so-called plan view refers to a view of the light emitting device 4 viewed from the +z direction side. Figure 4 In (b), the right direction of the paper is the x direction, the upper direction of the paper is the y direction, and the back direction of the paper is the z direction.

[0066] like Figure 4 As shown in (b) of FIG. 1 , the light emitting device 4 includes, from the bottom side (−y direction side), a surface emitting laser element array 10 , a condenser lens 60 , and a diffusion member 30 .

[0067] The surface emitting laser element array 10 includes a plurality of surface emitting laser elements. Here, as an example, the surface emitting laser element is a vertical cavity surface emitting laser VCSEL (Vertical Cavity Surface Emitting Laser). In the following, the surface emitting laser element is assumed to be a vertical cavity surface emitting laser VCSEL for explanation. Furthermore, the vertical cavity surface emitting laser VCSEL is referred to as VCSEL. Therefore, the surface emitting laser element array 10 is referred to as VCSEL array 10. Figure 4 In (b), light is schematically indicated by hatching. A surface emitting laser element or a vertical cavity surface emitting laser VCSEL is an example of a light emitting element, and the surface emitting laser element array 10 is an example of a light emitting element array.

[0068] like Figure 4 As shown in (a), a plurality of surface emitting laser elements (VCSEL) constitute a surface emitting laser element group. In addition, the surface emitting laser element group is recorded as a VCSEL group. The area where the VCSEL group is arranged is an arrangement area 100. Here, Figure 4 As shown in (a), eight VCSEL groups including seven VCSELs are formed. In addition, when distinguishing each VCSEL group, they are recorded as VCSEL group #1 to VCSEL group #8. The VCSEL groups are arranged so that four are arranged in the x direction and two are arranged in the y direction. That is, the number of VCSEL groups arranged in the arrangement area 100 in the x direction is greater than the number in the y direction. The VCSEL group is an example of a light-emitting element group.

[0069] Furthermore, of the seven VCSELs in each VCSEL group, two are arranged in the x direction and four are arranged in the y direction. In each VCSEL group, no VCSEL is provided on the upper right side of the paper. This is to provide a p-type ohmic electrode (see below). Figure 8). In addition, the VCSELs may be arranged so that the positions of the p-type ohmic electrodes are staggered. Thus, two VCSELs are arranged in the x direction and four VCSELs are arranged in the y direction. That is, in each VCSEL group, the number of VCSELs in the y direction is greater than the number in the x direction.

[0070] Here, when the VCSELs of each VCSEL group are denoted as VCSELij (i, j≧1), "i" is the number of the VCSEL group, and "j" is the number of the VCSEL in the VCSEL group. Here, VCSEL group #1 includes VCSELs 11 to 17. Figure 4 As shown in VCSEL group #1 in (a), in each VCSEL group, VCSELij with j being 1 to 3 and VCSELij with j being 4 to 8 are arranged in the -y direction. Also, VCSELij with j being 1 to 3 and VCSELij with j being 4 to 8 are arranged side by side in the -x direction. At this time, VCSELi1 and VCSELi5, VCSELi2 and VCSELi6, and VCSELi3 and VCSELi7 are arranged in the x direction.

[0071] In this specification, “to” indicates a plurality of components that are distinguished by numbers, and includes components before and after “to” and components with numbers in between. For example, VCSEL11 to VCSEL17 include VCSEL11 to VCSEL17 in the order of numbers.

[0072] like Figure 4 As shown in (b), the focusing lens 60 is arranged on the path of the light emitted by each VCSEL (sometimes recorded as the emission path), so that the expansion angle of the light emitted by each VCSEL is narrowed and incident on the diffusion component 30. The diffusion component 30 is designed to have a predetermined function when parallel light is incident. The VCSEL emits light with an expansion angle determined by the structure. Therefore, even if the light emitted by the VCSEL is directly incident on the diffusion component 30, the diffusion component 30 will not perform the designed function. Therefore, the expansion angle of the light emitted by the VCSEL is narrowed by the focusing lens 60 and is incident on the diffusion component 30. In addition, the so-called expansion angle refers to the full width at half maximum (Full Width at Half Maximum, FWHM) of the light emitted by the VCSEL. The focusing lens 60 is an example of an optical element.

[0073] The focusing lens 60 is, for example, a plano-convex lens whose -y direction side is flat, whose length in the x direction is Cx, and whose length in the y direction is Cy. Here, it is assumed that the length Cx in the x direction is the same as the length Cy in the y direction (Cx=Cy). In addition, the so-called circle includes, for example, an ellipse whose length Cx in the x direction is 0.95 times and 1.05 times the length Cy in the y direction. The major axis of the ellipse is not limited to the case of being in the x direction or the y direction. The focusing lens 60 is an example of a lens, and is not limited to a plano-convex lens.

[0074] The diffusion member 30 includes, for example, a resin layer having a concave-convex shape for diffusing light formed on the back side (-z direction) of a glass substrate having two parallel and flat surfaces. The diffusion member 30 is provided on the emission path of each VCSEL emitted through the focusing lens 60, and expands the expansion angle of the incident light and emits the light to the irradiation area 40. That is, the diffusion member 30 refracts or scatters the light through the concave-convex shape formed on the resin layer, and expands the incident light and emits it to the irradiation area 40. The x direction of the diffusion member 30 is the length Dx, and the y direction is the length Dy.

[0075] In addition, the diffusion member 30 may be replaced by a diffractive member such as a diffractive optical element (DOE) that changes the direction of light to a direction different from the direction of incident light and emits the light.

[0076] Figure 4 Although not shown in (b), the VCSEL array 10 is provided on a circuit substrate (not shown), and the condenser lens 60 and the diffuser member 30 are held at a predetermined distance from the VCSEL array 10 by a holding member (not shown) provided on the circuit substrate.

[0077] like Figure 4 As shown in (a), the arrangement area 100 of the VCSEL is set to have an aspect ratio close to 1:1. In addition, the focusing lens 60 is provided in a manner that includes the arrangement area 100. Thereby, the area (sometimes referred to as the size) of the circular focusing lens 60 is effectively used. As described above, in each VCSEL group, the number of VCSELs in the y direction is greater than the number in the x direction, and the VCSEL groups are configured so that the number in the x direction is greater than the number in the y direction. As a result, the aspect ratio of the arrangement area 100 is close to 1:1.

[0078] Figure 5 (a) and Figure 5 (b) is a diagram showing an arrangement region 100 of a light emitting device 4 to which the first embodiment is applied and an arrangement region 100 ′ of a light emitting device 4 ′ to which the first embodiment is not applied for comparison. Figure 5 (a) is an arrangement area 100 of the light emitting devices 4 according to the first embodiment. Figure 5 (b) is an arrangement region 100' to which the light emitting device 4' of the first embodiment is not applied. Figure 5 (a) and Figure 5 (b) and Figure 3 Similarly, the light emitting device 4, the light emitting device 4' and the irradiation area 40 are shown staggered in the vertical direction of the paper. Furthermore, the diffusion member 30 is shown separately in the light emitting device 4, the light emitting device 4'. In addition, it is assumed that the light emitting device 4, the light emitting device 4' each includes eight VCSEL groups (VCSEL group #1 to VCSEL group #8).

[0079] The irradiation region 40 of the light emitting device 4 to which the first embodiment is applied and the light emitting device 4' not to which the first embodiment is applied is the same. That is, the irradiation region 40 has a shape in which the length Sx in the x direction is greater than the length Sy in the y direction and the x direction is the long side.

[0080] Figure 5 In the light emitting device 4 to which the first embodiment is applied as shown in (a), the aspect ratio (length Lx: length Ly) of the arrangement region 100 is set close to 1:1. That is, the irradiation region 40 and the arrangement region 100 are not similar in shape. At this time, the shape of the arrangement region 110 of the VCSEL group #1 is not similar in shape to the shape of the irradiation region 41 irradiated by the VCSEL group #1.

[0081] on the other hand, Figure 5 In the light emitting device 4' shown in (b) of the embodiment not applying the first embodiment, the arrangement area 100' is set to be similar to the irradiation area 40. That is, when the length of the arrangement area 100' in the x direction is Lx' and the length in the y direction is Ly', the proportionality coefficient is set to k, the length Lx' in the x direction of the arrangement area 100' is Sx / k, and the length Ly' in the y direction of the arrangement area 100' is Sy / k. At this time, the shape of the arrangement area 110' of the VCSEL group #1 is similar to the shape of the irradiation area 41 irradiated by the VCSEL group #1. Thus, as Figure 5 As shown in (b), the upper and lower parts of the circular condenser lens 60' are not used. Therefore, if the area of ​​the arrangement region 100' is the same as the area of ​​the arrangement region 100, a condenser lens 60' larger than the condenser lens 60 of the light emitting device 4 according to the first embodiment will be used.

[0082] As described above, the light emitting device 4 to which the first embodiment is applied effectively utilizes the area of ​​the condenser lens 60 compared to the light emitting device 4 ′ to which the first embodiment is not applied.

[0083] (Equivalent circuit of VCSEL array 10)

[0084] Figure 61 is an example of an equivalent circuit of the VCSEL array 10 in the light emitting device 4 according to the first embodiment. Here, a control unit 50 for controlling the operation of the VCSEL array 10 is also shown. The left direction of the paper is the y direction. In addition, the control unit 50 is provided at Figure 2 The measurement control unit 8 in.

[0085] The VCSEL array 10 includes a plurality of VCSELs. Figure 4 (a) Similarly, seven VCSELs constitute one VCSEL group. Figure 6 In FIG. 1 , four VCSEL groups (VCSEL group # 1 to VCSEL group # 4 ) are shown.

[0086] The VCSEL array 10 includes a setting thyristor S for each VCSEL group. The VCSEL group and the setting thyristor S are connected in series. The number of the VCSEL group, that is, "i", is also indicated for the setting thyristor S. That is, the setting thyristor S included in the VCSEL group #1 is the setting thyristor S1.

[0087] The VCSEL array 10 further includes a plurality of transmission thyristors T, a plurality of coupling diodes D, a plurality of power line resistors Rg, a start diode SD, and current limiting resistors R1 and R2. Here, when distinguishing the plurality of transmission thyristors T, they are distinguished by marking the number of the VCSEL group, i.e., "i", as in the case of the transmission thyristors T1, T2, T3, ... The coupling diodes D and the power line resistors Rg are also the same. As described later, for example, the transmission thyristor T1 is provided in a manner corresponding to the VCSEL group #1.

[0088] Figure 6 The portion corresponding to i and 1 to 4 is shown. "i" in the VCSEL array 10 may also be a predetermined number. For example, it may be 128, 512, 1024, etc. The number of transmission thyristors T may be the same as the number of VCSEL groups. In addition, the number of transmission thyristors T may exceed the number of VCSEL groups or may be less than the number of VCSEL groups.

[0089] The transmission thyristors T are arranged in the order of transmission thyristors T1, T2, T3, ... along the -y direction. The coupling diodes D are arranged in the order of coupling diodes D1, D2, D3, ... along the -y direction. In addition, the coupling diode D1 is provided between the transmission thyristor T1 and the transmission thyristor T2. The same applies to the other coupling diodes D. Furthermore, the power line resistors Rg are also arranged in the order of power line resistors Rg1, Rg2, Rg3, ... along the -y direction.

[0090] The VCSEL and the coupling diode D are two-terminal elements having an anode and a cathode. The setting thyristor S and the transmission thyristor T are three-terminal elements having an anode, a cathode, and a gate. In addition, the gate of the transmission thyristor T is set to the gate Gt, and the gate of the setting thyristor S is set to the gate Gs. In addition, when distinguishing each from the others, "i" is marked in the same way as above.

[0091] Here, a portion including the VCSEL and the setting thyristor S is referred to as a light emitting portion 12 , and a portion including the transfer thyristor T, the coupling diode D, the start diode SD, the power line resistor Rg, and the current limiting resistors R1 and R2 is referred to as a driving portion 11 .

[0092] Next, the connection relationship between the elements (VCSEL, setting thyristor S, transfer thyristor T, etc.) will be described.

[0093] As described above, VCSELij and the setting thyristor Si are connected in series. That is, the anode of the setting thyristor Si is connected to the reference potential Vsub (ground potential (GND) or the like), and the cathode is connected in parallel to the anode of VCSELij.

[0094] The cathodes of the VCSELij are commonly connected to a lighting signal line 76 that supplies a lighting signal φI for controlling the VCSELij to be in a light-emitting / non-light-emitting state.

[0095] As will be described later, the reference potential Vsub is provided via the back electrode 90 (see Figure 7 , Figure 8 ) is supplied, and the back electrode 90 is provided on the back side of the substrate 80 constituting the VCSEL array 10.

[0096] The anode of the transfer thyristor T is connected to the reference potential Vsub. The cathodes of the odd-numbered transfer thyristors T1 and T3 are connected to the transfer signal line 72. The transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1.

[0097] The cathodes of the even-numbered transmission thyristors T2, T4, ... are connected to the transmission signal line 73. The transmission signal line 73 is connected to the φ2 terminal via the current limiting resistor R2.

[0098] The coupling diodes D are connected in series. That is, the cathode of one coupling diode D is connected to the anode of the coupling diode D adjacent in the -y direction. The anode of the start diode SD is connected to the transmission signal line 73, and the cathode is connected to the anode of the coupling diode D1.

[0099] The cathode of the start diode SD and the anode of the coupling diode D1 are connected to the gate Gt1 of the transfer thyristor T1. The cathode of the coupling diode D1 and the anode of the coupling diode D2 are connected to the gate Gt2 of the transfer thyristor T2. The other coupling diodes D are similarly connected.

[0100] The gate Gt of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rg. The power supply line 71 is connected to the Vgk terminal.

[0101] Furthermore, the gate Gti of the transfer thyristor Ti is connected to the gate Gsi of the setting thyristor Si.

[0102] The configuration of the control unit 50 will be described.

[0103] The control unit 50 generates a signal such as a lighting signal φI and supplies it to the VCSEL array 10. The VCSEL array 10 operates according to the supplied signal. The control unit 50 includes an electronic circuit. For example, the control unit 50 may be an integrated circuit (IC) configured to control the operation of the VCSEL array 10.

[0104] The control unit 50 includes a transmission signal generating unit 51 , a lighting signal generating unit 52 , a power supply potential generating unit 53 , and a reference potential generating unit 54 .

[0105] The transmission signal generating section 51 generates transmission signals φ1 and φ2 , supplies the transmission signal φ1 to the φ1 terminal of the VCSEL array 10 , and supplies the transmission signal φ2 to the φ2 terminal of the VCSEL array 10 .

[0106] The lighting signal generating unit 52 generates a lighting signal φI and supplies it to the φI terminal of the VCSEL array 10 via the current limiting resistor RI. The current limiting resistor RI may be provided in the VCSEL array 10. Furthermore, if the operation of the VCSEL array 10 does not require the current limiting resistor RI, the current limiting resistor RI may not be provided.

[0107] The power supply potential generating unit 53 generates a power supply potential Vgk and supplies it to the Vgk terminal of the VCSEL array 10. The reference potential generating unit 54 generates a reference potential Vsub and supplies it to the Vsub terminal of the VCSEL array 10. As an example, the power supply potential Vgk is -3.3 V. As described above, as an example, the reference potential Vsub is the ground potential (GND).

[0108] The transmission signals φ1 and φ2 generated by the transmission signal generating section 51 and the lighting signal φI generated by the lighting signal generating section 52 will be described later.

[0109] Figure 6 In the VCSEL array 10 shown, seven VCSELij (j=1 to 7) as a VCSEL group are connected to one transfer thyristor Ti via a setting thyristor Si.

[0110] As described later, by turning the transmission thyristor Ti into the on state, the setting thyristor Si connected to the transmission thyristor Ti is set to be able to be turned into the on state. Therefore, since the VCSEL is set to a state where it can emit light, it is recorded as the setting thyristor S. Moreover, when the setting thyristor Si becomes the on state, the VCSELij emits light. In addition, the transmission thyristor Ti is driven to transmit the on state in the order of "i". That is, in the transmission thyristor Ti, the on state is sequentially propagated. As a result, the transmission thyristor Ti causes the VCSEL group to light up in sequence. The transmission thyristor T is an example of a light-emitting indicator.

[0111] Here, a plurality of VCSELs constitute one VCSEL group. The VCSEL group is connected to each transfer thyristor T, and the plurality of VCSELs included in the VCSEL group emit light in parallel.

[0112] in addition, Figure 6 In the example shown, each VCSEL group includes the same number of VCSELs (seven in this case), but the number of VCSELs may differ between VCSEL groups.

[0113] VCSELs oscillate preferably in a low-order single transverse mode (single mode). In single mode, the VCSEL emits light from the light source (described later). Figure 8 The intensity profile of the light (exit light) emitted from the light exit port 310 is unimodal (characteristic of having one intensity peak). On the other hand, in a VCSEL that oscillates in multiple transverse modes (multimode) including high-order, the intensity profile is easily deformed, for example, becoming multi-peaked. Moreover, in a single mode, the spread angle of the light (exit light) emitted from the light emitting point is smaller than that in a multimode.

[0114] Furthermore, the smaller the area of ​​the light-emitting point, the easier it is for the VCSEL to oscillate in a single transverse mode (single mode). Therefore, the light output of a single-mode VCSEL is small. If you want to increase the light output and increase the area of ​​the light-emitting point, it is easy to convert to a multi-mode. Therefore, multiple VCSELs are set as a VCSEL group, and the multiple VCSELs contained in the VCSEL group emit light in parallel, thereby increasing the light output.

[0115] (Plane layout of VCSEL array 10)

[0116] Figure 7 FIG. 1 is a diagram showing an example of a planar layout of a VCSEL array 10 to which the first embodiment is applied. Figure 7 In the figure, the upward direction of the paper is the x direction, and the left direction is the y direction.

[0117] The VCSEL array 10 includes a semiconductor material capable of emitting laser light. For example, the VCSEL array 10 includes a GaAs-based compound semiconductor. Figure 8 ), the VCSEL array 10 is formed by separating a semiconductor layer stack having a plurality of GaAs-based compound semiconductor layers stacked on a p-type GaAs substrate 80 into a plurality of islands. In addition, the region remaining in the form of an island is referred to as an island. The operation of etching the semiconductor layer stack into an island shape and separating the elements is referred to as mesa etching. Figure 7 The planar layout of the VCSEL array 10 is described by referring to the islands 301 to 306 shown in the figure. In addition, the islands 301, 302, and 303 are provided for each VCSEL group. Therefore, when the islands 301, 302, and 303 are distinguished for each VCSEL group, they are sometimes marked with "i" as described above and recorded as islands 301-i, 302-i, and 303-i. In addition, Figure 7 , i is 1 to 8. Also, the number of VCSELs in the VCSEL group is denoted as "j" as described above. Here, j is 1 to 7. In this way, the VCSEL array 10 is formed on a common semiconductor substrate. Therefore, the light emitting device 4 is miniaturized.

[0118] The island 301-i is provided with a VCSELij and a thyristor Si. Figure 8 As shown, VCSELij and setting thyristor Si are stacked. In addition, Figure 7 In the figure, VCSELij and the set thyristor Si are expressed as VCSELij / Si. For example, when "i" is 1, it is expressed as VCSEL1j / S1. The islands 301-i where i is 1 to 4 and the islands 301-i where i is 5 to 8 are arranged in parallel along the -x direction. In addition, the islands 301-i where i is 1 to 4 and the islands 301-i where i is 5 to 8 are arranged in parallel along the -y direction.

[0119] In addition, in the island portion 301-i, Figure 4 As shown in VCSEL group #1 in (a), seven VCSELs are arranged. In addition, no reference numerals are given.

[0120] The island portion 302 - i is provided with a transfer thyristor Ti and a coupling diode Di. The island portion 302 - i is provided so as to be arranged along the −y direction.

[0121] The island 303 - i is provided with a power line resistor Rgi. The island 303 - i is provided so as to be arranged along the -y direction.

[0122] A start diode SD is provided in the island portion 304 , a current limiting resistor R1 is provided in the island portion 305 , and a current limiting resistor R2 is provided in the island portion 306 .

[0123] (Cross-sectional structure of VCSEL array 10)

[0124] Next, before describing the connection relationship between the island portions 301 to 306 , the cross-sectional structures of the island portions 301 and 302 will be described.

[0125] Figure 8 is a diagram showing a cross-sectional structure of the VCSEL array 10. In addition, Figure 8 yes Figure 7 1 is a cross-sectional view of the VCSEL array 10 on the line VIII-VIII in FIG. Figure 8 The cross-sectional view shown is a cross-sectional view taken from the left side on the paper surface, across the coupling diode D1, the transfer thyristor T1, the VCSEL11 / S1, and the VCSEL12 / S1, that is, showing the island portion 301-1 and the island portion 302-1.

[0126] First, the island portion 301-1 provided with the setting thyristor S and the VCSEL is described. Here, the setting thyristor S and the VCSEL are stacked (VCSEL11 / S1, VCSEL12 / S1). Figure 8 As shown, on a p-type GaAs substrate 80, a p-type anode layer (hereinafter referred to as a p-anode layer, and the same applies hereinafter) 81, an n-type gate layer (n-gate layer) 82, a p-type gate layer (p-gate layer) 83, and an n-type cathode layer (n-cathode layer) 84 constituting a setting thyristor S1 are stacked. That is, the setting thyristor S1 is configured such that the p-anode layer 81 is used as an anode, the n-gate layer 82 is used as an n-gate, the p-gate layer 83 is used as a p-gate, and the n-cathode layer 84 is used as a cathode.

[0127] Next, a tunnel junction layer 85 is stacked on the n cathode layer 84 .

[0128] Furthermore, a p-type anode layer (p anode layer) 86, a light emitting layer 87, and an n-type cathode layer (n cathode layer) 88 constituting VCSEL 11 and VCSEL 12 are stacked on the tunneling junction layer 85. That is, the VCSEL is configured with the p anode layer 86 as an anode, the light emitting layer 87 as a light emitting layer, and the n cathode layer 88 as a cathode.

[0129] It is assumed that the thyristor S1 and the VCSELs 11 and 12 are connected in series via a tunnel junction layer 85. The tunnel junction layer 85 will be described later.

[0130] In the VCSEL11 and VCSEL12 portions, the n cathode layer 88, the light emitting layer 87, and the p anode layer 86 are removed by etching to expose the tunneling junction layer 85 around the VCSEL. Here, the cross-sectional shape of the VCSEL is circular. That is, the VCSEL portion is formed in a cylindrical shape. Therefore, the VCSEL portion is referred to as a post 311 (see Figure 7 ).

[0131] The p anode layer 81 , the n gate layer 82 , the p gate layer 83 , the n cathode layer 84 , and the tunnel junction layer 85 constituting the setting thyristor S are continuous between the VCSELs ( VCSEL11 to VCSEL17 ) belonging to the VCSEL group # 1 .

[0132] Moreover, in the island portion 301-1, and further in the portion where the tunneling junction layer 85 and the n cathode layer 84 are removed to expose the p gate layer 83, a p ohmic electrode 331 is provided as the gate Gs1 of the thyristor S1. The p ohmic electrode 331 includes a metal material that can easily form an ohmic contact with a p-type semiconductor layer such as the p gate layer 83.

[0133] On the n cathode layer 88 of the VCSEL, an n ohmic electrode 321 is provided. The n ohmic electrode 321 includes a metal material that is easy to form an ohmic contact with the n-type semiconductor layer such as the n cathode layer 88. In addition, the n ohmic electrode 321 is provided in a circular shape so as to surround the light emitting port 310 (see Figure 7 ).

[0134] The p-anode layer 86 of the pillar portion 311 includes a current constriction layer 86b. Here, as an example, the p-anode layer 86 includes three layers: a lower p-anode layer 86a, a current constriction layer 86b, and an upper p-anode layer 86c. The current constriction layer 86b is a layer that includes a material with a high Al composition ratio such as AlAs, and Al is converted into Al by oxidation. 2 O 3 , thus, the resistance becomes high, forming a part where it is difficult for current to flow ( Figure 8 (blackened part in the figure).

[0135] The pillar portion 311 is provided in a cylindrical shape, so when the current constriction layer 86b is oxidized from the side of the exposed p-anode layer 86, the oxidation is advanced from the peripheral portion of the circular cross section toward the central portion. In addition, by not oxidizing the central portion, the central portion of the cross section of the VCSEL becomes a current passing region 86d where current flows easily, and the peripheral portion becomes a current blocking region 86e where current does not flow easily. In addition, the VCSEL generates light in the portion where the current path is restricted by the current passing region 86d of the light-emitting layer 87. The surface area of ​​the VCSEL corresponding to this current passing region 86d is a light-emitting point, and is a light emitting port 310.

[0136] The current constriction layer 86b is provided to make the VCSEL oscillate in a low-order single transverse mode (single mode). That is, by making the cross-sectional shape of the columnar portion 311 forming the VCSEL circular and oxidizing from the periphery, the cross-sectional shape of the light emitting port 310 is made circular and the area is reduced.

[0137] In addition, the peripheral part of the VCSEL has many defects caused by the mesa etching, which is easy to cause non-luminescent recoupling. Therefore, by providing the current blocking region 86e, the power consumed by the non-luminescent recoupling is suppressed. Thus, low power consumption and improved light extraction efficiency are achieved. In addition, the so-called light extraction efficiency refers to the amount of light that can be extracted per unit power.

[0138] Next, the island portion 302-1 provided with the transfer thyristor T1 and the coupling diode D1 is described. The transfer thyristor T1 includes a p anode layer 81, an n gate layer 82, a p gate layer 83, and an n cathode layer 84, similarly to the setting thyristor S. That is, the transfer thyristor T1 is configured such that the p anode layer 81 is used as an anode, the n gate layer 82 is used as an n gate, the p gate layer 83 is used as a p gate, and the n cathode layer 84 is used as a cathode. Here, a gate electrode (a p ohmic electrode 332 described later) is provided on the p gate layer 83.

[0139] The coupling diode D1 includes a p-gate layer 83 and an n-cathode layer 84. That is, the coupling diode D1 includes the p-gate layer 83 as an anode and the n-cathode layer 84 as a cathode.

[0140] In the island portion 302-1, the n cathode layer 88, the light emitting layer 87, the p anode layer 86, and the tunneling junction layer 85 of the portion where the thyristor S and the VCSEL are stacked are removed. In addition, the n cathode layer 84 is removed in the portion of the transfer thyristor T1 and the portion of the coupling diode D1, so that the n cathode layer 84 remains as the pillar portion 312 and the pillar portion 313.

[0141] An n-ohmic electrode 322 is provided as a cathode electrode of the transfer thyristor T1 on the n-cathode layer 84 of the pillar portion 312. Similarly, an n-ohmic electrode 323 is provided as a cathode electrode of the coupling diode D1 on the n-cathode layer 84 of the pillar portion 313.

[0142] The p ohmic electrode 332 provided on the p gate layer 83 functions as the gate Gt1 of the transfer thyristor T1 and the anode electrode of the coupling diode D1 .

[0143] Furthermore, an interlayer insulating layer 91 is provided so as to cover the surface. On the interlayer insulating layer 91, a wiring 75-1 is provided to connect the p-ohm electrode 331 (gate Gs1) provided on the island 301-1 and the p-ohm electrode 332 (gate Gt1) provided on the island 302-1, and a wiring 75-2 is provided to connect the p-ohm electrode (gate Gs2) provided on the island 301-2 and the p-ohm electrode (gate Gt1) provided on the island 302-2 via a through hole. Furthermore, on the interlayer insulating layer 91, a transmission signal line 72 connected to the n-ohm electrode 322 is provided. Furthermore, on the interlayer insulating layer 91, a transmission signal line 73 is provided. Furthermore, on the interlayer insulating layer 91, a wiring 74-2 connected to the n-ohm electrode 323 is provided via a through hole.

[0144] Furthermore, an interlayer insulating layer 92 is provided in a manner covering the surface. Also, a lighting signal line 76 connected to the n-ohm electrode 321 provided on the island 301-1 is provided on the interlayer insulating layer 92 via through holes provided in the interlayer insulating layer 92 and the interlayer insulating layer 91. That is, the wiring 75 (wiring 75-1, wiring 75-2) and the lighting signal line 76 form a multilayer wiring structure via the interlayer insulating layer 92. The wiring 75 is a wiring that connects the VCSEL group as an example of the light emitting element group and the transfer thyristor T as an example of the light emitting indication unit, and is a wiring that instructs the light emitting element group to emit light from the light emitting indication unit.

[0145] In addition, when the interlayer insulating layers 91 and 92 have poor transmittance to the light emitted from the VCSEL, the interlayer insulating layers 91 and 92 on the light emission port 310 may be replaced with a light emission layer having excellent transmittance to the light emitted from the VCSEL.

[0146] The islands 301, 302, 303, 304, 305, and 306 are separated from each other by removing the surrounding semiconductor layer stack by etching until the substrate 80. In addition, the etching may be performed until the p anode layer 81 is reached, or until a portion of the p anode layer 81 in the thickness direction is reached.

[0147] return Figure 7 , the other islands 303, 304, 305, and 306 are described. In the island 303, a power line resistor Rg1 is formed. In the island 303-1, the n cathode layer 88, the light emitting layer 87, the p anode layer 86, the tunneling junction layer 85, and the n cathode layer 84 in the semiconductor layer stack are removed to expose the p gate layer 83. A pair of p ohmic electrodes are provided on the exposed p gate layer 83. And the p gate layer 83 between the p ohmic electrodes is used as a resistor.

[0148] The island 304 is provided with a start diode SD. In the island 304, the n cathode layer 88, the light emitting layer 87, the p anode layer 86, and the tunnel junction layer 85 in the semiconductor layer stack are removed. In addition, the n cathode layer 84 exposes the p gate layer 83 except for the remaining pillar 314. In the start diode SD, the n cathode layer 84 constituting the pillar 314 is a cathode, and the p gate layer 83 is an anode. In addition, the n ohmic electrode provided on the n cathode layer 84 of the pillar 314 is a cathode electrode, and the p ohmic electrode provided on the exposed p gate layer 83 is an anode electrode.

[0149] The island 305 is provided with a current limiting resistor R1, and the island 306 is provided with a current limiting resistor R2. The islands 305 and 306 have the same structure as the island 303, and the p gate layer 83 between a pair of p ohmic electrodes provided on the exposed p gate layer 83 is used as the current limiting resistors R1 and R2, respectively.

[0150] The islands 301 to 306 and the connection relationship between the islands will be described.

[0151] As described above, the n cathode layer 88 which is the cathode of the VCSEL provided in the pillar portion 311 of the island portion 301 - 1 is connected in parallel to the lighting signal line 76 via the n ohmic electrode 321 . The other island portions 301 are similarly connected.

[0152] The cathode of the transmission thyristor T1 provided in the pillar portion 312 of the island portion 302-1, that is, the n cathode layer 88, is connected to the transmission signal line 72 via the n ohmic electrode 322. The same is true for the transmission thyristor T3 provided in the island portion 302-3 (the third island portion 302 located on the −y direction side). That is, the cathode (n cathode layer 88) of the transmission thyristor Ti of the odd number i is connected to the transmission signal line 72.

[0153] On the other hand, the cathode (n cathode layer 88) of the transfer thyristor T2 provided in the island 302-2 (the second island 302 located on the −y direction side) is connected to the transmission signal line 73. That is, the cathode (n cathode layer 88) of the even-numbered i transfer thyristor Ti is connected to the transmission signal line 73.

[0154] The gate Gs1 of the island 301-1, i.e., the p-ohmic electrode 331, and the gate Gt1 of the island 301-2, i.e., the p-ohmic electrode 332, are connected by the wiring 75-1. The cathode (n cathode layer 88) of the coupling diode D1 provided in the pillar 313 of the island 302-1 is connected via the n-ohmic electrode 323 (see Figure 8 ) and is connected to the wiring 74-2. The wiring 74-2 is connected to the p-ohmic electrode (blank) of the adjacent island 302-2 and the p-ohmic electrode (blank) of the power line resistor Rg2 of the island 303-2.

[0155] The p-ohm electrode 333 provided on the island portion 302-1 (provided on the p-gate layer 83 in the same manner as the p-ohm electrode 332 of the gate Gt1), one of the p-ohm electrodes of the power line resistor Rg1 provided on the island portion 303-1, and the cathode electrode of the start-up diode SD provided on the island portion 304, i.e., the n-ohm electrode, are connected via wiring 74-1.

[0156] The other p-ohm electrode of the power line resistor Rg1 of the island 303 - 1 is connected to the power line 71 . The power line 71 is connected to the Vgk terminal. The same applies to the other islands 303 .

[0157] The transmission signal line 72 is connected to one of the p-ohm electrodes (unsigned) of the current limiting resistor R1 of the island portion 305. The other p-ohm electrode (unsigned) of the current limiting resistor R1 is connected to the φ1 terminal. The transmission signal line 73 is connected to the p-ohm electrode of the start diode SD of the island portion 303 and to one of the p-ohm electrodes (unsigned) of the current limiting resistor R2 of the island portion 306. The other p-ohm electrode (unsigned) of the current limiting resistor R2 of the island portion 306 is connected to the φ2 terminal.

[0158] In the above, the island 301-1, the island 302-1, and the island 303-1 are used as examples for explanation, but the same is true for the other islands 301, 302, and 303. Figure 7 In the figure, for example, wiring 74 - 1 ( 74 ) and the like are labeled, and the other wirings 74 are labeled in the same manner.

[0159] <Thyristor>

[0160] Next, the operation of the setting thyristor S and the transfer thyristor T will be described. The setting thyristor S and the transfer thyristor T are collectively referred to as thyristors.

[0161] The thyristor is formed by stacking a p-anode layer 81 , an n-gate layer 82 , a p-gate layer 83 , and an n-cathode layer 84 .

[0162] As mentioned above, the thyristor is a semiconductor element having three terminals, namely, an anode, a cathode, and a gate, and is formed by stacking, for example, a p-type semiconductor layer (p-anode layer 81, p-gate layer 83) and an n-type semiconductor layer (n-gate layer 82, n-cathode layer 84) based on GaAs, GaAlAs, AlAs, etc. That is, the thyristor has a pnpn structure. Here, as an example, the forward potential (diffusion potential) Vd of the pn junction including the p-type semiconductor layer and the n-type semiconductor layer is set to 1.5V.

[0163] As an example, the reference potential Vsub of the p-type anode layer 81 is set to 0 V as a high-level potential (hereinafter referred to as "H"), and the voltage supplied to the Vgk terminal (see Figure 6) is set to -3.3 V as a low level potential (hereinafter referred to as "L"). Therefore, it is sometimes referred to as "H (0 V)" or "L (-3.3 V)". Figure 6 As shown, the Vgk terminal is connected to the gate (the gate Gt1 when the thyristor Th is the transfer thyristor T1 ) via the power supply line resistor Rg1 .

[0164] When a potential lower than the threshold voltage (negative potential with a large absolute value) is applied to the cathode, the thyristor in the off state, where no current flows between the anode and the cathode, changes to the on state (turns on). Here, the threshold voltage of the thyristor is the value obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the gate.

[0165] When the thyristor is turned on, the gate of the thyristor becomes a potential close to the anode potential. Here, the anode is 0V, so the gate becomes 0V. In addition, the cathode of the thyristor in the on state is a potential close to the potential obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the anode potential (the absolute value is recorded as the holding voltage). Here, the anode is 0V, so the cathode of the thyristor in the on state is a potential close to -1.5V (a negative potential with an absolute value greater than 1.5V). Here, the holding voltage is set to 1.5V.

[0166] The thyristor in the on state maintains the on state when a potential lower than the potential required to maintain the on state (a negative potential with a large absolute value) is continuously applied to the cathode and a current (maintaining current) capable of maintaining the on state is supplied.

[0167] On the other hand, the thyristor in the on state changes to the off state (turned off) when the cathode reaches a potential higher than the potential required to maintain the on state (the potential close to -1.5 V) (negative potential with a small absolute value, 0 V or positive potential).

[0168] <Tunneling junction layer 85>

[0169] Next, if Figure 8 As shown, the setting thyristor S and the VCSEL in the island portion 301 are stacked via the tunnel junction layer 85. Thus, the setting thyristor S and the VCSEL are connected in series.

[0170] Fig. 9 (a) to Fig. 9 (c) is a diagram for further explaining the stacked structure of the thyristor S and the VCSEL. Fig. 9 (a) is a schematic energy band diagram of a stacked structure of a thyristor S and a VCSEL. Fig. 9 (b) is the energy band diagram of the tunneling junction layer 85 under the reverse bias state. Fig. 9(c) shows the current-voltage characteristics of the tunnel junction layer 85 .

[0171] In Figure 7 , Figure 8 The voltage is applied between the lighting signal φI applied to the n-ohm electrode 321 and the reference potential Vsub of the back electrode 90, and the thyristor S and the VCSEL are set to be forward biased. Fig. 9 As shown in the energy band diagram of (a), the n ++ Layer 85a and p ++ The layers 85b are reverse biased.

[0172] The tunnel junction layer 85 is an n-type layer doped with n-type impurities at a high concentration. ++ The layer 85a is a p-type layer doped with p-type impurities at a high concentration. ++ Therefore, when the width of the depletion region is narrow and becomes forward biased, electrons from n ++ The conduction band on the layer 85a side tunnels to the p ++ The valence band of the layer 85b side (valence band) shows negative resistance characteristics (refer to Fig. 9 (c) forward bias side (+V).

[0173] On the other hand, Fig. 9 As shown in (b), when the tunneling junction layer 85 becomes reverse biased (-V), p ++ The potential Ev of the valence band (valence band) on the layer 85b side is n ++ The potential Ec of the conduction band (conduction band) on the layer 85a side is higher than that of the conduction band. ++ The valence band (valence band) of layer 85b tunnels to n ++ The conduction band (conduction band) on the layer 85a side. And, the greater the reverse bias voltage (-V), the easier it is for electrons to tunnel. Fig. 9 As shown on the reverse bias side (-V) of (c), the greater the reverse bias, the easier it is for current to flow in the tunnel junction layer 85 (tunnel junction).

[0174] Therefore, if Fig. 9 As shown in (a), when a voltage is applied so that the setting thyristor S and the VCSEL are each forward biased, and the setting thyristor S is turned on and changes to the on state, even if the tunneling junction layer 85 is reverse biased, current still flows from the setting thyristor S to the VCSEL.

[0175] In addition, a III-V compound layer may be used instead of the tunneling junction layer 85, wherein the III-V compound layer has metallic conductivity and is epitaxially grown on a III-V compound semiconductor layer. InNAs, which is described as an example of a material for a metallic conductive III-V compound layer, has a negative band gap energy when, for example, the combination ratio x of InN is in the range of about 0.1 to about 0.8. Moreover, InNSb has a negative band gap energy when, for example, the combination ratio x of InN is in the range of about 0.2 to about 0.75. A negative band gap energy means that there is no band gap. Therefore, it will exhibit the same conductive properties (conduction properties) as metals. That is, the so-called metallic conductive properties (conductivity) mean that, like metals, as long as there is a gradient in potential, current will flow.

[0176] In addition, the lattice constant of III-V compounds (semiconductors) such as GaAs and InP is In addition, the lattice constant is close to the lattice constant of Si, that is, about The lattice constant of Ge is about

[0177] In contrast, the lattice constant of InN, a III-V compound, is about The lattice constant of InAs is about Therefore, the lattice constant of InNAs, a compound of InN and InAs, can be similar to that of GaAs and the like. Close value.

[0178] Moreover, the lattice constant of InSb as a III-V compound is about Therefore, since the lattice constant of InN is about Therefore, the lattice constant of InNSb, a compound of InSb and InN, can be similar to that of GaAs and the like. Close value.

[0179] That is, InNAs and InNSb can be monolithically epitaxially grown with respect to a layer of a III-V compound (semiconductor) such as GaAs. Moreover, a layer of a III-V compound (semiconductor) such as GaAs can be monolithically stacked on a layer of InNAs or InNSb by epitaxial growth.

[0180] Therefore, if the setting thyristor S and the VCSEL are stacked in series via a metal conductive III-V compound layer instead of the tunneling junction layer 85, the n cathode layer 84 of the setting thyristor S and the p anode layer 86 of the VCSEL can be prevented from being reversely biased.

[0181] <Operation of stacked setting thyristor S and VCSEL>

[0182] Next, the operation of the stacked setting thyristor S and VCSEL will be described.

[0183] Here, the rise voltage of the VCSEL is set to 1.5 V. That is, the VCSEL emits light as long as a voltage of 1.5 V or more is applied between the anode and cathode of the VCSEL.

[0184] The lighting signal φI is assumed to be 0 V (“H (0 V)”) or −3.3 V (“L (−3.3 V)”). 0 V is a potential for turning off the VCSEL, and −3.3 V is a potential for turning on the VCSEL from the off state.

[0185] In the case of changing the VCSEL from the off state to the on state, the lighting signal φI is set to "L (-3.3V)". At this time, when -1.5V is applied to the gate Gs of the setting thyristor S, the threshold of the setting thyristor S becomes -3V obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the gate Gs (-1.5V). At this time, since the lighting signal φI is -3.3V, the setting thyristor S is turned on and changes from the off state to the on state, and the VCSEL also changes from the off state to the on state. That is, the VCSEL performs laser oscillation and emits light. Therefore, the voltage applied to the setting thyristor S in the on state (holding voltage Vr) is 1.5V, so 1.8V is applied to the laser diode LD. In addition, the rise voltage of the VCSEL is 1.5V, so the VCSEL continues to emit light.

[0186] On the other hand, when the lighting signal φI is set to 0 V, both ends of the series connection of the setting thyristor S and the VCSEL become 0 V, the setting thyristor S changes from the on state to the off state (turns off), and the VCSEL stops emitting light.

[0187] The operation of the VCSEL array 10 will be described in detail later.

[0188] (Structure of Semiconductor Layer Stack)

[0189] As described above, the semiconductor layer stack is formed by stacking the substrate 80 , the p anode layer 81 , the n gate layer 82 , the p gate layer 83 , the n cathode layer 84 , the tunneling junction layer 85 , the p anode layer 86 , the light emitting layer 87 , and the n cathode layer 88 .

[0190] As described above, the substrate 80 is described by taking p-type GaAs as an example, but it can also be n-type GaAs, intrinsic (i) GaAs without adding impurities. In addition, it can also be a semiconductor substrate containing InP, GaN, InAs, other III-V group, II-VI materials, sapphire, Si, Ge, etc. In the case of changing the substrate, the material stacked as a whole on the substrate is a material that roughly matches the lattice constant of the substrate (including deformation structure, deformation relaxation layer, metamorphic growth). As an example, InAs, InAsSb, GaInAsSb, etc. are used on an InAs substrate, InP, InGaAsP, etc. are used on an InP substrate, GaN, AlGaN, InGaN are used on a GaN substrate or a sapphire substrate, and Si, SiGe, GaP, etc. are used on a Si substrate. However, in the case where the substrate 80 is electrically insulating, a wiring for supplying a reference potential Vsub must be separately provided. Furthermore, when the semiconductor layer stacked body other than the substrate 80 is attached to another supporting substrate and the semiconductor layer stacked body is provided on the other supporting substrate, the lattice constants of the supporting substrate and the substrate do not need to match each other.

[0191] The p-anode layer 81 has an impurity concentration of, for example, 1×10 18 / cm 3 p-type Al 0.9 The GaAs and Al components can also be changed within the range of 0 to 1.

[0192] The n gate layer 82 has an impurity concentration of, for example, 1×10 17 / cm 3 n-type Al 0.9 The GaAs and Al components can also be changed within the range of 0 to 1.

[0193] The p-gate layer 83 has an impurity concentration of, for example, 1×10 17 / cm 3 p-type Al 0.9 The GaAs and Al components can also be changed within the range of 0 to 1.

[0194] The n cathode layer 84 has an impurity concentration of, for example, 1×10 18 / cm 3 n-type Al 0.9 The GaAs and Al components can also be changed within the range of 0 to 1.

[0195] The tunnel junction layer 85 includes n-type impurities doped at a high concentration. ++ The layer 85a is a p-type layer doped with n-type impurities at a high concentration. ++ The junction of layer 85b (refer to Fig. 9 (a)). ++Layer 85a and p ++ The layer 85b has an impurity concentration of, for example, 1×10 20 / cm 3 In addition, the impurity concentration of the usual junction is 10 17 / cm 3 ~10 18 / cm 3 .n ++ Layer 85a and p ++ The combination of layer 85b (hereinafter referred to as n ++ Layer 85a / p ++ Layer 85b) is, for example, n ++ GaInP / p ++ GaAs, n ++ GaInP / p ++ AlGaAs, n ++ GaAs / p ++ GaAs, n ++ AlGaAs / p ++ AlGaAs, n ++ InGaAs / p ++ InGaAs, n ++ GaInAsP / p ++ GaInAsP, n ++ GaAsSb / p ++ GaAsSb. In addition, the combination may be changed.

[0196] The p-anode layer 86 is formed by laminating a lower p-anode layer 86a, a current constriction layer 86b, and an upper p-anode layer 86c in this order. The lower p-anode layer 86a and the upper p-anode layer 86c have an impurity concentration of, for example, 5×10 17 / cm 3 p-type Al 0.9 The GaAs and Al components can also be changed within the range of 0 to 1.

[0197] The current constriction layer 86b is, for example, AlAs or p-type AlGaAs with a high Al impurity concentration. 2 O 3 , so that the resistance becomes high and the current blocking region 86e is formed. Alternatively, hydrogen ions (H + ), and a current blocking region 86e (H + ion implantation).

[0198] The light-emitting layer 87 is a quantum well structure formed by alternately stacking well layers and barrier layers. The well layers are, for example, GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, GaInP, etc., and the barrier layers are AlGaAs, GaAs, GaInP, GaInAsP, etc. In addition, the light-emitting layer 87 may also be a quantum wire or a quantum box (quantum dot).

[0199] The n cathode layer 88 has an impurity concentration of, for example, 5×10 17 / cm 3 n-type Al 0.9 The GaAs and Al components can also be changed within the range of 0 to 1.

[0200] These semiconductor layers are stacked by, for example, Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or the like to form a semiconductor layer stack.

[0201] In addition, the AlGaAs-based materials may be replaced with GaInP and the like. Moreover, a GaN substrate or an InP-based substrate may also be used. Moreover, the VCSEL including the p anode layer 86, the light emitting layer 87, and the n cathode layer 88 and the setting thyristor S and the transmission thyristor T including the p anode layer 81, the n gate layer 82, the p gate layer 83, and the n cathode layer 84 may be made of materials having different lattice constants, respectively. This can be achieved by metamorphic growth, or by growing the setting thyristor S and the transmission thyristor T separately from the VCSEL and pasting them together. At this time, the tunneling junction layer 85 only needs to roughly match the lattice constant of any one of them.

[0202] The VCSEL array 10 can be manufactured by known techniques such as photolithography and etching, and thus the description of the manufacturing method is omitted.

[0203] (Operation of VCSEL Array 10)

[0204] Fig.10 1 is a diagram showing an example of a timing chart for controlling the light emission / non-light emission of a VCSEL group in the VCSEL array 10. Figure 6 , Figure 7 The description will be made by taking as an example the case where each VCSEL group described in hereinafter includes seven VCSELs. Fig.10 , assume that time passes in alphabetical order (a, b, c, ...). Fig.10The timing chart shown shows the portion for controlling VCSEL group #1 to VCSEL group #4. The period for sequentially making VCSEL group #1 to VCSEL group #4 emit light is defined as period U-1 to period U-4. Here, as described later, the lengths of the periods U-1 to U-4 are different, but may be the same.

[0205] Reference Figure 6 To illustrate Fig.10 Time diagram.

[0206] At time a, Figure 6 The control unit 50 shown in the figure supplies power. Then, the reference potential Vsub is set to "H (0 V)" and the power supply potential Vgk is set to "L (-3.3 V)".

[0207] Next, the waveforms of the signals (transmission signals 1φ, φ2, lighting signal φI) are described. In addition, since periods U-1 to U-8 are basically the same, the description will be centered on period U-1. In addition, when periods U-1 to U-4 are not distinguished, they are recorded as period U.

[0208] The transmission signal φ1 is a signal that becomes "H(0V)" or "L(-3.3V)". The transmission signal φ1 is "H(0V)" at time a, and changes to "L(-3.3V)" at time b. And, at time i, it returns to "H(0V)". And, at time m, it changes to "L(-3.3V)" again. The transmission signal φ2 is also a signal that becomes "H(0V)" or "L(-3.3V)". The transmission signal φ2 is "H(0V)" at time a, and changes to "L(-3.3V)" at time h. And, at time n, it returns to "H(0V)".

[0209] After time b, the transmission signals φ1 and φ2 alternately switch between "H(0V)" and "L(-3.3V)" while sandwiching a period in which they become "L(-3.3V)" (for example, the period from time h to time i). Therefore, the period from time b when the transmission signal φ1 changes from "H(0V)" to "L(-3.3V)" until time h when the transmission signal φ2 changes from "H(0V)" to "L(-3.3V)" is defined as period U-1, and conversely, the period from time h when the transmission signal φ2 changes from "H(0V)" to "L(-3.3V)" until time m when the transmission signal φ1 changes from "H(0V)" to "L(-3.3V)" is defined as period U-2. The same applies to periods U-3 and U-4.

[0210] The lighting signal φI is a signal that becomes "H (0V)" or "L (-3.3V)". And, the lighting signal φI repeats "H (0V)" and "L (-3.3V)" during each period U, when one of the transmission signals φ1 and φ2 is "H (0V)" and the other is "L (-3.3V)", for example, from time c to time g in the period U-1, or from time j to time l in the period U-2. And, it is "H (0V)" during other periods.

[0211] Next, refer to Figure 6 To illustrate Fig.10 In addition, Fig.10 In FIG. 1 , the solid line indicates the period during which the VCSEL emits light.

[0212] At time a, Figure 1 The control unit 50 shown supplies power, the reference potential Vsub is set to "H (0V)", and the power supply potential Vgk is set to "L (-3.3V)". Therefore, the transmission signals φ1 and φ2 are set to "H (0V)". The cathode of the start diode SD becomes the power supply potential Vgk ("L (-3.3V)") via the power line resistor Rg1, and the anode becomes the transmission signal φ2 "H (0V)" via the current limiting resistor R2. Therefore, the start diode SD becomes forward biased, and the gate Gt1 of the transmission thyristor T1 becomes -1.5V. As a result, the threshold voltage of the transmission thyristor T1 becomes -3V.

[0213] At time b, the transfer signal φ1 changes from "H (0V)" to "L (-3.3V)". At this time, since the threshold voltage is -3V, the transfer thyristor T1 is turned on and changes from the off state to the on state. Then, the gate Gt1 becomes 0V. As a result, the gate Gs1 of the setting thyristor S1 connected to the gate Gt1 becomes 0V. Then, the threshold voltage of the setting thyristor S1 becomes -1.5V. At time b, the lighting signal Iφ is "H (0V)". That is, 0V is applied to the series connection of the setting thyristor S1 and VCSEL11 to VCSEL17. Therefore, the setting thyristor S1 is in the off state, and VCSEL11 to VCSEL17 do not emit light.

[0214] At time c, when the lighting signal φI changes from "H (0V)" to "L (-3.3V)", the setting thyristor S1 with a threshold voltage of -1.5V is turned on and changes from an off state to an on state. Then, as described above, a current flows through VCSEL11 to VCSEL17 and emits light. At this time, the cathode-anode of the setting thyristor S1 becomes 1.5V, and the cathode-anode of VCSEL11 to VCSEL17 becomes 1.8V. Therefore, the light emission of VCSEL11 to VCSEL17 is maintained. That is, at time c, VCSEL11 to VCSEL17 belonging to VCSEL group #1 emit light in parallel.

[0215] At time d, when the lighting signal φI changes from "L (-3.3V)" to "H (0V)", the two ends of the series connection of the setting thyristor S1 and VCSEL11 to VCSEL17 become 0V, the setting thyristor S1 is turned off and changes from the on state to the off state, and VCSEL11 to VCSEL17 become non-lighting. That is, at time d, VCSEL11 to VCSEL17 belonging to VCSEL group #1 become non-lighting in parallel. However, the threshold voltage of the setting thyristor S1 is maintained at -3V.

[0216] Therefore, at time e, when the lighting signal φI changes from "H (0 V)" to "L (-3.3 V)", the setting thyristor S1 with a threshold voltage of -3 V is turned on again and changes from the off state to the on state, and VCSEL11 to VCSEL17 emit light.

[0217] At time f, when the lighting signal φI changes from “L (-3.3 V)” to “H (0 V)”, the thyristor S1 is set to be turned off again and changes from the on state to the off state, and VCSEL11 to VCSEL17 become off.

[0218] That is, during the period U-1 from the moment b when the transmission signal φ1 changes from "H (0 V)" to "L (-3.3 V)" to the moment h when the transmission signal φ2 changes from "H (0 V)" to "L (-3.3 V)", the following operation is repeated, that is, the lighting signal φI changes from "H (0 V)" to "L (-3.3 V)", and then changes from "L (-3.3 V)" to "H (0 V)", thereby VCSEL11 to VCSEL17 belonging to VCSEL group #1 emit light in parallel in a pulsed manner (intermittently). In addition, four pulse lights are emitted during the period U-1.

[0219] Similarly, during the period U-2 from time h to time m, VCSEL21 to VCSEL27 belonging to VCSEL group #2 emit three pulses of light in parallel. Moreover, during the period U-3 from time m to time o, VCSEL31 to VCSEL34 belonging to VCSEL group #3 emit three pulses of light in parallel. In addition, the light emission time of each pulse in the period U-3 is set to be longer than that of the periods U-1 and U-2. Furthermore, during the period U-4 from time o to time r, VCSEL41 to VCSEL44 belonging to VCSEL group #4 emit five pulses of light in parallel. In addition, the light emission time of each pulse in the period U-4 is set to be shorter than that of the periods U-1 and U-2.

[0220] In the above, multiple pulse lights are emitted during the period U, but a single pulse light may be emitted. Furthermore, during the period U, as long as the lighting signal φI is maintained at "H (0V)", the two ends of the series connection of the thyristor S and the VCSEL are set to maintain 0V. Therefore, the VCSEL group does not emit light. That is, during the predetermined period U, the VCSEL group may also be maintained to be non-emitting.

[0221] At time b, the gate Gt1 of the transfer thyristor T1 becomes 0 V, and setting the gate Gs1 to 0 V via the wiring 75 - 1 is a light emission instruction from the transfer thyristor T1 . The same applies to other cases.

[0222] As described above, by using the driving unit 11, the on state is sequentially propagated between adjacent transmission thyristors T, thereby performing lighting control of the VCSEL group, that is, instructing the VCSEL group to emit light. The phenomenon that the on state is sequentially propagated between adjacent transmission thyristors T is called self-scanning. Sometimes, a light emitting element array such as the VCSEL array 10 that performs self-scanning is called a self-scanning light emitting element (Self-scanning Light Emitting Device, SLED) array. This makes it easy to control the light emitting element array.

[0223] In addition, instead of relying on self-scanning, a light emission instruction unit may be independently provided for each VCSEL group, and light emission instructions may be sequentially provided for the VCSEL groups.

[0224] Moreover, by making multiple VCSELs belonging to the VCSEL group emit light in parallel, compared with the case where the size of the light-emitting point is increased to increase the light output, the phenomenon of loss of uniformity of light emission, deformation of the light emission profile, or loss of light emission characteristics of the VCSEL, such as an increase in the spread angle, is suppressed.

[0225] (Arrangement of VCSEL Group)

[0226] Fig.11This is a diagram for explaining the arrangement of a VCSEL group in a VCSEL array 10 to which the first embodiment is applied. Fig.11 In the example, the VCSEL array 10 is Figure 4 (a) and Figure 4 (b) Figure 7 As shown, as an example, eight VCSEL groups are provided for explanation. Fig.11 is Figure 7 In FIG. 1 , the connection relationship between the gate Gt of the transfer thyristor T in the island portion 302 and the gate Gs of the setting thyristor S in the island portion 301 is derived and illustrated.

[0227] like Fig.11 As shown, islands 301-1 to 301-4 and islands 301-5 to 301-8 are arranged in the -x direction. Furthermore, the arrangement of islands 301-1 to 301-4 and the arrangement of islands 301-5 to 301-8 are arranged in parallel in the -y direction. Thus, wirings 75 (wirings 75-1 to 75-8) connecting gates Gt1 to Gt8 and gates Gs1 to Gs8 do not cross each other or are arranged close to each other.

[0228] Fig.11 In the arrangement shown, when the conduction state of the transfer thyristor T is sequentially transferred in the -y direction, the VCSEL groups are sequentially controlled to light up in the -x direction. That is, after the VCSEL groups are sequentially controlled to light up in the -x direction from VCSEL group #1 to VCSEL group #4 (lighting is completed), they are sequentially controlled to light up in the -x direction from VCSEL group #5 to VCSEL group #8. That is, the lighting control is performed in the direction (-x direction) orthogonal to the direction (-y direction) in which the conduction state of the transfer thyristor T is transferred. VCSEL group #1 to VCSEL group #4 are an example of a first light emitting element group, and VCSEL group #5 to VCSEL group #8 are an example of a second light emitting element group.

[0229] Fig.12 This is a diagram for explaining the arrangement of a VCSEL group in a VCSEL array 10 ′ to which the first embodiment is not applied, for comparison. Fig.12 In the VCSEL array 10 ′ shown, the connection relationship between the gate Gt of the transfer thyristor T in the island portion 302 and the gate Gs of the setting thyristor S in the island portion 301 is also derived and illustrated.

[0230] like Fig.12As shown, islands 301-1 to 301-2, islands 301-3 to 301-4, islands 301-5 to 301-6, and islands 301-7 to 301-8 are arranged in the -y direction. Furthermore, the arrangement of islands 301-1 to 301-2, the arrangement of islands 301-3 to 301-4, the arrangement of islands 301-5 to 301-6, and the arrangement of islands 301-7 to 301-8 are arranged in parallel in the -x direction. In this way, when the conduction state of the transfer thyristors T is sequentially transferred in the -y direction, the VCSEL groups in the arrangement region 100 are also sequentially controlled to light up in the -y direction. That is, after VCSEL group #1 and VCSEL group #2 are sequentially controlled to light up along the -y direction (lighting is completed), VCSEL group #3 and VCSEL group #4 are sequentially controlled to light up along the -y direction. The same is true for VCSEL group #5 to VCSEL group #8. That is, lighting control is performed in a direction (-y direction) parallel to the direction (-y direction) in which the on-state of the transfer thyristor T is transferred.

[0231] However, in the VCSEL array 10', the wiring 75-2 connecting the gate Gt2 and the gate Gs2 intersects with the wiring 75-3 connecting the gate Gt3 and the gate Gs3 (the portion indicated by α). Moreover, the wiring 75-2 connecting the gate Gt2 and the gate Gs2, the wiring 75-4 connecting the gate Gt4 and the gate Gs4, and the wiring 75-5 connecting the gate Gt5 and the gate Gs5 are close to each other (the portion indicated by β). Furthermore, the wiring 75-5 connecting the gate Gt5 and the gate Gs5 is close to the wiring 75-6 connecting the gate Gt6 and the gate Gs6 (the portion indicated by γ). Furthermore, the wiring 75-7 connecting the gate Gt7 and the gate Gs7 is close to the wiring 75-8 connecting the gate Gt8 and the gate Gs8 (the portion indicated by δ).

[0232] Fig.12 In the arrangement shown, lighting control is performed along a direction (-y direction) parallel to the direction (-y direction) in which the conduction state of the transfer thyristor T is transmitted, but the wiring 75 connecting the gate Gt of the transfer thyristor T in the island portion 302 and the gate Gs of the setting thyristor S in the island portion 301 cross or are close to each other, so it is difficult to set the wiring 75.

[0233] As explained above, as long as Fig.11 As shown in the VCSEL array 10 applicable to the first embodiment, the lighting control of the VCSEL group is performed in a direction orthogonal to the direction in which the conduction state of the transfer thyristor T is transmitted, and the wiring 75 connecting the gate Gt of the transfer thyristor T in the island portion 302 and the gate Gs of the setting thyristor S in the island portion 301 will not cross or be arranged close to each other.

[0234] in addition, Fig.11 In the embodiment, the VCSEL group is controlled to be lit in the -x direction, but the VCSEL group and the wiring 75 may be arranged so as to be controlled to be lit in the +x direction.

[0235] [Second embodiment]

[0236] In the VCSEL array 10 to which the first embodiment is applied, the lighting control of the VCSEL group is performed in a direction orthogonal to the direction in which the conduction state of the transmission thyristor T is transmitted. In addition, in the VCSEL array 10, the lighting control of the VCSEL group is performed in one of the directions orthogonal to the direction in which the conduction state of the transmission thyristor T is transmitted. In the VCSEL array 20 to which the second embodiment is applied, the lighting control of the VCSEL group is performed in a manner of alternating back and forth in a direction orthogonal to the direction in which the conduction state of the transmission thyristor T is transmitted. The other structures are the same as those in the first embodiment, so the description is omitted, and the different parts, namely, the arrangement of the VCSEL group in the VCSEL array 20, are described. In addition, the same symbols are marked on components having the same functions.

[0237] (Arrangement of VCSEL Group) Fig.13 This is a diagram for explaining the arrangement of a VCSEL group in a VCSEL array 20 to which the second embodiment is applied. Fig.13 In the embodiment, the VCSEL array 20 is as in the first embodiment. Figure 4 (a) and Figure 4 (b) Figure 7 As shown, eight VCSEL groups are included for illustration. Fig.13 In FIG. 1 , the connection relationship between the gate Gt of the transfer thyristor T in the island portion 302 and the gate Gs of the setting thyristor S in the island portion 301 is also derived and illustrated.

[0238] like Fig.13 As shown in FIG. 1 , islands 301-1 to 301-4 are arranged along the -x direction, and islands 301-5 to 301-8 are arranged along the +x direction. Fig.11 The islands 301-5 to 301-8 in the first embodiment are inverted in the y direction. Thus, the wirings 75 (wirings 75-1 to 75-8) connecting the gates Gt1 to Gt8 and the gates Gs1 to Gs8 do not cross or are arranged close to each other.

[0239] When the conduction state of the transfer thyristor T is sequentially transferred in the -y direction, in the arrangement area 100, VCSEL group #1 to VCSEL group #4 are sequentially controlled to light up in the -x direction. Next, VCSEL group #5 to VCSEL group #8 are sequentially controlled to light up in the +x direction. That is, in the VCSEL array 20 of the second embodiment, the lighting control of the VCSEL group is performed alternately in the direction orthogonal to the direction in which the conduction state of the transfer thyristor T is transferred (-x direction and +x direction). In addition, the wiring connecting the gate Gt of the transfer thyristor T in the island portion 302 and the gate Gs of the setting thyristor S in the island portion 301 is arranged so as not to cross or approach.

[0240] In the first and second embodiments, the VCSEL arrays 10 and 20 have a structure in which VCSELs are stacked on the setting thyristors S on the substrate 80. The VCSEL arrays 10 and 20 may have a structure in which the setting thyristors S are stacked on the VCSELs on the substrate 80.

[0241] Furthermore, the VCSEL is controlled to be in a light-emitting state and a non-light-emitting state, but it can also be set in advance to a light-emitting state with a small amount of light, and when the thyristor S is set to change from an off state to an on state, control is performed to increase the amount of light. Furthermore, control can be performed between VCSEL groups that are lit in sequence so that the light-emitting state is repeated.

[0242] In the first embodiment and the second embodiment, the lighting control of the VCSEL group is performed by self-scanning of the driving unit 11 including the transmission thyristor T that sequentially transmits the conductive state. This makes the lighting control of the VCSEL group easy. However, the driving unit 11 only needs to be able to independently control the lighting of the VCSEL group. Moreover, the VCSEL group does not need to be driven sequentially. In addition, the driving unit 11 may also include a transistor provided for each VCSEL group instead of the transmission thyristor T, etc.

Claims

1. A light emitting element array, comprising: A plurality of light-emitting indicating portions arranged toward a first direction; A first light emitting element group, in which a light emitting element group including a plurality of light emitting elements is arranged in a direction intersecting the first direction; a second light emitting element group, in which a light emitting element group including a plurality of light emitting elements is arranged along the first light emitting element group on the first direction side relative to the first light emitting element group; as well as a plurality of wirings, wherein the plurality of wirings are a plurality of wirings that connect the plurality of light-emitting indicating portions and the light-emitting element groups of the first light-emitting element group and the second light-emitting element group to perform light-emitting instructions, and are connected in the following manner, that is, when the plurality of light-emitting indicating portions sequentially perform light-emitting instructions toward the first direction, the first light-emitting element group sequentially emits light in a direction intersecting the first direction, and after the first light-emitting element group is lit, the second light-emitting element group sequentially emits light in a direction intersecting the first direction, The light emitting element group arranged in the first light emitting element group column and the light emitting element group arranged in the second light emitting element group column are composed of a semiconductor layer stacked body in which a plurality of semiconductor layers are stacked, and the light emitting element groups are separated from each other.

2. The light emitting element array according to claim 1, wherein The first light emitting element group and the second light emitting element group are arranged adjacent to each other. The wiring is connected in such a manner that a direction in which the light emitting elements in the first light emitting element group sequentially emit light is the same as a direction in which the light emitting elements in the second light emitting element group sequentially emit light.

3. The light emitting element array according to claim 1, wherein The first light emitting element group and the second light emitting element group are arranged adjacent to each other. The wiring is connected in such a manner that a direction in which the light emitting elements in the first light emitting element group sequentially emit light is opposite to a direction in which the light emitting elements in the second light emitting element group sequentially emit light.

4. The light emitting element array according to any one of claims 1 to 3, wherein A plurality of wirings for connecting each of the plurality of light-emitting indicator portions and the light-emitting element groups of the first light-emitting element group and the second light-emitting element group to provide light-emitting instructions are provided so as not to cross each other.

5. The light emitting element array according to any one of claims 1 to 3, wherein A plurality of wirings for connecting each of the plurality of light-emitting instruction units and the light-emitting element groups of the first light-emitting element group and the second light-emitting element group to provide light-emitting instruction are provided at most one between the light-emitting elements in the light-emitting element groups.

6. The light emitting element array according to any one of claims 1 to 3, wherein The plurality of light-emitting indication units sequentially perform light-emitting indication by self-scanning.

7. A light emitting device, comprising: The light emitting element array according to any one of claims 1 to 6; as well as The circular optical element has a size that includes the plurality of light emitting element groups included in the light emitting element array and is provided on emission paths of the plurality of light emitting element groups.

8. The light emitting device according to claim 7, wherein The optical element is a lens that narrows a spread angle of light emitted from the plurality of light emitting element groups.

9. The light emitting device according to claim 7 or 8, comprising: The diffusion member diffuses the light emitted from the plurality of light emitting element groups and transmitted through the optical element, and then emits the light.

10. The light emitting device according to claim 7 or 8, comprising: The diffraction member diffracts the light emitted from the plurality of light emitting element groups and transmitted through the optical element and emits the light.

11. An optical device comprising: The light emitting device according to any one of claims 7 to 10; as well as The light receiving unit receives reflected light emitted from the plurality of light emitting element groups included in the light emitting device and reflected by the object to be measured.

12. A measuring device comprising: The optical device according to claim 11; as well as The three-dimensional shape specifying unit specifies the three-dimensional shape of the object by measuring the three-dimensional shape based on the time from when light is emitted from the plurality of light emitting element groups included in the optical device to when light is received by the light receiving unit included in the optical device.

13. An information processing device, comprising: The measuring device as claimed in claim 12; as well as The authentication processing unit performs authentication processing related to the use of the own device based on the determination result of the three-dimensional shape determination unit included in the measurement device.

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