A low power consumption timing switch system and implementation method

Abstract

An ultra-low power consumption timing switch system and implementation method include an LX04 low-frequency oscillator, a frequency duty cycle adjustment module and a trigger module; the LX04 low-frequency oscillator, the frequency duty cycle adjustment module and the trigger module are connected in sequence, the LX04 low-frequency oscillator is used to generate a signal, the frequency duty cycle adjustment module adjusts the pulse output by the LX04 low-frequency oscillator as desired, and the trigger module uses the signal output by the frequency duty cycle adjustment module to control the on and off of the load. The timing switch contains an ultra-low power consumption frequency duty cycle adjustable timer, whose power consumption is much lower than that of the existing low-frequency oscillator, reaching the nW level, and the trigger module controls the on and off of the load through the signal of the timer. In this way, the static power consumption and timing power consumption of the system itself are greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of timing switches, and particularly relates to a low-power timing switch system and an implementation method thereof. Background Art

[0002] Existing measuring instruments often achieve the measurement function by periodically collecting environmental parameters through sensors. During the real-time detection process, a large amount of power consumption is consumed in the timing process when the sensors are not measuring. This brings inconvenience to many applications, especially in applications that require battery power supply or where battery replacement is inconvenient. Summary of the Invention

[0003] The purpose of the present invention is to provide a low-power timing switch system and an implementation method thereof to solve the above problems.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] A low-power timing switch system includes an LX04 low-frequency oscillator, a frequency duty cycle adjustment module, and a trigger module; the LX04 low-frequency oscillator, the frequency duty cycle adjustment module, and the trigger module are connected in sequence. The LX04 low-frequency oscillator is used to generate signals, the frequency duty cycle adjustment module adjusts the pulses output by the LX04 low-frequency oscillator according to expectations, and the trigger module uses the signals output by the frequency duty cycle adjustment module to control the on / off of the load;

[0006] The LX04 low-frequency oscillator includes three LX01 voltage detection chips, a pull-up resistor R1, a pull-up resistor R2, and a PMOS transistor Q1; the three LX01 voltage detection chips are respectively LX01-A, LX01-B, and LX01-C. One end of the pull-up resistor R1 is connected between the output of LX01-A and the input of LX01-B, and one end of the pull-up resistor R2 is connected between the output of LX01-B and the input of LX01-C. At the same time, one end of the pull-up resistor R2 and the output of LX01-B are connected to the gate of the PMOS transistor Q1. The other ends of the pull-up resistor R1 and the pull-up resistor R2 are both connected to the source of the PMOS transistor Q1. The output VOD1 of LX01-C is connected to the input of LX01-A and the drain of the PMOS transistor Q1; the source of the PMOS transistor Q1 is connected to the first power supply VDD1.

[0007] Further, the three LX01 voltage detection chips are all grounded.

[0008] Further, the frequency duty cycle adjustment module includes a frequency divider, a NOR gate, a resistor R3, and a capacitor C1; the output VOD1 of LX01-C is connected to the input of the frequency divider; the frequency divider has an output a and an output b, where the output a is directly connected to the input a of the NOR gate, and the output b is connected to the RC delay circuit composed of R3 and C1 to delay the signal on the output b path, and the positive electrode of C1 is connected to the other input b of the NOR gate.

[0009] Further, the negative electrode of C1 is grounded.

[0010] Further, the trigger module includes an LX01-D voltage detection circuit, a pull-up resistor R4, a PMOS-Q2, a power management module, and a load; the output OUT of the frequency duty cycle adjustment module is connected to the input end of the LX01-D voltage detection circuit. One end of the pull-up resistor R4 is connected to the output VOD2 of the LX01-D voltage detection circuit and at the same time connected to the gate of PMOS-Q2. The other end of the pull-up resistor R4 is connected to the drain of PMOS-Q2. The drain of PMOS-Q2 is connected to the second power supply VDD2, and the source of PMOS-Q2 is connected to the input end of the power management module; the load is arranged at the output end of the power management module.

[0011] Further, one end of the power management module is grounded.

[0012] A method for implementing a low-power timing switch includes the following steps:

[0013] When the input voltage Vin is lower than the threshold VTH of the LX01-D voltage detection circuit, the output is in a high-impedance state, and the output of LX01-D remains high. When the voltage of the input voltage Vin is higher than the threshold VTH of the LX01-D voltage detection circuit, the output is pulled to GND, and the output of the LX01-D voltage detection circuit is converted to low level and remains until the voltage of the input voltage Vin is lower than the falling threshold VTL of the LX01-D voltage detection circuit; when LX01-B outputs a high level, PMOS-Q1 is in a high-impedance state, and when it outputs a low level, PMOS-Q1 is turned on. The conduction and high-impedance states of PMOS-Q1 are complementary to those of LX01-C. When the output of LX01-C is in a high-impedance state, PMOS-Q1 is in a conducting state, and when the output of LX01-C is grounded, PMOS-Q1 is in a high-impedance state;

[0014] By adjusting the values of the resistor R3 and the capacitor C1 in the RC delay circuit to control the duty cycle of the periodic signal, that is, the ratio of the time when the load is activated to the downtime;

[0015] When the output VOD2 of the LX01 voltage detection circuit is low, PMOS-Q2 conducts, and VDD2 is converted by the power management into the voltage VDD3 required by the load, and the load system is activated. When the output of the LX01 voltage detection circuit is high, PMOS-Q2 disconnects, and the power management output VDD3 outputs 0V, and the load enters the shutdown state.

[0016] Compared with the prior art, the present invention has the following technical effects:

[0017] The present invention relates to a low-power timing switch device and an implementation method. This solution mainly consists of three parts: the LX04 low-frequency oscillator, which is the source of the signal; the frequency duty cycle adjustment module adjusts the pulses output by the LX04 as expected; and the trigger module uses the signal output by the frequency duty cycle adjustment module to control the on and off of the load. The LX04 low-frequency oscillator will generate an AC signal with a fixed period under a certain DC voltage. When R1 is 1.4 MΩ, R2 is 100 MΩ, the PMOS threshold voltage Vgs(th) = -1V, and the power supply VDD is 1.2V, the average power consumption is only 64 nA. This timing switch contains an ultra-low-power timer with adjustable frequency duty cycle, and its power consumption is much lower than that of existing low-frequency oscillators, reaching the nW level. The trigger module controls the on and off of the load through the signal of this timer. In this way, the static power consumption and timing power consumption of the system itself are greatly reduced.

[0018] The NOR gate performs a NOR operation on two signals for output. By adjusting the parameters of the RC delay circuit, the duty cycle of the output signal can be adjusted. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of the system structure of the present invention;

[0020] Figure 2 is a signal control schematic diagram of the LX01 voltage detection circuit in the present invention.

[0021] Figure 3 is the logical timing diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention is further described below with reference to the accompanying drawings:

[0023] Please refer to Figures 1 to 3 , the present invention relates to a low-power timing switch system and an implementation method. This solution mainly consists of three parts: the LX04 low-frequency oscillator, which is the source of the signal; the frequency duty cycle adjustment module adjusts the pulses output by the LX04 as expected; and the trigger module uses the signal output by the frequency duty cycle adjustment module to control the on and off of the load.

[0024] Among them, the LX04 low-frequency oscillator can be composed of three or more LX01 voltage detection chips. The output of LX01-A is connected to the input of LX01-B through the pull-up resistor R1. The output of LX01-B is connected to the input of LX01-C through the pull-up resistor R2 and is also connected to the gate of the PMOS transistor Q1. The output of LX01-C is connected to the input of LX01 through the pull-up resistor. The source of the PMOS transistor Q1 is connected to the power supply VDD1, and the drain is connected to the output terminal VOD1 of LX01-C. Under a certain DC voltage, this module will generate an AC signal with a fixed period. When R1 is 1.4 MΩ, R2 is 100 MΩ, the PMOS threshold voltage Vgs(th) = -1 V, and the power supply VDD is 1.2 V, the average power consumption is only 64 nA.

[0025] In the frequency duty cycle adjustment module, the output VOD1 of LX01-C is connected to the input of the frequency divider. The frequency division module can increase the waveform period generated by the LX04 oscillator. The frequency divider has two outputs a and b, and their logics are exactly opposite. Among them, a is directly connected to the NOR gate input a of the delay addition module, and b is connected to the RC delay circuit composed of R3 and C1 to delay the signal of the b path. The positive pole of C1 is connected to the other input b of the NOR gate. The NOR gate performs a NOR operation on the two signals and outputs. By adjusting the parameters of the RC delay circuit, the duty cycle of the output signal can be adjusted.

[0026] In the trigger module, the output OUT of the frequency duty cycle adjustment module is connected to the input end of the LX01 voltage detection circuit. Its output VOD2 is connected to the gate of the PMOS-Q2 through the pull-up resistor. The drain of the PMOS-Q2 is connected to VDD2, and the source is connected to the input end of the power management. The selection of the VDD2 voltage depends on the requirements of the load.

[0027] As Figure 1 shown, the present invention includes an LX04 low-frequency oscillator, a frequency duty cycle adjustment module, and a trigger module.

[0028] Among them, the LX04 ultra-low-power low-frequency oscillator is mainly composed of more than three LX01 passive voltage detection chips. Figure 1 Taking three LX01 voltage detection chips as an example for illustration. When the voltage of Vin is lower than the threshold VTH of the LX01 voltage detection circuit, the output is in a high-impedance state, and the output of LX01 remains high. When the voltage of Vin is higher than the threshold VTH of the LX01 voltage detection circuit, the output is pulled to GND, and the output of the LX01 voltage detection circuit is converted to a low level and remains until the voltage of Vin is lower than the falling threshold VTL of the LX01 voltage detection circuit. Its signal schematic diagram is as Figure 2As shown. The output of LX01-A is connected to the input of LX01-B through the pull-up resistor R1. The output of LX01-B is connected to the input of LX01-C through the pull-up resistor R2 and is also connected to the gate of the PMOS transistor Q1. When the output of LX01-B is high, PMOS-Q1 is in a high-impedance state. When the output is low, PMOS-Q1 is turned on. The output of LX01-C is connected to the input of LX01-A. The source of the PMOS transistor Q1 is connected to the power supply VDD1, and the drain is connected to the output terminal VOD1 of LX01-C. The on and high-impedance states of PMOS-Q1 are complementary to those of LX01-C. When the output of LX01-C is in a high-impedance state, PMOS-Q1 is in an on state. When the output of LX01-C is grounded, PMOS-Q1 is in a high-impedance state. In this way, not only the leakage current of the system is reduced, but also the waveform of the output signal is guaranteed to a certain extent. Under a certain DC voltage, this module will generate an AC signal with a fixed period. The frequency of this AC signal is affected by the resistance values of R1 and R2. An increase in the resistance value will reduce the signal frequency. To reduce the leakage current in the on state of LX01, resistors with large impedance are usually selected. When R1 is 2MΩ, R2 is 100MΩ, the PMOS threshold voltage Vgs(th)=-1V, and the power supply VDD1 is 1.2V, the average power consumption of this module is only 64nA.

[0029] In the frequency duty cycle adjustment module, the role of the frequency divider is to control the duration of the period, which is determined by the number of bits of the frequency divider. The outputs a and b of the frequency divider have opposite logics. Among them, the output a of the frequency divider is connected to the input interface a of the NOR gate, the output b of the frequency divider is connected to the RC delay circuit, and the positive pole of the capacitor C1 is connected to the input interface b of the NOR gate. By adjusting the values of the resistor R3 and the capacitor C1 in the RC delay circuit, the duty cycle of the periodic signal is controlled, that is, the ratio of the time when the load is activated to the downtime. The power supplies of the LX04 ultra-low-power low-frequency oscillator and the frequency duty cycle adjustment module are both powered by the low voltage VDD1.

[0030] In the trigger module, the output OUT of the NOR gate is connected to the input terminal Vin of the LX01-D voltage detection circuit. The output VOD2 of the LX01-D is connected to the gate of the PMOS transistor Q2 through the pull-up resistor R2. The source is connected to VDD2, and the drain is connected to the input Vin of the power management. Since the voltage of VDD2 is not adjusted and is not suitable as the power supply for the load, the VDD2 is subjected to DC conversion through the power management unit to convert it into a power supply suitable for the load. The output VDD3 of the power management module is connected to the positive pole of the load. When the LX01-D output VOD2 is low, the PMOS-Q2 is turned on, and VDD2 is converted into the voltage VDD3 required by the load through the power management, and the load system is activated. When the LX01-D output is high, the PMOS-Q2 is turned off, and the power management output VDD3 output is 0V, and the load enters the shutdown state.

[0031] Figure 3 is the logic timing diagram of the circuit of the present invention, showing the timing relationship between the LX04 output signal VOD1, the signals div_a and div_b of the frequency divider output a and b, the signal nor of the NOR gate output OUT, and the LX01-D output signal VOD2. The frequency divider multiple selected in the figure is 1 / 8, and the signal output by LX04 is frequency-divided. The div b and div a are logically opposite. Because the signal div_b passes through the delay circuit composed of R3 and C1, the rising edge and the falling edge will be extended and become gentle, resulting in a high-level pulse of the NOR gate signal nor during the rising edge stage of div_b. LX01-D will invert the logic of nor, and its output VOD2 is as Figure 3 shown.

Claims

1. A low power consumption timing switch system, characterized in that: It includes an LX04 low-frequency oscillator, a frequency duty cycle adjustment module and a trigger module; the LX04 low-frequency oscillator, the frequency duty cycle adjustment module and the trigger module are connected in sequence, the LX04 low-frequency oscillator is used to generate a signal, the frequency duty cycle adjustment module adjusts the pulse output by the LX04 low-frequency oscillator as desired, and the trigger module uses the signal output by the frequency duty cycle adjustment module to control the on and off of the load; The LX04 low-frequency oscillator includes three LX01 voltage detection chips, a pull-up resistor R1, a pull-up resistor R2 and a PMOS tube Q1; the three LX01 voltage detection chips are LX01-A, LX01-B and LX01-C, one end of the pull-up resistor R1 is connected between the output of LX01-A and the input of LX01-B, one end of the pull-up resistor R2 is connected between the output of LX01-B and the input of LX01-C, and one end of the pull-up resistor R2 and the output of LX01-B are connected to the gate of the PMOS tube Q1, the pull-up resistor R1 and the other end of the pull-up resistor R2 are both connected to the source of the PMOS tube Q1, and the output VOD1 of LX01-C is connected to the input of LX01-A and the drain of the PMOS tube Q1; the source of the PMOS tube Q1 is connected to the first power supply VDD1.

2. A low power consumption timing switch system according to claim 1, characterized in that: The three LX01 voltage detection chips are all grounded.

3. A low power consumption timing switch system according to claim 1, characterized in that: The frequency duty cycle adjustment module includes a frequency divider, a NOR gate, a resistor R3 and a capacitor C1; the output VOD1 of LX01-C is connected to the input of the frequency divider; the frequency divider has output a and output b, wherein output a is directly connected to input a of the NOR gate, and output b is connected to an RC delay circuit composed of R3 and C1 to delay the signal of output b, and the positive pole of C1 is connected to another input b of the NOR gate.

4. A low power consumption timing switch system according to claim 3, characterized in that: The negative terminal of C1 is connected to ground.

5. A low power consumption timing switch system according to claim 3, characterized in that: The trigger module includes an LX01-D voltage detection circuit, a pull-up resistor R4, a PMOS-Q2, a power management module and a load; the output OUT of the frequency duty cycle adjustment module is connected to the input end of the LX01-D voltage detection circuit, one end of the pull-up resistor R4 is connected to the output VOD2 of the LX01-D voltage detection circuit and is connected to the gate of PMOS-Q2, the other end of the pull-up resistor R4 is connected to the source of PMOS-Q2, the source of PMOS-Q2 is connected to the second power supply VDD2, and the drain of PMOS-Q2 is connected to the input end of the power management module; the load is set at the output end of the power management module.

6. A low power consumption timing switch system according to claim 5, characterized in that: One end of the power management module is grounded.

7. A method for implementing a low-power timer switch, characterized in that: A low-power timing switch system according to any one of claims 1 to 6, comprising the following steps: When the input voltage Vin is lower than the threshold VTH of the LX01-D voltage detection circuit, the output is in a high-impedance state, and the output of LX01-D remains high. When the voltage of the input voltage Vin is higher than the threshold VTH of the LX01-D voltage detection circuit, the output is pulled to GND, and the output of the LX01-D voltage detection circuit is converted to a low level and maintained until the voltage of the input voltage Vin is lower than the falling threshold VTL of the LX01-D voltage detection circuit. When LX01-B outputs a high level, PMOS-Q1 is in a high-impedance state. When the output is low, PMOS-Q1 is turned on. The conduction and high-impedance states of PMOS-Q1 and LX01-C complement each other. When the output of LX01-C is in a high-impedance state, PMOS-Q1 is in a conducting state. When the output of LX01-C is grounded, PMOS-Q1 is in a high-impedance state. The duty cycle of the periodic signal, i.e. the ratio of the load activation time to the load shutdown time, is controlled by adjusting the values ​​of the resistor R3 and the capacitor C1 in the RC delay circuit; When the LX01-D voltage detection circuit output VOD2 is low, PMOS-Q2 is turned on, VDD2 is converted into the voltage VDD3 required by the load through power management, and the load system is activated. When the LX01-D voltage detection circuit output is high, PMOS-Q2 is disconnected, the power management output VDD3 is 0V, and the load enters the shutdown state.

Images